Testing system of semiconductor structure and testing method thereof

Abstract

The invention discloses a test system of a semiconductor structure and a test method thereof. The test system comprises a transistor to be tested, a voltage scanning module and a voltage monitoring module. Wherein the voltage scanning module is connected with the drain electrode of the transistor to be tested and applies stepping voltage to the drain electrode. The voltage monitoring module is connected with the grid electrode of the transistor to be measured and monitors the change trend of the voltage of the grid electrode along with the change of the stepping voltage on the drain electrode. Therefore, stepping voltage is applied to the drain electrode of the transistor to be tested, and functional groups such as silicon-hydrogen bonds in the spacing layer are broken at high temperature, so that interface electric leakage is formed from the drain electrode to the grid electrode, namely, charges are abnormally accumulated on the grid electrode, grid electrode voltage deviation is caused, and the channel current characteristic is finally influenced. In addition, a novel electric leakage physical mechanism related to the transistor is provided, and quantitative correlation between the electric leakage physical mechanism and the electrical performance is provided.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a testing system of semiconductor structure and a testing method thereof. BACKGROUND

[0002] MOS (Metal-Oxide-Semiconductor) device is the core unit of integrated circuit, and its performance directly affects the quality of chip. In advanced semiconductor process, SiON process is often used for manufacturing CESL (Contact Etch Stop Layer) layer because it has both etching stop and ion implantation masking functions. However, the spacer material in SiON process may generate interface states or defects due to the breaking of silicon-hydrogen bond (Si-H) under high temperature environment, forming a leakage path along the spacer from Drain to Gate, resulting in abnormal accumulation of electric charge at Gate end, causing gate voltage offset, and ultimately affecting the channel current characteristics. SUMMARY

[0003] One purpose of the present application is to provide a testing system of semiconductor structure and a testing method thereof, which applies step voltage on the drain of the transistor to be tested to stimulate the interface leakage from the drain to the gate, and performs passive bias leakage detection on the transistor to be tested based on the voltage coupling and current response curve drawn.

[0004] To achieve the above purpose, one embodiment of the present application provides a testing system of semiconductor structure, characterized in that it comprises a transistor to be tested, a voltage scanning module and a voltage monitoring module; the voltage scanning module is connected to the drain of the transistor to be tested and applies step voltage to the drain; the voltage monitoring module is connected to the gate of the transistor to be tested and monitors the voltage change trend of the gate with the change of step voltage on the drain.

[0005] Optionally, the transistor to be tested can further comprise a spacer, which is located above the gate and the drain and directly contacts the top surface of the gate and the drain.

[0006] Optionally, the spacer is made of insulating material, and the insulating material includes silicon-hydrogen bond on the surface layer towards the gate and the drain of the transistor to be tested.

[0007] Optionally, the range of step voltage can be -5V ~ 5V.

[0008] Optionally, the step length of step voltage is a fixed step length, and the range of fixed step length can be 0.1V ~ 0.5V.

[0009] Optionally, the range of duration of step voltage can be 10ms ~ 20ms.

[0010] Optionally, the test system further comprises a substrate driving module connected to the substrate and the source of the transistor under test.

[0011] Optionally, the substrate driving module is configured to apply a 0V voltage to the substrate and the source.

[0012] Optionally, the transistor under test can be a MOS transistor or a CMOS transistor.

[0013] To achieve the above object, one embodiment of the present application provides a test method for a semiconductor structure, comprising:

[0014] providing a test system as described above;

[0015] applying a step voltage to the drain of the transistor under test by using the voltage scanning module in the test system, and obtaining the gate voltage and the drain current of the transistor under test on the leakage path caused by the interval layer after each fixed step increase of the step voltage;

[0016] drawing a gate-drain voltage coupling curve and a drain voltage-drain current response curve based on the step voltage and the corresponding gate voltage and drain current.

[0017] Optionally, the gate voltage of the transistor under test is in a proportional relationship with the drain voltage when the step voltage increases from small to large by the fixed step.

[0018] Optionally, the drain current of the transistor under test gradually increases until reaching a threshold value with the increase of the drain voltage when the step voltage increases from small to large by the fixed step.

[0019] In the present application, the test system comprises a transistor under test, a voltage scanning module and a voltage monitoring module; wherein the voltage scanning module is connected to the drain of the transistor under test and applies a step voltage to the drain; the voltage monitoring module is connected to the gate of the transistor under test and monitors the voltage change trend of the gate with the change of the step voltage on the drain. Thus,

[0020] By applying a step voltage to the drain of the transistor under test, the functional groups such as silicon-hydrogen bonds in the interval layer are broken at high temperature, so as to excite the interface leakage from the drain to the gate, that is, to cause the abnormal accumulation of charges on the gate, to induce the gate voltage shift, and finally to affect the channel current characteristics.

[0021] Further, since the test system in the present application applies voltage at the drain of the transistor to be tested, and synchronously detects the voltage generated at the gate, i.e. reverse excitation from the drain to the gate and passive monitoring, and through the step voltage and the corresponding gate voltage and drain current, the gate-drain voltage coupling curve (voltage coupling) and the drain voltage current response curve (current response) can be plotted, and further passive bias drain detection is performed on the transistor to be tested, i.e. a new physical mechanism of drain leakage and quantitative correlation of electrical performance of the transistor are proposed. BRIEF DESCRIPTION OF DRAWINGS

[0022] The accompanying drawings are included to provide a further understanding of embodiments of the application, and are incorporated in and constitute a part of this specification. The drawings

[0023] Figure 1 A system block diagram of a test system of a semiconductor structure in an embodiment of the present application is shown.

[0024] Figure 2 A partial structure cross-sectional view of a transistor to be tested is shown.

[0025] Figure 3 A schematic diagram of a gate-drain voltage coupling curve of a transistor to be tested is shown.

[0026] Figure 4 A schematic diagram of a drain voltage current response curve of a transistor to be tested is shown.

[0027] In Figures 1 to 4 which:

[0028] 10 - transistor to be tested, 20 - voltage scanning module, 30 - voltage monitoring module, 40 - substrate driving module, 100 - substrate, 110 - epitaxial layer, 120 - gate structure, 130 - spacer layer, G - gate, D - drain, S - source, 101 - trench isolation, P+-P type region.

[0029] In the drawings, the same components have the same reference numerals, and the drawings are not drawn according to the actual proportions. DETAILED DESCRIPTION

[0030] In order to make the technical solutions and advantages of the embodiments of the present application clearer, the technical solutions of the present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. Although the exemplary implementation methods of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the implementation described herein. On the contrary, these implementations are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0031] The present application will be described in more detail by referring to the following paragraphs and embodiments with reference to the accompanying drawings. The advantages and features of the present application will be more apparent from the following description and claims. It should be noted that the accompanying drawings are very simplified and use non-precise proportions, only for the purpose of facilitating and clearly assisting the description of the embodiments of the present application. It can be understood that the meanings of "on", "above" and "over" in the present application should be interpreted in the broadest way, so that "on" not only means the meaning of "on" with no intervening features or layers therebetween (i.e. directly on something), but also includes the meaning of "on" with intervening features or layers therebetween.

[0032] In addition, for ease of description, regional relative terms such as "on", "above", "over", "upper", "top" and the like can be used in this document to describe the relationship between one element or feature and another element or feature as shown in the drawings. In addition to the orientation depicted in the drawings, the regional relative terms are intended to cover different orientations of the device in use or operation. The device can be oriented in other ways (rotated 90 degrees or in other orientations) and the regional relative terms used herein can also be interpreted accordingly.

[0033] In the embodiments of the present application, the terms "first", "second", and the like are used to distinguish similar objects, and do not necessarily describe a specific order or sequence. It should be noted that the technical solutions described in the embodiments of the present application can be combined arbitrarily without conflict.

[0034] At present, the conventional transistor testing method is to actively apply a voltage to the gate, detect the drain current when the transistor is in the on state and the drain-source off current (Ioff) when the transistor is in the off state, and draw a gate-drain current curve and evaluate the off-state leakage performance.

[0035] Therefore, the defects existing in the prior art are:

[0036] 1. Passive bias effect of transistor gate cannot be monitored. In the current test, the control signal on the transistor gate is actively applied, and the passive voltage offset of the gate caused by the components and / or devices containing Si-H bonds in the spacer or sidewall and the influence on the transistor characteristic parameters cannot be captured, for example, in the SiON process, the leakage along the spacer from the drain to the gate is formed, which makes the charge accumulation at the gate and the gate voltage deviates from the normal value.

[0037] 2. The leakage path positioning is ambiguous. At present, the leakage is only indirectly judged by the abnormality of the leakage current (such as the increase of the drain-source off current Ioff), and the direct correlation between the leakage path and the gate bias cannot be established, and it is difficult to distinguish different failure mechanisms caused by the components and / or devices containing Si-H bonds in the spacer or sidewall, or gate oxide leakage, or junction leakage.

[0038] 3. The test dimension is single. The existing technology is limited to two-dimensional analysis of "voltage-current", and lacks characterization of "voltage-voltage" coupling relationship (VD-VG), and cannot quantify the dynamic influence of the drain voltage on the gate bias.

[0039] 4. Insufficient process compatibility. There is a lack of targeted test scheme for the interface state leakage mechanism specific to the SiON new process, such as Si-H bond (Si-H) breakage.

[0040] Therefore, the present application provides a test system for semiconductor structure and a test method thereof, so as to excite the interface leakage from the drain to the gate by applying a step voltage on the drain of the transistor to be tested, and to detect the passive bias leakage of the transistor to be tested based on the drawn voltage coupling and current response curve.

[0041] Please refer to Figure 1 , which is a system block diagram of the test system for semiconductor structure in an embodiment of the present application. As Figure 1 shown, the test system for semiconductor structure includes a transistor to be tested 10, a voltage scanning module 20, a voltage monitoring module 30 and a substrate driving module 40. Wherein, the voltage scanning module 20 is connected to the drain D of the transistor to be tested 10, and applies a step voltage to the drain D; the voltage monitoring module 30 is connected to the gate G of the transistor to be tested 10, and monitors the change trend of the voltage (hereinafter referred to as gate voltage) of the gate G with the change of the step voltage on the drain D; the substrate driving module 40 is connected to the substrate 100 and the source S of the transistor to be tested 10, and is used to apply a specific voltage such as 0V voltage to the 100 and the source S, that is, to ensure that the current flow direction of the transistor to be tested 10 meets the requirements during the detection process.

[0042] In one embodiment, the transistor under test 10 may be a MOS transistor, a CMOS transistor such as an NMOS transistor or a PMOS transistor, a FinFET fin structure, or a gate-enclosed array (GAA) structure, or any other semiconductor structure requiring gate leakage current evaluation, but is not limited thereto. Exemplarily, the appendix in the embodiments of the present invention... Figures 1 to 4 The diagrams are all drawn with NMOS transistor as an example for the transistor under test 10. The following parameter ranges are the corresponding parameter ranges when the transistor under test 10 is an NMOS transistor. When the transistor under test 10 is another semiconductor structure that needs to be evaluated for gate leakage current, the parameter ranges can be changed accordingly, and are not limited to this.

[0043] Please refer to Figure 2 As shown, the diagram depicts a partial cross-sectional view of the transistor under test in one embodiment of the present invention. Figure 2 As shown, the transistor under test 10, such as an NMOS transistor, may include a substrate 100, an epitaxial layer 110, a gate structure 120, an ion implantation region P-well, a trench isolation 101, a source (S), a drain (D), and a spacer layer 130. In one embodiment, the material of the substrate 100 may be any suitable substrate material well known to those skilled in the art, such as at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), etc. This application does not limit the material of the substrate 100. The epitaxial layer 110 is located on the substrate 100 and has a certain thickness along a direction perpendicular to the surface of the substrate 100. The ion implantation region P-well is located within the epitaxial layer 110, and the gate structure 120 is located on the epitaxial layer 110 and aligned with the ion implantation region P-well.

[0044] The gate structure 120 can include multiple layers of materials, for example, a gate oxide layer and a gate layer stacked in sequence from bottom to top, and the gate layer is electrically led out through a conductive plug to serve as the gate G of the transistor 10 to be tested; the source S and the drain D are respectively arranged in the ion implantation regions P on both sides of the gate structure 120; and the spacer layer 130 is arranged on the gate G and the drain D and directly contacts the top surfaces of the gate G and the drain D, that is, the spacer layer 130 wraps the surfaces of the gate structure 120 and the epitaxial layer 110 exposed on both sides of the gate structure 120. It should be understood that, in order to facilitate the application of voltage to the substrate 100, an ion implantation region of the same doping type as the substrate 100 can also be formed in the epitaxial layer 110 or the ion implantation region P well by ion implantation, for example, the embodiment can be a P-type region (indicated by reference numeral P+), but is not limited thereto. The trench isolation 101 can be arranged in the epitaxial layer 110 on both sides of the gate structure 120 to isolate multiple transistors to be tested. The material of the spacer layer 130 can be an insulating material, for example, silicon dioxide, silicon nitride, etc., and the surface layer on the side facing the gate G and the drain S of the transistor to be tested includes functional groups or dangling bonds, for example, silicon-hydrogen bonds (Si-H).

[0045] As shown in Figure 2 , in the process of testing the transistor to be tested by using the test system provided in the embodiment of the present application, a voltage needs to be applied to the drain of the transistor to be tested, that is, the voltage scanning module 20 is connected to the drain of the transistor to be tested, the gate of the transistor 10 to be tested is connected to the voltage monitoring module 30, and the substrate 100 and the source of the transistor to be tested are grounded. Then, by actively applying a voltage to the drain, an interface leakage is formed from the drain to the gate of the transistor 10 to be tested, which causes the accumulation of electric charges from the drain to the spacer layer 130 and the abnormal accumulation of the gate, thereby causing the voltage offset of the gate. Therefore, by using the test system provided in the embodiment of the present application, the leakage path of the transistor to be tested can be determined by applying a voltage to the drain, that is, the leakage mechanism can be accurately positioned, that is, the leakage caused by the spacer layer 130 (for example, the rupture of Si-H under high temperature in SiON process) can be quickly positioned, rather than the leakage caused by other mechanisms.

[0046] Further, based on the test system as shown in Figure 1 and Figure 2 , the present application further provides a test method of a semiconductor structure, that is, a test method for testing the leakage of the transistor 10 to be tested, which at least includes the following steps:

[0047] Step S101, providing the test system as shown in Figure 1 , wherein the transistor to be tested in the test system can be exemplarily as shown in Figure 2 .

[0048] Step S102, applying a step voltage to the drain D of the transistor 10 under test by the voltage scanning module 20 in the test system, and acquiring the gate voltage and the drain current of the transistor under test along the leakage path caused by the spacer layer 130 after each fixed step increase of the step voltage.

[0049] Step S103, drawing the gate-drain voltage coupling curve and the drain voltage current response curve based on the step voltage and the corresponding gate voltage and drain current.

[0050] Wherein, the gate voltage of the transistor under test is in a proportional relationship with the drain voltage as the step voltage increases from small to large with the fixed step. The drain current of the transistor under test gradually increases until reaching a threshold value as the drain voltage increases.

[0051] In the embodiment, the substrate 100 and the source S of the transistor 10 under test are grounded (0V), and then the voltage scanning module 20 is used to apply a step voltage to the drain D of the transistor 10 under test. The voltage range of the step voltage is 0V ~ 5V, that is, the voltage applied to the drain D is not only one voltage, but starts from 0V and gradually increases to 5V (VDD) with a fixed step (for example, 0.1V), and at each voltage point corresponding to each fixed step increase, it stays or lasts for Δt (for example, 10ms) to ensure that the charge accumulated in the gate reaches a steady state. For example, the step of the step voltage is a fixed step, and the range of the fixed step is 0.1V ~ 0.5V, that is, the fixed step can be 0.1V, 0.2V, 0.3V, 0.4V, 0.5V, etc. The duration of the step voltage ranges from 10ms to 20ms, but is not limited thereto. After each application of the step voltage to the drain of the transistor 10 under test, the gate voltage and the drain current are collected to form a discrete data point set {(VD_i, VG_i, ID_i)}, wherein VD_i is the step voltage value applied to the drain for the ith time, VG_i is the gate voltage collected after the step voltage applied to the drain for the ith time, and ID_i is the drain current collected after the step voltage applied to the drain for the ith time. Then, the voltage coupling and current response curves are drawn, that is, the coupling curve of the drain voltage and the gate voltage of the transistor under test is shown in FIG. 2, and the current response curve is shown in FIG. 3. Figure 3 Figure 4 It should be understood that in other embodiments, when the transistor 10 under test is a PMOS transistor, the range of the step voltage applied to the drain can be 0V ~ -5V, and other settings are the same as when the transistor 10 under test is an NMOS transistor, and are not limited thereto.

[0052] Please refer to​Figure 3 and Figure 4 are shown in FIG. 2A and FIG. 2B, respectively. Figure 3 is a schematic diagram of the gate-drain voltage coupling curve of the transistor to be tested; Figure 4 is a schematic diagram of the drain voltage-current response curve of the transistor to be tested. In Figure 3 , the horizontal axis is the drain voltage VD, and the vertical axis is the gate voltage VG, so as to reflect the gate bias shift induced by the drain voltage. Figure 4 , the horizontal axis is the drain voltage VD, and the vertical axis is the drain current ID, so as to reflect the modulation effect of the gate bias caused by the drain voltage on the channel current. Specifically, in Figure 3 , the blue dotted line is the gate-drain voltage coupling curve of the 5V NMOS transistor at 25°C (no leakage caused by SiON process), and obviously at this time the gate voltage VG≈0V, and the VD-VG curve basically remains horizontal; the yellow dotted line is the gate-drain voltage coupling curve of the 5V NMOS transistor at high temperature 150°C (leakage from the drain to the gate caused by the SiON process), and obviously at this time the gate voltage VG is linearly proportional to the drain voltage VD, and when the drain voltage VD=3.4V, the drain current reaches the 100uA current limit, at this time the gate coupling voltage also remains VG=1V and no longer increases (because the ID=100uA current limit is triggered, causing VD to no longer continue to step the 3.4~5V voltage, and VD actually remains 3.4V unchanged), and the slope K=0.294 reflects the leakage intensity. In Figure 4 , the blue dotted line is the drain current ID of the 5V NMOS transistor at 25°C, which is always close to 0 when the drain voltage VD continuously increases (for example, ID=3.5pA when VD=5V), which meets the cutoff characteristic; the yellow dotted line is the drain current ID of the 5V NMOS transistor at high temperature 150°C, which is caused by the leakage of the Si-H bond in the spacer layer, and then the gate coupling voltage (VG>Vth) occurs, so that the drain current ID rises to 50.2uA when the drain voltage VD=3V (coupling VG=0.86V), indicating that the channel is abnormally turned on. Obviously, the test system proposed in the embodiment of the present application can quantitatively correlate the leakage physical mechanism of the transistor to be tested with the electrical performance of the transistor.

[0053] To sum up, in the present application, the test system comprises a transistor to be tested, a voltage scanning module and a voltage monitoring module; wherein the voltage scanning module is connected to the drain of the transistor to be tested and applies a step voltage to the drain; the voltage monitoring module is connected to the gate of the transistor to be tested and monitors the change trend of the voltage of the gate with the change of the step voltage on the drain; thus, by applying a step voltage to the drain of the transistor to be tested, the functional groups such as silicon hydrogen bonds in the interval layer are broken at high temperature, so as to excite the interface leakage current from the drain to the gate, that is, to cause the abnormal accumulation of charges at the gate, to cause the gate voltage to deviate, and finally to affect the channel current characteristics. Further, since the test system in the present application applies a voltage to the drain of the transistor to be tested and synchronously detects the voltage generated on the gate, that is, the reverse excitation and passive monitoring from the drain to the gate, and by the step voltage and the corresponding gate voltage and drain current, the gate-drain voltage coupling curve (voltage coupling) and the drain voltage current response curve (current response) can be drawn, and further passive bias leakage detection is performed on the transistor to be tested, that is, a new leakage physical mechanism and quantitative correlation of electrical performance of the transistor are proposed.

[0054] The above only describes the preferred embodiments of the present application and is not used to limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A testing system for semiconductor structures, characterized in that, It includes a transistor under test (TUT), a voltage scanning module, and a voltage monitoring module; the voltage scanning module is connected to the drain of the TUT and applies a step voltage to the drain; the voltage monitoring module is connected to the gate of the TUT and monitors the voltage change trend of the gate as the step voltage on the drain changes.

2. The testing system as described in claim 1, characterized in that, The transistor under test further includes a spacer layer, which is located above the gate and drain and is in direct contact with the top surfaces of the gate and drain.

3. The testing system as described in claim 2, characterized in that, The spacer layer is an insulating material, and the insulating material includes silicon-hydrogen bonds on its surface along the side facing the gate and drain of the transistor under test.

4. The testing system as described in claim 1, characterized in that, The step voltage range is -5V to 5V.

5. The testing system as described in claim 4, characterized in that, The step size of the step voltage is a fixed step size, and the range of the fixed step size is 0.1V~0.5V.

6. The testing system as described in claim 4 or 5, characterized in that, The duration of the step voltage is in the range of 10ms to 20ms.

7. The testing system as described in claim 1, characterized in that, It also includes a substrate driving module, which is connected to the substrate and source of the transistor under test.

8. The testing system as described in claim 7, characterized in that, The substrate driving module is used to apply a 0V voltage to the substrate and the source.

9. The testing system as described in claim 1, characterized in that, The transistor under test includes a MOS transistor or a CMOS transistor.

10. A method for testing semiconductor structures, characterized in that, include: Provide a test system as described in any one of claims 1 to 9; Using the voltage scanning module in the test system, a step voltage is applied to the drain of the transistor under test, and after the step voltage is increased by a fixed step size each time, the gate voltage and leakage current of the transistor under test under the leakage path caused by the spacer layer are obtained respectively. Based on the step voltage and the corresponding gate voltage and drain current, plot the gate-drain voltage coupling curve and the drain voltage-current response curve.

11. The test method as described in claim 10, characterized in that, As the step voltage increases from small to large with the fixed step, the gate voltage of the transistor under test is directly proportional to its drain voltage.

12. The test method as described in claim 10, characterized in that, As the step voltage increases in fixed steps from small to large, the drain current of the transistor under test gradually increases with the increase of the drain voltage until it reaches the threshold.

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