Wafer-level semiconductor packaging structure and preparation method thereof

Abstract

The embodiment of the invention provides a wafer-level semiconductor packaging structure and a preparation method thereof, and relates to the technical field of photoelectric packaging, and the wafer-level semiconductor packaging structure comprises an optical chip, a light reflecting layer, a plastic packaging layer and an electric chip. The light reflecting layer is formed above the cavity to reflect light signals, so that the light signals can be directly transmitted from the side direction, a complicated optical structure does not need to be manufactured, the structure is simple, the manufacturing difficulty and the processing cost are reduced, and the processing period is shortened. Meanwhile, signal loss caused by insufficient refractive index and light transmittance of the optical structure is avoided, transmission signal loss is reduced, and transmission efficiency is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of photoelectric packaging, in particular to a wafer-level semiconductor packaging structure and a preparation method thereof. BACKGROUND

[0002] The light port of the traditional photoelectric device packaging body structure presents a trench morphology, and the light signal needs to be conducted vertically to the light port trench. However, due to the trench morphology, the light signal receiving range is small, and the light port needs to be protected from pollution damage, so an optical lens or other optical bridging structure needs to be attached at the light port position to make an optical channel.

[0003] However, on the one hand, the optical structure needs to be designed additionally, and the structure is complex, which increases the processing difficulty and cost; on the other hand, due to the limitation of the refractive index and light transmittance of the optical structure and the material, the transmission signal loss exists when the light signal passes through the optical structure, which undoubtedly limits the transmission rate. SUMMARY

[0004] The purpose of the present application is to provide a wafer-level semiconductor packaging structure and a preparation method thereof, in which the light signal can be directly conducted from the side, without the need to make a complex optical structure, thereby reducing the transmission signal loss and improving the transmission efficiency.

[0005] In a first aspect, the present application provides a wafer-level semiconductor packaging structure, comprising: an optical chip, one side edge of the optical chip being provided with a light port structure, the light port structure comprising a first optical surface, the first optical surface being exposed to the front surface of the optical chip and extending to the front surface edge of the optical chip; a light reflection layer, provided on the front surface of the optical chip and corresponding to the first optical surface, and a reflection cavity being formed between the light reflection layer and the first optical surface, the reflection cavity extending to the front surface edge of the optical chip and having an optical opening, the opening direction of the optical opening being parallel to the front surface of the optical chip, the light reflection layer being configured to reflect a light signal; a plastic encapsulation layer, provided at least on the front surface of the optical chip and covering the light reflection layer.

[0006] In an optional embodiment, the light port structure further comprises a second optical surface, the second optical surface being provided adjacent to the first optical surface and being exposed to the sidewall of the optical chip, and the optical opening being joined to the second optical surface.

[0007] In an optional embodiment, the front surface edge of the optical chip further forms a light port groove, the light port groove being in communication with the optical opening, and the second optical surface being configured to constitute a sidewall of the light port groove.

[0008] In an optional embodiment, the wafer-level semiconductor package structure further comprises an electrical chip, which is disposed in the plastic encapsulation layer and electrically connected with the optical chip.

[0009] In an optional embodiment, the electrical chip is disposed on the front surface of the optical chip and electrically connected with the optical chip, the front surface of the optical chip is further provided with a conductive post, the plastic encapsulation layer is disposed on the front surface of the optical chip and covers the electrical chip and the conductive post, an end of the conductive post away from the optical chip is exposed to the plastic encapsulation layer and provided with a conductive bump, and the conductive bump is electrically connected with the optical chip through the conductive post.

[0010] In an optional embodiment, the front surface of the electrical chip is provided with a first micro bump corresponding to be soldered to the front surface of the optical chip, and the back surface of the electrical chip is exposed to the plastic encapsulation layer.

[0011] In an optional embodiment, the conductive post is arranged around the electrical chip, and the conductive post is spaced apart from the optical reflection layer.

[0012] In an optional embodiment, the wafer-level semiconductor package structure further comprises an interposer, the optical chip and the electrical chip are attached to one side surface of the interposer and electrically connected with the interposer, the plastic encapsulation layer is disposed on one side surface of the interposer and covers the optical chip and the electrical chip, and the other side surface of the interposer is provided with a conductive bump, which is electrically connected with the interposer.

[0013] In an optional embodiment, the front surface of the electrical chip is provided with a first micro bump corresponding to be soldered to one side surface of the interposer, and the back surface of the electrical chip is exposed to the plastic encapsulation layer; the front surface of the optical chip is provided with a second micro bump corresponding to be soldered to one side surface of the interposer, and the back surface of the optical chip is exposed to the plastic encapsulation layer.

[0014] In an optional embodiment, the wafer-level semiconductor package structure further comprises a first redistribution layer and a second redistribution layer, the first redistribution layer is disposed on the front surface of the optical chip, the second redistribution layer is disposed on the back surface of the optical chip, and the first redistribution layer and the second redistribution layer are electrically connected, the electrical chip is attached to the first redistribution layer and electrically connected with the first redistribution layer, the plastic encapsulation layer is disposed on the front surface of the optical chip and covers the first redistribution layer and the electrical chip, and the second redistribution layer is further provided with a conductive bump away from one side of the first redistribution layer, and the conductive bump is electrically connected with the second redistribution layer.

[0015] In an optional embodiment, the optical chip is further provided with a conductive via filled with a conductive material, and the first redistribution layer is electrically connected with the second redistribution layer through the conductive via.

[0016] In an optional embodiment, the front surface of the electrical chip is provided with a first micro bump corresponding to be welded to the first redistribution layer, and the back surface of the electrical chip is exposed to the plastic encapsulation layer.

[0017] In an optional embodiment, the wafer-level semiconductor encapsulation structure further comprises a substrate, and the conductive bump is corresponding to be welded to the substrate.

[0018] In a second aspect, the present application provides a method for preparing a wafer-level semiconductor encapsulation structure, which is used to prepare the wafer-level semiconductor encapsulation structure as described in the foregoing embodiments, and the method comprises: providing a wafer with a plurality of optical chips, wherein each of the optical chips is provided with an optical port structure and an optical port groove, the optical port structure comprises a first optical surface, the first optical surface is exposed to the front surface of the optical chip and extends to the optical port groove; forming a protective layer covering the optical port structure and the optical port groove on the front surface of the optical chip; forming an optical reflection layer on the protective layer, wherein the optical reflection layer corresponds to the optical port structure; preparing a plastic encapsulation layer covering at least the optical reflection layer and the front surface of the optical chip; cutting the plastic encapsulation layer to form a first cut, wherein the first cut corresponds to the optical port groove and exposes the optical reflection layer; dicing the optical chip to form a second cut, wherein the second cut corresponds to the optical port groove and exposes the protective layer; removing the protective layer to form a reflection cavity between the optical reflection layer and the first optical surface; breaking the optical reflection layer along the optical port groove by a breakage process.

[0019] In an optional embodiment, the step of preparing a plastic encapsulation layer covering at least the optical reflection layer and the front surface of the optical chip comprises: forming a conductive column on the front surface of the optical chip; welding an electrical chip on the front surface of the optical chip; forming a plastic encapsulation layer on the front surface of the optical chip, wherein the plastic encapsulation layer covers the conductive column, the electrical chip, the optical reflection layer and the front surface of the optical chip; thinning the plastic encapsulation layer and exposing the conductive column; forming a conductive bump on the conductive column.

[0020] In an optional embodiment, the step of preparing the plastic encapsulation layer covering at least the light reflection layer and the front surface of the light chip comprises: cutting the wafer into a plurality of light chips; forming an intermediate layer on a glass slide; soldering the light chip and the electronic chip on the intermediate layer; forming a plastic encapsulation layer on the intermediate layer, wherein the plastic encapsulation layer covers the light reflection layer, the light chip and the electronic chip; removing the glass slide; forming conductive bumps on a side of the intermediate layer away from the plastic encapsulation layer.

[0021] In an optional embodiment, the light chip is internally provided with a conductive via hole filled with a conductive material, and before the step of preparing the plastic encapsulation layer covering at least the light reflection layer and the front surface of the light chip, the method further comprises: forming a first redistribution layer on the front surface of the light chip; thinning the back surface of the light chip and exposing the conductive via hole; forming a second redistribution layer on the back surface of the light chip, wherein the second redistribution layer is electrically connected to the first redistribution layer through the conductive via hole; forming conductive bumps on the second redistribution layer.

[0022] In an optional embodiment, the step of preparing the plastic encapsulation layer covering at least the light reflection layer and the front surface of the light chip comprises: soldering the electronic chip on the first redistribution layer; forming a plastic encapsulation layer on the front surface of the light chip, wherein the plastic encapsulation layer covers the electronic chip, the first redistribution layer and the light reflection layer.

[0023] The beneficial effects of the embodiments of the present application include: The wafer-level semiconductor packaging structure and the preparation method thereof provided by the embodiments of the present application are provided with a light port structure on one side edge of the light chip, a first optical surface of the light port structure is exposed to the front surface of the light chip and extends to the front surface edge of the light chip. Meanwhile, a light reflection layer corresponding to the first optical surface is also arranged on the front surface of the light chip, a reflection cavity is formed between the light reflection layer and the first optical surface, the reflection cavity extends to the front surface edge of the light chip, and an optical opening is formed, the opening direction of the optical opening is parallel to the front surface of the light chip, that is, a side opening is formed. The plastic encapsulation layer covers the light reflection layer, the light reflection layer can reflect the light signal, and the light signal transmission between the first optical surface and the optical opening is realized.

[0024] Compared with the prior art, the wafer-level semiconductor packaging structure and the preparation method thereof provided by the embodiments of the present application adopt the cavity structure with the sidewall opening, and the light reflection layer is formed above the cavity to reflect the light signal, so that the light signal can be directly conducted from the side, and therefore the complex optical structure does not need to be made, the structure is simple, the manufacturing difficulty and the processing cost are reduced, and the processing period is shortened. At the same time, the signal loss caused by the insufficient refractive index and light transmittance of the optical structure is avoided, the transmission signal loss is reduced, and the transmission efficiency is improved. BRIEF DESCRIPTION OF DRAWINGS

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some of the embodiments of the present application, and therefore should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0026] Figure 1 a schematic diagram of the wafer-level semiconductor packaging structure provided by the first embodiment of the present application; Figures 2 to 14 a process flow schematic diagram of the preparation method of the wafer-level semiconductor packaging structure provided by the first embodiment of the present application; Figure 15 a schematic diagram of the wafer-level semiconductor packaging structure provided by the second embodiment of the present application; Figures 16 to 24 a process flow schematic diagram of the preparation method of the wafer-level semiconductor packaging structure provided by the second embodiment of the present application; Figure 25 a schematic diagram of the wafer-level semiconductor packaging structure provided by the third embodiment of the present application; Figures 26 to 34 a process flow schematic diagram of the preparation method of the wafer-level semiconductor packaging structure provided by the third embodiment of the present application.

[0027] Figure: 100-wafer-level semiconductor packaging structure; 110-optical chip; 111-optical port structure; 112-first optical surface; 113-second optical surface; 114-optical port groove; 115-second micro bump; 116-conductive via; 120-light reflection layer; 121-reflective cavity; 122-optical opening; 130-plastic encapsulation layer; 140-electronic chip; 141-first micro bump; 150-conductive column; 151-conductive bump; 160-intermediate layer; 170-first redistribution layer; 180-second redistribution layer; 200-protection layer; 300-first cutout; 400-second cutout; 600-glass slide. DETAILED DESCRIPTION

[0028] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0029] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0030] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0031] In the description of this invention, it should be noted that if terms such as "upper," "lower," "inner," or "outer" are used to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of this invention is usually placed, they are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.

[0032] Furthermore, the terms "first" and "second" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0033] As disclosed in the background section, the optical port packaging structure of traditional optoelectronic devices, such as that disclosed in CN119095A, has a trench morphology for the optical port, with the trench opening facing upwards. The optical signal needs to be transmitted perpendicular to the optical port trench. However, due to the limitation of the trench morphology, the optical signal receiving range is small, and the optical port needs to be protected from contamination and damage. Therefore, it is necessary to mount an optical lens or other optical bridging structure (collectively referred to as optical structure) at the optical port position to create an optical channel.

[0034] However, on the one hand, optical structures require additional design and are complex, which increases the difficulty and cost of processing; on the other hand, due to the limitations of the refractive index and transmittance of optical structures and materials, light signals suffer transmission signal loss when passing through optical structures, and the signal loss is usually large, which undoubtedly limits the transmission rate.

[0035] To solve the above problems, the embodiment of the present application provides a novel wafer-level semiconductor packaging structure and a preparation method thereof, and it should be noted that the features in the embodiments of the present application can be combined with each other without conflict.

[0036] First embodiment Referring to Figure 1 The embodiment of the present application provides a wafer-level semiconductor packaging structure 100, and the optical signal can be directly conducted from the side without making a complex optical structure, thereby reducing the manufacturing difficulty and processing cost and shortening the processing cycle. Meanwhile, signal loss caused by insufficient refractive index and light transmittance of the optical structure is avoided, the transmission signal loss is reduced, and the transmission efficiency is improved.

[0037] The wafer-level semiconductor packaging structure 100 provided by the embodiment of the present application comprises an optical chip 110, an optical reflection layer 120, a plastic encapsulation layer 130 and an electrical chip 140. The optical chip 110 is provided with an optical port structure 111 at one side edge thereof. The optical port structure 111 comprises a first optical surface 112. The first optical surface 112 is exposed to the front surface of the optical chip 110 and extends to the front surface edge of the optical chip 110. The optical reflection layer 120 is arranged on the front surface of the optical chip 110 and corresponds to the first optical surface 112. A reflection cavity 121 is formed between the optical reflection layer 120 and the first optical surface 112. The reflection cavity 121 extends to the front surface edge of the optical chip 110 and has an optical opening 122. The opening direction of the optical opening 122 is parallel to the front surface of the optical chip 110. The optical reflection layer 120 is configured to reflect the optical signal. The plastic encapsulation layer 130 is arranged on the front surface of the optical chip 110 and encapsulates the optical reflection layer 120. The electrical chip 140 is arranged in the plastic encapsulation layer 130 and is electrically connected to the optical chip 110.

[0038] It should be noted that the front surface of the optical chip 110 in the embodiment refers to some surfaces of the optical chip 110 having electrical contact pads, which realize electrical connection through the front surface. The optical port structure 111 refers to the part of the optical chip 110 that realizes input / output of the optical signal and is located at the front surface edge region of the optical chip 110. The reflection cavity 121 can be formed between the optical reflection layer 120 and the first optical surface 112, and the reflection cavity 121 has the side opening optical opening 122, so as to realize the side wall opening cavity structure. The optical reflection layer 120 is used to reflect the optical signal, so the optical signal can be directly conducted from the side, and thus a complex optical structure is not needed, the structure is simple, the manufacturing difficulty and processing cost are reduced, and the processing cycle is shortened. Meanwhile, signal loss caused by insufficient refractive index and light transmittance of the optical structure is avoided, the transmission signal loss is reduced, and the transmission efficiency is improved.

[0039] Further, the optical port structure 111 further comprises a second optical surface 113, the second optical surface 113 is arranged adjacent to the first optical surface 112 and exposed to the side wall of the optical chip 110, and the optical opening 122 is connected to the second optical surface 113. Specifically, the second optical surface 113 is perpendicular to the first optical surface 112, wherein the second optical surface 113 is exposed to the side wall of the optical chip 110 along the vertical direction, and the first optical surface 112 is exposed to the front surface of the optical chip 110 along the horizontal direction, and the range of the first optical surface 112 is limited in the reflection cavity 121. Wherein the first optical surface 112 and the second optical surface 113 can realize the conduction of optical signals, and since the second optical surface 113 is directly exposed to the side wall of the optical chip 110, the lateral conduction of optical signals can be directly realized, avoiding signal loss. It is worth noting that the first optical surface 112 and the second optical surface 113 can realize the lateral conduction of optical signals, further reducing the transmission signal loss and improving the transmission efficiency.

[0040] In the embodiment, the front surface edge of the optical chip 110 is further formed with an optical port groove 114, the optical port groove 114 is in communication with the optical opening 122, and the second optical surface 113 is configured to constitute the side wall of the optical port groove 114. Specifically, the second optical surface 113 can be limited inward relative to the side wall of the optical chip 110 and constitute the side wall of the optical port groove 114 close to the optical port structure 111. The arrangement of the optical port groove 114 can avoid damaging the second optical surface 113 during the formation of the single optical chip 110, ensuring the integrity and optical conduction performance of the second optical surface 113.

[0041] In the embodiment, the electrical chip 140 is arranged on the front surface of the optical chip 110 and electrically connected with the optical chip 110, and the front surface of the optical chip 110 is further provided with a conductive column 150, and the plastic encapsulation layer 130 is arranged on the front surface of the optical chip 110 and encapsulates the electrical chip 140 and the conductive column 150. The end of the conductive column 150 away from the optical chip 110 is exposed to the plastic encapsulation layer 130 and is provided with a conductive bump 151, and the conductive bump 151 is electrically connected with the optical chip 110 through the conductive column 150. Specifically, the electrical chip 140 is attached to the front surface of the optical chip 110, and the optical chip 110 is electrically connected with the outside through the conductive column 150 and the conductive bump 151, and realizes the optoelectronic co-encapsulation structure through the plastic encapsulation layer 130.

[0042] Further, the front surface of the electric chip 140 is provided with a first micro bump 141 corresponding to the front surface of the optical chip 110, and the back surface of the electric chip 140 is exposed to the plastic sealing layer 130. Specifically, the electric chip 140 can be flip-chip welded on the front surface of the optical chip 110 through a TCB (Thermocompression Bonding) or FC (Flip Chip) process, and achieve face-to-face bonding with the optical chip 110. Since the electric chip 140 and the optical chip 110 can achieve face-to-face vertical interconnection, high-speed transmission can be achieved, meeting the demand of high-speed optical transmission and improving product performance. In the embodiment, the electrically conductive column 150 is arranged around the electric chip 140, and the electrically conductive column 150 is arranged apart from the light reflection layer 120. Specifically, the electric chip 140 can be multiple and be centrally bonded on the front surface of the optical chip 110, and the electrically conductive column 150 is multiple and arranged around the multiple electric chips 140. The specific number and distribution mode can be determined according to the circuit arrangement of the optical chip 110. And the electrically conductive column 150 is also arranged apart from the light reflection layer 120 to avoid affecting the light port structure 111.

[0043] It should be noted that the wafer-level semiconductor packaging structure 100 provided by the embodiment of the present application can also be mounted on a substrate or a PCB through an FC process, wherein the electrically conductive bump 151 on the electrically conductive column 150 can be welded on the substrate.

[0044] The embodiment of the present application also provides a preparation method of a wafer-level semiconductor packaging structure 100, which is used for preparing the wafer-level semiconductor packaging structure 100 described above, and the preparation method comprises the following steps: S1: providing a wafer with multiple optical chips 110.

[0045] For reference Figure 2 Each optical chip 110 is provided with a light port structure 111 and a light port groove 114, the light port structure 111 comprises a first optical surface 112 and a second optical surface 113, the first optical surface 112 is exposed to the front surface of the optical chip 110 and extends to the light port groove 114, and the second optical surface 113 can form a side wall of the light port groove 114 close to the light port structure 111.

[0046] It should be noted that one of the optical chips 110 is taken as an example to illustrate the whole process in the embodiment, and it can be understood that the wafer can be a PIC wafer (Photonic Integrated Circuit), which is formed with multiple optical chip 110 structures through a pre-process.

[0047] S2: Forming a protection layer 200 on the front surface of the optical chip 110 to cover the optical port structure 111 and the optical port groove 114.

[0048] Referring to Figure 3 Specifically, the protection layer 200 can be a polyimide material, and the protection layer 200 only covers the optical port structure 111 and the optical port groove 114, and exposes other areas of the front surface of the optical chip 110. In actual preparation of the protection layer 200, a multifunctional polyimide glue can be first filled on the front surface of the optical chip 110 and the optical port groove 114 by a gluing process to protect the optical port structure 111 and the optical port groove 114, and the glue material can only be affected by a special developer such as TMAH (Tetramethylammonium Hydroxide). Then a photoresist layer is processed and patterned on the area above the optical port structure 111 and the optical port groove 114 by a photolithography process, and the photoresist layer protects the underlying multifunctional polyimide glue from being removed by the developer. Then the polyimide layer outside the photoresist pattern is removed by a developing process using the developer. Finally, the photoresist is removed by a photolithography process, leaving the protection layer 200.

[0049] S3: Forming an optical reflection layer 120 on the protection layer 200.

[0050] Referring to Figure 4 The optical reflection layer 120 corresponds to the optical port structure 111. Specifically, the optical reflection layer 120 can be formed by deposition on the protection layer 200 and the front surface of the optical chip 110, and the optical reflection layer 120 can be a silicon dioxide layer. In actual preparation, the optical reflection layer 120 can be first formed by PECVD (Plasma Enhanced Chemical Vapor Deposition) process; then a photoresist pattern is processed on the area above the optical port structure 111 by a photolithography process, and the photoresist pattern protects the underlying optical reflection layer 120 from being removed by RIE (Reactive Ion Etching); finally, the areas except the pattern protected by the photoresist are removed by RIE etching process, and then the photoresist is removed to form the optical reflection layer 120 covering the protection layer 200. After the preparation of the optical reflection layer 120 is completed, a plastic encapsulation layer 130 can be prepared to cover at least the optical reflection layer 120 and the front surface of the optical chip 110, and the following steps can be performed.

[0051] S4: Forming a conductive pillar 150 on the front surface of the optical chip 110.

[0052] Referring to Figure 5Specifically, the conductive pillar 150 can be a copper pillar, and the conductive pillar 150 can be processed by a photoetching and electroplating process to have a height greater than the height of the light reflection layer 120, and correspond to the connection pads of the front surface of the light chip 110, so as to realize electrical conduction of the light chip 110. In addition, the conductive pillar 150 formed by the preparation can be used to form a mounting area.

[0053] S5: welding the electrical chip 140 to the front surface of the light chip 110.

[0054] Referring to Figure 6 Specifically, the electrical chip 140 can be welded to the PIC wafer by a TCB (Thermocompression Bonding) or FC (Flip Chip) process, that is, welded to the front surface of the light chip 110, so as to realize face-to-face vertical interconnection between the electrical chip 140 and the light chip 110.

[0055] S6: forming a plastic sealing layer 130 on the front surface of the light chip 110.

[0056] Referring to Figure 7 The plastic sealing layer 130 covers the conductive pillar 150, the electrical chip 140, the light reflection layer 120, and the front surface of the light chip 110. Specifically, a wafer-level plastic sealing process can be used to seal the wafer.

[0057] S7: thinning the plastic sealing layer 130 and exposing the conductive pillar 150.

[0058] Referring to Figure 8 Specifically, the plastic sealing layer 130 of the wafer can be thinned by a grinding process, and the copper pillar is exposed for subsequent processing. It should be noted that the height of the conductive pillar 150 can be the same as the height of the electrical chip 140, so that the back surface of the conductive pillar 150 and the electrical chip 140 can be exposed after grinding.

[0059] S8: forming a conductive bump 151 on the conductive pillar 150.

[0060] Referring to Figure 9 Specifically, the conductive bump 151 can be processed on the conductive pillar 150 by a photoetching and electroplating process, and the conductive bump 151 is used for welding with a PCB.

[0061] S9: thinning the wafer.

[0062] Referring to Figure 10 Specifically, the PIC wafer can be thinned by a grinding process, that is, the back surface of the light chip 110 is thinned.

[0063] S10: cutting the plastic sealing layer 130 to form a first cutout 300.

[0064] Referring to Figure 11 , the first cut 300 corresponds to the light port groove 114 and exposes the light reflection layer 120. Specifically, a wafer-level laser slotting process can be used to remove the encapsulant above the light reflection layer 120 and stop at the surface of the light reflection layer 120, forming the first cut 300. In actual production, the cutting position can be determined by pre-prepared alignment marks, and the first cut 300 is accurately aligned with the light port groove 114.

[0065] S11: Forming a second cut 400 by stealth dicing the optical chip 110.

[0066] Referring to Figure 12 , the second cut 400 corresponds to the light port groove 114 and exposes the protective layer 200. Specifically, a stealth dicing process is used to cut the bottom PIC wafer along the light port groove 114, thereby forming the second cut 400, which is aligned with the first cut 300 and can expose the protective layer 200 located in the light port groove 114.

[0067] Stealth dicing (SD) is an advanced wafer cutting technology mainly used to singulate chips on a wafer (i.e., cut into independent chips). Unlike traditional mechanical blade cutting or laser ablation cutting, it achieves separation in a "stealthy" way by forming a modified layer inside the wafer using infrared laser, and then separating the wafer along the modified layer through mechanical stretching, thermal stress or film expansion, etc., so that the chips are singulated, thereby significantly improving the strength, quality and production efficiency of the chips.

[0068] S12: Removing the protective layer 200 to form a reflection cavity 121 between the light reflection layer 120 and the first optical surface 112.

[0069] Referring to Figure 13 , specifically, through a developing process, a special developing solution is used to develop and remove the exposed multifunctional polyimide glue along the second cut 400, thereby forming a reflection cavity 121 with a side wall opening. The light reflection layer 120 is made above the reflection cavity 121 to reflect the light signal, so that the light signal can be directly conducted from the side after the subsequent process is completed, without the need to make complex optical structures, avoiding signal loss due to insufficient refractive index and light transmission rate of the optical structure.

[0070] S13: Breaking the light reflection layer 120 along the light port groove 114 through a splitting process.

[0071] Referring to Figure 14Specifically, the light reflection layer 120 can be processed again using the hidden cutting + split piece process, and specifically, the light reflection layer 120 can be disconnected using a film expansion method to prepare a single optical chip 110, and the process of the wafer-level semiconductor packaging structure 100 is completed.

[0072] Finally, the wafer-level semiconductor packaging structure 100 can be soldered on a PCB board or a substrate through an FC process.

[0073] In summary, the wafer-level semiconductor packaging structure 100 and the preparation method thereof provided by the embodiment of the present application are provided with an optical port structure 111 at one side edge of the optical chip 110, the first optical surface 112 of the optical port structure 111 is exposed to the front surface of the optical chip 110 and extends to the front surface edge of the optical chip 110. At the same time, the optical reflection corresponding to the first optical surface 112 is also provided on the front surface of the optical chip 110, the reflection cavity 121 is formed between the optical reflection layer 120 and the first optical surface 112, the reflection cavity 121 extends to the front surface edge of the optical chip 110, and the optical opening 122 is formed, the opening direction of the optical opening 122 is parallel to the front surface of the optical chip 110, that is, a side opening is formed. The plastic encapsulation layer 130 encapsulates the optical reflection layer 120, the optical reflection layer 120 can reflect the optical signal, and the optical signal transmission between the first optical surface 112 and the optical opening 122 is realized. Compared with the prior art, the wafer-level semiconductor packaging structure 100 and the preparation method thereof provided by the embodiment of the present application adopt a cavity structure with a side opening, and the optical reflection layer 120 is formed above the cavity to reflect the optical signal, so that the optical signal can be directly conducted from the side, and therefore a complex optical structure does not need to be made, the structure is simple, the manufacturing difficulty and processing cost are reduced, and the processing cycle is shortened. At the same time, the signal loss caused by the insufficient refractive index and light transmittance of the optical structure is also avoided, the transmission signal loss is reduced, and the transmission efficiency is improved. And the electrical chip 140 and the optical chip 110 can realize face-to-face vertical interconnection, so as to realize high-speed transmission, meet the demand of high-speed optical conduction, and improve the product performance. Second embodiment Referring to Figure 15 The wafer-level semiconductor packaging structure 100 provided by the embodiment of the present application has the same basic structure, principle, and technical effects as the first embodiment, and for brevity, the part not mentioned in this embodiment can refer to the corresponding content in the first embodiment.

[0074] The wafer-level semiconductor package structure 100 provided by the embodiment of the present application comprises an optical chip 110, an optical reflection layer 120, a plastic encapsulation layer 130, an electrical chip 140 and an interposer 160. The optical chip 110 is provided with an optical port structure 111 at one side edge thereof. The optical port structure 111 comprises a first optical surface 112. The first optical surface 112 is exposed to the front surface of the optical chip 110 and extends to the front surface edge of the optical chip 110. The optical reflection layer 120 is arranged on the front surface of the optical chip 110 and corresponds to the first optical surface 112. A reflection cavity 121 is formed between the optical reflection layer 120 and the first optical surface 112. The reflection cavity 121 extends to the front surface edge of the optical chip 110 and has an optical opening 122. The opening direction of the optical opening 122 is parallel to the front surface of the optical chip 110. The optical reflection layer 120 is configured to reflect optical signals. The plastic encapsulation layer 130 is arranged on the front surface of the optical chip 110 and encapsulates the optical reflection layer 120. The electrical chip 140 is arranged in the plastic encapsulation layer 130 and is electrically connected to the optical chip 110. The optical chip 110 and the electrical chip 140 are attached to one side surface of the interposer 160 and are electrically connected to the interposer 160. The plastic encapsulation layer 130 is arranged on one side surface of the interposer 160 and encapsulates the optical chip 110 and the electrical chip 140. The other side surface of the interposer 160 is provided with conductive bumps 151 which are electrically connected to the interposer 160.

[0075] In the embodiment, the interposer 160 is made of a high-density interconnection redistribution layer (RDL) which can realize high-density electrical interconnection between the electrical chip 140 and the optical chip 110. The electrical chip 140 and the optical chip 110 are attached to the interposer 160 at intervals, which can effectively reduce the package height.

[0076] Further, the front surface of the electrical chip 140 is provided with first micro-bumps 141 which are correspondingly soldered to one side surface of the interposer 160. The back surface of the electrical chip 140 is exposed to the plastic encapsulation layer 130. The front surface of the optical chip 110 is provided with second micro-bumps 115 which are correspondingly soldered to one side surface of the interposer 160. The back surface of the optical chip 110 is exposed to the plastic encapsulation layer 130. Specifically, the electrical chip 140 and the optical chip 110 can be soldered to the interposer 160 by TCB or FC process to realize soldering fixation and electrical interconnection. The plastic encapsulation layer 130 is arranged on the interposer 160 and protects the electrical chip 140 and the optical chip 110. The height of the electrical chip 140 and the optical chip 110 can be the same and they can be simultaneously exposed to the plastic encapsulation layer 130.

[0077] The embodiment of the present application further provides a preparation method of the wafer-level semiconductor package structure 100 for preparing the wafer-level semiconductor package structure 100 described above. The method comprises the following steps: S1: providing a wafer with a plurality of optical chips 110.

[0078] S2: Forming a protective layer 200 on the front surface of the optical chip 110 to cover the optical port structure 111 and the optical port groove 114.

[0079] S3: Forming an optical reflection layer 120 on the protective layer 200.

[0080] Wherein, the basic steps and process principles of steps S1 to S3 are the same as those of the first embodiment, and can be referred to the first embodiment for details.

[0081] S4: Cutting the wafer into multiple optical chips 110.

[0082] Referring to Figure 16 , specifically, the second micro-bump 115 can be first processed on the front surface of the optical chip 110 using photolithography and electroplating process, and the PIC wafer is cut into single pieces for soldering interconnection with the interposer 160. Mechanical cutting or laser cutting process can be used for cutting, and the cutting path needs to avoid the optical reflection layer 120. Wherein, the height of the second micro-bump 115 is greater than the protruding height of the optical reflection layer 120, which facilitates the subsequent encapsulation of the optical reflection layer 120 by the plastic sealing material.

[0083] S5: Forming an interposer 160 on the glass slide 600.

[0084] Referring to Figure 17 , specifically, the glass slide 600 can be used as a carrier, or other materials can be used as a carrier. A bonding glue layer can be coated on the surface of the glass slide 600, then a medium material is spin-coated, and a high-density interconnection redistribution layer (RDL) is formed.

[0085] S6: Soldering the optical chip 110 and the electrical chip 140 on the interposer 160.

[0086] Referring to Figure 18 , specifically, the TCB or FC process is used to mount the optical chip 110 and the electrical chip 140 on the interposer 160, wherein the first micro-bump 141 on the front surface of the electrical chip 140 is soldered on the interposer 160, and the second micro-bump 115 on the front surface of the optical chip 110 is soldered on the interposer 160, realizing fixed connection and electrical connection.

[0087] S7: Forming a plastic sealing layer 130 on the interposer 160.

[0088] Referring to Figure 19 , wherein the plastic sealing layer 130 encapsulates the optical reflection layer 120, the optical chip 110 and the electrical chip 140, and then the glass slide is polished to expose the optical chip 110 and the electrical chip 140. Specifically, the wafer is encapsulated by wafer-level encapsulation process, and the plastic sealing layer 130 can encapsulate the optical chip 110 and the electrical chip 140 inside, and fill the bottom area of the optical chip 110 and the electrical chip 140.

[0089] S8: Remove the glass substrate 600.

[0090] Referring to Figure 20 , specifically, the glass substrate 600 under the interposer 160 can be removed by debonding the bonding glue, so as to expose the surface of the interposer 160.

[0091] S9: Form conductive bumps 151 on the side of the interposer 160 away from the plastic package layer 130.

[0092] Referring to Figure 21 , specifically, after removing the glass substrate 600, the surface of the interposer 160 exposed can be processed to form conductive bumps 151 on the back of the redistribution layer by photolithography and electroplating process, for subsequent connection with the PCB or substrate.

[0093] S10: Cut the plastic package layer 130 to form a first cut 300.

[0094] Referring to Figure 22 , the first cut 300 corresponds to the light slot 114 and exposes the light reflection layer 120. Specifically, the wafer-level laser slotting process can be used to remove the plastic package and dielectric layer above the light reflection layer 120 and stop at the surface of the light reflection layer 120 to form the first cut 300. In actual production, the cutting position can be determined by pre-prepared alignment marks, and the first cut 300 is accurately aligned with the light slot 114.

[0095] S11: Form a second cut 400 by hidden cutting of the optical chip 110.

[0096] Referring to Figure 23 , the second cut 400 corresponds to the light slot 114 and exposes the protection layer 200. Specifically, the PIC wafer at the bottom is cut along the light slot 114 by hidden cutting process, thereby forming the second cut 400, which is aligned with the first cut 300 and can expose the protection layer 200 located in the light slot 114.

[0097] S12: Break the light reflection layer 120 along the light slot 114 by a breaking process.

[0098] Referring to Figure 24 , specifically, the light reflection layer 120 can be processed again by the hidden cutting + breaking process, and the light reflection layer 120 can be broken by using the film expansion method, thereby preparing a single optical chip 110 and completing the process of the wafer-level semiconductor package structure 100.

[0099] S13: Remove the protection layer 200 to form a reflection cavity 121 between the light reflection layer 120 and the first optical surface 112.

[0100] Please continue to see Figure 15 Specifically, by a developing process, the exposed multifunctional polyimide glue is removed by a special developing liquid along the developing direction, so as to form the side-wall-opened reflection cavity 121. The manufacturing sequence of the step S12 and the step S13 can be exchanged.

[0101] Finally, the wafer-level semiconductor packaging structure 100 can be welded on a PCB board or a substrate through an FC process.

[0102] In summary, the wafer-level semiconductor packaging structure 100 and the manufacturing method thereof provided by the embodiments of the present application adopt the cavity structure with the side-wall-opened cavity, the light reflection layer 120 is formed above the cavity to reflect the light signal, so that the light signal can be directly conducted from the side, and therefore, the complex optical structure does not need to be manufactured, the structure is simple, the manufacturing difficulty and the processing cost are reduced, and the processing period is shortened. Meanwhile, the signal loss caused by the insufficient refractive index and light transmittance of the optical structure is avoided, the transmission signal loss is reduced, and the transmission efficiency is improved. Furthermore, the electrical interconnection between the electrical chip 140 and the optical chip 110 is realized by the interposer 160, the wiring density is improved, and the packaging height is reduced.

[0103] Third embodiment Referring to Figure 25 The wafer-level semiconductor packaging structure 100 provided by the embodiments of the present application has the same basic structure, principle, and technical effects as the first embodiment, and for brief description, the part not mentioned in the present embodiment can refer to the corresponding content in the first embodiment.

[0104] The wafer-level semiconductor packaging structure 100 provided by the embodiments of the present application includes the optical chip 110, the light reflection layer 120, the plastic encapsulation layer 130, the electrical chip 140, the first redistribution layer 170, and the second redistribution layer 180. The optical chip 110 is provided with the optical port structure 111 at one side edge, and the optical port structure 111 includes the first optical surface 112. The first optical surface 112 is exposed to the front surface of the optical chip 110 and extends to the front surface edge of the optical chip 110. The light reflection layer 120 is arranged on the front surface of the optical chip 110 and corresponds to the first optical surface 112. The reflection cavity 121 is formed between the light reflection layer 120 and the first optical surface 112, extends to the front surface edge of the optical chip 110, and has the optical opening 122. The opening direction of the optical opening 122 is parallel to the front surface of the optical chip 110. The light reflection layer 120 is configured to reflect the light signal. The plastic encapsulation layer 130 is arranged on the front surface of the optical chip 110 and encapsulates the light reflection layer 120. The electrical chip 140 is arranged in the plastic encapsulation layer 130 and is electrically connected to the optical chip 110.

[0105] The first redistribution layer 170 is arranged on the front surface of the optical chip 110, the second redistribution layer 180 is arranged on the back surface of the optical chip 110, the first redistribution layer 170 and the second redistribution layer 180 are electrically connected, the electric chip 140 is attached to the first redistribution layer 170 and electrically connected with the first redistribution layer 170, the plastic encapsulation layer 130 is arranged on the front surface of the optical chip 110 and encapsulates the first redistribution layer 170 and the electric chip 140, and the second redistribution layer 180 is further provided with a conductive bump 151 on the side away from the first redistribution layer 170, and the conductive bump 151 is electrically connected with the second redistribution layer 180. Specifically, the first redistribution layer 170 and the second redistribution layer 180 are both high-density interconnection redistribution layers (RDL), and the first redistribution layer 170 can realize electrical interconnection between the electric chip 140 and the optical chip 110.

[0106] Further, the optical chip 110 is further provided with a conductive via hole 116 filled with a conductive material, and the first redistribution layer 170 is electrically connected with the second redistribution layer 180 through the conductive via hole 116. Specifically, the conductive via hole 116 can be a through-silicon via (TSV), and the conductive material can be copper, so that a copper column can be formed in the optical chip 110.

[0107] In the embodiment, the front surface of the electric chip 140 is provided with a first micro bump 141 corresponding to the first redistribution layer 170, and the back surface of the electric chip 140 is exposed to the plastic encapsulation layer 130. Specifically, the electric chip 140 can be attached on the first redistribution layer 170 through a TBC process or an FC process, and specifically, the first micro bump 141 can be welded on the corresponding pad of the first redistribution layer 170, so as to realize fixation and electrical connection.

[0108] The embodiment of the application further provides a preparation method of the wafer-level semiconductor packaging structure 100, which is used for preparing the wafer-level semiconductor packaging structure 100 described above, and the method comprises the following steps: S1: providing a wafer with a plurality of optical chips 110.

[0109] Each optical chip 110 is provided with an optical port structure 111 and an optical port groove 114, the optical port structure 111 comprises a first optical surface 112, the first optical surface 112 is exposed to the front surface of the optical chip 110 and extends to the optical port groove 114. Further, the TSV conductive via hole 116 is made inside the optical chip 110, and the conductive via hole 116 is filled with a conductive material. The conductive via hole 116 is arranged separately from the optical port structure 111.

[0110] S2: forming a protective layer 200 covering the optical port structure 111 and the optical port groove 114 on the front surface of the optical chip 110.

[0111] Specifically, the protective layer 200 can be a polyimide material, and the protective layer 200 only covers the optical port structure 111 and the optical port groove 114, and exposes other areas of the front surface of the optical chip 110.

[0112] S3: Forming the light reflection layer 120 on the protective layer 200.

[0113] The light reflection layer 120 corresponds to the optical port structure 111. The light reflection layer 120 can be formed by deposition on the protective layer 200 and the front surface of the optical chip 110, and the light reflection layer 120 can be a silicon dioxide layer.

[0114] S4: Forming the first RDL layer 170 on the front surface of the optical chip 110.

[0115] Referring to Figure 26 , specifically, the RDL layer is fabricated on the surface of the PIC wafer by photolithography and electroplating process, so as to form the first RDL layer 170 on the front surface of the optical chip 110, wherein the first RDL layer 170 has a certain gap with the light reflection layer 120, and can cover the conductive via 116 and realize electrical interconnection with the conductive via 116.

[0116] S5: Thinning the back surface of the optical chip 110 and exposing the conductive via 116.

[0117] Referring to Figure 27 , specifically, in actual preparation, a temporary glass slide 600 can be first attached to the front surface of the optical chip 110 by bonding process, and then the wafer is flipped and polished by grinding and CMP chemical mechanical polishing process to thin the wafer, that is, to thin the back surface of the optical chip 110, until the copper column in the conductive via 116 is exposed.

[0118] S6: Forming the second RDL layer 180 on the back surface of the optical chip 110.

[0119] Referring to Figure 28 , wherein the second RDL layer 180 is electrically connected to the first RDL layer 170 through the conductive via 116. Specifically, the RDL layer can be processed on the surface of the wafer again by photolithography and electroplating process to form the second RDL layer 180, wherein the second RDL layer 180 is electrically interconnected with the first RDL layer 170 through the conductive via 116.

[0120] S7: Forming the conductive bump 151 on the second RDL layer 180.

[0121] Referring to Figure 29 , specifically, the conductive bump 151 can be formed on the second RDL layer 180 again by photolithography and electroplating process, which is electrically interconnected with the second RDL layer 180 and used for connection with the PCB board or substrate.

[0122] Further, after the preparation of the conductive bump 151 is completed, a temporary other glass slide 600 can be bonded to the back of the PIC wafer by a bonding process, and then the glass slide 600 can be detached by a debonding process.

[0123] S8: The electrical chip 140 is welded on the first redistribution layer 170.

[0124] Referring to Figure 30 , specifically, the first micro bump 141 on the front of the electrical chip 140 can be welded on the pad on the surface of the first redistribution layer 170 by a TCB or FC process.

[0125] S9: The molding layer 130 is formed on the front of the optical chip 110.

[0126] Referring to Figure 31 , wherein the molding layer 130 covers the electrical chip 140, the first redistribution layer 170 and the light reflection layer 120. Specifically, the wafer is molded by a wafer-level molding process, so that the molding layer 130 can completely cover the first redistribution layer 170, the light reflection layer 120 and the electrical chip 140, and then the molding layer 130 is thinned by a grinding process to expose the back of the electrical chip 140, and the other glass slide 600 on the back of the wafer is detached by a debonding process.

[0127] S10: The molding layer 130 is cut to form a first cutout 300.

[0128] Referring to Figure 32 , wherein the first cutout 300 corresponds to the light slot 114 and exposes the light reflection layer 120. Specifically, the wafer-level laser slotting process can be used to remove the molding material above the light reflection layer 120 and stop on the surface of the light reflection layer 120 to form the first cutout 300.

[0129] S11: The second cutout 400 is formed by hidden cutting of the optical chip 110.

[0130] Referring to Figure 33 , wherein the second cutout 400 corresponds to the light slot 114 and exposes the protection layer 200. The PIC wafer at the bottom is cut along the light slot 114 by a hidden cutting process to form the second cutout 400, which is aligned with the first cutout 300 and can expose the protection layer 200 in the light slot 114.

[0131] S12: The light reflection layer 120 is broken along the light slot 114 by a cracking process.

[0132] Referring to Figure 34Specifically, the light reflection layer 120 can be processed again using the process of hidden cutting + split piece, and specifically, the light reflection layer 120 can be disconnected by using the film expansion method, so as to prepare a single optical chip 110.

[0133] S13: The protective layer 200 is removed to form a reflection cavity 121 between the light reflection layer 120 and the first optical surface 112.

[0134] Please continue to see Figure 25 Specifically, by the developing process, the exposed multifunctional polyimide glue is developed and removed by using a special developing solution, so as to form a side wall opening reflection cavity 121.

[0135] Wherein, the sequence of steps S12 and S13 can be exchanged.

[0136] Finally, the wafer level semiconductor packaging structure 100 can be welded on the PCB board or the substrate by the FC process.

[0137] In summary, the wafer level semiconductor packaging structure 100 and the preparation method thereof provided by the embodiment of the present application adopt the cavity structure with the side wall opening, the light reflection layer 120 is formed above the cavity to reflect the light signal, so that the light signal can be directly conducted from the side, and therefore, a complex optical structure does not need to be made, the structure is simple, the manufacturing difficulty and the processing cost are reduced, and the processing cycle is shortened. At the same time, the signal loss caused by the insufficient refractive index and light transmittance of the optical structure is also avoided, the transmission signal loss is reduced, and the transmission efficiency is improved. And the first redistribution layer 170 and the second redistribution layer 180 are adopted, so that the wiring density is improved, and the integration of the electrical chip 140 is higher. At the same time, the first redistribution layer 170 and the second redistribution layer 180 are electrically connected through the conductive via hole 116, the signal transmission path is shortened, the transmission efficiency is improved, and the packaging integration is further improved.

[0138] The above is only a specific embodiment of the present application, but the protection scope of the present application is not limited thereto, any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A wafer-level semiconductor packaging structure, characterized in that, include: An optical chip has an optical port structure on one side edge. The optical port structure includes a first optical surface, which is exposed on the front side of the optical chip and extends to the edge of the front side of the optical chip. A light-reflecting layer is disposed on the front side of the optical chip and corresponds to the first optical surface. A reflective cavity is formed between the light-reflecting layer and the first optical surface. The reflective cavity extends to the edge of the front side of the optical chip and has an optical opening. The opening direction of the optical opening is parallel to the front side of the optical chip. The light-reflecting layer is configured to reflect light signals. A molding layer is disposed at least on the front side of the optical chip and covers the light-reflecting layer.

2. The wafer-level semiconductor packaging structure according to claim 1, characterized in that, The optical port structure further includes a second optical surface, which is disposed adjacent to the first optical surface and exposed on the sidewall of the optical chip. The optical opening is connected to the second optical surface.

3. The wafer-level semiconductor packaging structure according to claim 2, characterized in that, The front edge of the optical chip also has an optical slot, which is connected to the optical opening, and the second optical surface is configured to form the sidewall of the optical slot.

4. The wafer-level semiconductor packaging structure according to claim 1, characterized in that, The wafer-level semiconductor packaging structure also includes an electrical chip, which is disposed within the molding layer and electrically connected to the optical chip.

5. The wafer-level semiconductor packaging structure according to claim 4, characterized in that, The electrical chip is disposed on the front side of the optical chip and is electrically connected to the optical chip. The front side of the optical chip is also provided with conductive pillars. The molding compound is disposed on the front side of the optical chip and covers the electrical chip and the conductive pillars. The end of the conductive pillar away from the optical chip is exposed to the molding compound and is provided with conductive bumps. The conductive bumps are electrically connected to the optical chip through the conductive pillars.

6. The wafer-level semiconductor packaging structure according to claim 5, characterized in that, The front side of the electrical chip is provided with a first microbump, which is soldered to the front side of the optical chip, and the back side of the electrical chip is exposed to the molding compound.

7. The wafer-level semiconductor packaging structure according to claim 5, characterized in that, The conductive pillars are arranged around the electrical chip, and the conductive pillars are spaced apart from the light-reflecting layer.

8. The wafer-level semiconductor packaging structure according to claim 4, characterized in that, The wafer-level semiconductor packaging structure further includes an interposer layer. The optical chip and the electrical chip are mounted on one side surface of the interposer layer and electrically connected to the interposer layer. The molding compound layer is disposed on one side surface of the interposer layer and covers the optical chip and the electrical chip. The other side surface of the interposer layer is provided with conductive bumps, which are electrically connected to the interposer layer.

9. The wafer-level semiconductor packaging structure according to claim 8, characterized in that, The front side of the electrical chip has a first microbump, which is soldered to one side of the interposer layer, and the back side of the electrical chip is exposed to the molding compound layer; the front side of the optical chip has a second microbump, which is soldered to one side of the interposer layer, and the back side of the optical chip is exposed to the molding compound layer.

10. The wafer-level semiconductor packaging structure according to claim 4, characterized in that, The wafer-level semiconductor packaging structure further includes a first super-wiring layer and a second super-wiring layer. The first super-wiring layer is disposed on the front side of the optical chip, and the second super-wiring layer is disposed on the back side of the optical chip. The first super-wiring layer and the second super-wiring layer are electrically connected. The electrical chip is mounted on the first super-wiring layer and is electrically connected to the first super-wiring layer. The molding compound is disposed on the front side of the optical chip and covers the first super-wiring layer and the electrical chip. A conductive bump is also disposed on the side of the second super-wiring layer away from the first super-wiring layer. The conductive bump is electrically connected to the second super-wiring layer.

11. The wafer-level semiconductor packaging structure according to claim 10, characterized in that, The optical chip is also provided with conductive vias, which are filled with conductive material, and the first redistribution layer is electrically connected to the second redistribution layer through the conductive vias.

12. The wafer-level semiconductor packaging structure according to claim 10, characterized in that, The front side of the electrical chip is provided with a first microbump, which is soldered to the first redistribution layer, and the back side of the electrical chip is exposed to the molding compound layer.

13. A method for fabricating a wafer-level semiconductor packaging structure, used to fabricate the wafer-level semiconductor packaging structure as described in claim 1, characterized in that, The method includes: A wafer having a plurality of optical chips is provided, wherein each of the optical chips is provided with an optical port structure and an optical port slot, the optical port structure including a first optical surface exposed on the front side of the optical chip and extending to the optical port slot; A protective layer is formed on the front side of the optical chip, covering the optical port structure and the optical port groove; A light-reflecting layer is formed on the protective layer, wherein the light-reflecting layer corresponds to the optical port structure; Prepare a molding compound that at least covers the light-reflecting layer and the front side of the optical chip; A first cut is formed by cutting the molding layer, wherein the first cut corresponds to the optical slot and exposes the light-reflecting layer; A second cut is formed by slicing the optical chip, wherein the second cut corresponds to the optical port slot and exposes the protective layer; Remove the protective layer to form a reflective cavity between the light-reflecting layer and the first optical surface; The light-reflecting layer is broken along the light aperture groove using a slicing process.

14. The method for fabricating a wafer-level semiconductor packaging structure according to claim 13, characterized in that, The step of preparing a molding compound layer that at least covers the light-reflecting layer and the front side of the optical chip includes: Conductive pillars are formed on the front side of the optical chip; The electrical chip is soldered to the front side of the optical chip; A molding compound is formed on the front side of the optical chip, wherein the molding compound covers the conductive pillar, the electrical chip, the light reflective layer, and the front side of the optical chip; Thin the molding layer and expose the conductive pillars; Conductive bumps are formed on the conductive pillars.

15. The method for fabricating a wafer-level semiconductor packaging structure according to claim 13, characterized in that, The step of preparing a molding compound layer that at least covers the light-reflecting layer and the front side of the optical chip includes: The wafer is cut into multiple optical chips; An intermediate layer is formed on the glass slide; The optical chip and the electrical chip are soldered onto an interlayer; A molding layer is formed on the interlayer, wherein the molding layer encapsulates the light-reflecting layer, the optical chip, and the electrical chip; Remove the glass slide; Conductive bumps are formed on the side of the interlayer away from the molding layer.

16. The method for fabricating a wafer-level semiconductor packaging structure according to claim 13, wherein the optical chip has conductive vias internally, and the conductive vias are filled with conductive material, characterized in that, Before the step of preparing a molding compound layer that at least covers the light-reflecting layer and the front side of the optical chip, the method further includes: A first overlay layer is formed on the front side of the optical chip; Thin the back side of the optical chip to expose the conductive via; A second wiring layer is formed on the back side of the optical chip, wherein the second wiring layer is electrically connected to the first wiring layer through the conductive via. Conductive bumps are formed on the second redistribution layer.

17. The method for fabricating a wafer-level semiconductor packaging structure according to claim 16, characterized in that, The step of preparing a molding compound layer that at least covers the light-reflecting layer and the front side of the optical chip includes: The electrical chip is soldered onto the first wiring layer; A molding compound is formed on the front side of the optical chip, wherein the molding compound covers the electrical chip, the first redistribution layer, and the light-reflecting layer.

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