Hardware circulation system and method, electronic equipment and storage medium

Abstract

The invention discloses a hardware circulation system and method, electronic equipment and a storage medium. The system comprises an instruction decoding unit, a circulation control unit, an instruction storage unit, a pipeline control unit and a context saving unit. The instruction decoding unit is used for decoding a program instruction, identifying a hardware loop instruction and decoding an instruction in a loop body defined by the hardware loop instruction to obtain a micro-operation signal. The loop control unit is used for managing execution of a loop body defined by a hardware loop instruction according to the hardware loop instruction. The instruction storage unit is used for receiving and storing the micro-operation signal. And the pipeline control unit is used for providing the micro-operation signal stored by the instruction storage unit to the execution unit. And the context storage unit is used for storing the key parameters of the loop control unit when the execution process of the loop body is interrupted, and the loop control unit continues to manage the execution of the loop body based on the key parameters after the interruption is returned.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of loop operation, and in particular to a hardware loop system and method, an electronic device and a storage medium. BACKGROUND

[0002] In embedded microcontroller and digital signal processor applications, algorithm loops and control loops exist widely. Such loops are currently implemented in software, i.e. through conditional jump instructions to control iteration. However, this implementation has significant defects: each loop iteration needs to perform a jump, resulting in the processor instruction pipeline being emptied, causing several clock cycle delays, i.e. jump penalty, which seriously reduces instruction execution efficiency and processor real-time performance. In addition, software loops need additional instructions to manage loop count and condition judgment, increasing instruction overhead, and their execution time is difficult to predict due to jump delay, which cannot meet the requirements of high real-time systems. SUMMARY

[0003] The present application aims to provide a hardware loop system and method, an electronic device and a storage medium, which can improve the real-time performance of loop operation.

[0004] In a first aspect, an embodiment of the present application provides a hardware loop system, comprising: an instruction decoding unit, configured to decode program instructions and identify a hardware loop instruction, and decode instructions in a loop body defined by the hardware loop instruction to obtain micro-operation signals; a loop control unit, connected with the instruction decoding unit, configured to, when the instruction decoding unit identifies the hardware loop instruction, manage execution of the loop body defined by the hardware loop instruction according to the hardware loop instruction; an instruction storage unit, connected with the loop control unit, configured to receive and store the micro-operation signals; a pipeline control unit, connected with the loop control unit, configured to, under control of the loop control unit, provide the micro-operation signals stored in the instruction storage unit to the execution unit; a context saving unit, connected with the loop control unit, configured to, in the case of an interruption occurring in the execution process of the loop body, save key parameters of the loop control unit, and after interruption return, the loop control unit continues to manage execution of the loop body based on the key parameters saved by the context saving unit; wherein the key parameters include starting address information, loop end address information, loop program count information and remaining loop count information of the loop body.

[0005] According to some embodiments of the present application, the loop control unit comprises: a loop control counter connected to the instruction decoding unit, the loop control counter being configured to store the number of iterations of the loop body and count after each iteration of the loop body is completed; a loop start address register connected to the instruction decoding unit, the loop start address register being configured to store the start instruction address of the loop body; a loop end address register connected to the instruction decoding unit, the loop end address register being configured to store the end instruction address of the loop body; a loop program counter configured to track and update the instruction address currently executed by the loop body during execution of the loop body.

[0006] According to some embodiments of the present application, the instruction storage unit comprises: a single instruction latch connected to the loop control unit; an instruction buffer connected to the loop control unit.

[0007] According to some embodiments of the present application, the context saving unit comprises: a hardware stack connected to the loop control unit.

[0008] According to some embodiments of the present application, the pipeline control unit is connected to the instruction decoding unit.

[0009] In a second aspect, embodiments of the present application provide a hardware loop control method, applied to the hardware loop system as described above, the method comprising: decoding and identifying a hardware loop instruction by an instruction decoding unit; decoding instructions in a loop body defined by the hardware loop instruction to obtain micro-operation signals; when the instruction decoding unit identifies the hardware loop instruction, managing execution of the loop body defined by the hardware loop instruction by a loop control unit according to the hardware loop instruction; receiving and storing the micro-operation signals by an instruction storage unit; under control of the loop control unit, providing the micro-operation signals stored by the instruction storage unit to an execution unit by a pipeline control unit; In the case that an interruption occurs in the execution process of the loop body, the critical parameters of the loop control unit are saved by a context saving unit, and after the interruption is returned, the execution of the loop body is continued by the loop control unit based on the critical parameters saved by the context saving unit; wherein the critical parameters include the start address information, the loop end address information, the loop program count information and the remaining loop count information of the loop body.

[0010] According to some embodiments of the present application, the continuing to manage the execution of the loop body based on the critical parameters saved by the context saving unit comprises: re-fetching and decoding the instructions of the loop body according to the start address information, to regenerate micro-operation signals in the instruction storage unit; continuing to execute the loop body based on the regenerated micro-operation signals, the loop end address information, the remaining loop count information and the loop program count information.

[0011] According to some embodiments of the present application, in the case that the loop control unit does not control the pipeline control unit to provide the micro-operation signals stored in the instruction storage unit to the execution unit, the pipeline control unit is configured to provide the micro-operation signals decoded by the instruction decoding unit in real time to the execution unit.

[0012] In a third aspect, embodiments of the present application provide an electronic device, comprising: at least one processor; at least one memory configured to store at least one program; when at least one of the programs is executed by at least one of the processors, the hardware loop control method as described above is implemented.

[0013] In a fourth aspect, embodiments of the present application provide a computer readable storage medium, wherein the computer readable storage medium stores a program executable by a processor, and the program executable by the processor is configured to implement the hardware loop control method as described above when executed by the processor.

[0014] In this embodiment, the hardware loop instruction is identified and the loop body is decoded by the instruction decoding unit, and the resulting micro-operation signals are cached in the instruction storage unit. Under the management of the loop control unit, the pipeline control unit directly provides micro-operation signals from the instruction storage unit to the execution unit, thereby completely avoiding the program jumps required by traditional software loops and the pipeline flushing problems caused by them in subsequent iterations of the loop, significantly improving instruction execution efficiency and real-time response capability. In addition, the context saving unit saves only key parameters, including the start address information of the loop body, the end address information of the loop, the loop program count information, and the remaining loop count information, when an interrupt occurs. After the interrupt returns, the loop state is restored based on the key parameters. With almost no increase in hardware overhead, the hardware loop can reliably cooperate with the interrupt handling mechanism, which can meet the needs of high real-time application scenarios such as embedded real-time control.

[0015] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0016] The present application will be further described below with reference to the accompanying drawings and embodiments, wherein: Fig. 1 Functional block diagram of an embodiment of the hardware loop system provided in this application; Fig. 2 A flowchart illustrating an embodiment of the hardware loop control method provided in this application; Fig. 3 A schematic diagram of an embodiment of the electronic device provided in this application.

[0017] Figure label: Instruction decoding unit 100, loop control unit 200, instruction storage unit 300, pipeline control unit 400, context storage unit 500, program memory 600, instruction fetch unit 700, multiplexer 800, execution unit 900, electronic device 910, processor 920, and memory 930. Detailed Implementation

[0018] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0019] In the description of this application, it should be understood that the orientation descriptions, such as up, down, etc., are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0020] In the description of this application, "multiple" refers to two or more. The use of "first" and "second" is for the purpose of distinguishing technical features only and should not be construed as indicating or implying relative importance, or implicitly indicating the number of technical features indicated, or the order in which the technical features are indicated.

[0021] In the description of this application, unless otherwise expressly defined, terms such as "setup," "installation," and "connection" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this application in conjunction with the specific content of the technical solution.

[0022] The following is based on Figs. 1 to 3 This application describes a hardware loop system, method, electronic device, and storage medium provided in its embodiments.

[0023] This application provides a hardware loop system, such as Fig. 1 As shown, it includes: The instruction decoding unit 100 is used to decode program instructions and identify hardware loop instructions, as well as to decode instructions within the loop body defined by the hardware loop instructions to obtain micro-operation signals. A loop control unit 200 is connected to an instruction decoding unit 100. The loop control unit 200 is used to manage the execution of the loop body defined by the hardware loop instruction when the instruction decoding unit 100 recognizes the hardware loop instruction. The instruction storage unit 300 is connected to the loop control unit 200 and is used to receive and store micro-operation signals. The pipeline control unit 400 is connected to the loop control unit 200. Under the control of the loop control unit 200, the pipeline control unit 400 provides the micro-operation signals stored in the instruction storage unit 300 to the execution unit 900. The context saving unit 500 is connected to the loop control unit 200. The context saving unit 500 is used to save the key parameters of the loop control unit 200 when the execution of the loop body is interrupted. After the interruption is returned, the loop control unit 200 continues to manage the execution of the loop body based on the key parameters saved by the context saving unit 500. The key parameters include the start address information of the loop body, the end address information of the loop, the loop program count information, and the remaining number of loops information.

[0024] In this embodiment, the instruction decoding unit 100 identifies the hardware loop instruction and decodes the loop body, and caches the obtained micro-operation signals in the instruction storage unit 300. Under the management of the loop control unit 200, the pipeline control unit 400 directly provides micro-operation signals from the instruction storage unit 300 to the execution unit 900, thereby completely avoiding the program jumps required by traditional software loops and the pipeline clearing problems caused by them in subsequent iterations of the loop, significantly improving instruction execution efficiency and real-time response capability. In addition, the context saving unit 500 saves only key parameters, including the start address information of the loop body, the end address information of the loop, the loop program count information, and the remaining loop count information, when an interrupt occurs. After the interrupt returns, the loop state is restored based on the key parameters. Without increasing hardware overhead, the hardware loop can reliably cooperate with the interrupt handling mechanism, which can meet the needs of high real-time application scenarios such as embedded real-time control.

[0025] In some embodiments of this application, the instruction decoding unit 100 is used to receive and decode program instruction streams, identify two specific types of hardware loop instructions: single instruction loop instructions and block loop instructions, decode the instructions inside the loop body defined by the hardware loop instructions, and output the corresponding micro-operation signals.

[0026] The loop control unit 200 is activated when the instruction decoding unit 100 recognizes a hardware loop instruction, and initializes the loop parameters according to the operands of the hardware loop instruction in order to manage the execution of the loop body defined by the hardware loop instruction.

[0027] During system operation, instructions are read from program memory 600 and sent to instruction decoding unit 100. For non-hardware loop instructions, the micro-operation signals generated by their decoding are directly sent to execution unit 900 via pipeline control unit 400. When instruction decoding unit 100 recognizes a hardware loop instruction, loop control unit 200 is activated and takes over control. During the first execution of the loop instruction, the micro-operation signals generated by its decoding are sent to execution unit 900 and stored in instruction memory unit 300. Starting from the second iteration of the loop, loop control unit 200 controls pipeline control unit 400 to directly provide the micro-operation signals cached in instruction memory unit 300 to execution unit 900 for execution until the loop ends, thereby avoiding pipeline cleanup caused by program jumps.

[0028] In some embodiments of this application, an instruction fetching unit 700 is also included. The instruction fetching unit 700 is connected to the program memory 600 and the instruction decoding unit 100, respectively. The instruction fetching unit 700 reads instructions from the program memory 600 and sends them to the instruction decoding unit 100.

[0029] When the execution of the loop body is interrupted, after completing the current instruction, the loop control unit 200 saves the key parameters to the context save unit 500. After the interruption returns, the loop control unit 200 restores the key parameters from the context save unit 500 and restarts the execution of the loop body based on the restored start address. At the same time, it manages the completion of the loop based on the restored loop end address information, loop program count information, and remaining loop count information.

[0030] In some embodiments of this application, the cycle control unit 200 includes: A loop control counter is connected to the instruction decoding unit 100. The loop control counter is used to store the number of iterations of the loop body and counts after each iteration of the loop body is completed. The loop start address register is connected to the instruction decoding unit 100 and is used to store the starting instruction address of the loop body. The loop end address register is connected to the instruction decoding unit 100 and is used to store the address of the end instruction of the loop body. The loop program counter is used to track and update the address of the currently executing instruction in the loop body during the execution of the loop body.

[0031] In this embodiment, the loop control counter is responsible for precisely managing the number of loop iterations, while the loop start address register and loop end address register define the instruction boundaries of the loop body. The loop program counter tracks the execution progress within the loop body in real time, thereby enabling precise and efficient management of the loop execution state. This allows the start, iteration, and termination of the loop to be completely controlled automatically by the hardware, thus completely eliminating the instruction overhead and pipeline penalties caused by condition judgments and address jumps in traditional software loops at the hardware level, significantly improving the determinism and efficiency of loop execution.

[0032] In some embodiments of this application, when the instruction decoding unit 100 decodes a single instruction loop instruction, its operand (i.e., the loop count) is loaded into the loop control counter; when decoding a block loop instruction, its second operand (i.e., the loop count) is loaded into the loop control counter. During loop execution, the loop control counter is automatically decremented after each complete loop iteration.

[0033] For single-instruction loop instructions, the address of the next instruction is loaded into the loop start address register. For block loop instructions, the address of the next instruction is loaded into the loop start address register, serving as the starting address of the loop body.

[0034] When decoding a block loop instruction, its first operand (i.e., the loop end address) is loaded into the loop end address register, which, together with the loop start address register, defines the instruction boundary of the loop body.

[0035] The loop program counter is used to track the current execution progress in real time during the execution of the loop body. For block loop instructions, at the beginning of the loop, the address in the loop start address register is loaded into the loop program counter, and the value of the loop program counter increments as the instruction is executed.

[0036] The loop control unit 200 provides precise state management for different types of hardware loop instructions: single-instruction loop instructions achieve efficient single-instruction repetition through the loop control counter and single-instruction address; block loop instructions achieve precise loop control of instruction blocks through the loop control counter, loop start address register, loop end address register, and loop program counter. All loop state progression and judgment are automatically completed by hardware, eliminating the overhead of software intervention.

[0037] In some embodiments of this application, the instruction storage unit 300 includes: A single instruction latch is connected to the loop control unit 200; The instruction buffer is connected to the loop control unit 200.

[0038] In this embodiment, the single instruction latch is used for single instruction loop instructions to latch and repeatedly supply micro-operations of a single instruction at extremely low hardware cost; the instruction buffer is used for block loop instructions to provide sequential caching and pipelined output of micro-operations for multiple instruction sequences within the loop, thereby enabling adaptive resource allocation according to the loop size. After the first execution of the loop, the micro-operations can be directly read from the corresponding cache unit, completely eliminating the overhead of repeated instruction fetching and decoding in subsequent iterations. This ensures that whether it is a single instruction fast repetition or a multi-instruction block loop, the core execution path can be efficiently decoupled from the front-end instruction fetching and decoding pipeline, thereby achieving zero-overhead loop control and extremely high instruction execution efficiency.

[0039] In some embodiments of this application, when the instruction decoding unit 100 decodes and identifies a single-instruction loop instruction, the micro-operation signal generated after the next instruction is decoded is captured and stored in the single-instruction latch during the first execution. When the instruction decoding unit 100 decodes and identifies a block loop instruction, during the first execution of the loop body, the micro-operation signals generated after decoding each instruction in the loop body are sequentially stored in the instruction buffer according to the execution order. During subsequent iterations of the loop body, the loop control unit 200 controls the pipeline control unit 400 to select the output of the instruction storage unit 300. For single-instruction loop instructions, the micro-operation signals latched in the single-instruction latch are repeatedly provided to the execution unit 900; for block loop instructions, the sequence of micro-operation signals buffered in the instruction buffer is sequentially and cyclically provided to the execution unit 900.

[0040] In some embodiments of this application, the context saving unit 500 includes: The hardware stack is connected to the loop control unit 200.

[0041] In this embodiment, the context saving unit 500 includes a hardware stack. The hardware stack, with its dedicated storage structure and hardware control logic, implements automatic push and pop operations for key parameters of the loop. When an interrupt occurs, the key parameters of the current hardware loop are automatically pushed onto the stack; upon interrupt return, the key parameters are precisely restored to the loop control unit 200 via a pop operation. The last-in-first-out (LIFO) storage structure of the hardware stack ensures that, in multi-level nested interrupt scenarios, the state of each interrupted hardware loop can be independently and completely saved and restored. This not only eliminates the corresponding software overhead and latency in traditional methods but also fundamentally guarantees the reliability and timing determinism of the hardware loop's response to interrupts during execution, thereby significantly enhancing real-time processing capabilities.

[0042] In some embodiments of this application, the pipeline control unit 400 is connected to the instruction decoding unit 100.

[0043] In this embodiment, the system can switch between a normal execution mode and a hardware loop mode. When the hardware loop is not being executed or is in the first iteration of the loop, the micro-operation signals generated by the real-time decoding of the instruction decoding unit 100 can be normally delivered to the execution unit 900 through the pipeline control unit 400, thereby maintaining the continuity of the processor's basic instruction execution flow. At the same time, the loop control unit 200 can precisely control the selection of the micro-operation signal source by the pipeline control unit 400 according to the loop execution state: either selecting the real-time decoding output of the instruction decoding unit 100 to process new instructions and initialize the loop, or switching to selecting the cached micro-operation signals in the instruction storage unit 300 to achieve efficient repeated execution of the loop body.

[0044] In some embodiments of this application, a multiplexer 800 is also included. The first input of the multiplexer 800 is connected to the output of the instruction decoding unit 100 to receive micro-operation signals decoded in real time. The second input of the multiplexer 800 is connected to the output of the instruction storage unit 300 to receive buffered micro-operation signals. The output of the multiplexer 800 is directly connected to the execution unit 900. The selection control terminal of the multiplexer 800 is connected to the pipeline control unit 400, which sends corresponding gating logic signals to the selection control terminal based on the status instructions issued by the loop control unit 200. During system operation, when the first iteration of a regular program or hardware loop needs to be executed, the pipeline control unit 400 drives the multiplexer 800 to select its first input, so that the micro-operation signal generated by real-time decoding is sent to the execution unit 900. When the subsequent iteration of the hardware loop needs to be executed, the pipeline control unit 400 drives the multiplexer 800 to switch and select its second input, so that the micro-operation signal cached in the instruction storage unit 300 is sent to the execution unit 900. Thus, it works in coordination with the control logic of the pipeline control unit 400 to realize efficient and seamless switching between different execution modes of the hardware loop system.

[0045] In addition, embodiments of this application provide a hardware loop control method, applied to the hardware loop system described above, such as... Fig. 2 As shown, the method includes: Step S100: The program instructions are decoded by the instruction decoding unit 100 and the hardware loop instructions are identified; Step S200: Decode the instructions within the loop body defined by the hardware loop instruction to obtain the micro-operation signal; Step S300: When the instruction decoding unit 100 recognizes the hardware loop instruction, the loop control unit 200 manages the execution of the loop body defined by the hardware loop instruction according to the hardware loop instruction; Step S400: Receive and store micro-operation signals through instruction storage unit 300; Step S500: Under the control of the loop control unit 200, the micro-operation signals stored in the instruction storage unit 300 are provided to the execution unit 900 through the pipeline control unit 400; Step S600: If the execution of the loop body is interrupted, the key parameters of the loop control unit 200 are saved through the context saving unit 500; Step S700: After returning from the interrupt, the loop control unit 200 continues to manage the execution of the loop body based on the key parameters saved by the context saving unit 500; wherein, the key parameters include the start address information of the loop body, the end address information of the loop, the loop program count information, and the remaining loop count information.

[0046] The method embodiments provided in this application can implement the various processes implemented in the above system embodiments and achieve the same beneficial effects. To avoid repetition, they will not be described again here.

[0047] In some embodiments of this application, the step S700 of "continuing to manage the execution of the loop body based on the key parameters saved by the context saving unit 500" is further explained. Step S700 includes: Step S710: Based on the starting address information, fetch the instruction again and decode the loop body instruction to regenerate the micro-operation signal in the instruction storage unit 300; Step S720: Based on the regenerated micro-operation signal, loop end address information, loop program count information, and remaining loop count information, continue executing the loop body.

[0048] In this embodiment, the instruction fetch and decode operations are first re-initiated based on the saved loop start address, thereby re-caching the micro-operation information in the instruction storage unit 300. Then, the system determines the execution boundary of the loop body based on the restored loop end address information and locates the precise breakpoint within the loop body based on the loop program count information. Subsequently, the system automatically resumes the interrupted loop execution process based on the synchronously restored remaining loop count information, ensuring that after responding to any interruption, it can accurately return to the precise breakpoint and correct context of the loop execution. This not only completely eliminates the performance overhead and time uncertainty of traditional software methods, but also ensures the integrity and real-time performance of the loop execution sequence with pure hardware logic, thereby achieving reliable and efficient coordination between loop execution and interrupt handling at the hardware level.

[0049] In some embodiments of this application, when the loop control unit 200 does not control the pipeline control unit 400 to provide the micro-operation signals stored in the instruction storage unit 300 to the execution unit 900, the pipeline control unit 400 is used to provide the micro-operation signals generated by the instruction decoding unit 100 in real time to the execution unit 900.

[0050] In this embodiment, when the loop control unit 200 is inactive, i.e., no hardware loop instruction is detected or a completed loop has not started a new iteration, the loop control unit 200 outputs a corresponding control signal to the pipeline control unit 400. The pipeline control unit 400 responds to the control signal and selects its input terminal connected to the instruction decoding unit 100 as a valid input source. Subsequently, all program instructions fetched from the program memory 600, after being decoded in real-time by the instruction decoding unit 100, generate micro-operation signals that are directly sent to the execution unit 900 for execution via the pipeline control unit 400. This process continues until the instruction decoding unit 100 detects a new hardware loop instruction again. At this time, the loop control unit 200 is activated and changes the control signal output to the pipeline control unit 400, thereby switching the source of the micro-operation signals to the instruction storage unit 300 and initiating a new round of hardware loop execution, thus ensuring a smooth and automatic switching between the hardware loop function and the basic instruction pipeline.

[0051] In addition, one embodiment of this application also discloses an electronic device 910, such as... Fig. 3 As shown, it includes: At least one processor 920; At least one memory 930 is used to store at least one program; The hardware loop control method described above is implemented when at least one program is executed by at least one processor 920.

[0052] The electronic device 910 provided in this application embodiment can implement the various processes implemented in the above method embodiments and achieve the same beneficial effects. To avoid repetition, it will not be described again here.

[0053] In addition, embodiments of this application provide a computer-readable storage medium storing a processor-executable program, which, when executed by a processor, is used to implement the hardware loop control method described above.

[0054] The computer-readable storage medium provided in this application embodiment can implement the various processes implemented in the above method embodiments and achieve the same beneficial effects. To avoid repetition, it will not be described again here.

[0055] It will be understood by those skilled in the art that all or some of the steps and systems in the methods disclosed above can be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, which can include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, as is known to those skilled in the art, communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0056] The embodiments of this application have been described in detail above with reference to the accompanying drawings. However, this application is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of this application.

Claims

1. A hardware loop system, characterized in that, include: The instruction decoding unit is used to decode program instructions and identify hardware loop instructions, and to decode instructions within the loop body defined by the hardware loop instructions to obtain micro-operation signals. A loop control unit, connected to the instruction decoding unit, is used to manage the execution of a loop body defined by the hardware loop instruction when the instruction decoding unit recognizes the hardware loop instruction. An instruction storage unit is connected to the loop control unit and is used to receive and store the micro-operation signals; A pipeline control unit is connected to the loop control unit. The pipeline control unit is used to provide the micro-operation signal stored in the instruction storage unit to the execution unit under the control of the loop control unit. A context saving unit is connected to the loop control unit. The context saving unit is used to save key parameters of the loop control unit when the execution of the loop body is interrupted. After the interruption is returned, the loop control unit continues to manage the execution of the loop body based on the key parameters saved by the context saving unit. The key parameters include the start address information of the loop body, the end address information of the loop, the loop program count information, and the remaining loop count information.

2. The hardware loop system according to claim 1, characterized in that, The cycle control unit includes: A loop control counter is connected to the instruction decoding unit. The loop control counter is used to store the number of iterations of the loop body and counts after each iteration of the loop body is completed. A loop start address register, which is connected to the instruction decoding unit, is used to store the starting instruction address of the loop body; A loop end address register, which is connected to the instruction decoding unit, is used to store the end instruction address of the loop body; A loop program counter is used to track and update the address of the instruction currently being executed by the loop body during the execution of the loop body.

3. The hardware loop system according to claim 1, characterized in that, The instruction storage unit includes: A single instruction latch, wherein the single instruction latch is connected to the loop control unit; An instruction buffer is connected to the loop control unit.

4. The hardware loop system according to claim 1, characterized in that, The context saving unit includes: A hardware stack connected to the loop control unit.

5. The hardware loop system according to claim 1, characterized in that: The pipeline control unit is connected to the instruction decoding unit.

6. A hardware loop control method, characterized in that, Applied to the hardware loop system as described in any one of claims 1 to 5, the method comprises: The instruction decoding unit decodes program instructions and identifies hardware loop instructions. The instructions within the loop body defined by the hardware loop instruction are decoded to obtain micro-operation signals; When the instruction decoding unit recognizes the hardware loop instruction, the loop control unit manages the execution of the loop body defined by the hardware loop instruction according to the hardware loop instruction; The micro-operation signals are received and stored through the instruction storage unit; Under the control of the loop control unit, the pipeline control unit provides the micro-operation signals stored in the instruction storage unit to the execution unit; In the event of an interruption during the execution of the loop, the key parameters of the loop control unit are saved through the context saving unit. After the interruption is resolved, the loop control unit continues to manage the execution of the loop based on the key parameters saved by the context saving unit. The key parameters include the start address information of the loop, the end address information of the loop, the loop program count information, and the remaining number of loop iterations.

7. The hardware loop control method according to claim 6, characterized in that, The method of continuing to manage the execution of the loop body based on the key parameters saved by the context saving unit includes: Based on the starting address information, the instructions of the loop body are fetched again and decoded to regenerate the micro-operation signals in the instruction storage unit; Based on the regenerated micro-operation signal, the loop end address information, the remaining loop count information, and the loop program count information, the loop body continues to be executed.

8. The hardware loop control method according to claim 6, characterized in that: When the loop control unit does not control the pipeline control unit to provide the micro-operation signal stored in the instruction storage unit to the execution unit, the pipeline control unit is used to provide the micro-operation signal generated by the instruction decoding unit in real time to the execution unit.

9. An electronic device, characterized in that, include: At least one processor; At least one memory for storing at least one program; The hardware loop control method of claim 6 is implemented when at least one of the programs is executed by at least one of the processors.

10. A computer-readable storage medium, characterized in that, It stores a processor-executable program, which, when executed by the processor, is used to implement the hardware loop control method as described in claim 6.

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