Fault processing method, electronic device, storage medium and program product

Abstract

The application discloses a fault processing method, an electronic device, a storage medium and a program product, and relates to the technical field of computers, including determining, based on sending information of a first signal sent by a controller, a first component for data communication in the controller to be faulty and a plurality of second components to be related to faults, and then sending a first reset signal to the first component or sending a second reset signal to the plurality of second components, and synchronously updating fault record parameters in a register, so that the problem of single recovery strategy caused by restarting the entire controller due to local faults in the related art can be effectively avoided, the technical problem of long service interruption time and poor service continuity caused by global reset is solved, and the technical effect of adopting a differentiated recovery strategy according to the specific characteristics of faults is achieved, while the fault processing efficiency is improved, and the service continuity of the controller is maximally ensured.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a fault handling method, electronic device, storage medium, and program product. Background Technology

[0002] When the Baseboard Management Controller (BMC) fails, the fault is usually handled by a Complex Programming Logic Device (CPLD).

[0003] In related technologies, the CPLD handles faults by monitoring the periodically transmitted pulse signals from the BMC. If the CPLD does not receive a pulse signal from the BMC within a preset time, it needs to trigger the reset of each component in the BMC to restart the BMC and complete the fault handling. However, in the above process, some components may fail while others operate normally, causing server service interruption and resulting in low efficiency in fault handling. Summary of the Invention

[0004] This application provides a fault handling method, electronic device, storage medium, and program product to at least solve the problem of low efficiency in fault handling in related technologies.

[0005] This application provides a fault handling method, including:

[0006] Obtain the transmission information of the first signal sent by the controller, wherein the transmission information indicates that the first signal was sent based on the first frequency or that the first signal was not sent;

[0007] When transmitting information by sending a first signal based on a first frequency, it is determined that a first component corresponding to the first frequency in the controller has malfunctioned, and a first reset signal is sent to the first component. The first component is used for data communication of the controller.

[0008] When the first signal is not sent, a second reset signal is sent to multiple preset second components in the controller.

[0009] The fault record parameters in the register are updated. These parameters are used to record information about resetting the first or second component in the controller.

[0010] This application also provides a fault handling apparatus, comprising: an acquisition module, a determination module, a sending module, and an update module, wherein,

[0011] The acquisition module is used to acquire the transmission information of the first signal sent by the controller, wherein the transmission information is whether the first signal is sent based on the first frequency or no first signal is sent.

[0012] The determination module is used to determine that a first component corresponding to the first frequency in the controller has failed when the information is transmitted as a first signal based on a first frequency, and to send a first reset signal to the first component. The first component is used for data communication of the controller.

[0013] The transmitting module is used to send a second reset signal to a plurality of preset second components in the controller when the first signal is not sent;

[0014] The update module is used to update the fault record parameters in the register. The fault record parameters are used to record information about resetting the first or second component in the controller.

[0015] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for implementing the steps of any of the above-described fault handling methods when executing the computer program.

[0016] This application also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of any of the above-described fault handling methods.

[0017] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described fault handling methods.

[0018] The fault handling method, electronic device, storage medium, and program product provided in this application can determine the fault of the first component used for data communication in the controller and the related faults of multiple preset second components based on the transmission information of the first signal sent by the controller. Then, a first reset signal is sent to the first component or a second reset signal is sent to multiple second components in a targeted manner, and the fault record parameters in the register are updated synchronously. Therefore, it can effectively avoid the problem of the single recovery strategy caused by the need to restart the entire controller due to local faults in related technologies, and solve the technical problems of long service interruption time and poor business continuity caused by global reset. It achieves the technical effect of adopting differentiated recovery strategies according to the specific characteristics of the fault, improving fault handling efficiency while maximizing the protection of the controller's service continuity. Attached Figure Description

[0019] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the system architecture provided for an embodiment of this application;

[0021] Figure 2 A flowchart illustrating a fault handling method provided in an embodiment of this application;

[0022] Figure 3 A waveform diagram of the first signal provided in an embodiment of this application;

[0023] Figure 4 A flowchart illustrating another fault handling method provided in an embodiment of this application;

[0024] Figure 5 A flowchart illustrating another fault handling method provided in an embodiment of this application;

[0025] Figure 6 This is a schematic diagram showing the connection between the controller and registers provided in an embodiment of this application;

[0026] Figure 7 This is a schematic diagram of the structure of a fault handling device provided in an embodiment of this application;

[0027] Figure 8 This is a schematic diagram of another fault handling device provided in an embodiment of this application;

[0028] Figure 9 A schematic diagram of the structure of the electronic device provided in this application. Detailed Implementation

[0029] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, other embodiments obtained by those of ordinary skill in the art without creative effort are all within the protection scope of this application.

[0030] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0031] In related technologies, the CPLD handles faults by monitoring the periodically transmitted pulse signals from the BMC. If the CPLD does not receive a pulse signal from the BMC within a preset time, it needs to trigger the reset of each component in the BMC to restart the BMC and complete the fault handling. However, in the above process, some components may fail while others operate normally, causing server service interruption and resulting in low efficiency in fault handling.

[0032] To address the aforementioned issues, in this embodiment, when fault handling is required, the transmission information of a first signal sent by the controller is obtained. This transmission information indicates whether the first signal is sent based on a first frequency or not. When the transmission information indicates the first signal is sent based on the first frequency, a fault is determined in the first component corresponding to that first frequency in the controller, and a first reset signal is sent to the first component, which is used for data communication within the controller. When the transmission information indicates the first signal is not sent, a second reset signal is sent to multiple preset second components in the controller. The fault record parameters in the register are updated; these parameters record information about resetting the first or second component in the controller. In this way, different fault types of the controller can be accurately distinguished based on the transmission information of the first signal. Targeted partial resets of the first component or centralized resets of the second component can be performed, and fault parameters can be recorded synchronously. Precise partial resets can be performed for component-level faults, and global resets can be performed for system-level faults. Corresponding fault reset information is automatically recorded, achieving intelligent hierarchical processing and precise recovery of controller faults. This improves fault handling efficiency while effectively ensuring the continuity of the controller's core services.

[0033] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0034] This section describes the specific application environment architecture or hardware architecture upon which the fault handling method depends. (References) Figure 1 , Figure 1 This is a schematic diagram of the system architecture provided for an embodiment of this application. Please refer to [link / reference]. Figure 1This includes electronic devices. Electronic devices can be any device with on-device computing capabilities, such as servers and terminal devices.

[0035] Electronic devices are equipped with a BMC and a CPLD. The BMC and CPLD can transmit signals to each other. When the BMC of the electronic device is operating normally, the BMC can periodically send pulse signals of a certain frequency to the CPLD. When the BMC of the electronic device fails and the CPLD does not receive the pulse signals sent by the BMC, the CPLD can send a reset signal to the BMC, triggering a specific component in the BMC to perform a reset operation, thereby completing the fault handling.

[0036] Figure 2 This is a flowchart illustrating a fault handling method provided in an embodiment of this application, as shown below. Figure 2 As shown, an embodiment of this application provides a fault handling method, which is described in detail below:

[0037] S201. Obtain the transmission information of the first signal sent by the controller.

[0038] The execution subject of this application embodiment can be an electronic device or a fault handling device installed in the electronic device. The fault handling device can be implemented by software or by a combination of software and hardware.

[0039] The information to be sent may be either a first signal sent based on a first frequency or no first signal sent.

[0040] The transmitted information is characteristic information used to indicate the operating status of the controller (BMC). That is, the electronic device can determine the specific fault characteristics of the BMC based on the transmitted information. For example, when the transmitted information is a first signal transmitted based on a first frequency, it indicates that the BMC is currently operating normally or there is a partial component failure. The electronic device can determine that the fault characteristic of the BMC is fault A. When the transmitted information is no first signal transmitted, it indicates that a critical component of the BMC has failed. The electronic device can determine that the fault characteristic of the BMC is fault B. The fault level of fault B is much greater than that of fault A.

[0041] The first signal can be a pulse signal sent by the controller BMC to the CPLD. In practical applications, the first signal can be a dog-feeding signal, that is, the BMC can output through a specific interface and send a pulse signal in the form of a square wave to the CPLD.

[0042] In some embodiments, the electronic device may obtain the transmission information of the first signal sent by the controller based on the following implementation: determining the first number of first signals received within a preset time period; when the first number is greater than 0, determining the transmission frequency of the first signal based on the preset time period and the first number, and determining the transmission information according to the transmission frequency; when the first number is 0, determining that the transmission information is that no first signal was sent.

[0043] The preset duration can be the pre-set monitoring cycle duration of the CPLD, that is, the preset duration can be the duration for the CPLD to receive the first signal sent by the BMC. For example, the preset duration can be 1 second.

[0044] The first quantity can be the number of times the first signal is transmitted, that is, the number of complete pulse cycles of the first signal transmitted by the BMC detected by the CPLD. The complete pulse cycle includes a complete transition process from high level to low level and then back to high level. For example, the first quantity can be 1 pulse per second.

[0045] In some embodiments, the electronic device can determine the first number of first signals received within a preset duration by using the timer module, edge detection module, and counter module integrated within the CPLD: activating the timer module corresponding to the preset duration in the CPLD, while simultaneously resetting the counter module; when the pulse of the first signal transitions from low to high level, the edge detection circuit module captures the rising edge state and generates a counting trigger signal; the counter module responds to the counting trigger signal to perform cumulative counting, and hardware logic ensures that only one valid count is triggered in any pulse cycle, thereby avoiding the problem of repeated counting caused by signal jitter or prolonged high levels.

[0046] After the preset time period is reached, the counter module stops counting, latches the current count value, and outputs it to the CPLD. This latched value is the first count. After latching is complete, the counter automatically performs a clearing operation, the timer is also reset, and the entire system then enters the next monitoring cycle, preparing to start a new round of counting.

[0047] The transmission frequency indicates the operating status of the BMC (Browser Control Controller). The value of the transmission frequency can reflect the health status of different functional modules inside the controller. For example, under normal BMC operation, the transmission frequency can be 1 Hz, that is, one first signal is output every 1 second. When the BMC malfunctions, the transmission frequency can be 0.2 Hz, that is, one first signal is output every 5 seconds. It should be noted that the transmission frequency under different operating conditions can be determined according to the actual service requirements of the BMC. This embodiment does not limit this.

[0048] In some embodiments, the electronic device can determine the transmission frequency based on a first quantity and a preset duration. Specifically, based on the first quantity, the target duration of each complete pulse signal within the preset duration is determined, and based on the target duration, the transmission frequency is determined. For example, if the first signal transmitted by the controller in normal operation is 1 Hz and the first signal transmitted in fault condition is 0.2 Hz, the preset duration can be set to 10 seconds. If the first quantity of the first signal is 10 within 10 seconds and the target duration is 1 second, then the transmission frequency is 1 Hz. If the first quantity of the first signal is 2 within 10 seconds and the target duration is 5 seconds, then the transmission frequency is 0.2 Hz.

[0049] Optionally, the electronic device can identify the preset frequency of the BMC by measuring the time interval between two consecutive rising edges of pulses. Specifically, a high-precision timer inside the CPLD records the time difference between adjacent rising edges, and the reciprocal of this time difference is the real-time frequency transmitted by the BMC. For example, if the measured pulse interval is 1 second, the identified transmission frequency is 1 Hz; if the pulse interval is 5 seconds, the identified transmission frequency is 0.2 Hz.

[0050] In some embodiments, the electronic device may determine the information to be transmitted based on the transmission frequency in the following manner: when the transmission frequency is a first frequency, it is determined that the information to be transmitted is a first signal transmitted based on the first frequency; when the transmission frequency is a second frequency, it is determined that the controller is operating normally.

[0051] The first frequency is the transmission frequency used by the controller when it detects a fault in a specific functional module. In this embodiment, the first frequency is the transmission frequency used when the internal I2C controller of the BMC fails. For example, the first frequency can be 0.2 Hz.

[0052] Optionally, in practical applications, the first frequency can be the transmission frequency used when other specific controllers within the BMC fail. For any specific controller, the first frequency may be the same or different, and needs to be set according to the actual needs of the controller. The specific controller can be an eSPI controller, a PCIe controller, or an SPI flash controller.

[0053] The second frequency is the transmission frequency used by the controller when each component is operating normally. In this embodiment, the second frequency can be 1Hz.

[0054] Below, in conjunction with Figure 3 The waveform of the first signal is illustrated through specific examples.

[0055] Figure 3 For a waveform diagram of the first signal provided in the embodiments of this application, please refer to [link / reference]. Figure 3The waveform presents as a periodically stable square wave pulse sequence. Each pulse signal is a standard complete rectangular wave of "high level - low level - high level" (marked with a rectangle in the figure). If its pulse repetition frequency is 1Hz, the period T1 = 1 second. In this mode, the regularity of the pulses and the specific frequency (second frequency) indicate that all functional modules inside the controller are in normal working condition.

[0056] For example, if the first frequency is 0.2 Hz and the second frequency is 1 Hz, when the electronic device determines that the transmission frequency is 0.2 Hz, it means that the current controller outputs one complete pulse signal every 5 seconds, and it can be determined that the transmitted information is a first signal transmitted based on the first frequency; when the electronic device determines that the transmission frequency is 1 Hz, it means that the current controller outputs one complete pulse signal every 1 second, and it can be determined that the controller is operating normally.

[0057] S202. When the information is transmitted as a first signal based on a first frequency, it is determined that a first component corresponding to the first frequency in the controller has malfunctioned, and a first reset signal is sent to the first component.

[0058] The first component is used for data communication with the controller. In this embodiment, the first component is an internal I2C controller of the BMC.

[0059] Optionally, in practical applications, the first frequency can be the transmission frequency used when other specific controllers within the BMC fail. For example, the first component can be an eSPI controller, a PCIe controller, and an SPI flash controller.

[0060] The first reset signal is used to trigger the first component to perform a hardware reset.

[0061] In some embodiments, the electronic device may send a first reset signal to a first component based on the following implementation: determining a first reset pin associated with the first component; outputting a low-level signal to the first reset pin to determine that the level state of the first reset pin has switched to a low-level state; and after determining that the low-level state has lasted for a first duration, switching the level state of the first reset pin to a high-level state.

[0062] The first reset pin can be a hardware interface associated with the first component, meaning that the first component can be triggered to perform a reset operation via the first reset pin. In some embodiments, the first component is an I2C controller, and the first reset pin can be the I2C controller's reset pin I2C_RST, wherein the first reset pin is connected to the CPLD.

[0063] Optionally, if the first component is an eSPI controller, the first reset pin is the eSPI controller's reset pin eSPI_RST; if the first component is a PCIe controller, the first reset pin is the PCIe controller's reset pin PCIe_RST; if the first component is an SPI flash controller, the first reset pin is the SPI flash controller's reset pin SPI_RST.

[0064] In some embodiments, when the CPLD identifies the transmission frequency as the first frequency based on its internal logic circuitry, it indicates an abnormality in the I2C specific bus of the BMC. In this case, fault handling is required via the first reset pin, i.e., pulling down I2C_RST to reset the I2C bus controller, thereby releasing and restoring the bus. For example, after the CPLD identifies a transmission frequency of 0.2Hz, it confirms the I2C bus abnormality and initiates partial recovery; it outputs a low level to the I2C_RST pin for a preset time to ensure the controller is fully reset; after receiving the low-level signal, the I2C bus controller clears its own abnormal state (e.g., bus lock-up, erroneous data buffer, etc.) and restores to the factory default initial operating parameters; after the reset is completed, the CPLD restores the I2C_RST pin level to a high level, the controller resumes normal operation, and the I2C bus resumes communication.

[0065] S203. When the first signal is not sent, a second reset signal is sent to a plurality of preset second components in the controller.

[0066] The second component is used to indicate key components inside the controller. For example, the second component may be the processor core, various buses, and most of the controller. In the embodiments of this application, the second component does not include the DDR memory controller.

[0067] The second reset signal is used to trigger multiple second components to perform a hardware reset.

[0068] In some embodiments, the electronic device may send a second reset signal to a plurality of preset second components in the controller based on the following implementation: determining a second reset pin associated with the plurality of preset second components; outputting a low-level signal to the second reset pin to determine that the level state of the second reset pin is switched to a low-level state; and after determining that the low-level state lasts for a second duration, switching the level state of the second reset pin to a high-level state.

[0069] The second reset pin can be a hardware interface associated with multiple second components, meaning that multiple second components can be triggered to perform reset operations via the second reset pin. In some embodiments, the second reset pin can be SOC_RST, and the second reset pin is connected to the CPLD.

[0070] In some embodiments, SOC_RST is a reset of the entire SoC system of the BMC, including the CPU core, various buses, and most of the controllers (i.e., the second component), but the BMC is not powered off, similar to restarting a computer's operating system. Furthermore, SOC_RST is configured not to reset the DDR controller BMC memory module. In this way, the DDR initialization process is not involved when restarting the BMC, which can greatly improve the restart speed of the BMC and avoid the long time required for DDR training.

[0071] In some embodiments, when the CPLD identifies that the first signal has not been received based on its internal logic circuitry, it indicates that a critical process in the BMC is stuck and cannot be recovered after multiple attempts, or that the current system kernel is panicking or the system is crashing. In such cases, fault handling is required via the second reset pin, i.e., pulling SOC_RST low to restart the BMC and thus restore the BMC system program. For example, the CPLD continuously monitors for the absence of the first signal sent by the BMC and outputs a low level to the SOC_RST pin for a preset period of time to ensure that the controller is completely reset. After multiple second components receive the low-level signal, they specifically: reset the processor core, for example, clear register data and run instructions to restore the initial execution state; reset the internal bus, for example, reset the bus protocol and communication timing to resolve the bus deadlock problem; reset most of the controllers; after the reset is completed, the CPLD will restore the SOC_RST pin level to a high level, and the SOC system will reload the firmware program and initialize the core module.

[0072] In some embodiments, after sending a second reset signal to a plurality of preset second components in the controller, the method includes: updating a first parameter in a register, the first parameter being used to record the number of times the second reset signal is sent to the plurality of second components.

[0073] In some embodiments, the CPLD is provided with a counter register for accumulating the number of times a specific type of reset operation occurs, i.e., a first parameter. For example, before sending a second reset signal to a plurality of preset second components in the controller, the first parameter in the counter register is 0. After the second reset signal is sent to the plurality of preset second components in the controller for the first time, the first parameter in the counter register is updated to 1. If the second reset signal is continuously sent, the counter register needs to be incremented, i.e., the first parameter value is continuously incremented by 1.

[0074] S204. Update the fault record parameters in the register.

[0075] The fault logging parameters are used to record information about resetting the first or second component in the controller. This ensures that fault information remains traceable after a server restart or CPLD power failure, providing a basis for subsequent maintenance and troubleshooting.

[0076] In some embodiments, the CPLD is provided with a status register to record the fault type that triggers the current reset operation, i.e., fault recording parameters. For example, when the BMC is running normally, the status value of the status register inside the CPLD is 0; when the status value is 1, it indicates that the current reset is triggered by the first component (e.g., the I2C controller) at the first frequency; when the status value is 2, it indicates that the current reset is triggered by the second component (system-level component) that is missing the first signal.

[0077] In some embodiments, after completing the reset operation of the first or second component, the CPLD immediately performs parameter updates to ensure data timeliness. The specific steps are as follows: Locking the status register: The CPLD first sends a lock signal to the status register to prevent other modules from reading and writing simultaneously, thus avoiding data conflicts; Reading current parameters: If it is a repeated fault of the same component, the historical record corresponding to that component (e.g., the cumulative number of resets) is read from the register; Writing updated parameters: According to the current reset operation, the fault component identifier, reset type identifier, reset trigger time, and reset execution status are updated, and the cumulative number of resets is incremented by 1 (i.e., the fault record parameter); Unlocking the register: After the update is completed, the register lock is released, allowing the BMC to read the parameters through the data communication interface.

[0078] In some embodiments, the electronic device may update the fault record parameters in the register based on the following implementation: receiving a read request sent by the controller through the first component, the read request being used to read the fault record parameters in the register; sending the updated fault record parameters to the controller; and clearing the fault record parameters.

[0079] In some embodiments, the CPLD and BMC can communicate based on an available communication interface (i.e., the I2C bus corresponding to the first component) to ensure the reliability of data transmission. The specific steps are as follows: Request verification and response: After receiving a read request, the CPLD needs to verify the legality of the request, specifically including verifying whether the register address in the request is the status register address corresponding to the fault record, and the format specification, etc., to avoid false responses caused by communication interference; Parameter encapsulation and transmission: After the verification is passed, the CPLD reads the updated fault record parameters (e.g., fault component identifier, reset timestamp, cumulative count) from the status register, encapsulates them according to a preset data format, and feeds them back to the BMC through the communication interface corresponding to the first component; Transmission confirmation mechanism: Responding communication is adopted to ensure that the BMC successfully receives the data. After confirming that the data has been successfully sent to the BMC, the fault record parameters are cleared. For example, if the fault record parameter in the status register is 2, it is cleared to 0, indicating that the current controller has resumed normal operation.

[0080] exist Figure 2 In the illustrated embodiment, when fault handling is required, the transmission information of a first signal sent by the controller is obtained. This transmission information indicates whether the first signal is sent based on a first frequency or not. When the transmission information indicates the first signal is sent based on the first frequency, a fault is determined in the first component corresponding to that first frequency in the controller, and a first reset signal is sent to the first component, which is used for data communication within the controller. When the transmission information indicates the first signal is not sent, a second reset signal is sent to multiple preset second components in the controller. The fault record parameters in the register are updated; these parameters record information about resetting the first or second component in the controller. In this way, different fault types of the controller can be accurately distinguished based on the transmission information of the first signal. Targeted partial resets of the first component or centralized resets of the second component can be performed, and fault parameters can be recorded synchronously. Precise partial resets can be performed for component-level faults, and global resets can be performed for system-level faults. Corresponding fault reset information is automatically recorded, achieving intelligent hierarchical processing and precise recovery of controller faults. This improves fault handling efficiency while effectively ensuring the continuity of the controller's core services.

[0081] Based on any of the above embodiments, the method for handling faults in the controller after the electronic device sends a second reset signal to a plurality of preset second components in the controller will be described in detail.

[0082] Figure 4 This is a flowchart illustrating another fault handling method provided in an embodiment of this application. Please refer to... Figure 4 ,include:

[0083] S401. Determine whether the first signal at the second frequency has been received.

[0084] In some embodiments, after the CPLD sends a second reset signal (system-level reset) to the BMC, multiple preset second components of the BMC (including core modules such as the internal bus controller) will complete a hardware reset process triggered by the reset signal. Specifically, the second reset pin remains low for a second duration before returning to a high level. At this time, the second components begin to execute an initialization sequence, including key operations such as loading the default configuration, detecting the core hardware links, and resuming the main program execution. Furthermore, after the second reset signal is executed, the CPLD starts a monitoring cycle matching the second frequency to monitor in real time whether the BMC resumes sending the first signal of the second frequency, representing a normal state, within a specified time.

[0085] S402. After receiving the first signal at the second frequency, determine that multiple second components have been successfully reset.

[0086] In some embodiments, when the CPLD receives a first signal with a second frequency (e.g., 1Hz) sent by the BMC after a reset, it can determine that the multiple second components have been successfully reset. Specifically, the BMC can only resume sending pulse signals stably at the normal frequency after its operating system kernel has loaded normally and the system core services have been initialized. Therefore, the received second frequency signal essentially constitutes a "system returned to normal" status acknowledgment message actively sent by the BMC to the CPLD. Based on this acknowledgment, the CPLD will terminate the current fault recovery process, ensuring the integrity of the fault handling process and the reliability of system autonomy.

[0087] S403. After failing to receive the first signal at the second frequency, a third reset signal is sent to the controller.

[0088] The third reset signal is used to instruct the controller to reset.

[0089] In some embodiments, after not receiving the first signal of the second frequency, since SOC_RST cannot completely reset, if the DDR module or other modules experience memory data corruption, DDR controller state disorder or other hardware abnormalities, even if the CPLD executes SOC_RST multiple times, the BMC cannot be restored. That is, the CPLD can directly send a third reset signal to the controller.

[0090] Specifically, the electronic device may send a third reset signal to the controller in the following manner: identify a third reset pin associated with the controller; output a low-level signal to the third reset pin to determine that the level state of the third reset pin has switched to a low-level state; and after determining that the low-level state has lasted for a third duration, switch the level state of the third reset pin to a high-level state.

[0091] The third reset pin can be a hardware interface associated with the controller, meaning that the controller components can be triggered to perform reset operations via the third reset pin. In some embodiments, the third reset pin can be CHIP_RST, which is connected to the CPLD. CHIP_RST is a hardware-level reset of the BMC itself, equivalent to an AC cycle. This reset action will reinitialize all modules, representing the most thorough and lowest-level hardware reset.

[0092] Specifically, after determining that the SOC_RST reset is invalid, the CPLD outputs a low level on the CHIP_RST pin; the BMC is powered down, including: resetting the internal power module; thoroughly initializing all components (e.g., DDR memory controller, CPU, bus, etc.) to clear hardware-level anomalies; after the reset is complete, the CPLD restores the CHIP_RST pin level to a high level, and the BMC is powered on again to start up and restore the initial state from the lowest level.

[0093] In some embodiments, the electronic device may send a third reset signal to the controller based on the following implementation: repeatedly sending a second reset signal to a plurality of second components; and sending a third reset signal to the controller when the number of times the second reset signal is repeatedly sent reaches a first threshold and no first signal of the second frequency is received.

[0094] The first threshold is used to determine whether the number of times the second reset signal is sent exceeds the normal range. For example, the first threshold can be 10, that is, if the number of times the second reset signal is sent exceeds 10 and the first signal of the second frequency is still not received, a third reset signal is sent to the controller.

[0095] In some embodiments, the electronic device can use an adaptive threshold method to dynamically adjust the first threshold. Specifically, the electronic device can dynamically adjust the threshold of the counter register based on the historical number of resets of the BMC. That is, the first threshold is determined based on the aging degree of each piece of hardware in the BMC. For example, for hardware with a high degree of aging, after the CPLD detects frequent SOC_RST resets (e.g., 7 consecutive times), it automatically reduces the threshold from 10 times to 5 times, triggering the CHIP_RST reset in advance to avoid reset failures caused by hardware aging. This technique solves the problem of reset failures or resource waste caused by fixed thresholds through dynamic threshold adjustment, and significantly improves the hardware reliability and maintenance efficiency of the BMC.

[0096] In some embodiments, after the CPLD sends a third reset signal to the controller, the fault record parameters in the register are updated, that is, the status value in the status register is 3, indicating that this reset is triggered by the failure of the controller components due to frequent sending of the second reset signal.

[0097] In some embodiments, the electronic device can employ a neural network model to predict potential faults (e.g., DDR controller malfunction) using historical logs and sensor data. This allows for the pre-emptive adjustment of a first frequency (e.g., reducing it to 0.2Hz) to trigger a pre-recovery action by the CPLD. Specifically, by analyzing historical logs (e.g., high-frequency SOC_RST reset records) and sensor data using a neural network model, the BMC can predict potential faults and pre-emptively reduce the watchdog timer frequency to 0.2Hz, triggering a pre-recovery action by the CPLD (e.g., lowering SOC_RST). For example, when the model detects a continuous increase in DDR controller temperature and historical logs showing an increase in the SOC_RST reset frequency, the BMC proactively reduces the watchdog timer frequency to 0.2Hz. Upon recognizing this, the CPLD pre-emptively executes a SOC_RST reset, preventing system crashes caused by DDR faults. This technique, through a closed-loop logic of data prediction, proactive intervention, and pre-recovery, solves the problem of delayed fault recovery, significantly improving the predictive maintenance capabilities of the BMC and system availability.

[0098] exist Figure 4 In the illustrated embodiment, since the success of the system-level reset can be determined by continuously monitoring whether the first signal at the second frequency is received after sending the second reset signal to the controller, and the retransmission mechanism is used to avoid misjudgment when the reset fails, and a more thorough third reset signal is triggered in time after the reset failure is confirmed, the technical problem of traditional solutions that may fall into infinite restart or stop recovery due to the inability to determine the reset effect is effectively solved. The technical effect of ensuring the reliability of fault recovery through a multi-level verification mechanism is achieved, which improves the success rate of system self-recovery while minimizing service interruption time.

[0099] Figure 5 This is a flowchart illustrating another fault handling method provided in an embodiment of this application. Please refer to... Figure 5 Applied to controllers, including:

[0100] S501. Obtain the fault status of each component of the controller.

[0101] Fault status is used to indicate the health status of each hardware functional module inside the controller, including normal status, communication failure status, and system-level fault status.

[0102] In some embodiments, the BMC can periodically read the status registers of each functional module. After detecting that the status flag bit in the register is 1 for a certain period of time, it determines that the component has failed. After detecting that the status flag bit in the register is 0 for a certain period of time, it determines that the component has not failed and continues to detect other components.

[0103] S502. When the fault status indicates that the first component has failed, a first signal is sent to the register based on the first frequency corresponding to the first component.

[0104] In some embodiments, when a fault state indicates that the first component has failed, the BMC performs a software reset operation. If the first component still fails, it is confirmed that the component has entered a hardware fault state requiring external intervention. Based on the first frequency corresponding to the first component, a first signal is sent to the register. For example, the first frequency is set to 0.2 Hz, and a first signal based on 0.2 Hz is sent to the CPLD.

[0105] In some embodiments, after the BMC receives the first reset signal sent by the CPLD, the BMC can send a read request to the register through the first component, read the fault record parameters in the register, and record the fault record parameters.

[0106] S503. When the fault status indicates that the second component has failed, stop sending the first signal to the register.

[0107] In some embodiments, when a critical component such as the processor core fails, a system-level fault is confirmed, and it is necessary to stop sending the first signal to the CPLD to ensure timely fault handling of the BMC.

[0108] In some embodiments, after the BMC receives the second reset signal sent by the CPLD, the BMC can send a read request to the register through the first component, read the fault record parameters in the register, and record the fault record parameters.

[0109] S504. When the fault status indicates that there is no faulty component, a first signal is sent to the register based on the second frequency.

[0110] In some embodiments, when the BMC is operating normally, it is necessary to periodically send a first signal to the CPLD. For example, the second frequency is set to 1 Hz, and a first signal based on 1 Hz is sent to the CPLD.

[0111] exist Figure 5 In the illustrated embodiment, since the transmission strategy of the first signal can be dynamically adjusted according to the fault status of each component of the controller, when a fault of the first component is detected, the signal transmission is actively stopped when a system-level fault of the second component is detected, and normal communication on the second frequency is maintained when there is no fault, the problem of the single recovery strategy caused by the inability to distinguish the fault type in the traditional solution is effectively solved. It overcomes the technical defects such as mismatch of recovery measures and long service interruption time caused by the inability to accurately identify the fault level. It realizes the implementation of differentiated recovery strategies according to the severity of the fault, which improves the pertinence of fault handling while maximizing the continuity of the controller's core services, and significantly improves the intelligence level and operation and maintenance efficiency of system fault management.

[0112] Below, in conjunction with Figure 6 The connection between the controller and the register is illustrated through specific examples.

[0113] Figure 6 For a schematic diagram of the connection between the controller and registers provided in the embodiments of this application, please refer to [link / reference]. Figure 6The system includes a controller (BMC) and a register (CPLD). The BMC includes a watchdog timer (WDT) module and a WDT status monitoring module. The WDT module is connected to the CPLD via the BMC's general purpose input / output (GPIO) pins as a watchdog timer (WDT). The WDT status monitoring module is connected to the CPLD's register access interface via an I2C bus. The BMC's SOC_RST and CHIP_RST reset pins are connected to the CPLD. I2C_RST, eSPI_RST, PCIe_RST, and SPI_RST can be selectively connected to the CPLD according to business requirements.

[0114] Below, based on Figure 6 The process for troubleshooting is described below:

[0115] Level 1 Frequency and Level 1 Recovery: Under normal system operation, after startup, the BMC controls the GPIO pin "WDT" via its WDT watchdog module to continuously output a periodic pulse signal at a frequency of 1Hz, completing a full level switch of "high-low-high" once per second. The CPLD monitors this pulse signal in real time through its internal logic circuit. When a stable 1Hz frequency is detected, it determines that the BMC is in a healthy operating state. In this state, the CPLD does not trigger any reset operation or perform any recovery action; it only sets the value of its internal status register (watchdog status register) to 0, meaning the fault record parameter status value is 0.

[0116] Secondary Frequency and Secondary Recovery: Taking the connection between I2C_RST and CPLD as an example in this case, other module controllers can also be connected as needed. When the BMC detects a local fault such as a hangup on a specific I2C bus during operation, it first attempts to restore the communication channel via software. If software recovery fails, the BMC's WDT watchdog module switches the output frequency of the GPIO pin "WDT" to 0.2Hz, i.e., outputting a complete pulse cycle every 5 seconds. After the CPLD recognizes this specific frequency, it determines that the BMC has an I2C bus abnormality and immediately performs secondary partial recovery: by pulling low the I2C_RST reset pin connected to the BMC, it performs a hardware reset of the faulty I2C bus controller, thereby releasing and restoring the bus communication. Furthermore, the CPLD updates the value of the watchdog status register to 1. After the BMC recovers, it reads this status value through the WDT status detection module, records the corresponding hardware reset log, and clears the register value. This partial recovery method only affects the faulty module and does not interrupt other services of the BMC.

[0117] Level 3 Frequency and Level 3 Recovery: In the BMC, if a critical process hangs and fails to recover after multiple attempts, the WDT watchdog module will proactively stop feeding the watchdog, or passively fail to generate pulse signals due to system kernel panic or system crash. If the CPLD detects no pulse signal for 180 consecutive seconds (adjustable according to actual needs), it determines that the BMC system has crashed or is hanging and performs Level 3 recovery: restarting the BMC system by pulling the SOC_RST reset signal low. This reset method significantly shortens system restart time by preserving the DDR controller state and skipping the lengthy memory initialization process. The CPLD simultaneously sets the watchdog status register to 2 and increments the watchdog counter register by 1, i.e., increments the first parameter value by 1. After the BMC recovers, its WDT status detection module reads these register values ​​via the I2C bus, records the corresponding BMC SOC_RST reset log, and clears the values ​​of the status register and counter register.

[0118] Ultimate Recovery Logic: For extreme failure scenarios where SOC_RST cannot be recovered, such as DDR memory data corruption or memory controller status malfunction, when the CPLD continuously fails to detect the watchdog signal, it will repeatedly execute the SOC_RST operation, incrementing the watchdog counter register value each time. When this counter value exceeds 10 times (the first threshold can be determined according to actual needs), it indicates that 10 consecutive system-level resets have failed. The CPLD will then trigger an ultimate reset, i.e., pull the CHIP_RST signal low to perform a complete hardware reset of the BMC and set the watchdog status register to 3. After the BMC recovers, its WDT status detection module reads this status value through the I2C bus, records the log of the corresponding BMC triggering the CHIP_RST reset, and clears the values ​​of the status register and counter register.

[0119] Based on the above process, this solution employs a multi-level fault self-recovery method for a server management system based on watchdog monitoring. Depending on the BMC's (Browser Control Center) health status, different frequency watchdog pulses (e.g., 1Hz, 0.2Hz) are sent to the CPLD. Upon receiving these pulses from the BMC, the CPLD adopts different reset strategies and promptly updates the values ​​of its custom status register and counter register. This allows the BMC to read the status values ​​of these registers after recovery and record corresponding log information, facilitating problem identification and localization by maintenance personnel. In this way, on the one hand, automatically selecting the watchdog frequency and the most suitable reset strategy based on its own health status improves BMC intelligence and shortens BMC SoC restart time; on the other hand, the multi-level reset method greatly enhances the reliability and security of the BMC, while the log recording also facilitates problem identification and localization by maintenance personnel.

[0120] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0121] Figure 7 This is a schematic diagram of a fault handling device provided in an embodiment of this application. Figure 7 As shown, embodiments of this application also provide a fault handling device 70, including: an acquisition module 71, a determination module 72, a sending module 73, and an update module 74, wherein,

[0122] The acquisition module 71 is used to acquire the transmission information of the first signal sent by the controller, wherein the transmission information is whether the first signal is sent based on the first frequency or no first signal is sent.

[0123] The determination module 72 is used to determine that a first component corresponding to the first frequency in the controller has failed when the information is transmitted as a first signal based on a first frequency, and to send a first reset signal to the first component. The first component is used for data communication of the controller.

[0124] The transmitting module 73 is used to send a second reset signal to a plurality of preset second components in the controller when the transmitting information is not a first signal;

[0125] The update module 74 is used to update the fault record parameters in the register. The fault record parameters are used to record information about resetting the first or second component in the controller.

[0126] For a description of the features in the embodiment corresponding to the fault handling device, please refer to the relevant description of the embodiment corresponding to the fault handling method, which will not be repeated here.

[0127] In one possible implementation, the acquisition module 71 is specifically used for:

[0128] Determine the first number of first signals received within a preset time period;

[0129] When the first quantity is greater than 0, the transmission frequency of the first signal is determined based on the preset duration and the first quantity, and the transmission information is determined according to the transmission frequency;

[0130] When the first quantity is 0, it is determined that the information sent is not the first signal sent.

[0131] In one possible implementation, the acquisition module 71 is further configured to:

[0132] When the transmission frequency is the first frequency, it is determined that the transmitted information is a first signal transmitted based on the first frequency;

[0133] When the transmission frequency is the second frequency, it is determined that the controller is operating normally.

[0134] In one possible implementation, the determining module 72 is specifically used for:

[0135] Determine the first reset pin associated with the first component;

[0136] Output a low-level signal to the first reset pin to determine that the level state of the first reset pin has switched to a low-level state;

[0137] After determining that the low-level state lasts for a first duration, the level state of the first reset pin is switched to the high-level state.

[0138] In one possible implementation, the sending module 73 is specifically used for:

[0139] Determine the second reset pin associated with a plurality of preset second components;

[0140] Output a low-level signal to the second reset pin to confirm that the level state of the second reset pin has switched to a low-level state;

[0141] After determining that the low-level state lasts for a second duration, the level state of the second reset pin is switched to the high-level state.

[0142] In one possible implementation, the apparatus further includes a first processing module, which is specifically used for:

[0143] Determine whether the first signal at the second frequency has been received;

[0144] After receiving the first signal at the second frequency, it is determined that multiple second components have been successfully reset;

[0145] After failing to receive the first signal at the second frequency, a third reset signal is sent to the controller, which instructs the controller to perform a reset.

[0146] In one possible implementation, the first processing module is further configured to:

[0147] Repeatedly send a second reset signal to multiple second components;

[0148] When the number of times the second reset signal is repeatedly sent reaches the first threshold and no first signal at the second frequency is received, a third reset signal is sent to the controller.

[0149] In one possible implementation, the apparatus further includes a second processing module, which is specifically used for:

[0150] The receiver controller sends a read request through the first component. The read request is used to read the fault record parameters in the register.

[0151] Send the updated fault record parameters to the controller and clear the fault record parameters.

[0152] Figure 8 This is a schematic diagram of another fault handling device provided in an embodiment of this application. Figure 8 As shown, embodiments of this application also provide a fault handling apparatus 80, including: an acquisition module 81 and a transmission module 82, wherein,

[0153] The acquisition module 81 is used to acquire the fault status of each component of the controller;

[0154] The transmitting module 82 is used to send a first signal to the register based on the first frequency corresponding to the first component when the fault status indicates that the first component has failed.

[0155] The transmitting module 82 is also used to stop sending the first signal to the register when the fault status indicates that the second component has failed;

[0156] The transmitting module 82 is also configured to transmit a first signal to the register based on a second frequency when the fault status indicates that there is no faulty component.

[0157] For a description of the features in the embodiment corresponding to the fault handling device, please refer to the relevant description of the embodiment corresponding to the fault handling method, which will not be repeated here.

[0158] Figure 9 A schematic diagram of the structure of the electronic device provided in this application. Figure 9 As shown, the electronic device 90 provided in this embodiment includes at least one processor 91 and a memory 92. Optionally, the electronic device 90 further includes a communication component 93. The processor 91, memory 92, and communication component 93 are connected via a bus.

[0159] In a specific implementation, at least one processor 91 executes computer execution instructions stored in memory 92, causing at least one processor 91 to execute the above-described fault handling method embodiment.

[0160] The specific implementation process of processor 91 can be found in the above method embodiments, and its implementation principle and technical effect are similar. It will not be repeated here.

[0161] In the above embodiments, it should be understood that the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in the application can be directly manifested as being executed by a hardware processor, or executed by a combination of hardware and software modules within the processor.

[0162] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage device.

[0163] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.

[0164] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described fault handling method embodiments when it is run.

[0165] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0166] Embodiments of this application also provide a computer program product, including a computer program that, when executed by a processor, implements the steps in any of the above-described fault handling method embodiments.

[0167] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described fault handling method embodiments.

[0168] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for specific applications, but such implementations should not be considered beyond the scope of this application.

[0169] The above provides a detailed description of a fault handling method provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and its core ideas. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A fault handling method, characterized in that, include: Obtain transmission information of a first signal sent by the controller, wherein the transmission information indicates whether the first signal is sent or not based on a first frequency, and the first signal is a pulse signal; When the information is transmitted by sending the first signal based on the first frequency, it is determined that the first component corresponding to the first frequency in the controller has failed, and a first reset signal is sent to the first component, the first component being used for data communication of the controller; When the transmitted information is that the first signal is not transmitted, a second reset signal is sent to a plurality of preset second components in the controller, the second components being used to indicate key components inside the controller; The fault recording parameters in the register are updated. These fault recording parameters are used to record information about resetting the first or second component in the controller. Obtaining the transmission information of the first signal sent by the controller includes: Determine the first number of the first signals received within a preset time period; When the first quantity is greater than 0, the transmission frequency of the first signal is determined based on the preset duration and the first quantity, and the transmission information is determined according to the transmission frequency; When the first quantity is 0, it is determined that the information sent is not the first signal sent.

2. The method according to claim 1, characterized in that, Determining the transmission information based on the transmission frequency includes: When the transmission frequency is the first frequency, it is determined that the transmitted information is the transmission of the first signal based on the first frequency; When the transmission frequency is the second frequency, it is determined that the controller is operating normally.

3. The method according to claim 1, characterized in that, Sending a first reset signal to the first component includes: Determine the first reset pin associated with the first component; Output a low-level signal to the first reset pin to determine that the level state of the first reset pin has switched to a low-level state; After determining that the low-level state lasts for a first duration, the level state of the first reset pin is switched to a high-level state.

4. The method according to claim 1, characterized in that, Sending a second reset signal to a plurality of preset second components in the controller, including: Determine the second reset pin associated with the preset plurality of second components; Output a low-level signal to the second reset pin to determine that the level state of the second reset pin has switched to a low-level state; After determining that the low-level state lasts for a second duration, the level state of the second reset pin is switched to a high-level state.

5. The method according to claim 1, characterized in that, After sending a second reset signal to a plurality of preset second components in the controller, the method further includes: Determine whether the first signal at the second frequency has been received; After receiving the first signal at the second frequency, it is determined that the plurality of second components have been successfully reset; After failing to receive the first signal at the second frequency, a third reset signal is sent to the controller, which instructs the controller to perform a reset.

6. The method according to claim 5, characterized in that, Sending a third reset signal to the controller includes: The second reset signal is repeatedly sent to the plurality of second components; When the number of times the second reset signal is repeatedly sent reaches a first threshold and no first signal at the second frequency is received, a third reset signal is sent to the controller.

7. The method according to claim 6, characterized in that, After updating the fault record parameters in the register, the method further includes: The controller receives a read request sent through the first component, the read request being used to read fault record parameters in the register; The updated fault record parameters are sent to the controller, and the fault record parameters are cleared.

8. A fault handling method, characterized in that, Applied to a controller, the method includes: Obtain the fault status of each component of the controller; When the fault status indicates that the first component has failed, a first signal is sent to the register based on the first frequency corresponding to the first component, and the first signal is a pulse signal; When the fault status indicates that the second component has failed, the first signal is stopped being sent to the register. The second component is used to indicate critical components inside the controller. When the fault status indicates that there is no faulty component, the first signal is sent to the register based on the second frequency; Wherein, when the fault state indicates that the first component has failed, sending a first signal to the register based on the first frequency corresponding to the first component includes: When the fault status indicates that the first component has failed, a software reset operation is performed. If the first component continues to fail, it is confirmed that the first component has entered a hardware fault state requiring external intervention, and a first signal is sent to the register based on the first frequency corresponding to the first component. The step of stopping sending the first signal to the register when the fault state indicates that the second component has failed includes: When the fault status indicates that the second component has failed, a system-level fault is confirmed, and the sending of the first signal to the register is stopped.

9. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the fault handling method as described in any one of claims 1 to 8 when executing the computer program.

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