Rocket telemetry system fault injection design and self-recovery method based on TTE bus
By employing fault injection design and self-recovery method of TTE bus in the launch vehicle telemetry system and utilizing FIFO buffering mechanism, the problem of TTE bus synchronization jitter is difficult to reproduce, achieving real-time and accurate data transmission and improving system test coverage and reliability.
Patent Information
- Application Number
- CN202511571639.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-30
- Publication Date
- 2026-02-13
AI Technical Summary
In the existing technology, the fault injection and self-recovery methods of TTE bus in the launch vehicle telemetry system have not been effectively applied, resulting in the difficulty in reproducing synchronization jitter and affecting the real-time performance and accuracy of data transmission.
A fault injection design and self-recovery method based on the TTE bus are adopted. By using the FIFO buffering mechanism of the data acquisition device and the receiving device, UDP jitter type faults are injected, and data recovery is performed when the fault occurs, so as to ensure the real-time performance and accuracy of data transmission.
This improved the test coverage of the TTE bus of the launch vehicle telemetry system, exposed potential design flaws, ensured that the system works correctly in failure scenarios, and maintained time determinism, safety and availability.
Smart Images
Figure CN121523969A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of integrated data transmission technology for telemetry systems, and specifically to a fault injection design and self-recovery method for rocket telemetry systems based on the TTE bus. Background Technology
[0002] The launch vehicle telemetry system bus is used for data exchange between various integrated electronic devices and determines the overall performance of the launch vehicle telemetry system. In recent years, with the increasing demands of launch vehicles on electrical systems, traditional buses such as 1553B still have value in areas of simple, low-bandwidth, and high-reliability control. However, new-generation spacecraft, due to their massive data volumes and complex collaborative control requirements, necessitate the selection of higher-speed, more deterministic, and more reliable networked buses. TTE bus communication technology is a real-time Ethernet solution based on "time-triggered" communication. It integrates deterministic time-triggered communication mechanisms with standard Ethernet technology, achieving the high real-time performance, high reliability, and security required by space missions while increasing bandwidth. It has been widely used in the aerospace field both domestically and internationally.
[0003] TTE bus fault injection and self-recovery technology is an important means of verifying bus reliability and robustness. At present, the fault injection and self-recovery schemes of TTE bus are based on the bus protocol principle, and there is a lack of fault injection and self-recovery methods for actual application in launch vehicle telemetry systems. Summary of the Invention
[0004] The technical problem solved by this invention is to overcome the gaps in existing technologies and provide a fault injection design and self-recovery method for rocket telemetry systems based on the TTE bus, as well as a data communication system. This solves the problem of difficult reproduction of synchronization jitter on the TTE bus of launch vehicle telemetry systems, establishes a test method for injecting interference into periodic data, and improves the test coverage of the system's TTE bus. Based on the fault injection mechanism, a self-recovery communication method for TTE end-node data is proposed. Under fault injection conditions, data recovery is completed in a timely manner through buffer settings, ensuring the real-time performance and accuracy of data transmission.
[0005] The technical solution of this invention is:
[0006] Firstly, a fault injection design and self-recovery method for a rocket telemetry system based on the TTE bus, including the following steps:
[0007] 1) When the system is powered on, the data acquisition equipment performs telemetry data acquisition and transmits TT frame data to the data receiving equipment in small frame communication cycles through the TTE bus network. The data receiving equipment then completes the telemetry framing and downlink work.
[0008] 2) Fault injection was performed on the data acquisition equipment, affecting the output of TT frame data of the data acquisition equipment;
[0009] 3) Determine whether UDP jitter has occurred during TTE bus network synchronization. If UDP jitter has occurred, proceed to step 4); otherwise, return to step 1) until data transmission is completed.
[0010] 4) Perform recovery processing on the data acquisition equipment and data receiving equipment.
[0011] Preferably, the method for performing fault injection in the data acquisition equipment is as follows:
[0012] The data acquisition device includes: a transmitting SoC module;
[0013] The sending SoC module in the data acquisition device performs program verification or program upgrade, which causes UDP jitter and affects the output of TT frame data of the data acquisition device.
[0014] Preferably, during the process of sending the SoC module for program verification or program upgrade, BE frame data of not less than 100KB / s is generated, which affects the output of TT frame data of the data acquisition device, i.e., UDP jitter occurs.
[0015] Preferably, the method for determining whether UDP jitter occurs during TTE bus network synchronization is as follows:
[0016] The data receiving device includes: a receiving SoC module and a receiving FPGA module;
[0017] Check whether the receiving SoC module has received the framed data for this small frame communication cycle;
[0018] If the framed data of the current small frame communication cycle is received, the receiving SoC module in the control data receiving device will forward the TT frame data to the receiving FPGA module, which will then complete the telemetry framed downlink work and return to step 1) until the data transmission work is completed.
[0019] If the number of consecutive verification failures is less than 3 small frame communication cycles, the receiving SoC module in the control data receiving device discards the TT frame data of the current small frame communication cycle and returns to step 1) until the data transmission is completed.
[0020] If the number of consecutive verification failures is not less than 3 small frame communication cycles, then UDP jitter is determined to have occurred, and the process proceeds to step 4.
[0021] Preferably, the method for recovery processing by the transmitting SOC module of the data acquisition device is as follows:
[0022] At the beginning of each small frame communication cycle, check if the transmit FIFO in the transmit SOC module is empty. If it is empty, write the TT frame data of the current small frame communication cycle to the transmit FIFO. If not, discard the data currently buffered in the transmit FIFO and discard the TT frame data to be sent in the current small frame communication cycle, and return to step 1) to wait for the TT frame data transmission of the next small frame communication cycle.
[0023] Preferably, the method for the data receiving device's receiving SOC module to perform recovery processing is as follows:
[0024] Within the current small frame communication cycle, perform two read operations on the receive FIFO in the receive SOC module, and then return to step 1) to wait for the TT frame data transmission of the next small frame communication cycle.
[0025] Secondly,
[0026] A data communication system for a launch vehicle telemetry system, implementing a fault injection design and self-recovery method for a rocket telemetry system based on a TTE bus as described in the first aspect, includes: a data acquisition device and a data receiving device; data transmission between the data acquisition device and the data receiving device is performed via a TTE bus;
[0027] The data acquisition device includes: a transmitting FPGA module and a transmitting SoC module; the transmitting SoC module includes: a transmitting processing module and a transmitting FIFO;
[0028] The data receiving device includes: a receiving SoC module and a receiving FPGA module; the receiving SoC module includes: a receiving processing module and a receiving FIFO;
[0029] Transmitting FPGA module: performs frame processing on the acquired data, obtains framed data, and transmits it to the transmission processing module in the transmitting SoC module;
[0030] Transmit Processing Module: Receives framed data output from the transmit FPGA module, encapsulates it according to the virtual link number and data length defined in the bus scheduling table, obtains TT frame data, and transmits it to the transmit FIFO. During fault testing, program verification or upgrades may occur, resulting in UDP jitter and affecting the output of TT frame data. When UDP jitter occurs, at the beginning of each small frame communication cycle, it checks whether the buffered data in the transmit FIFO is empty. If it is empty, it writes the TT frame data for the current small frame communication cycle to the transmit FIFO; otherwise, it discards the currently buffered data in the transmit FIFO, along with the TT frame data expected to be sent in the current small frame communication cycle, and waits for the next small frame communication cycle to arrive before continuing the transmission of TT frame data.
[0031] Transmit FIFO: Receives TT frame data output by the transmit processing module, performs buffering processing, and after receiving an external transmit interrupt command, transmits the buffered TT frame data to the receive FIFO of the receive SoC module via the network switch according to the small frame communication cycle.
[0032] Receive FIFO: Receives TT frame data output from the network switch, performs buffering processing, and sends the buffered TT frame data to the receive SoC module according to the small frame communication cycle;
[0033] The receiving and processing module receives TT frame data sent by the receiving FIFO according to the small frame communication cycle; it verifies whether the data is framed within the small frame communication cycle. If the verification is successful, the TT frame data is forwarded to the FPGA module. If the number of consecutive verification failures is less than 3 small frame communication cycles, the TT frame data for the current small frame communication cycle is discarded, and the TT frame data transmission and reception work continues after the arrival of the next small frame communication cycle. If the number of consecutive verification failures is not less than 3 small frame communication cycles, UDP jitter is determined to have occurred. When UDP jitter occurs, two read operations are performed within the current small frame communication cycle, and then the TT frame data transmission and reception work continues after the arrival of the next small frame communication cycle.
[0034] FPGA receiving module: Receives TT frame data transmitted from the receiving processing module, performs framing, and forms a data stream for output to the external system.
[0035] Preferably, the transmitting FPGA module completes the data framing process before the start of each small frame communication cycle planned by the TTE bus.
[0036] Preferably, during the process of sending and processing modules performing program verification or program upgrades, BE frame data of not less than 100KB / s is generated.
[0037] Preferably, data transmission between the receiving SoC module and the receiving FPGA module is performed via an EMIF bus.
[0038] Compared with the prior art, the advantages of the present invention are mainly reflected in the following aspects:
[0039] 1) This invention employs injected UDP jitter type faults, such as during program verification or upgrades in the sending or receiving SoC module. The system generates a large volume of BE data. Due to the time-consuming processing of BE, TT data is lost because it is not processed in time, thus causing jitter through the system's TTE bus synchronization, thereby exposing potential design flaws and weaknesses in the data transmission process of integrated electronic devices.
[0040] 2) This invention adopts an optimized receive / send FIFO caching mechanism, which can realize data self-recovery in a timely manner, and verifies the effectiveness of fault injection technology to ensure that the system can work correctly under preset fault scenarios.
[0041] 3) This invention can ensure that the launch vehicle telemetry system can maintain time determinism, security and availability when the TTE bus experiences UDP jitter type failures. Attached Figure Description
[0042] Figure 1 This is a flowchart of the TTE bus fault injection and data self-recovery process of the present invention.
[0043] Figure 2 This is a timing logic diagram of the data acquisition and editing combination and the measurement and control combination in one embodiment of the present invention.
[0044] Figure 3 This is a flowchart of data communication based on the FIFO mechanism. Detailed Implementation
[0045] To better describe the present invention, the present invention will be described in detail below with reference to schematic diagrams and examples.
[0046] A data communication system for a launch vehicle telemetry system includes: a data acquisition device and a data receiving device; the data acquisition device and the data receiving device transmit data via a TTE bus.
[0047] The data acquisition equipment includes: a transmitting FPGA module and a transmitting SoC module;
[0048] Data transmission between the transmitting FPGA module and the transmitting SoC module is conducted via the EMIF bus.
[0049] The transmit SoC module includes: a transmit processing module and a transmit FIFO;
[0050] Transmitting FPGA module: The acquired data is processed into frames to obtain framed data and transmitted to the transmission processing module in the transmitting SoC module.
[0051] The transmitting FPGA module completes the data framing process before the start of each small frame communication cycle (internal system transmission cycle, 5ms) planned on the TTE bus. The time when the transmitting FPGA module completes the data framing process is no later than 100us before the start of each small frame communication cycle (internal system transmission cycle, 5ms) planned on the TTE bus.
[0052] The FPGA module frame processing method in this embodiment of the invention is as follows: the data acquisition device uses a 5ms communication cycle for each small frame, and sends 15 subframes to the data receiving device in each small frame communication cycle. Four small frames form a large frame, which is sent four times in total, that is, the communication cycle of a large frame is 20ms, and the sending time points are 0ms, 5ms, 10ms, and 15ms.
[0053] The transmitting processing module of the transmitting SoC module receives the framed data output by the transmitting FPGA module, encapsulates it according to the virtual link number and data length defined in the bus scheduling table, obtains TT frame data, and transmits it to the transmitting FIFO. During fault testing, program verification or program upgrades are performed, generating BE frame data of not less than 100KB / s, which causes UDP jitter and affects the output of TT frame data. When UDP jitter occurs, at the beginning of each small frame communication cycle, it checks whether the buffered data in the transmitting FIFO is empty. If it is empty, it writes the TT frame data of the current small frame communication cycle to the transmitting FIFO. If not, it discards the currently buffered data in the transmitting FIFO and the TT frame data to be sent in the current small frame communication cycle, and waits for the next small frame communication cycle to arrive before continuing the transmission of TT frame data.
[0054] Transmit FIFO: Receives TT frame data output by the transmit processing module, performs buffering processing, and after receiving an external transmit interrupt command, transmits the buffered TT frame data to the receive FIFO of the receive SoC module via the network switch according to the small frame communication cycle.
[0055] The data receiving device includes: a receiving SoC module and a receiving FPGA module;
[0056] The receiving SoC module includes: a receiving processing module and a receiving FIFO;
[0057] Receive FIFO: Receives TT frame data output from the network switch, performs buffering processing, and sends the buffered TT frame data to the receive SoC module according to the small frame communication cycle;
[0058] The receiving and processing module receives TT frame data output from the transmitting SoC via a receiving FIFO, verifies whether it conforms to the frame data of the current small frame communication cycle, and if the verification is successful, forwards the TT frame data to the FPGA module through the internal EMIF bus. If the number of consecutive verification failures is less than 3 small frame communication cycles, the TT frame data of the current small frame communication cycle is discarded, and the TT frame data transmission and reception work continues after the arrival of the next small frame communication cycle. If the number of consecutive verification failures is not less than 3 small frame communication cycles, it is determined that UDP jitter has occurred. When UDP jitter occurs, two read operations are performed within the current small frame communication cycle, and then the TT frame data transmission and reception work continues after the arrival of the next small frame communication cycle.
[0059] Data is transmitted between the receiving SoC module and the receiving FPGA module via the EMIF bus.
[0060] FPGA receiving module: Receives TT frame data transmitted from the receiving SoC module, performs framing, and forms a data stream for output to the external system.
[0061] like Figure 1 As shown, a fault injection design and self-recovery method for a rocket telemetry system based on the TTE bus are as follows:
[0062] 1) When the system is powered on, the data acquisition equipment collects telemetry data and transmits it to the data receiving equipment. The data receiving equipment then completes the telemetry framing and downlinking. Data self-recovery requires both the data acquisition equipment and the data receiving equipment to operate simultaneously.
[0063] 2) Fault injection in data acquisition equipment: Based on the operating mechanism of the SOC chip, UDP jitter is injected, for example, during program verification or program upgrade. Since the current SOC chip software is single-threaded, the large amount of time spent processing BE frame data causes TT frame data to be lost due to untimely processing. When using BE frames for UDP program verification or upgrade, the TTE bus uses a hardware synchronization mechanism, which does not affect the synchronization of PCF frames in the entire system's TTE network.
[0064] 3) By checking whether the received SoC module receives framed data of the current small frame communication cycle, it is determined whether UDP jitter has occurred in the TTE bus network synchronization. Specifically, if the verification is successful, the TT frame data is forwarded to the FPGA module through the internal EMIF bus of the device, and the process returns to step 1) until the data transmission is completed. Otherwise, the data is discarded. If the verification fails for no less than 3 small frame communication cycles, an error is reported and the process proceeds to step 4).
[0065] 4) Based on the operating mechanism of the SOC chip, determine if the system has generated UDP jitter, and perform recovery processing on the transmitting SOC module of the data acquisition device and the receiving SOC module of the data receiving device.
[0066] The method for recovery processing by the transmitting SOC module of the data acquisition device is as follows:
[0067] At the beginning of each small frame communication cycle, the transmit FIFO direction of the transmit SOC module checks whether the buffered data in the transmit FIFO is empty. If it is empty, the transmit SOC module of the data acquisition device writes the TT frame data of the current small frame communication cycle to the transmit FIFO. If not, it discards the currently buffered data in the transmit FIFO and also discards the TT frame data to be sent in the current small frame communication cycle, and returns to step 1) to wait for the TT frame data transmission of the next small frame communication cycle.
[0068] The method for recovery processing by the receiving SOC module of the data receiving device is as follows:
[0069] The receiving FIFO direction of the SOC module is used to perform two read operations within the current small frame communication cycle when reading data from the receiving FIFO. This ensures that the FIFO does not buffer redundant data, guarantees real-time data transmission, and enables rapid recovery after a UDP jitter-type fault. Then, it returns to step 1) to wait for the transmission of the next small frame communication cycle.
[0070] Example
[0071] The operating timing sequence of the data acquisition and editing integrated module (i.e., data acquisition device) and the measurement and control integrated data integration module (i.e., data receiving device) in one embodiment of the present invention is shown below. Figure 2 .
[0072] like Figure 3 As shown, data transmission between the acquisition / editing and measurement / control units uses TT frames, which are the highest priority and most deterministic data frames on the TTE bus. Regular transmissions with non-real-time requirements, such as software upgrades and parameter configurations, use BE frames, operating between TT and PCF frames. Ping commands and UDP data transmissions fall under the BE frame range.
[0073] This invention proposes a fault injection design and self-recovery method for a rocket telemetry system based on the TTE bus. The system adopts a distributed integrated electronic architecture design. Based on the communication between data acquisition and data integration equipment, a UDP jitter type fault is artificially injected into the TTE bus to achieve synchronous jitter of the TTE bus in the launch vehicle telemetry system. Based on the fault injection mechanism, a self-recovery communication method for TTE end nodes is proposed. Under fault injection conditions, data recovery is completed in a timely manner through buffer settings, ensuring the real-time performance and accuracy of data transmission. This invention can be applied to data communication equipment such as the acquisition and editing combination and the telemetry and control combination of launch vehicle telemetry systems.
[0074] While the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Any person skilled in the art can make possible variations and modifications to the technical solutions of the present invention using the disclosed methods and techniques without departing from the spirit and scope of the invention. Therefore, any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention, without departing from the content of the technical solutions of the present invention, shall fall within the protection scope of the present invention. Where there is no conflict, the embodiments of this application and the technical features thereof can be combined with each other.
[0075] The contents not described in detail in this specification are common knowledge to those skilled in the art.
Claims
1. A fault injection design and self-recovery method for a rocket telemetry system based on a TTE bus, characterized in that, Including the following steps: 1) When the system is powered on, the data acquisition device collects telemetry data and transmits TT frame data to the data receiving device according to the frame communication cycle through the TTE bus network. The data receiving device then completes the telemetry framing and downlink work. 2) Injecting faults into the data acquisition equipment affects the output of TT frame data. 3) Determine whether UDP jitter has occurred during TTE bus network synchronization. If UDP jitter has occurred, proceed to step 4); otherwise, return to step 1) until data transmission is completed. 4) Perform recovery processing on the data acquisition equipment and data receiving equipment.
2. The fault injection design and self-recovery method for a rocket telemetry system based on a TTE bus according to claim 1, characterized in that, The specific methods for fault injection in data acquisition equipment are as follows: The data acquisition device includes: a transmitting SoC module; The sending SoC module in the data acquisition device performs program verification or program upgrade, which causes UDP jitter and affects the output of TT frame data of the data acquisition device.
3. The fault injection design and self-recovery method for a rocket telemetry system based on a TTE bus according to claim 2, characterized in that, During the process of sending data to the SoC module for program verification or upgrade, BE frame data of not less than 100KB / s is generated, which affects the output of TT frame data of the data acquisition device, i.e., UDP jitter occurs.
4. A fault injection design and self-recovery method for a rocket telemetry system based on a TTE bus, as described in any one of claims 1-3, characterized in that, The method for determining whether UDP jitter has occurred during TTE bus network synchronization is as follows: The data receiving device includes: a receiving SoC module and a receiving FPGA module; Check whether the receiving SoC module has received the framed data for the current communication period; If the framed data of the current communication period is received, the receiving SoC module in the control data receiving device forwards the TT frame data to the receiving FPGA module, which then completes the telemetry framed downlink work and returns to step 1) until the data transmission work is completed. If the number of consecutive verification failures is less than 3 frame communication cycles, the receiving SoC module in the control data receiving device discards the TT frame data of the current frame communication cycle and returns to step 1) until the data transmission is completed. If the number of consecutive verification failures is not less than 3 frame communication cycles, then UDP jitter is determined to have occurred, and the process proceeds to step 4.
5. The fault injection design and self-recovery method for a rocket telemetry system based on a TTE bus according to claim 4, characterized in that, The method for recovery processing by the SOC module of the data acquisition device is as follows: At the beginning of each frame communication cycle, check if the transmit FIFO in the transmit SOC module is empty. If it is empty, write the TT frame data of the current frame communication cycle to the transmit FIFO. If not, discard the data currently buffered in the transmit FIFO and discard the TT frame data to be sent in the current frame communication cycle, and return to step 1) to wait for the TT frame data transmission of the next frame communication cycle.
6. The fault injection design and self-recovery method for a rocket telemetry system based on a TTE bus according to claim 5, characterized in that, The method for recovery processing by the receiving SOC module of the data receiving device is as follows: Within the current frame communication cycle, perform two read operations on the receive FIFO in the receive SOC module, and then return to step 1) to wait for the TT frame data transmission of the next frame communication cycle.
7. A data communication system for a launch vehicle telemetry system, implementing the fault injection design and self-recovery method for a rocket telemetry system based on a TTE bus as described in claim 1, characterized in that... include: Data acquisition equipment and data receiving equipment; Data acquisition and data receiving devices transmit data via a TTE bus. The data acquisition device includes: a transmitting FPGA module and a transmitting SoC module; the transmitting SoC module includes: a transmitting processing module and a transmitting FIFO; The data receiving device includes: a receiving SoC module and a receiving FPGA module; the receiving SoC module includes: a receiving processing module and a receiving FIFO; Transmitting FPGA module: performs frame processing on the acquired data, obtains framed data, and transmits it to the transmission processing module in the transmitting SoC module; Transmit Processing Module: Receives framed data output from the transmit FPGA module, encapsulates it according to the virtual link number and data length defined in the bus scheduling table, obtains TT frame data, and transmits it to the transmit FIFO. During fault testing, program verification or upgrades may occur, resulting in UDP jitter and affecting the output of TT frame data. When UDP jitter occurs, at the beginning of each frame communication cycle, it checks whether the buffered data in the transmit FIFO is empty. If it is empty, it writes the TT frame data for the current frame communication cycle to the transmit FIFO; otherwise, it discards the buffered data in the transmit FIFO and the TT frame data to be transmitted in the current frame communication cycle, waiting for the next frame communication cycle to arrive before continuing the transmission of TT frame data. Transmit FIFO: Receives TT frame data output by the transmit processing module, performs buffering processing, and after receiving an external transmit interrupt command, transmits the buffered TT frame data to the receive FIFO of the receive SoC module via the network switch according to the frame communication cycle. Receive FIFO: Receives TT frame data output from the network switch, performs buffering processing, and sends the buffered TT frame data to the receive SoC module according to the frame communication cycle; The receiving and processing module receives TT frame data sent by the receiving FIFO according to the frame communication cycle; it verifies whether the data is framed within the frame communication cycle. If the verification is successful, the TT frame data is forwarded to the FPGA module. If the number of consecutive verification failures is less than 3 frame communication cycles, the TT frame data for the current frame communication cycle is discarded, and the TT frame data transmission and reception are resumed after the arrival of the next frame communication cycle. If the number of consecutive verification failures is not less than 3 frame communication cycles, UDP jitter is determined to have occurred. When UDP jitter occurs, two read operations are performed within the current frame communication cycle, and then the TT frame data transmission and reception are resumed after the arrival of the next frame communication cycle. FPGA receiving module: Receives TT frame data transmitted from the receiving processing module, performs framing, and forms a data stream for output to the external system.
8. The data communication system for a launch vehicle telemetry system according to claim 1, characterized in that, Before the start of each frame communication cycle planned by the TTE bus, the FPGA module completes the data framing process to be transmitted.
9. A data communication system for a launch vehicle telemetry system according to claim 1, characterized in that, During program verification or upgrade, the sending and processing module generates BE frame data of no less than 100KB / s, which affects the output of TT frame data of the data acquisition device, i.e., UDP jitter occurs.
10. A data communication system for a launch vehicle telemetry system according to claim 1, characterized in that, Data is transmitted between the receiving SoC module and the receiving FPGA module via the EMIF bus.