A power prediction method based on two-stage excitation and MAXIMUM SDF Hamming characteristics

Abstract

This invention provides a power consumption prediction method based on dual-stage excitation and MAXIMUM SDF Hamming features. The method includes constructing interface files and test platform files, verifying the correctness of the interface files, and then generating a synthesized netlist file and delay file by importing library files, reference circuit netlist files, interface files, and test platform files. The delay file is read and Hamming distances between adjacent cycles are statistically output using dual-stage excitation at the rising edge of the clock. Finally, the Hamming distances and flipped Hamming distances of the signals are extracted from the VCD file, and power consumption regression analysis is performed to output the actual power consumption and the predicted power consumption or relative power consumption. This invention is applicable to power consumption prediction of RTL-level circuits and gate-level circuits, and can provide early rapid evaluation and high-precision prediction in the later stages.

Description

Technical Field

[0001] This invention relates to the field of power consumption prediction methods, and more particularly to a power consumption prediction method based on two-stage excitation and MAXIMUM SDF Hamming features. Background Technology

[0002] As the complexity of integrated circuit (IC) design continues to increase, the need to predict power consumption during the design and verification process has become increasingly urgent. Accurate power consumption estimation is crucial for optimizing IC performance, efficiency, and reliability, especially under conditions of increasing design complexity and stricter power constraints. Machine learning-based power prediction can address the early identification and mitigation of excessive power consumption in benchmark circuits, thereby reducing costs.

[0003] Reference circuits are mainly divided into two types: RTL-level circuits and gate-level circuits. RTL-level circuits represent an abstract level in digital circuit design, primarily describing data transfer between registers and combinational logic operations. Gate-level circuits are the concrete implementation level in digital circuit design, composed of basic logic gates (such as AND gates, OR gates, NOT gates, etc.). The accuracy of RTL-level power prediction is generally lower than that of gate-level prediction because RTL-level models do not consider all physical implementation details. Gate-level power prediction typically requires a longer runtime, especially in large-scale designs, resulting in high costs, long cycles, and increased power consumption.

[0004] Traditional "total switching rate" features are coarse and fail to characterize the switching behavior of specific signals in adjacent cycles; under random excitation, active signals exhibit large jitter and unstable errors. Traditional methods based on analog or switching counts have limitations in predicting power consumption, failing to fully capture the true behavioral changes of signals under certain high-frequency and sensitive operations. These methods are relatively coarse, making it difficult to characterize the switching behavior of specific signals in adjacent cycles, resulting in large fluctuations and insufficient stability in prediction results. Summary of the Invention

[0005] Purpose of the invention: The purpose of this invention is to provide a power consumption prediction method based on two-stage excitation and MAXIMUM SDF Hamming features to solve the problem of large fluctuations in active signals under traditional random excitation, improve the accuracy of active signal values, and realize realistic gate delay simulation.

[0006] Technical solution: The power consumption prediction method of the present invention includes:

[0007] S1. Read the input signals, output signals, and CK signals from the netlist file, and construct the interface file and test platform file;

[0008] S2. Verify the correctness of the interface / excitation in the interface file and output a waveform file in FSDB format;

[0009] S3. By importing library files, reference circuit netlist files, interface files, and test platform files, simulate and generate the logic synthesized netlist file, delay file, and constraint file.

[0010] S4. Read the delay file, use dual-stage excitation and count the Hamming distance between adjacent cycles at the rising edge of the clock, while masking the X / Z state and exporting the FSDB waveform file.

[0011] S5. Convert the FSDB waveform file to a VCD file;

[0012] S6. Extract the Hamming distance of the input signal, output signal, and CK signal from the VCD file periodically, and the flip Hamming distance between the current output and the previous output, ignoring the X / Z state, and output a CSV file.

[0013] S7. Use the PTPX tool to obtain the actual power consumption of the netlist file;

[0014] S8. Perform power consumption regression analysis based on CSV files, and output the actual power consumption and predicted power consumption or relative power consumption.

[0015] Furthermore, the interface file described in step S1 includes definitions of input signals and output signals, mapping the inputs and outputs of the netlist file of the reference circuit to the interface file to simplify the interface.

[0016] Further, the test platform file mentioned in step S1 is used to generate input stimuli and capture output responses. The input stimuli adopt a switching activity to determine the number of flips caused by the stimuli. The Hamming distance between consecutive output states is calculated by comparing the previous signal with the next signal. Finally, the obtained signal is converted into waveform data and dumped into a waveform file in FSDB format to view the waveform signal and observe the changes in Hamming eigenvalues ​​and the total number of flips.

[0017] Further, the target library, link library, synthesis library, and symbol library in the library file described in step S3 are read, and the netlist file and the constructed interface file and test platform file are combined to generate the netlist file and delay file after logic synthesis through simulation.

[0018] Further, in step S4, the first stage of the dual-stage excitation applies a completely random input vector for at least 25,000 clock cycles to the circuit under test; the second stage pre-generates 1,000 to 2,000 fixed random vectors, applies them sequentially, and counts the Hamming distance between adjacent cycles; during the sampling stage, all bits with X / Z in the current or previous clock cycle are skipped directly, and only the bits with 0 / 1 are counted to generate the fixed random vectors and store them in an array; an SDF module is added to load the synthesis delay file using the MAXIMUM angle, and an FSDB waveform capture module is added to generate waveforms that support Verdi debugging; and the excitation and delay synchronization module ensures that the excitation and delay are in the same simulation environment.

[0019] Further, in step S5, the FSDB waveform file is converted into a VCD file using the fsdb2vcd command.

[0020] Further, step S7 includes:

[0021] Set the top-level netlist name, the path to the netlist file generated after logic synthesis, the path to the constraint file generated after logic synthesis, the path to the additional constraint file to be built, and the path to the VCD file converted from the FSDB waveform file.

[0022] The path for configuring library files;

[0023] Connect all necessary libraries, read them in the PTPX tool in the order of reading the technology library, reading the netlist, and reading the timing constraints, then open the power analysis and parse the VCD file to update the power consumption value, and output the actual power consumption report.

[0024] Furthermore, the power consumption regression analysis described in step S8 uses linear regression or XGBoost algorithm to train the Hamming distance features, generates predicted power consumption, compares the actual power consumption obtained using the PTPX tool with the predicted power consumption, and evaluates the model performance using mean squared error (MSE) and coefficient of determination (R²).

[0025] Beneficial effects: Compared with the prior art, the present invention has the following significant advantages: By extracting Hamming distance features from clock, input and output signals, analyzing bit transitions and incorporating excitation and delay signals into the test platform file, it can better solve the problem of large fluctuations in switching activity signals under random excitation of traditional signals, and improve the accuracy of switching activity signals, thereby better correlated with dynamic power consumption and generating more accurate predictions; Compared with the traditional total switching rate, the periodic Hamming feature is more strongly correlated with dynamic power consumption under MAX SDF, and the two-stage excitation can significantly reduce sample variance, thereby making the prediction more stable. Attached Figure Description

[0026] Figure 1A flowchart illustrating the power consumption prediction method provided in an embodiment of the present invention;

[0027] Figure 2 This is a schematic diagram illustrating the specific process of the power consumption prediction method provided in this embodiment of the invention;

[0028] Figure 3 This is a waveform diagram generated by the present invention based on the reference circuit netlist file, test platform file, and interface file;

[0029] Figure 4 This is a waveform diagram generated by the present invention based on the netlist file, delay file, test platform file, and simulation file of the simulation library after logic synthesis. Detailed Implementation

[0030] The technical solution of the present invention will be further described below with reference to the accompanying drawings.

[0031] To address the technical challenges of traditional power prediction methods, such as coarse total switching rate characteristics, large activity jitter under random excitation, low accuracy of RTL-level power prediction, and long gate-level power prediction time, and to achieve improved prediction accuracy, computational efficiency, and scalability for complex designs, such as… Figure 1 As shown, this invention creatively proposes a power prediction method based on dual-stage excitation and MAXIMUM SDF Hamming features. By reading and analyzing two-level netlists and simulated waveforms (FSDB / VCD), key features such as the Hamming distance of the output / interface are extracted at the periodic boundary of the clock rising edge, effectively capturing the actual signal transition behavior, thus significantly improving prediction accuracy compared to general switching counts. An automated test platform is built through configurable interface files and a test platform (supporting dual-stage excitation and MAX angle SDF back-indexing), unifying the simplified workflow of simulation, waveform conversion, feature extraction, and machine learning regression, minimizing costs. It is compatible with various reference circuits and modules, and its parameterization is transferable, meeting the dual needs of early rapid evaluation and later high-precision prediction.

[0032] Please refer to Figure 2 The power consumption prediction method includes the following steps:

[0033] S1. Read the input signals, output signals, and CK signals from the netlist file, and construct the interface file and test platform file.

[0034] Specifically, the interface file defines input and output signals, mapping the inputs and outputs of the reference circuit's netlist file to the interface file, thus simplifying the interface. The testbench file mainly defines the clock signal, input and output signals, storage of the previous output value, Hamming distance calculation variables, and the total number of toggle cycles.

[0035] For example, a 30,000-cycle test is first used to prevent the circuit from starting with all zeros and to reduce the activity rate. After waiting 5µs for all signals to stabilize, the test cycle is executed to display the output and Hamming distance for each cycle. Finally, the number of toggle cycles is displayed to end the simulation. An excitation signal is added to apply a completely random input vector to the circuit under test for at least 25,000 clock cycles. 1,000 to 2,000 fixed random vectors are pre-generated, applied sequentially, and the Hamming distance between adjacent cycles is counted. X / Z masking is performed; during the sampling phase, all bits with X / Z present in the current or previous cycle are skipped, and only pure 0 / 1 bits are counted. Only when the current bit and the bit from the previous cycle are both 0 or 1 are allowed to enter the internal processing; all bits involving X / Z in the current or previous cycle are skipped and not counted in the toggle statistics. Finally, the fixed random vectors are generated using {$random} and stored in an array.

[0036] Traditional power estimation techniques count switches from VCD files or simulation-based analyses, typically relying on general switching activity metrics that fail to capture specific signal behavior. This invention extracts Hamming distance features from clock, input, and output signals, performs more detailed analysis of bit transitions, and incorporates excitation and delay signals into the test platform file. This better addresses the problem of large fluctuations in switching activity signals under random excitation, improving the accuracy of switching activity signals. The technical solution provided by this invention correlates better with dynamic power consumption, resulting in more accurate predictions. Compared to traditional total switching rate, periodic Hamming features are more strongly correlated with dynamic power consumption under MAX SDF; dual-stage excitation significantly reduces sample variance, leading to more stable predictions.

[0037] S2. Verify the correctness of the interface / excitation in the interface file, and output a waveform file in FSDB format for easy waveform verification.

[0038] Specifically, the verification process ensures that the input and output signals defined in the interface file correspond correctly to the signals in the reference circuit netlist file, thus guaranteeing the accuracy of subsequent simulations.

[0039] For example, waveform data can be recorded in FSDB format by writing $fsdbDumpfile and $fsdbDumpvars in the test platform file, as shown in the attached figure. Figure 3 As shown, the waveform graph allows you to view the values ​​of din, dout, hamming, and total_flip, providing a better view of the dynamic transformations in the netlist file and facilitating subsequent power consumption calculations and predictions.

[0040] S3. By importing library files, reference circuit netlist files, interface files, and test platform files, simulate and generate the synthesized netlist file, delay file, and constraint file.

[0041] Specifically, it mainly involves the synthesis configuration files of Synopsys Design Compiler, which include the settings for the target library, link library, symbol library, and synthesis library. Then, it reads the netlist file of the reference circuit and the interface file for building the design using S1, and finally generates the netlist file, delay file, and delay file after logic synthesis. The delay file can be understood as the file generated after logic synthesis, which is generated by customizing a delay information.

[0042] S4. Read the delay file, use dual-stage excitation and output Hamming distance between adjacent cycles at the rising edge of the clock, while masking the X / Z state, and export the FSDB waveform file.

[0043] Specifically, using `$sdf_annotate(...,"MAXIMUM")`, a two-stage excitation is performed. At the rising edge of CK, the Hamming distance between adjacent cycles is calculated by sampling the offset time, and X / Z is masked, exporting the FSDB waveform file. Based on the netlist and delay files generated in step S3, the interface file and the base circuit's netlist file are replaced with the netlist file generated after logic synthesis. The generated delay file is then imported into the test platform file. This step is based on step S2, adding the delay file within it. The main code is `$sdf_annotate(" ",uut, , , "MAXIMUM")`, used to load the standard delay format (SDF) file for post-simulation timing verification. The generated waveform is shown in the attached figure. Figure 4 As shown in the figure, the running results are generated as shown in Table 1 below.

[0044] Table 1: Results of Hamming eigenvalue simulation

[0045] circuit Sample size Total number of flips Average period Maximum number of loops Switching activity rate Traditional switching rate S1423 1200 1715 1.43 5 28.6% 21.8%

[0046] S5. Convert the FSDB waveform file to a VCD file.

[0047] Specifically, the fsdb2vcd command is used to convert FSDB waveform files into VCD files that can be used for feature extraction, facilitating subsequent processing and analysis.

[0048] S6. Extract the Hamming distance of the input signal, output signal, and CK signal from the VCD file periodically, and the flip Hamming distance between the current output and the previous output, ignoring the X / Z state, and output a CSV file.

[0049] Specifically, the CK / IN / OUT identifiers are precisely mapped from the VCD file, and ham_dout_flip, ham_din_dout, time_s, etc. are extracted periodically, ignoring the X / Z states, and a CSV file is output. ham_dout_flip can be understood as the total number of different items between the previous and current output values, ham_din_dout as the total number of different items between the current input and output, and time_s as the runtime between the previous and current feature values.

[0050] For example, the process reads a VCD file, extracts specific signals, verifies and processes these signals to determine their correctness, and finally converts the raw waveform data into a structured tabular data CSV file. Python's main functions include parsing standard VCD file formats, extracting signal definitions and timing data, supporting automatic time scale identification, sampling timing and data input / output bit widths, calculating the Hamming distance between input (din) and output (dout) and the flipped Hamming distance between the current output and the previous output, and ignoring unknown values ​​(X / Z).

[0051] S7. Obtain the actual power consumption using the PTPX tool. First, set the top-level netlist name, then set the path of the netlist file (.v) generated after logic synthesis, then set the path of the constraint file (.sdc) generated after logic synthesis, then set the path of the additional constraint file (.tcl) you wrote, then set the path of the VCD file converted from the FSDB file, and then configure the library files (including the main process library .db and the process library .lib).

[0052] Connect all the necessary libraries, read them in the PTPX tool in the order of reading the technology library, reading the netlist, and reading the timing constraints, then open the power analysis tool to parse the VCD file to update the power consumption value, and finally output the actual power consumption report.

[0053] S8. Perform power consumption regression analysis based on CSV files, and output the actual power consumption and predicted power consumption or relative power consumption.

[0054] Specifically, power regression is performed based on CSV files, outputting the actual power consumption plus the predicted power consumption, or the relative power consumption and optional linear calibration when there are no labels. In this process, based on the CSV files generated by feature extraction, the power regression analysis uses linear regression or XGBoost algorithms to train the Hamming distance features, generating CSV files of accurate power consumption and predicted power consumption. The actual power consumption and predicted power consumption are compared using the PTPX tool, and the model performance is evaluated using mean squared error (MSE) and coefficient of determination (R²).

[0055] Traditional methods require extensive logic simulations or iterative power analysis, which is computationally intensive for large-scale designs. The technical solution provided in this invention reduces processing time and resource requirements by integrating FSDB generation, netlist synthesis, VCD conversion, and machine learning into a streamlined workflow. Hamming distance features simplify feature extraction, while machine learning efficiently processes these features to provide rapid predictions. Training can be completed with a minimal feature set, reducing the cost of large-scale signal screening. Simultaneously, standard EDA tools are utilized in conjunction with a novel feature extraction process. This ensures scalability, enabling the handling of increasing IC complexity without sacrificing accuracy or efficiency. It supports early RTL operation and later accuracy upgrades with SDF; the interface / test platform can be reused for different reference circuits.

[0056] The technical solution provided by this invention is applicable to power consumption prediction of RTL-level circuits and gate-level circuits, and can provide early rapid evaluation and high-precision prediction in later stages. In the early stages of circuit design, this method can be used to estimate the power consumption of the circuit, helping designers to identify and optimize power consumption problems early. In the later stages of circuit design, this method can provide more accurate power consumption prediction, providing a reliable reference for the power consumption performance of the final product.

[0057] In practical applications, the two-stage excitation strategy ensures full activation of the circuit state. The first stage's random input vector enables the circuit to reach a stable operating state, while the second stage's fixed random vector guarantees the repeatability and comparability of the test results. By statistically analyzing the Hamming distance between adjacent cycles at the rising edge of the clock, the state changes of the circuit during operation can be accurately captured, providing key features for power consumption prediction. Simultaneously, the extraction and analysis process of the MAXIMUM SDF Hamming features ensures the accuracy and reliability of power consumption prediction. Through Hamming distance analysis of the input signal, output signal, and clock signal, the dynamic power consumption characteristics of the circuit under different operating conditions can be effectively captured, providing effective feature data for subsequent power consumption regression analysis.

Claims

1. A power consumption prediction method based on two-stage excitation and MAXIMUM SDF Hamming features, characterized in that, include: S1. Read the input signals, output signals, and CK signals from the netlist file, and construct the interface file and test platform file; S2. Verify the correctness of the interface / excitation in the interface file and output a waveform file in FSDB format; S3. By importing library files, reference circuit netlist files, interface files, and test platform files, simulate and generate the synthesized netlist files, delay files, and constraint files. S4. Read the delay file, use dual-stage excitation and count the Hamming distance between adjacent cycles at the rising edge of the clock, while masking the X / Z state and exporting the FSDB waveform file. The two-stage incentive includes: First stage: Apply a completely random input vector with a preset clock cycle to the circuit under test; Second stage: Pre-generate a fixed random vector, apply it sequentially and count the Hamming distance of adjacent cycles; mask the bits with X / Z states in the current or previous cycle, only count the bits with 0 / 1 states, generate a fixed random vector and store it in an array; S5. Convert the FSDB waveform file to a VCD file; S6. Extract the Hamming distance of the input signal, output signal, and CK signal from the VCD file periodically, and the flip Hamming distance between the current output and the previous output, ignoring the X / Z state, and output a CSV file. S7. Use the PTPX tool to obtain the actual power consumption of the netlist file; S8. Perform power consumption regression analysis based on CSV files, and output the actual power consumption and predicted power consumption or relative power consumption.

2. The power consumption prediction method according to claim 1, characterized in that, The interface file mentioned in step S1 contains definitions of input signals and output signals, and maps the inputs and outputs of the netlist file of the reference circuit to the interface file to simplify the interface.

3. The power consumption prediction method according to claim 1, characterized in that, The test platform file mentioned in step S1 is used to generate input stimuli and capture output responses. The input stimuli adopt a switching activity to determine the number of flips caused by the stimuli. The Hamming distance between consecutive output states is calculated by comparing the previous signal with the next signal. Finally, the obtained signal is converted into waveform data and dumped into a waveform file in FSDB format to view the waveform signal and observe the changes in Hamming eigenvalues ​​and the total number of flips.

4. The power consumption prediction method according to claim 1, characterized in that, Read the target library, link library, synthesis library, and symbol library from the library file described in step S3, and combine them with the netlist file, the constructed interface file, and the test platform file to perform simulation to generate the netlist file and delay file after logic synthesis.

5. The power consumption prediction method according to claim 1, characterized in that, In step S4, the first stage of the dual-stage excitation applies a completely random input vector for at least 25,000 clock cycles to the circuit under test; the second stage pre-generates 1,000 to 2,000 fixed random vectors, applies them sequentially, and counts the Hamming distance between adjacent cycles; during the sampling stage, all bits with X / Z in the current or previous clock cycle are skipped directly, and only the 0 / 1 bits are counted to generate the fixed random vectors and store them in an array; an SDF module is added to load the synthesis delay file with the MAXIMUM angle, and an FSDB waveform capture module is added to generate waveforms that support Verdi debugging; to ensure that the excitation and delay synchronization module can make the excitation and delay in the same simulation environment.

6. The power consumption prediction method according to claim 1, characterized in that, Step S5 uses the fsdb2vcd command to convert the FSDB waveform file into a VCD file.

7. The power consumption prediction method according to claim 1, characterized in that, Step S7 includes: Set the top-level netlist name, the path to the netlist file generated after logic synthesis, the path to the constraint file generated after logic synthesis, the path to the additional constraint file to be built, and the path to the VCD file converted from the FSDB waveform file. The path for configuring library files; Connect all necessary libraries, read them in the PTPX tool in the order of reading the technology library, reading the netlist, and reading the timing constraints, then open the power analysis and parse the VCD file to update the power consumption value, and output the actual power consumption report.

8. The power consumption prediction method according to claim 1, characterized in that, The power consumption regression analysis described in step S8 uses linear regression or XGBoost algorithm to train the Hamming distance features, generates predicted power consumption, compares the actual power consumption obtained using the PTPX tool with the predicted power consumption, and evaluates the model performance using mean squared error (MSE) and coefficient of determination (R²).

9. The power consumption prediction method according to claim 1, characterized in that, This method is applicable to power consumption prediction for both RTL-level and gate-level circuits, providing rapid early assessment and high-precision later prediction.

10. A computer-readable storage medium, characterized in that, It stores program code that, when executed by a processor, implements the power consumption prediction method as described in any one of claims 1 to 9.

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