Semiconductor device layout, verification method thereof and semiconductor device
By combining standard parametric cells and design rule check files, the critical film dimensions of semiconductor device layouts are automatically verified, overcoming the shortcomings of manual verification and enabling the design of semiconductor devices with smaller area and higher density.
Patent Information
- Application Number
- CN202511715302.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-20
- Publication Date
- 2026-02-13
AI Technical Summary
In existing technologies, minimum value verification of semiconductor device layout relies on manual control, making it difficult to ensure that semiconductor devices meet minimum requirements, which affects chip area and product competitiveness.
By providing standard parameterized units, key film layer patterns are selected to perform preset deformation operations. The patterns are verified by checking the design rules and determining the target size of the key film layers to ensure that the film layer spacing in the semiconductor device layout meets the preset minimum value.
While ensuring performance, we can reduce the layout area of semiconductor devices, increase the device density of chips in a limited space, and enhance product competitiveness.
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Figure CN121525601A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular, to a semiconductor device layout and a verification method thereof, and a semiconductor device. BACKGROUND
[0002] In the technical field of semiconductor manufacturing, a parameterized cell library (pcell) is a process library file indispensable for each chip process development package, and is usually used for designing a layout by a research and development engineer.
[0003] The size of a semiconductor device directly affects the size of a chip area and the competitiveness of a product. However, the verification of the minimum value of the semiconductor device in the parameterized cell library still relies on manual control by the research and development engineer.
[0004] Therefore, how to ensure that the semiconductor device layout meets the minimum value requirement becomes a problem to be solved. SUMMARY
[0005] Based on this, the embodiments of the present application provide a semiconductor device layout and a verification method thereof, and a semiconductor device.
[0006] According to some embodiments, the present application provides a verification method of a semiconductor device layout, the method comprising:
[0007] providing a standard parameterized cell as a layout pattern of a plurality of film layers in the semiconductor device layout;
[0008] selecting a key film layer pattern in the layout pattern of the plurality of film layers to perform a preset deformation operation to obtain a verification pattern;
[0009] providing a design rule check file, the design rule check file including a preset minimum value of the spacing between the plurality of film layer patterns in the semiconductor device layout;
[0010] verifying the verification pattern according to the design rule check file, and determining a target size of the key film layer according to the verification result of the verification pattern.
[0011] In the verification method of the semiconductor device layout in the above embodiments, by selecting a key film layer pattern in the layout pattern of the plurality of film layers to perform a preset deformation operation to obtain a verification pattern, and then verifying the verification pattern according to the design rule check file, and determining a target size of the key film layer according to the verification result of the verification pattern, in this way, on the basis of ensuring the performance of the semiconductor device, it can be ensured that the target size of the key film layer in the obtained verification pattern meets the preset minimum value of the spacing between the plurality of film layer patterns in the semiconductor device layout in the design rule check file, so as to minimize the area of the semiconductor device layout as much as possible, which is conducive to the research and development engineer to place more semiconductor devices in the limited area of the layout, thereby improving the competitiveness of the product.
[0012] In some embodiments, the preset deformation operation is performed on the key film layer pattern to obtain a verification pattern, including:
[0013] The preset deformation operation is performed on the key film layer pattern to obtain a verification pattern;
[0014] In some embodiments, the preset deformation operation is performed on the key film layer pattern to obtain a verification pattern, including:
[0015] The preset deformation operation is performed on the key film layer pattern to obtain a verification pattern.
[0016] In some embodiments, the verification pattern is verified according to the design rule check file, and a target size of the key film layer is determined according to a verification result of the verification pattern, including:
[0017] whether a distance between the verification pattern and a sidewall of a layout pattern of a film layer adjacent to the verification pattern is greater than a preset minimum value;
[0018] If not, the preset deformation operation is performed again on the key film layer pattern to obtain a new verification pattern, and the new verification pattern is verified again according to the design rule check file; if yes, the verification result of the verification pattern is output as the target size of the key film layer.
[0019] In some embodiments, the plurality of film layers include a first doped layer, a second doped layer, a first active layer, a second active layer, a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer; the first doped layer and the second doped layer are arranged horizontally and spaced apart; the first active layer is located on the first doped layer; the first active layer is located on the second doped layer; the semiconductor layer is located on at least the second active layer, and the semiconductor layer has an extension in a vertical direction; the first conductive layer is located on the first active layer, the second conductive layer is located on the extension of the semiconductor layer, the third conductive layer and the fourth conductive layer are located on the second active layer, and are located on both sides of the semiconductor layer;
[0020] The first preset minimum value a of the interval between the sidewall opposite to the layout pattern of the semiconductor layer and the layout pattern of the second conductive layer, the second preset minimum value b of the interval between the sidewall opposite to the layout pattern of the second active layer and the layout pattern of the second conductive layer, the third preset minimum value c of the interval between the sidewall opposite to the layout pattern of the semiconductor layer and the layout pattern of the second active layer, the fourth preset minimum value d of the interval between the sidewall opposite to the layout pattern of the semiconductor layer and the layout pattern of the second conductive layer, the fifth preset minimum value e of the interval between the sidewall opposite to the layout pattern of the second active layer and the layout pattern of the third conductive layer, the sixth preset minimum value f of the interval between the sidewall opposite to the layout pattern of the second active layer and the layout pattern of the second doped layer, the seventh preset minimum value g of the interval between the sidewall opposite to the layout pattern of the first active layer and the layout pattern of the first doped layer, and the eighth preset minimum value h of the interval between the sidewall opposite to the layout pattern of the first active layer and the layout pattern of the second active layer are included in the design rule checking file.
[0021] In some embodiments, the preset deformation operation is performed on a key film layer pattern in the layout pattern of the plurality of film layers to obtain a verification pattern, including:
[0022] The layout pattern of the first active layer is selected as the key film layer pattern to perform the preset deformation operation to obtain a first verification pattern.
[0023] The layout pattern of the second active layer is selected as the key film layer pattern to perform the preset deformation operation to obtain a second verification pattern.
[0024] Whether the interval between the sidewall opposite to the layout pattern of the adjacent film layer of the verification pattern and the layout pattern of the verification pattern is greater than the preset minimum value is verified, and the target size of the key film layer is determined according to the verification result of the verification pattern, including:
[0025] Whether the interval between the sidewall opposite to the layout pattern of the second conductive layer and the second verification pattern is greater than the second preset minimum value b is verified.
[0026] Whether the interval between the sidewall opposite to the layout pattern of the semiconductor layer and the second verification pattern is greater than the third preset minimum value c is verified.
[0027] Whether the interval between the sidewall opposite to the layout pattern of the third conductive layer and the second verification pattern is greater than the fifth preset minimum value e is verified.
[0028] Whether the interval between the sidewall opposite to the layout pattern of the second doped layer and the second verification pattern is greater than the sixth preset minimum value f is verified.
[0029] Whether the interval between the sidewall opposite to the layout pattern of the first doped layer and the first verification pattern is greater than the seventh preset minimum value g is verified.
[0030] Whether the interval between the sidewall opposite to the second verification pattern and the first verification pattern is greater than the eighth preset minimum value h is verified.
[0031] If all the verification results in the above verification operation are no, the preset deformation operation is performed again on the key film layer pattern to obtain a new first verification pattern and a new second verification pattern, and the first verification pattern and the second verification pattern are verified again according to the design rule check file; if any verification result in the above verification operation is yes, the verification result of the first verification pattern and the second verification pattern is output as the target size of the first active layer and the second active layer.
[0032] In some embodiments, the preset deformation operation is performed on a key film layer pattern in a plurality of film layer layout patterns to obtain a verification pattern, including:
[0033] The preset deformation operation is performed on a layout pattern of the semiconductor layer as the key film layer pattern to obtain the verification pattern;
[0034] The distance between the verification pattern and the sidewall of the layout pattern of the adjacent film layer is verified whether it is greater than a preset minimum value, and the target size of the key film layer is determined according to the verification result of the verification pattern, including:
[0035] The distance between the verification pattern and the sidewall of the layout pattern of the second conductive layer is verified whether it is greater than a first preset minimum value a;
[0036] The distance between the verification pattern and the sidewall of the layout pattern of the second active layer is verified whether it is greater than a third preset minimum value c;
[0037] The distance between the verification pattern and the sidewall of the layout pattern of the second conductive layer is verified whether it is greater than a fourth preset minimum value d;
[0038] If all the verification results in the above verification operation are no, the preset deformation operation is performed again on the key film layer pattern to obtain a new verification pattern, and the verification pattern is verified again according to the design rule check file; if any verification result in the above verification operation is yes, the verification result of the verification pattern is output as the target size of the semiconductor layer.
[0039] In some embodiments, the preset deformation operation is performed on a key film layer pattern in a plurality of film layer patterns to obtain a verification pattern, including:
[0040] The boundary line of the key film layer pattern is obtained, the boundary line of the key film layer pattern is expanded outward by a preset distance in sequence, and the verification pattern is enclosed;
[0041] In some embodiments, the preset deformation operation is performed on a key film layer pattern in a plurality of film layer patterns to obtain a verification pattern, including:
[0042] The boundary line of the key film layer pattern is obtained, the boundary line of the key film layer pattern is expanded outward by a preset distance in sequence, and the verification pattern is enclosed;
[0043] In some embodiments, the preset distance is 0.001 grid.
[0044] According to some embodiments, the present application further provides a semiconductor device layout, which is verified by the verification method of the semiconductor device layout in any of the above embodiments.
[0045] According to some embodiments, the present application further provides a semiconductor device, which is prepared based on the semiconductor device layout in any of the above embodiments. BRIEF DESCRIPTION OF DRAWINGS
[0046] Figure 1 A flowchart schematic diagram of a verification method of a semiconductor device layout according to an embodiment of the present application;
[0047] Figure 2 A schematic diagram of a semiconductor device layout in a verification method of a semiconductor device layout according to an embodiment of the present application;
[0048] Figure 3 A schematic diagram of a layout obtained in step S01 and step S302 in a verification method of a semiconductor device layout according to an embodiment of the present application;
[0049] Figure 4 A schematic diagram of a layout obtained in step S303 in a verification method of a semiconductor device layout according to an embodiment of the present application;
[0050] Figure 5 A schematic diagram of a layout obtained in step S71a to step S71f in a verification method of a semiconductor device layout according to an embodiment of the present application;
[0051] Figure 6 A schematic diagram of a layout obtained in step S72a to step S72c in a verification method of a semiconductor device layout according to an embodiment of the present application.
[0052] Reference signs: 11, first doped layer; 12, second doped layer; 21, first active layer; 22, second active layer; 30, semiconductor layer; 41, first conductive layer; 42, second conductive layer; 43, third conductive layer; 44, fourth conductive layer. DETAILED DESCRIPTION
[0053] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.
[0054] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description herein is for describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.
[0055] In the case of "comprising", "having", "including", and "containing", specific embodiments are foreseen and can be prepared by means which are presently or future known, unless otherwise explicitly defined herein. In the description herein, relative terms are used to describe one structural feature in relation to the other structural feature. These relative terms are intended to encompass different positional relationships between the structural features depending on the context in which they are used. For example, if a structural feature is referred to as being "above" or "on" another structural feature, it can be directly above or on the other structural feature or there can be one or more intervening structural features. Conversely, if a structural feature is referred to as being "directly above" or "directly on" another structural feature, there can be no intervening structural features. It will be appreciated that, although terms such as first, second, third, and the like can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.
[0056] Furthermore, the thicknesses of the respective layers and regions in the drawings can be exaggerated for the purpose of clarity. When a portion of a layer, film, region, plate, etc. is said to be "on" another portion, this means that the portion can be directly on the other portion or there can be an intervening layer, film, region, plate, etc. between them. Also, it will be understood that when a portion of a layer, film, region, plate, etc. is said to be "on" another portion, it can be directly on the other portion or there can be an intervening layer, film, region, plate, etc. between them.
[0057] It will be understood that when an element or layer is referred to as being "on" or "adjacent" another element or layer, it can be directly on or adjacent the other element or layer or intervening elements or layers can also be present. In contrast, when an element is referred to as being "directly on" or "directly adjacent" another element or layer, there are no intervening elements or layers present. It will also be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.
[0058] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientations depicted in the figures. For example, if a device is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
[0059] Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present disclosure. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the present disclosure should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. The regions illustrated in the figures are schematic and many of the regions are not drawn to scale. Thus, the figures illustrate the relative positioning of the illustrated areas but not necessarily the actual placement of the areas relative to each other.
[0060] Based on this, the embodiments of the present application provide a semiconductor device layout and a verification method thereof, and a semiconductor device.
[0061] Referring to Figure 1 According to some embodiments, the present application provides a verification method of a semiconductor device layout. The verification method of the semiconductor device layout comprises the following steps.
[0062] In step S10, a standard parameterized cell is provided as a layout pattern of a plurality of film layers in the semiconductor device layout.
[0063] In step S30, a key film layer pattern in the layout pattern of the plurality of film layers is selected to perform a preset deformation operation to obtain a verification pattern.
[0064] In step S50, a design rule check file is provided, and the design rule check file includes a preset minimum value of a distance between the plurality of film layer patterns in the semiconductor device layout.
[0065] In step S70, the verification pattern is verified according to the design rule check file, and a target size of the key film layer is determined according to a verification result of the verification pattern.
[0066] In the semiconductor device layout verification method of the above embodiment, the key film layer pattern in the layout pattern of the plurality of film layers is selected to perform the preset deformation operation to obtain a verification pattern, the verification pattern is verified according to the design rule check file, and according to the verification result of the verification pattern, the target size of the key film layer is determined. In this way, on the basis of ensuring the performance of the semiconductor device, it can be ensured that the target size of the key film layer in the obtained verification pattern meets the preset minimum value of the spacing between the plurality of film layer patterns in the semiconductor device layout in the design rule check file, so as to minimize the area of the semiconductor device layout as much as possible. This is beneficial to the research and development engineers to place more semiconductor devices in the limited area of the layout, thereby improving the product competitiveness.
[0067] In the above embodiments of the present disclosure, unless otherwise specified herein, the execution of each step in the method does not have strict sequence limitation, and these steps can not necessarily be executed in the order described, and can be executed in other execution manners. Moreover, at least a part of each step can include a plurality of sub-steps or a plurality of stages, and these sub-steps or stages do not necessarily have to be executed at the same time, but can be executed at different times. Moreover, the execution sequence of these sub-steps or stages does not necessarily have to be sequential, but can be executed in rotation or alternation with other steps or at least a part of the sub-steps or stages of other steps.
[0068] In order to more clearly illustrate the semiconductor structure preparation method provided by the above embodiments, the following will combine Figures 1 to 6 The method is described in detail.
[0069] For example, in step S10, a standard parameter unit is provided as a layout pattern of a plurality of film layers in a semiconductor device layout. Different layout patterns can be created according to the names of different standard parameter units, and then placed in the semiconductor device layout in sequence.
[0070] In some embodiments, the semiconductor device can be a MOS tube.
[0071] For example, in step S10, a standard parameter unit is provided as a layout pattern of a plurality of film layers in a semiconductor device layout. Different layout patterns can be created according to the names of different standard parameter units, and then placed in the semiconductor device layout in sequence. Figure 2As shown, in some embodiments, the plurality of film layers include a first doped layer 11, a second doped layer 12, a first active layer 21, a second active layer 22, a semiconductor layer 30, a first conductive layer 41, a second conductive layer 42, a third conductive layer 43, and a fourth conductive layer 44; the first doped layer 11 and the second doped layer 12 are arranged horizontally at intervals; the first active layer 21 is located on the first doped layer 11; the first active layer 21 is located on the second doped layer 12; the semiconductor layer 30 is located at least on the second active layer 22, and the semiconductor layer 30 has an extension portion in the vertical direction; the first conductive layer 41 is located on the first active layer 21, the second conductive layer 42 is located on the extension portion of the semiconductor layer 30, and the third conductive layer 43 and the fourth conductive layer 44 are located on the second active layer 22 and are located on both sides of the semiconductor layer 30.
[0072] For example, the semiconductor layer 30 is made of polycrystalline silicon.
[0073] For example, the first doped layer 11 is N-type and the second doped layer 12 is P-type.
[0074] like Figure 3 As shown, in some embodiments, step S30, selecting key film layer patterns from the layout patterns of multiple film layers and performing a preset deformation operation to obtain a verification pattern, includes:
[0075] Step S301: Select the layout pattern of the first active layer 21 as the key film layer pattern and perform a preset deformation operation to obtain the first verification pattern.
[0076] Step S302: Select the layout pattern of the second active layer 22 as the key film layer pattern and perform a preset deformation operation to obtain the second verification pattern;
[0077] like Figure 4 As shown, in some other embodiments, step S30, selecting key film layer patterns from the layout patterns of multiple film layers and performing a preset deformation operation to obtain a verification pattern, includes:
[0078] Step S303: Select the layout pattern of semiconductor layer 30 as the key film layer pattern and perform a preset deformation operation to obtain the verification pattern.
[0079] Combination Figure 3 and Figure 4 To understand this, in some embodiments, step S30, selecting a key film pattern from multiple film patterns and performing a preset deformation operation to obtain a verification pattern, includes:
[0080] Step S31: Select the key membrane pattern from multiple membrane patterns and perform an enlargement operation to obtain a verification pattern.
[0081] In some embodiments, the step S31, the key film layer pattern in the plurality of film layer patterns is selected to perform the expanding operation to obtain the verification pattern, including:
[0082] The step S311, the boundary line of the key film layer pattern is acquired, and the boundary line of the key film layer pattern is expanded outward by a preset distance in sequence, and is enclosed into the verification pattern.
[0083] In combination Figure 3 With Figure 4 It is understood that, in some embodiments, the step S30, the key film layer pattern in the plurality of film layer patterns is selected to perform the preset deformation operation to obtain the verification pattern, including:
[0084] The step S32, the key film layer pattern in the plurality of film layer patterns is selected to perform the shrinking operation to obtain the verification pattern.
[0085] In some embodiments, the step S32, the key film layer pattern in the plurality of film layer patterns is selected to perform the shrinking operation to obtain the verification pattern, including:
[0086] The step S322, the boundary line of the key film layer pattern is acquired, and the boundary line of the key film layer pattern is reduced inward by a preset distance in sequence, and is enclosed into the verification pattern.
[0087] In some embodiments, the preset distance is 0.001 grid.
[0088] For example, in the step S50, the design rule checking file is provided, and the preset minimum value of the interval between the plurality of film layer patterns in the semiconductor device layout is included in the design rule checking file;
[0089] In some embodiments, the first preset minimum value a of the interval between the semiconductor layer 30 and the layout pattern opposite sidewall of the second conductive layer 42, the second preset minimum value b of the interval between the second active layer 22 and the layout pattern opposite sidewall of the second conductive layer 42, the third preset minimum value c of the interval between the semiconductor layer 30 and the layout pattern opposite sidewall of the second active layer 22, the fourth preset minimum value d of the interval between the semiconductor layer 30 and the layout pattern opposite sidewall of the second conductive layer 42, the fifth preset minimum value e of the interval between the third conductive layer 43 and the layout pattern opposite sidewall of the second active layer 22, the sixth preset minimum value f of the interval between the second active layer 22 and the layout pattern opposite sidewall of the second doped layer 12, the seventh preset minimum value g of the interval between the first active layer 21 and the layout pattern opposite sidewall of the first doped layer 11, and the eighth preset minimum value h of the interval between the first active layer 21 and the layout pattern opposite sidewall of the second active layer 22 are included in the design rule checking file.
[0090] In combination Figure 5 With Figure 6To understand this, in some embodiments, step S70, verifying the verification pattern according to the design rule check document, and determining the target size of the key film layer based on the verification result of the verification pattern, includes:
[0091] Step S701: Verify whether the distance between the verification pattern and the relative sidewalls of the pattern of the adjacent film layer is greater than the preset minimum value;
[0092] Step S702: If not, perform the preset deformation operation on the key film layer pattern again to obtain a new verification pattern, and verify the verification pattern again according to the design rule check document; if yes, output the verification result of the verification pattern as the target size of the key film layer.
[0093] like Figure 5 As shown, in the embodiment where the layout pattern of the first active layer 21 is selected as the key film layer pattern and a preset deformation operation is performed to obtain the first verification pattern, and the layout pattern of the second active layer 22 is selected as the key film layer pattern and a preset deformation operation is performed to obtain the second verification pattern, step S70, verifying whether the distance between the relative sidewalls of the verification pattern and the layout patterns of its adjacent film layers is greater than a preset minimum value, and determining the target size of the key film layer based on the verification result of the verification pattern, includes:
[0094] Step S71a: Verify whether the distance between the opposite sidewalls of the second verification pattern and the layout pattern of the second conductive layer 42 is greater than the second preset minimum value b;
[0095] Step S71b: Verify whether the distance between the opposite sidewalls of the second verification pattern and the layout pattern of the semiconductor layer 30 is greater than the third preset minimum value c;
[0096] Step S71c: Verify whether the distance between the opposite sidewalls of the second verification pattern and the layout pattern of the third conductive layer 43 is greater than the fifth preset minimum value e;
[0097] Step S71d: Verify whether the spacing between the opposite sidewalls of the second verification pattern and the layout pattern of the second doped layer 12 is greater than the sixth preset minimum value f;
[0098] Step S71e: Verify whether the distance between the opposite sidewalls of the first verification pattern and the layout pattern of the first doped layer 11 is greater than the seventh preset minimum value g;
[0099] Step S71f: Verify whether the distance between the opposite sidewalls of the first verification pattern and the second verification pattern is greater than the eighth preset minimum value h;
[0100] Step S71g, if all the verification results in the verification operations of steps S71a to S71f are no, performing the preset deformation operation on the critical film layer pattern again to obtain a new first verification pattern and a new second verification pattern, and verifying the first verification pattern and the second verification pattern again according to the design rule check file; if any of the verification results in the verification operations of steps S71a to S71f is yes, outputting the verification result of the first verification pattern and the second verification pattern as the target size of the first active layer 21 and the second active layer 22.
[0101] In some embodiments, in the embodiment in which the preset deformation operation is performed on the layout pattern of the semiconductor layer 30 as the critical film layer pattern to obtain the verification pattern, step S70, verifying whether the distance between the verification pattern and the sidewall of the layout pattern of the film layer adjacent to the verification pattern is greater than a preset minimum value, and determining the target size of the critical film layer according to the verification result of the verification pattern, comprises:
[0102] Step S72a, verifying whether the distance between the verification pattern and the sidewall of the layout pattern of the second conductive layer 42 is greater than a first preset minimum value a;
[0103] Step S72b, verifying whether the distance between the verification pattern and the sidewall of the layout pattern of the second active layer 22 is greater than a third preset minimum value c;
[0104] Step S72c, verifying whether the distance between the verification pattern and the sidewall of the layout pattern of the second conductive layer 42 is greater than a fourth preset minimum value d;
[0105] Step S72d, if all the verification results in the verification operations of steps S72a to S72c are no, performing the preset deformation operation on the critical film layer pattern again to obtain a new verification pattern, and verifying the verification pattern again according to the design rule check file; if any of the verification results in the verification operations of steps S72a to S72c is yes, outputting the verification result of the verification pattern as the target size of the semiconductor layer 30.
[0106] According to some embodiments, the present application further provides a semiconductor device layout, which is verified by the verification method of the semiconductor device layout in any of the above embodiments.
[0107] According to some embodiments, the present application further provides a semiconductor device, which is prepared based on the semiconductor device layout in any of the above embodiments
[0108] Any combination of the technical features in the above-described embodiments can be made, and for the sake of brevity, not all possible combinations are described, however, as long as there is no conflict, any combination of the technical features should be considered within the scope of the present disclosure.
[0109] The above-described embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the patent scope of the present application. It should be pointed out that, for ordinary skilled persons in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the patent protection scope of the present application should be subject to the appended claims.
Claims
1. A method for verifying the layout of a semiconductor device, characterized in that, The method includes: It provides standard parameterization units for use as layout patterns of multiple film layers in semiconductor device layouts; A preset deformation operation is performed on the key film layer pattern in the layout pattern of the multiple film layers to obtain a verification pattern; A design rule check file is provided, which includes a preset minimum value for the spacing between multiple film layer patterns in the semiconductor device layout; The verification pattern is verified according to the design rules check document, and the target size of the key film layer is determined based on the verification results of the verification pattern.
2. The method for verifying semiconductor device layout according to claim 1, characterized in that, The step of selecting a key film pattern from the plurality of film patterns and performing a preset deformation operation to obtain a verification pattern includes: Select a key film layer pattern from the plurality of film layer patterns and perform an enlargement operation to obtain a verification pattern; or A key membrane pattern among the multiple membrane patterns is selected and reduced in size to obtain a verification pattern.
3. The method for verifying semiconductor device layout according to claim 2, characterized in that, The step of verifying the verification pattern according to the design rule check document and determining the target size of the key film layer based on the verification result of the verification pattern includes: Verify whether the distance between the verification pattern and the relative sidewalls of the layout pattern of its adjacent film layer is greater than a preset minimum value; If not, then perform the preset deformation operation on the key film pattern again to obtain a new verification pattern, and verify the verification pattern again according to the design rule check document; if yes, then output the verification result of the verification pattern as the target size of the key film.
4. The method for verifying semiconductor device layout according to claim 3, characterized in that, The plurality of membrane layers include: A first doped layer and a second doped layer are arranged horizontally at intervals; The first active layer is located on the first doped layer; The second active layer and the first active layer are located on the second doped layer; A semiconductor layer, wherein the semiconductor layer is at least located on the second active layer, and the semiconductor layer has an extension in the vertical direction; The system comprises a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer. The first conductive layer is located on the first active layer, the second conductive layer is located on an extension of the semiconductor layer, and the third and fourth conductive layers are located on the second active layer and on both sides of the semiconductor layer. The design rule check document includes the following preset minimum values in the semiconductor device layout: a) a first preset minimum value a, b) a second preset minimum value b, c) a third preset minimum value c, d) a fourth preset minimum value d, e) a fifth preset minimum value e, f) a sixth preset minimum value f, g) a seventh preset minimum value g, and h) a fifth preset minimum value h.
5. The method for verifying semiconductor device layout according to claim 4, characterized in that, The step of selecting key film layer patterns from the layout patterns of the multiple film layers and performing a preset deformation operation to obtain a verification pattern includes: The layout pattern of the first active layer is selected as the key film layer pattern and a preset deformation operation is performed to obtain the first verification pattern. The layout pattern of the second active layer is selected as the key film layer pattern and a preset deformation operation is performed to obtain the second verification pattern; The verification process, which verifies whether the distance between the verification pattern and the relative sidewalls of the layout patterns of adjacent film layers is greater than a preset minimum value, and determines the target size of the key film layer based on the verification result of the verification pattern, includes: Verify whether the distance between the opposite sidewalls of the second verification pattern and the layout pattern of the second conductive layer is greater than the second preset minimum value b; Verify whether the distance between the opposite sidewalls of the second verification pattern and the layout pattern of the semiconductor layer is greater than a third preset minimum value c; Verify whether the distance between the opposite sidewalls of the second verification pattern and the layout pattern of the third conductive layer is greater than the fifth preset minimum value e; Verify whether the spacing between the opposite sidewalls of the second verification pattern and the layout pattern of the second doped layer is greater than a sixth preset minimum value f; Verify whether the distance between the opposite sidewalls of the first verification pattern and the layout pattern of the first doped layer is greater than the seventh preset minimum value g; Verify whether the distance between the opposite sidewalls of the first verification pattern and the second verification pattern is greater than the eighth preset minimum value h; If all verification results in the above verification operations are negative, then the preset deformation operation is performed again on the key film layer pattern to obtain a new first verification pattern and a new second verification pattern, and the first verification pattern and the second verification pattern are verified again according to the design rule check document; if any verification result in the above verification operations is positive, then the verification results of the first verification pattern and the second verification pattern are output as the target size of the first active layer and the second active layer.
6. The method for verifying semiconductor device layout according to claim 4, characterized in that, The step of selecting key film layer patterns from the layout patterns of the multiple film layers and performing a preset deformation operation to obtain a verification pattern includes: The layout pattern of the semiconductor layer is selected as the key film layer pattern and a preset deformation operation is performed to obtain the verification pattern; The verification process, which verifies whether the distance between the verification pattern and the relative sidewalls of the layout patterns of adjacent film layers is greater than a preset minimum value, and determines the target size of the key film layer based on the verification result of the verification pattern, includes: Verify whether the distance between the verification pattern and the layout pattern of the second conductive layer on opposite sidewalls is greater than a first preset minimum value a; Verify whether the distance between the verification pattern and the layout pattern of the second active layer relative to each other's sidewalls is greater than a third preset minimum value c; Verify whether the distance between the verification pattern and the layout pattern of the second conductive layer on opposite sidewalls is greater than a fourth preset minimum value d; If all verification results in the above verification operations are negative, then the preset deformation operation is performed again on the key film layer pattern to obtain a new verification pattern, and the verification pattern is verified again according to the design rule check file; if any verification result in the above verification operations is positive, then the verification result of the verification pattern is output as the target size of the semiconductor layer.
7. The method for verifying semiconductor device layout according to claim 2, characterized in that, The step of selecting a key film layer pattern from the plurality of film layer patterns and performing an enlargement operation to obtain a verification pattern includes: Obtain the boundary line of the key membrane pattern, and extend the boundary line of the key membrane pattern outward by a preset distance to form the verification pattern. The step of selecting a key membrane pattern from the plurality of membrane patterns and performing a reduction operation to obtain a verification pattern includes: Obtain the boundary line of the key membrane pattern, and sequentially reduce the boundary line of the key membrane pattern inward by a preset distance to form the verification pattern.
8. The method for verifying semiconductor device layout according to claim 7, characterized in that, The preset distance is 0.001grid.
9. A semiconductor device layout, characterized in that, Verification was performed using the semiconductor device layout verification method as described in any one of claims 1-8.
10. A semiconductor device, characterized in that, It is fabricated based on the semiconductor device layout as described in claim 9.