Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device, relates to the technical field of display, and is used for reducing the number of wires extending in a second direction in the display panel. In the display panel, a data line comprises a first data line, and the first data line is connected with a first pixel circuit and a second pixel circuit; the scanning line comprises a first sub-scanning line and a second sub-scanning line, the first sub-scanning line is connected with the first pixel circuit, and the second sub-scanning line is connected with the second pixel circuit; the display panel further comprises a first power supply signal line and an initialization signal line which are electrically connected with the pixel circuit. Wherein the display panel at least meets one of the following conditions: the first power supply signal lines extend along the second direction, and at least one first power supply signal line is arranged between adjacent first data lines along the first direction; or the initialization signal lines extend in the second direction, and at least one initialization signal line is arranged between every two adjacent first data lines in the first direction.

Description

Technical Field

[0001] This application relates to the field of display technology, and more specifically to a display panel and display device. Background Technology

[0002] With the continuous development of science and technology, more and more electronic devices with display functions are being widely used in people's daily lives and work, bringing great convenience and becoming an indispensable tool for people today. The main component of electronic devices that realizes the display function is the display panel.

[0003] Currently, display panels have the problem of having a large number of data cables. Summary of the Invention

[0004] In view of this, this application provides a display panel and a display device to reduce the number of data lines in the display panel.

[0005] In a first aspect, embodiments of this application provide a display panel, including: Subpixels, which include pixel circuitry and light-emitting elements; Scan lines are connected to pixel circuits and extend along a first direction. The data cable is connected to the pixel circuit and extends along a second direction, where the first and second directions intersect. The sub-pixel includes at least a first sub-pixel and a second sub-pixel. The first sub-pixel includes a first pixel circuit and a first light-emitting element. The second sub-pixel includes a second pixel circuit and a second light-emitting element. The first light-emitting element and the second light-emitting element emit different colors of light. The data line includes a first data line, which is connected to a first pixel circuit and a second pixel circuit; The scan line includes a first scan line, which includes a first sub-scan line and a second sub-scan line. The first sub-scan line is connected to a first pixel circuit, and the second sub-scan line is connected to a second pixel circuit. The display panel also includes a first power signal line and an initialization signal line. The first power signal line is connected to the pixel circuit, and the initialization signal line is also connected to the pixel circuit. The display panel must meet at least one of the following requirements: The first power signal line extends along the second direction, and along the first direction, at least one first power signal line is included between adjacent first data lines; or... The initialization signal line extends along the second direction, and along the first direction, there is at least one initialization signal line between adjacent first data lines.

[0006] Optionally, both the first power signal line and the initialization signal line extend along the second direction; Along the first direction, each adjacent first data line includes at least one first power signal line and at least one initialization signal line.

[0007] Optionally, the display panel includes pixels, and the pixels include at least a first sub-pixel and a second sub-pixel arranged along a first direction; Along the first direction, a first gap is included between the first pixel circuit and the second pixel circuit; The display panel must meet at least one of the following requirements; The first power signal line extends along a second direction, and along the first direction, at least one of the first data line and the first power signal line is located in a first gap; or... The initialization signal line extends along the second direction, and along the first direction, at least one of the first data line and the initialization signal line is located in the first gap.

[0008] Optionally, both the first power signal line and the initialization signal line extend along the second direction; Along the first direction, at least one of the first data line, the first power signal line, and the initialization signal line is located in the first gap.

[0009] Optionally, the display panel includes a first area and a second area; The display panel must meet at least one of the following requirements: The first power signal line extends along the second direction. Along the first direction, in the first region, adjacent first data lines are comprised of M1 first power signal lines, and in the second region, adjacent first data lines are comprised of M2 first power signal lines, where M1 > M2 ≥ 0; or... The initialization signal lines extend along the second direction and along the first direction. In the first region, there are N1 initialization signal lines between adjacent first data lines, and in the second region, there are N2 initialization signal lines between adjacent first data lines, where N1 > N2 ≥ 0.

[0010] Optionally, the display panel includes a first area and a second area; Both the first power signal line and the initialization signal line extend along the second direction; Along the first direction, in the first region, adjacent first data lines include MS1 first power signal lines and NS1 initialization signal lines. In the second region, adjacent first data lines include MS2 first power signal lines and NS2 initialization signal lines, wherein MS1≥0, NS1≥0, MS2≥0, and NS2≥0. The display panel must meet at least one of the following requirements: MS1 ≠ MS2; or, NS1 ≠ NS2.

[0011] Optionally, MS1 > MS2 ≥ 0, and 0 ≤ NS1 ≤ NS2.

[0012] Optionally, MS1 > MS2 ≥ 0, and NS1 ≥ MS2 ≥ 0.

[0013] Optionally, along the first direction, the width of the first data line is W1, the width of the first power signal line is W2, and the width of the initialization signal line is W3; wherein, The display panel must meet at least one of the following requirements: W1 < W2; or, W3 < W2.

[0014] Optionally, W2-W3>W3-W1≥0.

[0015] Optional, 0 ≤ W2 - W3 < W3 - W1.

[0016] Optionally, the sub-pixel also includes a third sub-pixel, which includes a third pixel circuit and a third light-emitting element. The first light-emitting element, the second light-emitting element, and the third light-emitting element emit different colors of light. The data line includes a second data line, which is connected to the third pixel circuit.

[0017] Optionally, the sub-pixel also includes a fourth sub-pixel, which includes a fourth pixel circuit and a fourth light-emitting element. The first light-emitting element, the second light-emitting element, the third light-emitting element, and the fourth light-emitting element emit different colors of light. The second data line is connected to the fourth pixel circuit.

[0018] Optionally, along the first direction, at least one second data line is included between adjacent first data lines; or, Along the first direction, there is at least one first data line between adjacent second data lines.

[0019] Optionally, the first power signal line extends along the second direction; Along the first direction, at least one first power signal line is included between adjacent first data lines and second data lines.

[0020] Optionally, the initialization signal line extends along the second direction; Along the first direction, at least one initialization signal line is included between adjacent first and second data lines.

[0021] Optionally, the first power signal line and the initialization signal line extend along the second direction; Along the first direction, at least one first power signal line is included between adjacent sets of first data lines and second data lines, and at least one initialization signal line is included between adjacent sets of first data lines and second data lines.

[0022] Optionally, the first power signal line and the initialization signal line extend along the second direction; Along the first direction, the first data line, the second data line, the first power signal line, and the initialization signal line are arranged in at least one of the following orders: First data line, first power signal line, second data line, initialization signal line; or, First data line, initialization signal line, second data line, first power signal line.

[0023] Optionally, the first power signal line and the initialization signal line extend along the second direction; Along the first direction, there is at least one first power signal line and at least one initialization signal line between adjacent first and second data lines.

[0024] Optionally, along the first direction, the first data line, the second data line, the first power signal line, and the initialization signal line are arranged in at least one of the following orders: First data line, first power signal line, initialization signal line, second data line; or, First data line, initialization signal line, first power signal line, second data line.

[0025] Optionally, the first power signal line and the initialization signal line extend along the second direction; Along the first direction, there is at least one first data line and one second data line between adjacent first power signal lines and initialization signal lines.

[0026] Optionally, along the first direction, the first data line, the second data line, the first power signal line, and the initialization signal line are arranged in at least one of the following orders: First power signal line, first data line, second data line, initialization signal line; or, First power signal line, second data line, first data line, initialization signal line; or, Initialize the signal line, first data line, second data line, and first power signal line; or, Initialize the signal line, second data line, first data line, and first power signal line.

[0027] Optionally, the display panel includes pixels, and the pixels include a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged along a first direction; Along the first direction, a first gap is included between the first pixel circuit and the second pixel circuit, a second gap is included between the second pixel circuit and the third pixel circuit, and a third gap is included between the third pixel circuit and the adjacent pixel circuit in another pixel; wherein, At least two of the first data line, the second data line, the first power signal line, and the initialization signal line are located in one of the first gap, the second gap, and the third gap.

[0028] Optionally, the display panel includes pixels, and the pixels include a first sub-pixel, a second sub-pixel, a third sub-pixel and a fourth sub-pixel arranged along a first direction; Along a first direction, a first gap is included between the first pixel circuit and the second pixel circuit, a second gap is included between the second pixel circuit and the third pixel circuit, a third gap is included between the third pixel circuit and the fourth pixel circuit, and a fourth gap is included between the fourth pixel circuit and the adjacent pixel circuit in another pixel; wherein, The first data line, the second data line, the first power signal line, and the initialization signal line are each located in one of the first gap, the second gap, the third gap, and the fourth gap, respectively.

[0029] Optionally, the display panel includes pixels, and the pixels include a first sub-pixel, a second sub-pixel, a third sub-pixel and a fourth sub-pixel arranged along a first direction; Along a first direction, a first gap is included between the first pixel circuit and the second pixel circuit, a second gap is included between the second pixel circuit and the third pixel circuit, a third gap is included between the third pixel circuit and the fourth pixel circuit, and a fourth gap is included between the fourth pixel circuit and the adjacent pixel circuit in another pixel; wherein, At least two of the first data line, the second data line, the first power signal line, and the initialization signal line are located in one of the first gap, the second gap, the third gap, and the fourth gap.

[0030] Optionally, the first light-emitting element emits red light, the second light-emitting element emits green light, and the third light-emitting element emits blue light. or, The first light-emitting element emits red light, the second light-emitting element emits blue light, and the third light-emitting element emits green light. or, The first light-emitting element emits green light, the second light-emitting element emits blue light, and the third light-emitting element emits red light.

[0031] Optionally, the first light-emitting element emits red light, the second light-emitting element emits green light, the third light-emitting element emits blue light, and the fourth light-emitting element emits white light; or... The first light-emitting element emits red light, the second light-emitting element emits blue light, the third light-emitting element emits green light, and the fourth light-emitting element emits white light; or, The first light-emitting element emits red light, the second light-emitting element emits white light, the third light-emitting element emits green light, and the fourth light-emitting element emits blue light; or, The first light-emitting element emits blue light, the second light-emitting element emits white light, the third light-emitting element emits red light, and the fourth light-emitting element emits green light; or, The first light-emitting element emits green light, the second light-emitting element emits white light, the third light-emitting element emits red light, and the fourth light-emitting element emits blue light; or, The first light-emitting element emits green light, the second light-emitting element emits blue light, the third light-emitting element emits red light, and the fourth light-emitting element emits white light.

[0032] Optionally, the pixel circuits of R sub-pixels arranged along the first direction are connected to the same first power signal line, and the pixel circuits of S sub-pixels arranged along the first direction are connected to the same initialization signal line, where R≥1 and S≥1.

[0033] Optional, R=S.

[0034] Optional, R < S.

[0035] Optional, R > S.

[0036] Optionally, the pixel circuits of R sub-pixels are connected to the first power signal line via the first connection line, and the pixel circuits of S sub-pixels are connected to the initialization signal line via the second connection line.

[0037] Optionally, in a direction perpendicular to the substrate of the display panel, at least one first connecting line and at least one second connecting line do not overlap.

[0038] Optionally, in a direction perpendicular to the substrate of the display panel, at least one first connecting line and at least one second connecting line at least partially overlap.

[0039] Optionally, the width of at least one first connecting line is greater than the width of at least one second connecting line.

[0040] Optionally, along the first direction, the first connecting line connected to the first power signal line is located on the same side of the first power signal line, and the second connecting lines connected to the initialization signal line are distributed on both sides of the initialization signal line; or, Along the first direction, the first connecting lines connected to the first power signal line are distributed on both sides of the first power signal line, and the second connecting lines connected to the initialization signal line are located on the same side of the initialization signal line.

[0041] Optionally, the number of second connecting lines distributed on both sides of the initialization signal line along the first direction is equal; or, Along the first direction, the number of first connecting lines distributed on both sides of the first power signal line is equal.

[0042] Optionally, along the first direction, the first connecting line connected to the first power signal line is located on the same side of the first power signal line, and the second connecting line connected to the initialization signal line is located on the same side of the first power signal line; or, Along the first direction, the first connecting lines connected to the first power signal line are distributed on both sides of the first power signal line, and the second connecting lines connected to the initialization signal line are distributed on both sides of the initialization signal line.

[0043] Optionally, the number of first connecting lines distributed on both sides of the first power signal line along the first direction is equal; or, Along the first direction, the number of second connection lines distributed on both sides of the initialization signal line is equal.

[0044] Optionally, the first sub-pixel and the second sub-pixel are arranged along a first direction; The first sub-scan line is connected to the first node of the first pixel circuit, and the second sub-scan line is connected to the first node of the second pixel circuit. Along the second direction, the distance between the first sub-scan line and the first node of the first pixel circuit is D1, and the distance between the second sub-scan line and the first node of the second pixel circuit is D2, where D1≥0, D2≥0, and D1≠D2.

[0045] Optionally, the first sub-pixel and the second sub-pixel are arranged along a first direction; The first sub-scan line is connected to the first node of the first pixel circuit, and the second sub-scan line is connected to the first node of the second pixel circuit. Along the second direction, the distance between the first sub-scan line and the first node of the first pixel circuit is D1, and the distance between the second sub-scan line and the first node of the second pixel circuit is D2, where D1≥0, D2≥0, and D1=D2.

[0046] Optionally, the first scan line is connected to the first transistor of the pixel circuit, and the first node is the gate of the first transistor.

[0047] Optionally, the first node in the first pixel circuit is located at the same position as the first node in the second pixel circuit.

[0048] Optionally, the first pixel circuit includes P1 transistors and Q1 capacitors, and the second pixel circuit includes P2 transistors and Q2 capacitors, where P1≥1, Q1≥1, P2≥1, and Q2≥1. The arrangement of P1 transistors and Q1 capacitors in the first pixel circuit is the same as the arrangement of P2 transistors and Q2 capacitors in the second pixel circuit.

[0049] Optionally, the position of the first node in the first pixel circuit is different from that of the first node in the second pixel circuit.

[0050] Optionally, the first pixel circuit includes P1 transistors and Q1 capacitors, and the second pixel circuit includes P2 transistors and Q2 capacitors, where P1≥1, Q1≥1, P2≥1, and Q2≥1. The first scan line is connected to the first transistor of the pixel circuit, and the first node is the gate of the first transistor; The arrangement of at least the first transistor among the P1 transistors and Q1 capacitors in the first pixel circuit is different from the arrangement of at least the first transistor among the P2 transistors and Q2 capacitors in the second pixel circuit.

[0051] Optionally, along the second direction, the first sub-scan line is located on the first side of the first node of the first pixel circuit, and the second sub-scan line is located on the second side of the first node of the second pixel circuit, with the first side and the second side being opposite sides along the second direction.

[0052] Optionally, along the second direction, the first sub-scan line is located on the first side of the first node of the first pixel circuit, and the second sub-scan line is located on the first side of the first node of the second pixel circuit.

[0053] Optionally, the first sub-scan line is connected to the first node of the first pixel circuit via a first transition line, and the second sub-scan line is connected to the first node of the second pixel circuit via a second transition line. Along the second direction, the length of the first transition line is L1, and the length of the second transition line is L2; ​​wherein, L1≥0, L2≥0, and L1 = L2, or L1 ≠ L2.

[0054] Optionally, the width of the first sub-scan line is W1, and the width of the second sub-scan line is W2; wherein, (D1-D2)×(W1-W2)>0.

[0055] Optionally, the scan line also includes a second scan line, which is connected to the first pixel circuit, and the second scan line is first connected to the second pixel circuit; or, The scan line also includes a second scan line, which includes a third sub-scan line and a fourth sub-scan line. The third sub-scan line is connected to the first pixel circuit, and the fourth sub-scan line is connected to the second pixel circuit.

[0056] Optionally, the pixel circuit includes a first transistor and a second transistor; The first scan line is connected to the first transistor; The second scan line is connected to the second transistor.

[0057] Optionally, the first sub-scan line, the second sub-scan line, the third sub-scan line, and the fourth sub-scan line are arranged along the second direction, and the arrangement order satisfies at least one of the following: First sub-scan line, second sub-scan line, third sub-scan line, fourth sub-scan line; or, First sub-scan line, third sub-scan line, second sub-scan line, fourth sub-scan line; or, First sub-scan line, third sub-scan line, fourth sub-scan line, second sub-scan line.

[0058] Optionally, the sub-pixel also includes a third sub-pixel, which includes a third pixel circuit and a third light-emitting element. The first light-emitting element, the second light-emitting element, and the third light-emitting element emit different colors of light. The first data line is connected to the third pixel circuit; The first scan line includes a fifth sub-scan line, which is connected to the third pixel circuit.

[0059] Optionally, the sub-pixel also includes a fourth sub-pixel, which includes a fourth pixel circuit and a fourth light-emitting element. The first light-emitting element, the second light-emitting element, the third light-emitting element, and the fourth light-emitting element emit different colors of light. The first data line is connected to the fourth pixel circuit; The first scan line includes a sixth sub-scan line, which is connected to the fourth pixel circuit.

[0060] Optionally, the data line provides data signals to the pixel circuitry; The scan lines provide scan signals to the pixel circuits; among them, The first data line provides a first data signal to the first pixel circuit, and the first data line provides a second data signal to the second pixel circuit; The first scan line provides a first scan signal to the pixel circuit. The first scan signal includes a first sub-scan signal and a second sub-scan signal. The first sub-scan line provides the first sub-scan signal to the first pixel circuit, and the second sub-scan line provides the second sub-scan signal to the second pixel circuit.

[0061] Optionally, within one screen refresh cycle of the display panel, there is no overlap between the effective pulses of the first sub-scan signal and the effective pulses of the second sub-scan signal.

[0062] Optionally, after the effective pulse of the first sub-scan signal ends, the data signal on the first data line changes from the first data signal to the second data signal, and then the effective pulse of the second sub-scan signal is turned on.

[0063] Optionally, within one screen refresh cycle of the display panel, the effective pulses of the first sub-scan signal and the effective pulses of the second sub-scan signal at least partially overlap.

[0064] Optionally, the effective pulse of the second sub-scan signal is turned on before the effective pulse of the first sub-scan signal ends; After the effective pulse of the first sub-scan signal ends, the effective pulse of the second sub-scan signal ends; After the effective pulse of the first sub-scan signal ends, the first data signal jumps to the second data signal.

[0065] Optionally, the display panel includes a T-row of subpixel rows arranged along the second direction and multiple first sub-scan lines and multiple second sub-scan lines; Within one screen refresh cycle of the display panel, the effective pulse of the second sub-scan signal on the second sub-scan line connected to the pixel circuit of the i-th sub-pixel row overlaps at least partially with the effective pulse of the first sub-scan signal on the first sub-scan line connected to the pixel circuit of the j-th sub-pixel row, 0≤i≤T, 0≤j≤T, and i≠j.

[0066] Optionally, the display panel includes a T-row of subpixel rows arranged along the second direction and multiple first sub-scan lines and multiple second sub-scan lines; Within one screen refresh cycle of the display panel, there is no overlap between the effective pulse of the second sub-scan signal on the second sub-scan line connected to the pixel circuit of the i-th sub-pixel row and the effective pulse of the first sub-scan signal on the first sub-scan line connected to the pixel circuit of the j-th sub-pixel row, 0≤i≤T, 0≤j≤T, and i≠j.

[0067] Optionally, the display panel includes a T-row of subpixel rows arranged along the second direction and multiple first sub-scan lines and multiple second sub-scan lines; Within one screen refresh cycle of the display panel, the effective pulse of the first sub-scan signal on the first sub-scan line connected to the pixel circuit of the i-th sub-pixel row is activated earlier than the effective pulse of the second sub-scan signal on the second sub-scan line connected to the pixel circuit of the i-th sub-pixel row, and the effective pulse of the first sub-scan signal on the first sub-scan line connected to the pixel circuit of the j-th sub-pixel row is activated later than the effective pulse of the second sub-scan signal on the second sub-scan line connected to the pixel circuit of the j-th sub-pixel row, 0≤i≤T, 0≤j≤T, and i≠j.

[0068] Optionally, the width of the effective pulse of the first sub-scan signal is equal to the width of the effective pulse of the second sub-scan signal.

[0069] Optionally, the width of the effective pulse of the first sub-scan signal is greater than or less than the width of the effective pulse of the second sub-scan signal.

[0070] Optionally, the start time of the effective pulse of the first sub-scan signal is earlier than the start time of the effective pulse of the second sub-scan signal; or, The start time of the effective pulse of the first sub-scan signal is later than the start time of the effective pulse of the second sub-scan signal.

[0071] Optionally, the operation of the display panel includes an initialization phase and a sampling phase; During the initialization phase, the initialization signal is received on the initialization signal line; During the sampling phase, the signal on the initialization signal line is in a floating state.

[0072] Optionally, the light-emitting element of the display panel includes a first electrode and a second electrode; The first electrode is connected to the pixel circuit, and the second electrode is connected to the second power signal line to receive the second power signal; wherein... The initialization signal line receives the second power signal.

[0073] Optionally, the display panel may also include a control unit, which is electrically connected to a data cable; The control unit includes a storage module and a control module; The storage module stores the mapping relationship between the display parameters of the display panel and the data voltage; The control module is used to retrieve the corresponding data voltage from the storage module according to the display parameters and provide the data voltage to the data line.

[0074] Optionally, the pixel circuit includes at least a first transistor, a second transistor, a third transistor, and a first capacitor; The first transistor is connected between the data line and the gate of the third transistor; The second transistor is connected between the initialization signal line and the light-emitting element; The third transistor is connected between the first power signal line and the light-emitting element; The first capacitor is connected between the gate of the third transistor and the light-emitting element, or the first capacitor is connected between the first power signal line and the gate of the third transistor; wherein, The gate of the first transistor is connected to the first scan line; or, The gate of the second transistor is connected to the first scan line.

[0075] Optionally, the pixel circuit includes at least a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and a first capacitor; The first transistor is connected between the data line and the first terminal of the seventh transistor; The second transistor is connected between the first terminal and the gate of the seventh transistor; The third transistor is connected between the first electrode of the seventh transistor and the light-emitting element; The fourth transistor is connected between the initialization signal line and the light-emitting element; The fifth transistor is connected between the initialization signal line and the gate of the seventh transistor; The sixth transistor is connected between the first power signal line and the second terminal of the seventh transistor; The first capacitor is connected between the gate of the seventh transistor and the light-emitting element; or, the first capacitor is connected between the first power signal line and the gate of the seventh transistor. The gate of the first transistor is connected to the first scan line.

[0076] Secondly, embodiments of the present invention provide a display device including the display panel described above.

[0077] The display panel and display device provided in the embodiments of the present invention reduce the number of data lines in the display panel by electrically connecting the first data line to the first pixel circuit and the second pixel circuit respectively, compared with the method of connecting the first pixel circuit and the second pixel circuit to each of the two data lines. This reduces the number of pins in the data driving circuit electrically connected to the data lines, thereby simplifying the structure of the display panel.

[0078] Based on this, embodiments of the present invention include at least one first power signal line between adjacent first data lines. Alternatively, at least one initialization signal line is included between adjacent first data lines. While reducing the number of data lines, the space freed up by reducing the number of data lines in the display area can be used to install the aforementioned power signal line or initialization signal line, thereby improving the space utilization rate within the display area. Furthermore, by placing at least one initialization signal line or first power signal line between two adjacent first data lines, embodiments of the present invention can prevent the first data lines from being excessively concentrated in a certain area of ​​the display area, allowing the first data lines to be distributed as much as possible, which is beneficial for improving the transmission of data signals within the first data lines. Attached Figure Description

[0079] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0080] Figure 1 A schematic diagram of a display panel provided in an embodiment of the present invention; Figure 2 A schematic diagram of the equivalent circuit of a sub-pixel provided in an embodiment of the present invention; Figure 3 A schematic diagram of another display panel provided in an embodiment of the present invention; Figure 4 A schematic diagram of yet another display panel provided in an embodiment of the present invention; Figure 5 A schematic diagram of yet another display panel provided in an embodiment of the present invention; Figure 6 A schematic diagram of yet another display panel provided in an embodiment of the present invention; Figure 7 A schematic diagram of yet another display panel provided in an embodiment of the present invention; Figure 8 A schematic diagram of yet another display panel provided in an embodiment of the present invention; Figure 9 This is a schematic diagram of a display panel layout provided in an embodiment of the present invention; Figure 10 A schematic diagram of yet another display panel provided in an embodiment of the present invention; Figure 11 A schematic diagram of yet another display panel provided in an embodiment of the present invention; Figure 12 A schematic diagram of yet another display panel provided in an embodiment of the present invention; Figure 13 A schematic diagram of yet another display panel provided in an embodiment of the present invention; Figure 14 A schematic diagram of yet another display panel provided in an embodiment of the present invention; Figure 15 A schematic diagram of yet another display panel provided in an embodiment of the present invention; Figure 16 A schematic diagram of yet another display panel provided in an embodiment of the present invention; Figure 17 This is a schematic diagram of another display panel provided in an embodiment of the present invention; Figure 18 A schematic diagram of yet another display panel provided in an embodiment of the present invention; Figure 19 A schematic diagram of yet another display panel provided in an embodiment of the present invention; Figure 20 A schematic diagram of yet another display panel provided in an embodiment of the present invention; Figure 21 A schematic diagram of another display panel provided in an embodiment of the present invention; Figure 22 A schematic diagram of another display panel provided in an embodiment of the present invention; Figure 23 A schematic diagram of another display panel provided in an embodiment of the present invention; Figure 24 A schematic diagram of yet another display panel provided in an embodiment of the present invention; Figure 25 A schematic diagram of yet another display panel provided in an embodiment of the present invention; Figure 26 A schematic diagram of yet another display panel provided in an embodiment of the present invention; Figure 27 A schematic diagram of yet another display panel provided in an embodiment of the present invention; Figure 28 This is a schematic diagram of the working timing of a display panel provided in an embodiment of the present invention; Figure 29 This is a schematic diagram of the working timing of another display panel provided in an embodiment of the present invention; Figure 30 This is a schematic diagram illustrating the working timing of another display panel provided in an embodiment of the present invention; Figure 31 This is a schematic diagram illustrating the working timing of another display panel provided in an embodiment of the present invention; Figure 32 This is a schematic diagram illustrating the working timing of another display panel provided in an embodiment of the present invention; Figure 33This is a schematic diagram illustrating the working timing of another display panel provided in an embodiment of the present invention; Figure 34 A schematic diagram of a control unit in a display panel provided in an embodiment of the present invention; Figure 35 A schematic diagram of an equivalent circuit for another sub-pixel provided in an embodiment of the present invention; Figure 36 A schematic diagram of an equivalent circuit for another sub-pixel provided in an embodiment of the present invention; Figure 37 A schematic diagram of an equivalent circuit for another sub-pixel provided in an embodiment of the present invention; Figure 38 This is a schematic diagram of a display device provided in an embodiment of the present invention. Detailed Implementation

[0081] To better understand the technical solution of the present invention, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0082] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0083] The terminology used in the embodiments of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. The singular forms “a,” “the,” and “the” as used in the embodiments of this invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0084] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0085] This invention provides a display panel, such as... Figure 1 As shown, Figure 1 This is a schematic diagram of a display panel provided in an embodiment of the present invention. The display panel includes sub-pixels 1, scan lines 2, and data lines 3.

[0086] Among them, such as Figure 2 As shown, Figure 2This is a schematic diagram of an equivalent circuit for a sub-pixel according to an embodiment of the present invention. The sub-pixel 1 includes a pixel circuit 101 and a light-emitting element 102 that are electrically connected to each other. The pixel circuit 101 is used to provide a driving current to the light-emitting element 102 to drive the light-emitting element 102 to light up. Figure 2 As shown, scan line 2 is connected to pixel circuit 101 in sub-pixel 1. Data line 3 is connected to pixel circuit 101.

[0087] like Figure 1 As shown, scan line 2 extends along the first direction h11; data line 3 extends along the second direction h12, and the first direction h11 and the second direction h12 intersect.

[0088] like Figure 1 As shown, sub-pixel 1 includes at least a first sub-pixel 11 and a second sub-pixel 12. Correspondingly, pixel circuit 101 includes a first pixel circuit 1011 and a second pixel circuit 1012, and light-emitting element 102 includes a first light-emitting element 1021 and a second light-emitting element 1022. The first sub-pixel 11 includes the aforementioned first pixel circuit 1011 and first light-emitting element 1021, and the second sub-pixel 12 includes the aforementioned second pixel circuit 1012 and second light-emitting element 1022. In this embodiment of the invention, the first light-emitting element 1021 and the second light-emitting element 1022 emit different colors of light.

[0089] like Figure 1 As shown, data line 3 includes a first data line 31, which is connected to the first pixel circuit 1011 and the second pixel circuit 1012; scan line 2 includes a first scan line 21, which includes a first sub-scan line 211 and a second sub-scan line 212. The first sub-scan line 211 is connected to the first pixel circuit 1011, and the second sub-scan line 212 is connected to the second pixel circuit 1012.

[0090] For example, such as Figure 2 As shown, the first pixel circuit 1011 and the second pixel circuit 1012 include a first transistor T1, a first data line 31 is electrically connected to the first electrode of the first transistor T1, a first sub-scan line 211 is electrically connected to the gate of the first transistor T1 of the first pixel circuit 1011, and a second sub-scan line 212 is electrically connected to the gate of the first transistor T1 of the second pixel circuit 1012.

[0091] In this embodiment of the invention, by electrically connecting the first data line 31 to the first pixel circuit 1011 and the second pixel circuit 1012 respectively, compared with the method of connecting the first pixel circuit 1011 and the second pixel circuit 1012 to each of them with a data line, the number of data lines in the display panel can be reduced, thereby simplifying the structure of the display panel.

[0092] likeFigure 1 As shown, the display panel also includes a first power signal line 4 and an initialization signal line 5. The first power signal line 4 is connected to the pixel circuit 101. The first power signal line 4 transmits a first power signal PVDD, the magnitude of which is related to the driving current generated by the pixel circuit 101. Figure 2 As shown, the initialization signal line 5 is connected to the pixel circuit 101.

[0093] The display panel must meet at least one of the following requirements: like Figure 1 As shown, the first power signal line 4 extends along the second direction h12 and along the first direction h11, with at least one first power signal line 4 between adjacent first data lines 31. This arrangement reduces the number of data lines while increasing the distance between adjacent first data lines. Furthermore, this embodiment of the invention allows the first power signal line 4 to be placed in the original location used for data lines, resulting in a more uniform distribution of the first power signal line 4 and the first data line 31. This avoids excessive concentration of the same type of signal lines in a certain area. Since the pixel circuit needs to receive the aforementioned data signals and first power signals during operation, this embodiment of the invention, by uniformly distributing the first power signal line 4 and the first data line 31 in the display panel, facilitates faster reception of the first power signal and data signals by the pixel circuit. This avoids excessive transmission delay caused by one of the first power signal lines 4 and the first data line 31 being too far from the pixel circuit, and also prevents excessive time differences in the reception of the first power signal and data signals by the pixel circuit, thus achieving better signal transmission.

[0094] Or, such as Figure 3 As shown, Figure 3 This is a schematic diagram of another display panel provided in an embodiment of the present invention. The initialization signal line 5 extends along the second direction h12 and along the first direction h11, with at least one initialization signal line 5 between adjacent first data lines 31. By adopting this arrangement, while reducing the number of data lines 3, the space freed up by reducing the number of data lines 3 in the display area can be used to install the aforementioned initialization signal line 5, thereby improving the space utilization rate within the display area. Furthermore, by placing at least one initialization signal line 5 between two adjacent first data lines 31, this embodiment of the present invention can avoid excessive concentration of the first data lines 31 in a certain area of ​​the display area, allowing the first data lines 31 to be dispersed as much as possible, which is beneficial for improving the transmission of data signals in the first data lines 31.

[0095] For example, such as Figure 4 As shown, Figure 4This is a schematic diagram of another display panel provided in an embodiment of the present invention. The first power signal line 4 and the initialization signal line 5 both extend along the second direction h12; along the first direction h11, there is at least one first power signal line 4 and at least one initialization signal line 5 between adjacent first data lines 31.

[0096] By adopting this configuration, while electrically connecting the first data line 31 to the first pixel circuit 1011 and the second pixel circuit 1012 respectively, the number of data lines in the display panel can be reduced, thereby allowing for a larger distance between adjacent first data lines 31. Based on this, embodiments of the present invention can provide at least one first power signal line 4 and at least one initialization signal line 5 between adjacent first data lines 31, fully utilizing the space saved by reducing the number of data lines. Furthermore, it can improve the uniformity of the distribution of traces transmitting different types of signals within the display area, allowing the pixel circuits electrically connected to the three types of signal lines to be positioned closer to each other. This facilitates faster reception of data signals, power signals, and initialization signals by the pixel circuits, avoiding the severe signal transmission delay caused by placing the pixel circuits too far from any of the three types of signal lines.

[0097] like Figure 1 and Figure 3 As shown, the display panel includes pixels 10, each pixel 10 including at least a first sub-pixel 11 and a second sub-pixel 12 arranged along a first direction h11, and a plurality of pixels 10 arranged along the first direction h11; along the first direction h11, a first gap G1 is included between the first pixel circuit 1011 and the second pixel circuit 1012; the display panel satisfies at least one of the following: The first power signal line 4 extends along the second direction h12 and along the first direction h11, at least one of the first data line 31 and the first power signal line 4 is located in the first gap G1. Figure 1 The first data line 31 is located in the first gap G1 as an example.

[0098] Alternatively, the initialization signal line 5 extends along the second direction h12 and along the first direction h11, with at least one of the first data line 31 and the initialization signal line 5 located in the first gap G1. Figure 3 The initialization signal line 5 is located in the first gap G1 as an example.

[0099] By adopting this configuration, the first data line 31 is electrically connected to the first pixel circuit 1011 and the second pixel circuit 1012 respectively. Compared with the configuration where each of the first pixel circuit 1011 and the second pixel circuit 1012 is connected to a separate data line, the number of data lines in the display panel can be reduced, thereby simplifying the structure of the display panel. Furthermore, this embodiment of the invention places at least one of the first data line 31 and the first power signal line 4 in the first gap G1, or places at least one of the first data line 31 and the initialization signal line 5 in the first gap G1. Since the traces within the first gap G1 do not overlap with the pixel circuits, the parasitic capacitance between the first data line 31, the first power signal line 4, or the initialization signal line 5 and the pixel circuits can be reduced. Moreover, this configuration fully utilizes the space saved in the first gap G1 after reducing the number of data lines, improving the space utilization rate within the first gap G1 without needing to increase the width of the first gap G1.

[0100] In an optional embodiment, the present invention may also have both the first power signal line 4 and the initialization signal line 5 extend along the second direction h12. As described above, by electrically connecting the first data line 31 to the first pixel circuit 1011 and the second pixel circuit 1012 respectively, compared with the method of connecting each of the first pixel circuit 1011 and the second pixel circuit 1012 to a separate data line, the number of data lines in the display panel can be reduced. Since the data lines extend along the second direction h12, more wiring space extending along the second direction h12 can be freed up in the display panel. By having both the first power signal line 4 and the initialization signal line 5 extend along the second direction h12, the present invention can make full use of the wiring space extending along the second direction h12 in the display panel.

[0101] Furthermore, along the first direction h11, embodiments of the present invention may place at least one of the first data line 31, the first power signal line 4, and the initialization signal line 5 in the first gap G1. For example, embodiments of the present invention may place one of the three in the first gap G1, such as placing the first data line 31 in the first gap G1, or placing the first power signal line 4 in the first gap G1, or placing the initialization signal line 5 in the first gap G1.

[0102] In another alternative implementation, the present invention may also place two of the first data line 31, the first power signal line 4, and the initialization signal line 5 in the first gap G1. For example, the first data line 31 and the first power signal line 4 may be placed in the first gap G1; or the first data line 31 and the initialization signal line 5 may be placed in the first gap G1; or the first power signal line 4 and the initialization signal line 5 may be placed in the first gap G1.

[0103] For example, two of the first data line 31, the first power signal line 4, and the initialization signal line 5 may be located in the same first gap G1; or, in this embodiment of the invention, multiple first pixel circuits 1011 and multiple second pixel circuits 1012 may be provided in the display panel, and correspondingly, there may be multiple first gaps G1. In this embodiment of the invention, two of the first data line 31, the first power signal line 4, and the initialization signal line 5 may be located in different first gaps G1.

[0104] In another alternative embodiment, the first data line 31, the first power signal line 4, and the initialization signal line 5 may be located in the first gap G1. For example, the three may be located in the same gap G1, or they may be located in different first gaps G1.

[0105] like Figure 5 As shown, Figure 5 This is a schematic diagram of another display panel provided in an embodiment of the present invention. The display panel includes a first region A1 and a second region A2; the display panel satisfies at least one of the following: The first power signal line 4 extends along the second direction h12 and along the first direction h11. In the first region A1, there are M1 first power signal lines 4 between adjacent first data lines 31, and in the second region A2, there are M2 first power signal lines 4 between adjacent first data lines 31, wherein M1 > M2 ≥ 0. Figure 5 The example uses M1=1 and M2=0.

[0106] By adopting this configuration, while reducing the number of data lines 3, the number of first power signal lines 4 can be adjusted according to the different operational requirements of the pixel circuits in different areas. For example, the first area A1 may include a larger number of first power signal lines 4, while another area may include a smaller number of first power signal lines 4, such as the second area A2. While ensuring that the pixel circuits can receive the first power signal, the number and position of the first power signal lines 4 can be rationally arranged, improving the design flexibility of the display panel and further enhancing its display effect. For example, as shown... Figure 5 As shown, in this embodiment of the invention, the four-column pixel circuit in the first region A1 and the four-column pixel circuit in the second region A2 can be connected together to the first power signal line 4 in the first region A1.

[0107] Or, such as Figure 6 As shown, Figure 6This is a schematic diagram of another display panel provided in an embodiment of the present invention. In this embodiment of the present invention, the initialization signal line 5 can also be extended along the second direction h12 and along the first direction h11. In the first region A1, N1 initialization signal lines 5 are included between adjacent first data lines 31, and in the second region A2, N2 initialization signal lines 5 are included between adjacent first data lines 31, wherein N1 > N2 ≥ 0. Figure 6 The example uses N1=1 and N2=0.

[0108] By adopting this configuration, while reducing the number of data lines 3, the number of initialization signal lines 5 can be adjusted according to the different working requirements of the pixel circuits in different areas. For example, the first area A1 can include a larger number of initialization signal lines 5, while another area can include a smaller number of initialization signal lines 5, such as the second area A2. While ensuring that the pixel circuits can receive the initialization signal, the number and position of the initialization signal lines 5 can be reasonably arranged, which can improve the design flexibility of the display panel and further improve the display effect of the display panel.

[0109] For example, such as Figure 6 As shown, in this embodiment of the invention, the four-column pixel circuit in the first region A1 and the four-column pixel circuit in the second region A2 can be connected together to the initialization signal line 5 in the first region A1.

[0110] In another alternative implementation, such as Figure 7 As shown, Figure 7 This is a schematic diagram of another display panel provided in an embodiment of the present invention. The display panel includes a first region A1 and a second region A2. A first power signal line 4 and an initialization signal line 5 both extend along a second direction h12. Along the first direction h11, in the first region A1, MS1 first power signal lines 4 and NS1 initialization signal lines 5 are included between adjacent first data lines 31, and in the second region A2, MS2 first power signal lines 4 and NS2 initialization signal lines 5 are included between adjacent first data lines 31, wherein MS1≥0, NS1≥0, MS2≥0, and NS2≥0; the display panel satisfies at least one of the following: MS1≠MS2; or NS1≠NS2. Figure 7 The example uses MS1=1, NS1=0, MS2=0, and NS2=1.

[0111] This arrangement allows different signal lines extending along the second direction h12, such as the first power signal line 4 and the initialization signal line 5, to be distributed as evenly as possible in different areas. For example, if the first area A1 has a large number of first power signal lines 4, this embodiment of the invention can set a larger number of initialization signal lines 5 in the second area A2, avoiding the concentration of the first power signal lines 4 and initialization signal lines 5 in a single area. This improves the uniformity of signal reception by different pixel circuits in a row of pixel circuits. A row of pixel circuits refers to multiple pixel circuits arranged along the first direction h11. Furthermore, this arrangement avoids the concentration of multiple types of signal lines in a single area, such as preventing the first power signal line 4 and initialization signal line 5 from being concentrated in the first area A1, which would result in high wiring pressure in the first area A1 and wasted space in the second area A2.

[0112] For example, in embodiments of the present invention, MS1 > MS2 ≥ 0, and 0 ≤ NS1 ≤ NS2. For instance, as... Figure 7 As shown, in this embodiment of the invention, MS1=1, NS1=0, MS2=0, and NS2=1 can be configured. This configuration allows the first power signal line 4 and the initialization signal line 5 to be alternately arranged in the first region A1 and the second region A2, avoiding the concentration of certain types of signal lines in a specific area and improving wiring uniformity.

[0113] In another alternative implementation, embodiments of the present invention may also set MS1 > MS2 ≥ 0 and NS1 ≥ MS2 ≥ 0. For example, as Figure 8 As shown, Figure 8 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Figure 8 Using MS1=1, MS2=0, NS1=1, and NS2=0 as an illustration, this configuration effectively places as many first power signal lines 4 and initialization signal lines 5 as possible in the first region A1 and as few as possible in the second region A2. This shortens the distance between the pixel circuits in the first region A1 and the first power signal lines 4 and initialization signal lines 5, improving the speed at which the pixel circuits in the first region A1 receive the first power signal and initialization signal, as well as the accuracy of the signals received by the pixel circuits in the first region A1. Furthermore, by minimizing the placement of the first power signal lines 4 and initialization signal lines 5 in the second region A2, this embodiment of the invention reduces the wiring pressure in the second region A2, which is beneficial for improving the light transmittance of the second region A2. The solution provided by this embodiment of the invention satisfies the different display requirements of the first region A1 and the second region A2 respectively.

[0114] like Figure 9 As shown, Figure 9This is a schematic diagram of a display panel provided in an embodiment of the present invention. Along the first direction h11, the width of the first data line 31 is W1, the width of the first power signal line 4 is W2, and the width of the initialization signal line 5 is W3. The display panel satisfies at least one of the following: W1 < W2; or W3 < W2.

[0115] In this embodiment of the invention, by electrically connecting the first data line 31 to the first pixel circuit 1011 and the second pixel circuit 1012 respectively, compared to connecting each of the first pixel circuit 1011 and the second pixel circuit 1012 to a separate data line, the number of data lines in the display panel can be reduced, thereby simplifying the structure of the display panel. Furthermore, by setting a larger width W2 for the first power signal line 4, this embodiment of the invention can fully utilize the vertical wiring space saved by reducing the number of data lines, where vertical refers to the second direction h12. Moreover, increasing the width of the first power signal line 4 can reduce its resistance, thereby reducing the voltage drop of the first power signal during transmission. In this embodiment of the invention, the first power signal is directly related to the driving current generated by the pixel circuit. The driving current affects the brightness of the light-emitting element; therefore, by adopting the method provided in this embodiment of the invention, the stability of the driving current can be ensured, which is beneficial to improving the brightness uniformity of the light-emitting element at different locations.

[0116] In one embodiment, the present invention allows W2-W3 > W3-W1 ≥ 0. Using this setting, the width difference between the initialization signal line 5 and the first power signal line 4 can be set relatively large. For example, within a certain space, the width of the first power signal line 4 is maximized, while the width of the initialization signal line 5 can be set to be comparable to the width of the first data line 31, and both widths are smaller than the width of the first power signal line 4. This prioritizes ensuring that the first power signal line 4 has the smallest possible resistance within a certain space, thereby ensuring the stability of the driving current and improving the brightness uniformity of the light-emitting elements at different locations.

[0117] In another alternative implementation, embodiments of the present invention may allow 0 ≤ W2 - W3 < W3 - W1. For example, embodiments of the present invention may appropriately increase the width of both the initialization signal line 5 and the first power signal line 4 to reduce their resistance. Optionally, such as Figure 9 As shown, in this embodiment of the invention, the widths of the initialization signal line 5 and the first power signal line 4 can be made equal, and both can be made greater than the width of the first data line 31.

[0118] For example, such as Figure 1 , Figure 3 , Figure 4 , Figure 9 and Figure 10 As shown,Figure 10 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Sub-pixel 1 further includes a third sub-pixel 13. The third sub-pixel 13 includes a third pixel circuit 1013 and a third light-emitting element 1023. The first light-emitting element 1021, the second light-emitting element 1022 and the third light-emitting element 1023 emit different colors of light. The light emitted by the first light-emitting element 1021, the second light-emitting element 1022 and the third light-emitting element 1023 can be mixed to emit white light.

[0119] like Figure 1 , Figure 3 , Figure 4 , Figure 9 and Figure 10 As shown, data line 3 also includes a second data line 32, which is connected to the third pixel circuit 1013.

[0120] Optional, such as Figure 1 , Figure 3 , Figure 4 and Figure 10 As shown, along the first direction h11, the first sub-pixel 11, the second sub-pixel 12, and the third sub-pixel 13 can be arranged in a repeating sequence.

[0121] For example, such as Figure 1 , Figure 3 and Figure 4 As shown, the second data line 32 is also electrically connected to another first pixel circuit 1011.

[0122] Or, such as Figure 9 and Figure 10 As shown, sub-pixel 1 also includes a fourth sub-pixel 14, which includes a fourth pixel circuit 1014 and a fourth light-emitting element 1024. The first light-emitting element 1021, the second light-emitting element 1022, the third light-emitting element 1023, and the fourth light-emitting element 1024 emit different colors of light. The second data line 32 is connected to the third pixel circuit 1013 and the fourth pixel circuit 1014. That is, the third pixel circuit 1013 and the fourth pixel circuit 1014 share a second data line 32 to reduce the number of data lines 3 and simplify wiring.

[0123] For example, such as Figure 1 , Figure 3 and Figure 4 As shown, data line 3 also includes a third data line 33, which is electrically connected to the second pixel circuit 1012 and the third pixel circuit 1023.

[0124] For example, such as Figure 1 , Figure 3 , Figure 4 and Figure 10As shown, along the first direction h11, at least one second data line 32 is included between adjacent first data lines 31; or, along the first direction h11, at least one first data line 31 is included between adjacent second data lines 32. This arrangement allows the first data lines 31 and second data lines 32 to be arranged alternately in the display panel, improving their distribution uniformity and helping to reduce the distance between the first data lines 31 and second data lines 32 and their respective connected pixel circuits.

[0125] For example, such as Figure 1 , Figure 3 , Figure 4 and Figure 10 As shown, the first power signal line 4 extends along the second direction h12; along the first direction h11, at least one first power signal line 4 is included between adjacent first data lines 31 and second data lines 32. This arrangement fully utilizes the space between the first data lines 31 and second data lines 32. Furthermore, when connecting the first power signal line 4 to a pixel circuit electrically connected to the first data lines 31 and second data lines 32, placing the first power signal line 4 between the first data lines 31 and second data lines 32 reduces the distance between the first power signal line 4 and the connected pixel circuit, which helps to reduce voltage drop loss of the first power signal during transmission.

[0126] For example, such as Figure 1 , Figure 3 , Figure 4 and Figure 10 As shown, the initialization signal line 5 extends along the second direction h12; along the first direction h11, at least one initialization signal line 5 is included between adjacent first data lines 31 and second data lines 32. This arrangement fully utilizes the space between the first data lines 31 and second data lines 32. Furthermore, when connecting the initialization signal line 5 to a pixel circuit electrically connected to the first data lines 31 and second data lines 32, placing the initialization signal line 5 between the first data lines 31 and second data lines 32 reduces the distance between the initialization signal line 5 and the connected pixel circuit, which helps to reduce the voltage drop loss of the signal transmitted by the initialization signal line 5 during transmission.

[0127] For example, such as Figure 1 , Figure 3 , Figure 4 and Figure 10As shown, the first power signal line 4 and the initialization signal line 5 extend along the second direction h12; along the first direction h11, at least one first power signal line 4 is included between adjacent sets of first data lines 31 and second data lines 32, and at least one initialization signal line 5 is included between adjacent sets of first data lines 31 and second data lines 32. This arrangement avoids the first power signal line 4 and the initialization signal line 5 being located between the same set of first data lines 31 and second data lines 32, allowing them to be distributed as widely as possible. After the display panel has been operating for a long time, this improves the uniformity of the first power signal and initialization signal received by different pixel circuits.

[0128] For example, in embodiments of the present invention, the first power signal line 4 and the initialization signal line 5 may extend along the second direction h12; along the first direction h11, the first data line 31, the second data line 32, the first power signal line 4, and the initialization signal line 5 may be arranged in at least one of the following orders: First data line 31, first power signal line 4, second data line 32, initialization signal line 5; or, first data line 31, initialization signal line 5, second data line 32, first power signal line 4. Figure 1 The arrangement is illustrated by the order of first data line 31, first power signal line 4, second data line 32, and initialization signal line 5. Figure 3 The arrangement is illustrated in the order of first data line 31, initialization signal line 5, second data line 32, and first power signal line 4.

[0129] By adopting this setting method, the first power signal line 4 and the initialization signal line 5 can be avoided from being located between the same group of first data lines 31 and second data lines 32. This allows the first power signal line 4 and the initialization signal line 5 to be set as dispersed as possible. After the display panel has been working for a long time, the uniformity of the first power signal and initialization signal received by different pixel circuits can be improved.

[0130] like Figure 11 and Figure 12 As shown, Figure 11 and Figure 12The diagram illustrates two other display panels provided in this embodiment of the invention. The first power signal line 4 and the initialization signal line 5 extend along the second direction h12. Along the first direction h11, at least one first power signal line 4 and at least one initialization signal line 5 are included between adjacent first data lines 31 and second data lines 32. With this arrangement, when the first power signal line 4 and the initialization signal line 5 are electrically connected to the pixel circuits electrically connected to the first data lines 31 and second data lines 32, placing the first power signal line 4 and the initialization signal line 5 between the first data lines 31 and second data lines 32 can reduce the distance between the first power signal line 4 and the initialization signal line 5 and the connected pixel circuits, which helps to reduce the voltage drop loss of the signals transmitted by the first power signal line 4 and the initialization signal line 5 during transmission.

[0131] Along the first direction h11, the first data line 31, the second data line 32, the first power signal line 4, and the initialization signal line 5 are arranged in at least one of the following orders: First data line 31, first power signal line 4, initialization signal line 5, second data line 32; or, first data line 31, initialization signal line 5, first power signal line 4, second data line 32.

[0132] Figure 11 and Figure 12 The arrangement of the first data line 31, the first power signal line 4, the initialization signal line 5, and the second data line 32 is shown in the diagram. Alternatively, as... Figure 13 and Figure 14 As shown, Figure 13 and Figure 14 These are schematic diagrams of two other display panels provided in embodiments of the present invention, wherein... Figure 13 and Figure 14 The arrangement of the first data line 31, initialization signal line 5, first power signal line 4, and second data line 32 is shown in the diagram.

[0133] like Figure 1 and Figure 10As shown, the first power signal line 4 and the initialization signal line 5 extend along the second direction h12; along the first direction h11, at least one first data line 31 and one second data line 32 are included between adjacent first power signal lines 4 and initialization signal lines 5. This arrangement, placing the first power signal line 4 and the initialization signal line 5 on opposite sides of the first data line 31 and the second data line 32, facilitates the connection of more pixel circuits. For example, the first power signal line 4 can be electrically connected not only to the pixel circuits electrically connected to the first data line 31 or the second data line 32, but also to other pixel circuits. Similarly, the initialization signal line 5 can be electrically connected not only to the pixel circuits electrically connected to the first data line 31 or the second data line 32, but also to other pixel circuits.

[0134] Along the first direction h11, the first data line 31, the second data line 32, the first power signal line 4, and the initialization signal line 5 are arranged in at least one of the following orders: First power signal line 4, first data line 31, second data line 32, initialization signal line 5; Or, such as Figure 1 and Figure 10 As shown, the first power signal line is 4, the second data line is 32, the first data line is 31, and the initialization signal line is 5. Alternatively, initialize signal line 5, first data line 31, second data line 32, and first power signal line 4; Alternatively, initialize signal line 5, second data line 32, first data line 31, and first power signal line 4.

[0135] For example, such as Figure 15 As shown, Figure 15 This is a schematic diagram of another display panel provided in an embodiment of the present invention. The display panel includes pixels 10. Each pixel 10 includes a first sub-pixel 11, a second sub-pixel 12, and a third sub-pixel 13 arranged along a first direction h11. Along the first direction h11, a first gap G1 is included between the first pixel circuit 1011 and the second pixel circuit 1012, a second gap G2 is included between the second pixel circuit 1012 and the third pixel circuit 1013, and a third gap G3 is included between the third pixel circuit 1013 and a pixel circuit 101 adjacent to it in another pixel 10, such as the first pixel circuit 1011.

[0136] For example, in embodiments of the present invention, at least two of the first data line 31, the second data line 32, the first power signal line 4, and the initialization signal line 5 may be located in one of the first gap G1, the second gap G2, and the third gap G3.

[0137] For example,Figure 15 The diagram illustrates the arrangement of the first power signal line 4 and the initialization signal line 5 within the first gap G1. This arrangement avoids overlap between vertical traces, such as the first data line 31, the second data line 32, the first power signal line 4, and the initialization signal line 5, and the pixel circuit, thereby reducing parasitic capacitance between these vertical traces and the pixel circuit. Furthermore, this arrangement fully utilizes the space saved by reducing the number of data lines, improving space utilization within the gap without needing to increase its width.

[0138] In another alternative implementation, such as Figure 16 As shown, Figure 16 This is a schematic diagram of another display panel provided in an embodiment of the present invention. The display panel includes pixels 10. Each pixel 10 includes a first sub-pixel 11, a second sub-pixel 12, a third sub-pixel 13, and a fourth sub-pixel 14 arranged along a first direction h11. Along the first direction h11, a first gap G1 is included between the first pixel circuit 1011 and the second pixel circuit 1012, a second gap G2 is included between the second pixel circuit 1012 and the third pixel circuit 101, a third gap G3 is included between the third pixel circuit 1013 and the fourth pixel circuit 1014, and a fourth gap G4 is included between the fourth pixel circuit 101 and the pixel circuit 101 adjacent to it in another pixel 10. The first data line 31, the second data line 32, the first power signal line 4, and the initialization signal line 5 are each located in one of the first gap G1, the second gap G2, the third gap G3, and the fourth gap G4. Figure 16 The diagram illustrates the arrangement of the initialization signal line 5 in the first gap G1, the first data line 31 in the second gap G2, the first power signal line 4 in the third gap G3, and the second data line 32 in the fourth gap G4. This arrangement allows different traces to be located in different gaps, making full use of the space saved by reducing the number of data lines and improving the uniformity of the trace distribution.

[0139] It should be noted that, as Figure 16 As shown, when pixels 10 are repeatedly arranged along the first direction h11, the pixel circuit adjacent to the fourth pixel circuit 101 can be the first pixel circuit 1011 in another pixel 10. When pixels 10 are arranged in other ways, the pixel circuit adjacent to the fourth pixel circuit 101 can also be other pixel circuits in another pixel 10, and the embodiments of the present invention do not limit this.

[0140] Optional, such as Figure 14As shown, the display panel includes pixels 10, each pixel 10 including a first sub-pixel 11, a second sub-pixel 12, a third sub-pixel 13, and a fourth sub-pixel 14 arranged along a first direction h11. Along the first direction h11, a first gap G1 exists between the first pixel circuit 1011 and the second pixel circuit 1012, a second gap G2 exists between the second pixel circuit 1012 and the third pixel circuit 101, a third gap G3 exists between the third pixel circuit 1013 and the fourth pixel circuit 1014, and a fourth gap G4 exists between the fourth pixel circuit 101 and adjacent pixel circuits 101 of another pixel 10, such as the first pixel circuit 1011. At least two of the first data line 31, the second data line 32, the first power signal line 4, and the initialization signal line 5 are located within one of the first gap G1, the second gap G2, the third gap G3, and the fourth gap G4. Figure 14 As shown, the first data line 31 and the second data line 32 are located in the same fourth gap G4 as an illustration.

[0141] For example, Figure 1 , Figure 3 , Figure 4 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 and Figure 16 The first light-emitting element 1021 emits red light, the second light-emitting element 1022 emits green light, and the third light-emitting element 1023 emits blue light; or, the first light-emitting element 1021 emits red light, the second light-emitting element 1022 emits blue light, and the third light-emitting element 1023 emits green light; or, the first light-emitting element 1021 emits green light, the second light-emitting element 1022 emits blue light, and the third light-emitting element 1023 emits red light.

[0142] For example, Figure 10 , Figure 12 , Figure 14 and Figure 16The first light-emitting element 1021 emits red light, the second light-emitting element 1022 emits green light, the third light-emitting element 1023 emits blue light, and the fourth light-emitting element 1024 emits white light; or, the first light-emitting element 1021 emits red light, the second light-emitting element 1022 emits blue light, the third light-emitting element 1023 emits green light, and the fourth light-emitting element 1024 emits white light; or, the first light-emitting element 1021 emits red light, the second light-emitting element 1022 emits white light, the third light-emitting element 1023 emits green light, and the fourth light-emitting element 1024 emits blue light. Alternatively, the first light-emitting element 1021 emits blue light, the second light-emitting element 1022 emits white light, the third light-emitting element 1023 emits red light, and the fourth light-emitting element 1024 emits green light; or, the first light-emitting element 1021 emits green light, the second light-emitting element 1022 emits white light, the third light-emitting element 1023 emits red light, and the fourth light-emitting element 1024 emits blue light; or, the first light-emitting element 1021 emits green light, the second light-emitting element 1022 emits blue light, the third light-emitting element 1023 emits red light, and the fourth light-emitting element 1024 emits white light.

[0143] Optionally, in embodiments of the present invention, the green sub-pixel and the blue sub-pixel can be electrically connected to different data lines. The light-emitting element in the green sub-pixel emits green light, while the light-emitting element in the blue sub-pixel emits blue light. The blue sub-pixel requires a higher data voltage, while the green sub-pixel requires a lower data voltage, resulting in a significant difference in their luminous efficiency. If both are connected to the same sub-pixel, the voltage switching will be substantial. By electrically connecting the green and blue sub-pixels to different data lines, embodiments of the present invention can reduce the data voltage switching.

[0144] In one optional implementation, along the first direction h11, the embodiments of the present invention can position the first power signal line and the first data line on both sides of the blue sub-pixel, with both the power signal line and the first data line adjacent to the blue sub-pixel. The voltage difference between the first power signal and the data signal transmitted by the first power signal line and the first data line respectively is small. Using this arrangement, a more balanced electric field environment can be provided for the blue sub-pixel that requires a larger data voltage.

[0145] For example, in this embodiment of the invention, the pixel circuits 101 of R sub-pixels 1 arranged along the first direction h11 are connected to the same first power signal line 4, and the pixel circuits 101 of S sub-pixels 1 arranged along the first direction h11 are connected to the same initialization signal line 5, where R≥1 and S≥1. Figure 1 ,Figure 3 , Figure 11 , Figure 13 , Figure 15 The example uses R=S=6. Figure 10 , Figure 12 , Figure 14 , Figure 16 The example uses R=S=4.

[0146] In an optional implementation, embodiments of the present invention may set R=S. This configuration allows the loads on the first power signal line 4 and the initialization signal line 5 to be as consistent as possible.

[0147] In another alternative implementation, the embodiments of the present invention may also set R < S. This arrangement can shorten the distance between the first power signal line 4 and the pixel circuit connected to it, which helps to reduce the voltage drop of the first power signal.

[0148] In another alternative implementation, the embodiments of the present invention may further set R > S. This arrangement can shorten the distance between the initialization signal line 5 and the pixel circuit connected to it, which helps to reduce the voltage drop of the initialization signal.

[0149] like Figure 1 , Figure 3 , Figure 4 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 and Figure 16 As shown, the pixel circuits 101 of R sub-pixels 1 are connected to the first power signal line 4 via the first connection line 41, and the pixel circuits 101 of S sub-pixels 1 are connected to the initialization signal line 5 via the second connection line 51. This configuration reduces the number of the first power signal line 4 and the initialization signal line 5.

[0150] For example, the pixel circuit 101 of R sub-pixels 1 connected to the first power signal line 4 via the first connection line 41 and the pixel circuit 101 of S sub-pixels 1 connected to the initialization signal line 5 via the second connection line 51 can be completely identical, or at least partially identical, or completely different. This embodiment of the invention does not limit this. Figure 1 , Figure 3 and Figure 10 To illustrate with completely different examples. Figure 4 Using partial similarities as an illustration. Figure 11 , Figure 13 , Figure 15 , Figure 11 , Figure 12 , Figure 13 , Figure 14, Figure 15 and Figure 16 Using identical examples as an illustration.

[0151] For example, such as Figure 9 As shown, in a direction perpendicular to the substrate of the display panel, at least one first connecting line 41 and at least one second connecting line 51 do not overlap. This arrangement reduces the parasitic capacitance between the first connecting line 41 and the second connecting line 51.

[0152] In another alternative implementation, for example, such as Figure 17 As shown, Figure 17 This is a schematic diagram of another display panel layout provided in an embodiment of the present invention. In the direction perpendicular to the substrate of the display panel, at least one first connecting line 41 and at least one second connecting line 51 at least partially overlap to reduce the space occupied by the first connecting line 41 and the second connecting line 51 for the lateral traces.

[0153] For example, such as Figure 17 As shown, the width of at least one first connecting line 41 is greater than the width of at least one second connecting line 51. This is to reduce the voltage drop of the first power signal during transmission. In this embodiment of the invention, the first power signal is directly related to the driving current generated by the pixel circuit. The driving current affects the brightness of the light-emitting element. Therefore, by adopting the method provided in this embodiment of the invention, the stability of the driving current can be guaranteed, which is beneficial to improving the brightness uniformity of the light-emitting element at different locations.

[0154] In one alternative implementation, exemplarily, such as Figure 18 As shown, Figure 18 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Along the first direction h11, a first connecting line 41 connected to a first power signal line 4 is located on the same side of the first power signal line 4, and a second connecting line 51 connected to an initialization signal line 5 is distributed on both sides of the initialization signal line 5. By adopting this arrangement, multiple pixel circuit arrays connected to the first power signal line 4 can be located on the same side of the first power signal line 4, and multiple pixel circuit arrays electrically connected to the initialization signal line 5 can be located on both sides of the initialization signal line 5. This makes the distance between the initialization signal line 5 and the multiple different pixel circuit arrays connected to it tend to be consistent, thereby improving the consistency of the initialization signals received by the multiple different pixel circuit arrays.

[0155] Alternatively, in another alternative implementation, such as Figure 19 As shown, Figure 19This is a schematic diagram of another display panel provided in an embodiment of the present invention. Along the first direction h11, first connecting lines 41 connected to the first power signal line 4 are distributed on both sides of the first power signal line 4, and second connecting lines 51 connected to the initialization signal line 5 are located on the same side of the initialization signal line 5. By adopting this arrangement, multiple pixel circuit arrays connected to the initialization signal line 5 can be located on the same side of the initialization signal line 5, and multiple pixel circuit arrays electrically connected to the first power signal line 4 can be located on both sides of the first power signal line 4. This makes the distance between the first power signal line 4 and the multiple different pixel circuit arrays connected to it tend to be consistent, thereby improving the consistency of the first power signal received by the multiple different pixel circuit arrays.

[0156] For example, along the first direction h11, the embodiments of the present invention can make the number of second connecting lines 51 distributed on both sides of the initialization signal line 5 equal.

[0157] like Figure 18 As shown, there are two second connection lines 51 on both sides of the initialization signal line 5. The two second connection lines 51 on the left side of the initialization signal line 5 are electrically connected to the first pixel circuit 1011 and the second pixel circuit 1012, respectively, and the two second connection lines 51 on the right side of the initialization signal line 5 are electrically connected to the third pixel circuit 1013 and the fourth pixel circuit 1014, respectively.

[0158] It should be noted that, Figure 18 This illustration only shows two second connecting lines 51 located on the same side of the initialization signal line 5 being interconnected, that is, the second connecting line 51 electrically connected to the first pixel circuit 1011 is connected to the initialization signal line 5 through the second connecting line 51 electrically connected to the second pixel circuit 1012. In another optional embodiment, the two second connecting lines 51 located on the same side of the initialization signal line 5 may also be unconnected, and this embodiment is not limited thereto.

[0159] Alternatively, in another optional implementation, along the first direction h11, the number of first connecting lines 41 distributed on both sides of the first power signal line 4 may be equal.

[0160] like Figure 19 As shown, there are two first connecting lines 41 on both sides of the first power signal line 4. The two first connecting lines 41 on the left side of the first power signal line 4 are electrically connected to the first pixel circuit 1011 and the second pixel circuit 1012, respectively, and the two first connecting lines 41 on the right side of the first power signal line 4 are electrically connected to the third pixel circuit 1013 and the fourth pixel circuit 1014, respectively.

[0161] It should be noted that, Figure 19This illustration only shows two first connecting lines 41 located on the same side of the first power signal line 4 being interconnected, that is, the first connecting line 41 electrically connected to the first pixel circuit 1011 is connected to the first power signal line 4 through the first connecting line 41 electrically connected to the second pixel circuit 1012. In another optional embodiment, the two first connecting lines 41 located on the same side of the first power signal line 4 may not be interconnected, and this embodiment is not limited thereto.

[0162] In yet another alternative implementation, such as Figure 20 As shown, Figure 20 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Along the first direction h11, a first connecting line 41 connected to a first power signal line 4 is located on the same side of the first power signal line 4, and a second connecting line 51 connected to an initialization signal line 5 is located on the same side of the initialization signal line 5. With this arrangement, multiple pixel circuit arrays connected to the first power signal line 4 can be located on the same side of the first power signal line 4, and multiple pixel circuit arrays connected to the initialization signal line 5 can be located on the same side of the initialization signal line 5.

[0163] Alternatively, in another alternative implementation, such as Figure 10 As shown, along the first direction h11, first connecting lines 41 connected to the first power signal line 4 are distributed on both sides of the first power signal line 4, and second connecting lines 51 connected to the initialization signal line 5 are distributed on both sides of the initialization signal line 5. This arrangement allows multiple pixel circuit arrays connected to the first power signal line 4 to be located on both sides of the first power signal line 4, and also allows multiple pixel circuit arrays electrically connected to the initialization signal line 5 to be located on both sides of the initialization signal line 5. This makes the distance between the first power signal line 4 and the multiple different pixel circuit arrays connected to it more consistent, improving the consistency of the first power signal received by the multiple different pixel circuit arrays. Similarly, making the distance between the initialization signal line 5 and the multiple different pixel circuit arrays connected to it more consistent improves the consistency of the initialization signal received by the multiple different pixel circuit arrays.

[0164] For example, along the first direction h11, the number of first connecting lines 41 distributed on both sides of the first power signal line 4 is equal; Figure 10 The diagram illustrates two first connecting lines 41 located on each side of the first power signal line 4. This arrangement allows the distance between pixel circuits electrically connected to different first connecting lines 41 and the first power signal line 4 to be closer, reducing the delay differences in signals received by different pixel circuits.

[0165] Alternatively, in another optional implementation, the number of second connecting lines 51 distributed on both sides of the initialization signal line 5 along the first direction h11 is equal. Figure 10 The diagram illustrates two second connection lines 51 located on both sides of the initialization signal line 5. This arrangement allows the pixel circuits electrically connected to different second connection lines 51 to be closer together with the initialization signal line 5, reducing the delay differences in signals received by different pixel circuits.

[0166] For example, such as Figure 21 As shown, Figure 21 This is a schematic diagram of a display panel layout provided in another embodiment of the present invention. A first sub-pixel 11 and a second sub-pixel 12 are arranged along a first direction h11. A first sub-scan line 211 is connected to a first node N1 of a first pixel circuit 1011, and a second sub-scan line 212 is connected to a first node N1 of a second pixel circuit 1012. Along the second direction h12, the distance between the first sub-scan line 211 and the first node N1 of the first pixel circuit 1011 is D1, and the distance between the second sub-scan line 212 and the first node N1 of the second pixel circuit 1012 is D2, where D1 ≥ 0 and D2 ≥ 0. When the distance D1 = 0, it indicates that the first sub-scan line 211 and the first node N1 of the first pixel circuit 1011 overlap in a direction perpendicular to the substrate of the display panel. When the distance D2 = 0, it indicates that the second sub-scan line 212 and the first node N1 of the second pixel circuit 1012 overlap in a direction perpendicular to the substrate of the display panel. Optionally, in this embodiment of the invention, D1 ≠ D2. Figure 21 The example uses D2 > 0 and D1 = 0.

[0167] For example, such as Figure 9 As shown, the first sub-pixel 11 and the second sub-pixel 12 are arranged along the first direction h11; the first sub-scan line 211 is connected to the first node N1 of the first pixel circuit 1011, and the second sub-scan line 212 is connected to the first node N1 of the second pixel circuit 1012; along the second direction h12, the distance between the first sub-scan line 211 and the first node N1 of the first pixel circuit 1011 is D1, and the distance between the second sub-scan line 212 and the first node N1 of the second pixel circuit 1012 is D2, where D1≥0, D2≥0, and D1=D2. Figure 9 The first sub-scan line 211 and the first node N1 of the first pixel circuit 1011 overlap in a direction perpendicular to the substrate of the display panel, and the second sub-scan line 212 and the first node N1 of the second pixel circuit 1012 overlap in a direction perpendicular to the substrate, i.e., D1=D2=0, as an illustration.

[0168] For example, such as Figure 2As shown, the pixel circuit 101 includes a first transistor T1, a first scan line 21 connected to the first transistor T1, and a first node N1 serving as the gate of the first transistor T1. The signal from the first scan line 21 can control the first transistor T1 to turn on or off.

[0169] For example, such as Figure 22 As shown, Figure 22 This is a schematic diagram of another display panel layout provided by an embodiment of the present invention. In this embodiment, the position of the first node N1 in the first pixel circuit 1011 can be the same as the position of the first node N1 in the second pixel circuit 1012. The position of the first node in the pixel circuit refers to its position relative to a reference point. For example, this reference point includes the first capacitor C1 in the pixel circuit. Figure 22 The diagram illustrates a scenario where the first node N1 in the first pixel circuit 1011 is located below the first capacitor C1, and the first node N1 in the second pixel circuit 1012 is also located below the first capacitor C1. This arrangement allows the first pixel circuit 1011 and the second pixel circuit 1012 to use the same layout, facilitating design and manufacturing.

[0170] Optionally, in this embodiment of the invention, the first pixel circuit 1011 includes P1 transistors and Q1 capacitors, and the second pixel circuit 1012 includes P2 transistors and Q2 capacitors, where P1≥1, Q1≥1, P2≥1, and Q2≥1. For example, in this embodiment of the invention, both the first pixel circuit 1011 and the second pixel circuit 1012 can be configured as follows: Figure 2 The design is as shown. In this case, both the first pixel circuit 1011 and the second pixel circuit 1012 include three transistors and one capacitor. That is, P1=P2=3; Q1=Q2=1. Figure 22 The map shown is Figure 2 The circuit structure shown corresponds to this.

[0171] For example, such as Figure 22 As shown, in this embodiment of the invention, the arrangement positions of P1 transistors and Q1 capacitors in the first pixel circuit 1011 are set to be the same as the arrangement positions of P2 transistors and Q2 capacitors in the second pixel circuit 1012. This arrangement allows the first pixel circuit 1011 and the second pixel circuit 1012 to use the same layout, facilitating design and manufacturing.

[0172] It should be noted that transistors in the same position can have the same or different dimensions. Similarly, capacitors in the same position can also have the same or different dimensions; this embodiment of the invention does not limit this. For example, in this embodiment, the channel width-to-length ratio of transistors in the pixel circuit connected to some colors of light-emitting elements can be set to be larger, while the channel width-to-length ratio of transistors in the pixel circuit connected to other colors of light-emitting elements can be set to be smaller.

[0173] In another alternative implementation, the positions of the first node N1 in the first pixel circuit 1011 and the first node N1 in the second pixel circuit 1012 may be different. Figure 9 The diagram illustrates the situation where the first node N1 in the first pixel circuit 1011 is located to the lower left of the first capacitor C1, and the first node N1 in the second pixel circuit 1012 is located to the lower right of the first capacitor C1. This arrangement allows for flexible adjustment of the position of the first node N1 according to wiring requirements.

[0174] Optionally, in this embodiment of the invention, the first pixel circuit 1011 includes P1 transistors and Q1 capacitors, and the second pixel circuit 1012 includes P2 transistors and Q2 capacitors, where P1≥1, Q1≥1, P2≥1, and Q2≥1; the first scan line 21 is connected to the first transistor T1 of the pixel circuit 101, and the first node N1 is the gate of the first transistor T1; the arrangement position of at least the first transistor T1 among the P1 transistors and Q1 capacitors in the first pixel circuit 1011 is different from the arrangement position of at least the first transistor T1 among the P2 transistors and Q2 capacitors in the second pixel circuit 1012. Figure 9 The diagram illustrates the situation where the first transistor T1 in the first pixel circuit 1011 is located to the lower left of the first capacitor C1, and the first transistor T1 in the second pixel circuit 1012 is located to the lower right of the first capacitor C1. This arrangement allows for flexible adjustment of the position of the first transistor T1 according to wiring requirements.

[0175] like Figure 23 As shown, Figure 23 This is a schematic diagram of the layout of another display panel provided in an embodiment of the present invention. Along the second direction h12, the first sub-scan line 211 is located on the first side of the first node N1 of the first pixel circuit 1011, and the second sub-scan line 212 is located on the second side of the first node N1 of the second pixel circuit 1012. The first side and the second side are opposite sides along the second direction h12. Figure 23The diagram illustrates a scenario where the first sub-scan line 211 is located below the first node N1 of the first pixel circuit 1011, and the second sub-scan line 212 is located above the first node N1 of the second pixel circuit 1012. This arrangement increases the distance between the first sub-scan line 211 and the second sub-scan line 212, which helps reduce the coupling between them.

[0176] Optional, such as Figure 9 As shown, along the second direction h12, the first sub-scan line 211 is located on the first side of the first node N1 of the first pixel circuit 1011, and the second sub-scan line 212 is located on the first side of the first node N1 of the second pixel circuit 1012. This arrangement allows the first sub-scan line 211 and the second sub-scan line 212 to be grouped together, which helps to shorten the length of the connection between the first sub-scan line 211 or the second sub-scan line 212 and the first node N1, thereby improving the consistency of signal transmission between the first sub-scan line 211 or the second sub-scan line 212.

[0177] like Figure 9 and Figure 21 As shown, the first sub-scan line 211 is connected to the first node N1 of the first pixel circuit 1011 through the first transition line 61, and the second sub-scan line 212 is connected to the first node N1 of the second pixel circuit 1012 through the second transition line 62; along the second direction h12, the length of the first transition line 61 is L1, and the length of the second transition line 62 is L2; ​​wherein, L1≥0, L2≥0, and L1=L2, or, L1≠L2. Figure 9 The example uses L1=L2. Figure 21 Using L1≠L2 as an example, the first transition line 61 and the second transition line 62 can be set according to the distance between the first sub-scan line 211 and the second sub-scan line 212 and their respective first nodes N1. Optionally, the first transition line 61 and the second transition line 62 can be straight lines or broken lines.

[0178] For example, such as Figure 21 As shown, in this embodiment of the invention, the width of the first sub-scan line 211 is W1, and the width of the second sub-scan line 212 is W2; wherein (D1-D2)×(W1-W2)>0. This configuration allows the resistances of the first sub-scan line 211 and the second sub-scan line 212 to tend to be consistent, which is beneficial for improving the charging consistency of the first sub-pixel 11 and the second sub-pixel 12. Figure 21 The example uses D1=0, D2>0, and W1<W2.

[0179] like Figure 24 As shown, Figure 24This is a schematic diagram of another display panel provided in an embodiment of the present invention. The scan line 2 further includes a second scan line 22, which extends along the first direction h11, as shown in Figure 2. The pixel circuit 101 further includes a second transistor T2, and the second scan line 22 is connected to the second transistor T2. The second scan line 22 is connected to the second transistor T2 in the first pixel circuit 1011 and also to the second transistor T2 in the second pixel circuit 1012.

[0180] Alternatively, in another implementation, such as Figure 25 As shown, Figure 25 This is a schematic diagram of another display panel provided in an embodiment of the present invention. The second scan line 22 includes a third sub-scan line 221 and a fourth sub-scan line 222. The third sub-scan line 221 is connected to the first pixel circuit 1011, and the fourth sub-scan line 222 is connected to the second pixel circuit 1012. With this configuration, the second transistor T2 in the first pixel circuit 1011 and the second transistor T2 in the second pixel circuit 1012 can independently receive scan signals; for example, they can be controlled to conduct in a time-division manner.

[0181] For example, such as Figure 2 As shown, the pixel circuit 101 includes a first transistor T1 and a second transistor T2; the first scan line 21 is connected to the first transistor T1; and the second scan line 22 is connected to the second transistor T2.

[0182] The first sub-scan line 211, the second sub-scan line 212, the third sub-scan line 221, and the fourth sub-scan line 222 are arranged along the second direction h12, and the arrangement order satisfies at least one of the following: the first sub-scan line 211, the second sub-scan line 212, the third sub-scan line 221, and the fourth sub-scan line 222; or the first sub-scan line 211, the third sub-scan line 221, the second sub-scan line 212, and the fourth sub-scan line 222; or the first sub-scan line 211, the third sub-scan line 221, the fourth sub-scan line 222, and the second sub-scan line 212.

[0183] Figure 25 The arrangement is illustrated by the order of the first sub-scan line 211, the second sub-scan line 212, the third sub-scan line 221, and the fourth sub-scan line 222.

[0184] In yet another alternative implementation, such as Figure 26 and Figure 27 As shown, Figure 26 and Figure 27The following is a schematic diagram of two other display panels provided in the embodiments of the present invention. Sub-pixel 1 further includes a third sub-pixel 13. The third sub-pixel 13 includes a third pixel circuit 1013 and a third light-emitting element 1023. The first light-emitting element 1021, the second light-emitting element 1022 and the third light-emitting element 1023 emit different colors of light. The first data line 31 is also connected to the third pixel circuit 1013. The first scan line 21 includes a fifth sub-scan line 213, which is connected to the third pixel circuit 101.

[0185] When the display panel is operating, the first data line 31 provides a third data signal to the third pixel circuit 1013. This first scan signal includes a fifth sub-scan signal, which is provided by the fifth sub-scan line 213. The first pixel circuit 1011, the second pixel circuit 1012, and the third pixel circuit 1013 can each receive the data signal provided by the first data line 31 under the control of the first sub-scan line 211, the second sub-scan line 212, and the fifth sub-scan line 213. For example, the first data line 31 can provide a first data signal to the first pixel circuit 1011, a second data signal to the second pixel circuit 1012, and a third data signal to the third pixel circuit 1013.

[0186] This configuration can further reduce the number of first data lines 31 and simplify the structure of the display panel.

[0187] For example, such as Figure 27 As shown, sub-pixel 1 also includes a fourth sub-pixel 14, which includes a fourth pixel circuit 1014 and a fourth light-emitting element 1024. The first light-emitting element 1021, the second light-emitting element 1022, the third light-emitting element 1023 and the fourth light-emitting element 1024 emit different colors of light. The first data line 31 is also connected to the fourth pixel circuit 1014. The first scan line 21 includes a sixth sub-scan line 214, which is connected to the fourth pixel circuit 1014.

[0188] When the display panel is operating, the first data line 31 provides a fourth data signal to the fourth pixel circuit 1014. This first scan signal includes a sixth sub-scan signal, which is provided by the sixth sub-scan line 214. The first pixel circuit 1011, second pixel circuit 1012, third pixel circuit 1013, and fourth pixel circuit 1014 can receive the data signal provided by the first data line 31 under the control of the first sub-scan line 211, second sub-scan line 212, fifth sub-scan line 213, and sixth sub-scan line 214, respectively. For example, the first data line 31 can provide a first data signal to the first pixel circuit 1011, a second data signal to the second pixel circuit 1012, a third data signal to the third pixel circuit 1013, and a fourth data signal to the fourth pixel circuit 1014.

[0189] This configuration can further reduce the number of first data lines 31 and simplify the structure of the display panel.

[0190] For example, in this embodiment of the invention, the data line 3 provides a data signal to the pixel circuit 101; the scan line 2 provides a scan signal to the pixel circuit 101; wherein, the first data line 31 provides a first data signal to the first pixel circuit 1011, and the first data line 31 provides a second data signal to the second pixel circuit 1012; the first scan line 2 provides a first scan signal to the pixel circuit 101, such as... Figure 28 As shown, Figure 28 This is a schematic diagram of the working timing of a display panel provided in an embodiment of the present invention. The first scanning signal includes a first sub-scanning signal S211 and a second sub-scanning signal S212. The first sub-scanning line 211 provides the first sub-scanning signal S211 to the first pixel circuit 1011, and the second sub-scanning line 212 provides the second sub-scanning signal S212 to the second pixel circuit 1012.

[0191] For example, such as Figure 28 As shown, within one screen refresh cycle of the display panel, there is no overlap between the effective pulses of the first sub-scan signal S211 and the effective pulses of the second sub-scan signal S212. Figure 28 The effective pulses of both are illustrated by a low level.

[0192] Optionally, after the effective pulse of the first sub-scan signal S211 ends, the data signal on the first data line 31 switches from the first data signal to the second data signal, and then the effective pulse of the second sub-scan signal S212 is activated. This configuration allows sufficient switching time for the data signal on the first data line 31, preventing the first data signal corresponding to the first sub-pixel 11 from being mistakenly written into the second sub-pixel 12.

[0193] For example, such asFigure 29 As shown, Figure 29 This is a schematic diagram illustrating the operating timing of another display panel according to an embodiment of the present invention. Within one screen refresh cycle of the display panel, the effective pulses of the first sub-scan signal S211 and the effective pulses of the second sub-scan signal S212 at least partially overlap. This arrangement helps to shorten the screen refresh cycle of the display panel and improve its refresh rate.

[0194] like Figure 29 As shown, the effective pulse of the second sub-scan signal S212 begins before the effective pulse of the first sub-scan signal S211 ends; the effective pulse of the second sub-scan signal S212 ends after the effective pulse of the first sub-scan signal S211 ends; and the first data signal changes to the second data signal after the effective pulse of the first sub-scan signal S211 ends. This configuration helps to shorten the screen refresh cycle of the display panel and improve its refresh rate.

[0195] like Figure 1 As shown, the display panel includes a T-row of sub-pixel rows 1r arranged along the second direction h12, a plurality of first sub-scan lines 211, and a plurality of second sub-scan lines 212; Figure 1 The diagram uses two sub-pixel rows 1r as an example.

[0196] like Figure 30 As shown, Figure 30 This is a schematic diagram illustrating the operating timing of another display panel according to an embodiment of the present invention. Within one screen refresh cycle of the display panel, the effective pulses of the second sub-scan signal S212_i on the second sub-scan line 212 connected to the pixel circuit 101 of the i-th sub-pixel row 1r and the effective pulses of the first sub-scan signal S211_j on the first sub-scan line 211 connected to the pixel circuit 101 of the j-th sub-pixel row 1r at least partially overlap, 0≤i≤T, 0≤j≤T, and i≠j. This configuration can shorten the screen refresh cycle of the display panel, which is beneficial for improving the refresh rate of the display panel.

[0197] like Figure 31 As shown, Figure 31This is a schematic diagram of the working timing of another display panel provided in an embodiment of the present invention. Within one screen refresh cycle of the display panel, the effective pulses of the second sub-scan signal S212_i on the second sub-scan line 212 connected to the pixel circuit 101 of the i-th sub-pixel row 1r and the effective pulses of the first sub-scan signal S211_j on the first sub-scan line 211 connected to the pixel circuit 101 of the j-th sub-pixel row 1r do not overlap, 0≤i≤T, 0≤j≤T, and i≠j. Using this method, the pixel circuit 101 of the i-th sub-pixel row 1r and the pixel circuit 101 of the j-th sub-pixel row 1r can perform data signal writing in a time-division manner, making the data signal writing more stable and avoiding mutual interference between data signals of different sub-pixel rows.

[0198] like Figure 1 As shown, the display panel includes a T-row of sub-pixel rows 1r arranged along the second direction h12, multiple first sub-scan lines 211, and multiple second sub-scan lines 212. Combined with... Figure 32 As shown, Figure 32 This is a schematic diagram illustrating the operating timing of another display panel according to an embodiment of the present invention. Within one screen refresh cycle of the display panel, the effective pulse of the first sub-scan signal S211_i on the first sub-scan line 211 connected to the pixel circuit 101 of the i-th sub-pixel row 1r is activated earlier than the effective pulse of the second sub-scan signal S212_i on the second sub-scan line 212 connected to the pixel circuit 101 of the i-th sub-pixel row 1r. Conversely, the effective pulse of the first sub-scan signal S211_j on the first sub-scan line 211 connected to the pixel circuit 101 of the j-th sub-pixel row 1r is activated later than the effective pulse of the second sub-scan signal S212_j on the second sub-scan line 212 connected to the pixel circuit 101 of the j-th sub-pixel row 1r, where 0≤i≤T, 0≤j≤T, and i≠j. Using this configuration, the first pixel circuits in some pixel rows can begin charging first, while the second pixel circuits in other pixel rows begin charging later, thus balancing the charging consistency of pixel circuits in different areas.

[0199] For example, in one optional implementation, the width of the effective pulse of the first sub-scan signal S211 can be made equal to the width of the effective pulse of the second sub-scan signal S212. By using this setting, the write time of the data voltage of the first pixel circuit 1011 can be made equal to the write time of the data voltage of the second pixel circuit 1012, thereby improving the charging consistency of the first pixel circuit 1011 and the second pixel circuit 1012.

[0200] In another optional embodiment, the width of the effective pulse of the first sub-scan signal S211 may be greater than or less than the width of the effective pulse of the second sub-scan signal S212. Using this setting, the write time of the data voltage of the first pixel circuit 1011 can be greater than or less than the write time of the data voltage of the second pixel circuit 1012, thereby matching the charging of the first pixel circuit 1011 and the second pixel circuit 1012 with different display requirements.

[0201] Optional, such as Figure 28 , Figure 29 , Figure 30 , Figure 31 and Figure 32 As shown, in this embodiment of the invention, the effective pulse of the first sub-scan signal S211 can be turned on earlier than the effective pulse of the second sub-scan signal S212.

[0202] Or, such as Figure 33 As shown, Figure 33 This is a schematic diagram of the working timing of another display panel provided in an embodiment of the present invention. In this embodiment of the present invention, the effective pulse of the first sub-scan signal S211 can be turned on later than the effective pulse of the second sub-scan signal S212.

[0203] For example, in an embodiment of the present invention, the operation of the display panel includes an initialization phase and a sampling phase; in the initialization phase, Figure 2 The initialization signal is received on the initialization signal line 5 shown. The second transistor T2 is turned on, and the initialization signal can be written to the anode of the light-emitting element 102 through the second transistor T2 to reset the light-emitting element 102. During the sampling phase, the signal on the initialization signal line 5 is in a floating state. The initialization signal line 5 can provide the potential of the first electrode of the third transistor T3 to the external compensation circuit. The external compensation circuit can adjust the voltage on the data line 3 according to the received potential of the first electrode of the third transistor T3, thereby achieving external compensation for the pixel circuit.

[0204] Optional, such as Figure 2 As shown, the light-emitting element 102 of the display panel includes a first electrode E1 and a second electrode E2; the first electrode E1 is connected to the pixel circuit 101, and the second electrode E2 is connected to the second power signal line 7 to receive a second power signal; wherein, the aforementioned initialization signal line 5 can receive the second power signal. For example, the voltage of the second power signal can be less than the voltage of the first power signal.

[0205] Optional, such as Figure 34 As shown, Figure 34This is a schematic diagram of a control unit in a display panel according to an embodiment of the present invention. The display panel further includes a control unit 8 and a data line. Figure 34 Electrical connection (not shown); the control unit 8 includes a storage module 81 and a control module 82; the storage module 81 stores the mapping relationship between the display parameters of the display panel and the data voltage; the control module 82 is used to retrieve the corresponding data voltage from the storage module 81 according to the display parameters and provide the data voltage to the data line.

[0206] For example, the above mapping relationship can be obtained by testing the first batch of panels. The specific testing process includes lighting the panel with a certain data voltage for a certain period of time, detecting the corresponding brightness, and storing the correspondence between brightness, time, and data voltage.

[0207] This configuration allows the data voltage supplied to the data line to correspond to the display parameters, compensating for factors such as the drift of the threshold voltage of the driving transistor in the pixel circuit. This helps improve the stability of the driving current generated by the pixel circuit and enhances the display consistency of the display panel.

[0208] For example, such as Figure 2 As shown, the pixel circuit 101 includes at least a first transistor T1, a second transistor T2, a third transistor T3, and a first capacitor C1; the first transistor T1 is connected between the data line 3 and the gate of the third transistor T3; the second transistor T2 is connected between the initialization signal line 5 and the light-emitting element 102; the third transistor T3 is connected between the first power signal line 4 and the light-emitting element 102; exemplarily, the third transistor T3 is a driving transistor. The first capacitor C1 is connected between the gate of the third transistor T3 and the light-emitting element 102; exemplarily, as... Figure 2 As shown, in this embodiment of the invention, the third transistor T3 can be configured as an N-type transistor.

[0209] Or, such as Figure 35 As shown, Figure 35 This is a schematic diagram of an equivalent circuit for another sub-pixel provided in an embodiment of the present invention. In this embodiment, the first capacitor C1 can also be connected between the first power signal line 4 and the gate of the third transistor T3; as shown... Figure 35 As shown, in this embodiment of the invention, the third transistor T3 can be configured to include a P-type transistor.

[0210] In this embodiment of the invention, the gate of the first transistor T1 is connected to the first scan line 21; or, in this embodiment of the invention, the gate of the second transistor T2 may also be connected to the first scan line 21. Figure 2 and Figure 35 The second transistor T2 is connected to the second scan line 22 as an example.

[0211] In another alternative implementation, such as Figure 36 As shown, Figure 36 This is a schematic diagram of an equivalent circuit for another sub-pixel provided in an embodiment of the present invention. The pixel circuit includes at least a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor, and a first capacitor. The first transistor T1 is connected between the data line 3 and the first terminal of the seventh transistor T7. For example, the seventh transistor T7 is a driving transistor, and the second transistor T2 can be used as a threshold compensation transistor. The second transistor T2 is connected between the first terminal and the gate of the seventh transistor T7. The third transistor T3 is connected between the first terminal of the seventh transistor T7 and the light-emitting element 102. The fourth transistor T4 is connected between the initialization signal line 5 and the light-emitting element 102. The fifth transistor T5 is connected between the initialization signal line 5 and the gate of the seventh transistor T7. The sixth transistor T6 is connected between the first power signal line 4 and the second terminal of the seventh transistor T7.

[0212] For example, such as Figure 36 As shown, the first capacitor C1 is connected between the gate of the seventh transistor T7 and the light-emitting element 102; optionally, the seventh transistor T7 includes an N-type transistor.

[0213] Or, such as Figure 37 As shown, Figure 37 The present invention provides an equivalent circuit diagram of another sub-pixel. The first capacitor C1 can also be connected between the first power signal line 4 and the gate of the seventh transistor T7. Optionally, the seventh transistor T7 includes a P-type transistor.

[0214] Among them, such as Figure 36 and Figure 37 As shown, the gate of the first transistor T1 is connected to the first scan line 21. For example, the gate of the second transistor T2 can also be connected to the first scan line 21. The gates of the fourth transistor T4 and the fifth transistor T5 can be connected to the second scan line 22. The gates of the third transistor T3 and the sixth transistor T6 are connected to the third scan line 23.

[0215] Based on the same inventive concept, embodiments of the present invention also provide a display device, such as... Figure 38 As shown, Figure 38 This is a schematic diagram of a display device provided in an embodiment of the present invention. The display device includes the display panel 100 described above. The specific structure of the display panel 100 has been described in detail in the above embodiments and will not be repeated here. Of course, Figure 38 The display device shown is for illustrative purposes only. The display device can be any electronic device with display function, such as a mobile phone, tablet computer, laptop computer, e-reader or television.

[0216] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0217] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that, include: Sub-pixel, the sub-pixel comprising pixel circuitry and light-emitting elements; A scan line, which is connected to the pixel circuit, extends along a first direction; A data line, which is connected to the pixel circuit, extends along a second direction, and the first direction intersects the second direction; The sub-pixel includes at least a first sub-pixel and a second sub-pixel. The first sub-pixel includes a first pixel circuit and a first light-emitting element. The second sub-pixel includes a second pixel circuit and a second light-emitting element. The first light-emitting element and the second light-emitting element emit light of different colors. The data line includes a first data line, which is connected to the first pixel circuit and the second pixel circuit. The scan line includes a first scan line, the first scan line includes a first sub-scan line and a second sub-scan line, the first sub-scan line is connected to the first pixel circuit, and the second scan line is connected to the second pixel circuit; The display panel further includes a first power signal line and an initialization signal line, wherein the first power signal line is connected to the pixel circuit, and the initialization signal line is connected to the pixel circuit; wherein... The display panel must satisfy at least one of the following: The first power signal line extends along the second direction, and along the first direction, at least one first power signal line is included between adjacent first data lines; or... The initialization signal line extends along the second direction, and along the first direction, at least one initialization signal line is included between adjacent first data lines.

2. The display panel according to claim 1, characterized in that, Both the first power signal line and the initialization signal line extend along the second direction; Along the first direction, there is at least one first power signal line and at least one initialization signal line between adjacent first data lines.

3. The display panel according to claim 1, characterized in that, The display panel includes pixels, and the pixels include at least a first sub-pixel and a second sub-pixel arranged along the first direction; Along the first direction, a first gap is included between the first pixel circuit and the second pixel circuit; The display panel shall satisfy at least one of the following: The first power signal line extends along the second direction, and along the first direction, at least one of the first data line and the first power signal line is located in the first gap; or... The initialization signal line extends along the second direction, and along the first direction, at least one of the first data line and the initialization signal line is located in the first gap.

4. The display panel according to claim 3, characterized in that, Both the first power signal line and the initialization signal line extend along the second direction; Along the first direction, at least one of the first data line, the first power signal line, and the initialization signal line is located in the first gap.

5. The display panel according to claim 1, characterized in that, The display panel includes a first area and a second area; The display panel must satisfy at least one of the following: The first power signal line extends along the second direction. Along the first direction, in the first region, adjacent first data lines are connected by M1 first power signal lines, and in the second region, adjacent first data lines are connected by M2 first power signal lines, where M1 > M2 ≥ 0; or, The initialization signal line extends along the second direction. Along the first direction, in the first region, there are N1 initialization signal lines between adjacent first data lines, and in the second region, there are N2 initialization signal lines between adjacent first data lines, wherein N1 > N2 ≥ 0.

6. The display panel according to claim 1, characterized in that, The display panel includes a first area and a second area; Both the first power signal line and the initialization signal line extend along the second direction; Along the first direction, in the first region, adjacent first data lines include MS1 first power signal lines and NS1 initialization signal lines; in the second region, adjacent first data lines include MS2 first power signal lines and NS2 initialization signal lines, wherein MS1≥0, NS1≥0, MS2≥0, and NS2≥0. The display panel must satisfy at least one of the following: MS1 ≠ MS2; or, NS1 ≠ NS2.

7. The display panel according to claim 6, characterized in that, MS1>MS2≥0, and 0≤NS1≤NS2.

8. The display panel according to claim 6, characterized in that, MS1>MS2≥0, and NS1≥MS2≥0.

9. The display panel according to claim 1, characterized in that, Along the first direction, the width of the first data line is W1, the width of the first power signal line is W2, and the width of the initialization signal line is W3; wherein, The display panel must satisfy at least one of the following: W1 < W2; or, W3 < W2.

10. The display panel according to claim 9, characterized in that, W2-W3>W3-W1≥0.

11. The display panel according to claim 9, characterized in that, 0 ≤ W2 - W3 < W3 - W1.

12. The display panel according to claim 1, characterized in that, The sub-pixel also includes a third sub-pixel, which includes a third pixel circuit and a third light-emitting element. The first light-emitting element, the second light-emitting element, and the third light-emitting element emit different colors of light. The data line includes a second data line, which is connected to the third pixel circuit.

13. The display panel according to claim 12, characterized in that, The sub-pixel also includes a fourth sub-pixel, which includes a fourth pixel circuit and a fourth light-emitting element. The first light-emitting element, the second light-emitting element, the third light-emitting element, and the fourth light-emitting element emit different colors of light. The second data line is connected to the fourth pixel circuit.

14. The display panel according to claim 12 or 13, characterized in that, Along the first direction, at least one second data line is included between adjacent first data lines; or, Along the first direction, at least one of the first data lines is included between adjacent second data lines.

15. The display panel according to claim 12 or 13, characterized in that, The first power signal line extends along the second direction; Along the first direction, at least one first power signal line is included between adjacent first data lines and second data lines.

16. The display panel according to claim 12 or 13, characterized in that, The initialization signal line extends along the second direction; Along the first direction, at least one of the initialization signal lines is included between adjacent first data lines and second data lines.

17. The display panel according to claim 12 or 13, characterized in that, The first power signal line and the initialization signal line extend along the second direction; Along the first direction, at least one first power signal line is included between adjacent sets of first data lines and second data lines, and at least one initialization signal line is included between adjacent sets of first data lines and second data lines.

18. The display panel according to claim 12 or 13, characterized in that, The first power signal line and the initialization signal line extend along the second direction; Along the first direction, the first data line, the second data line, the first power signal line, and the initialization signal line are arranged in at least one of the following orders: The first data line, the first power signal line, the second data line, and the initialization signal line; or, The first data line, the initialization signal line, the second data line, and the first power signal line.

19. The display panel according to claim 12 or 13, characterized in that, The first power signal line and the initialization signal line extend along the second direction; Along the first direction, at least one first power signal line and at least one initialization signal line are included between adjacent first data lines and second data lines.

20. The display panel according to claim 19, characterized in that, Along the first direction, the first data line, the second data line, the first power signal line, and the initialization signal line are arranged in at least one of the following orders: The first data line, the first power signal line, the initialization signal line, and the second data line; or, The first data line, the initialization signal line, the first power signal line, and the second data line.

21. The display panel according to claim 12 or 13, characterized in that, The first power signal line and the initialization signal line extend along the second direction; Along the first direction, at least one first data line and one second data line are included between adjacent first power signal lines and initialization signal lines.

22. The display panel according to claim 21, characterized in that, Along the first direction, the first data line, the second data line, the first power signal line, and the initialization signal line are arranged in at least one of the following orders: The first power signal line, the first data line, the second data line, and the initialization signal line; or, The first power signal line, the second data line, the first data line, and the initialization signal line; or, The initialization signal line, the first data line, the second data line, and the first power signal line; or, The initialization signal line, the second data line, the first data line, and the first power signal line.

23. The display panel according to claim 12, characterized in that, The display panel includes pixels, and the pixels include a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged along the first direction; Along the first direction, a first gap is included between the first pixel circuit and the second pixel circuit, a second gap is included between the second pixel circuit and the third pixel circuit, and a third gap is included between the third pixel circuit and an adjacent pixel circuit in another pixel; wherein, At least two of the first data line, the second data line, the first power signal line, and the initialization signal line are located in one of the first gap, the second gap, and the third gap.

24. The display panel according to claim 13, characterized in that, The display panel includes pixels, and the pixels include a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel arranged along the first direction; Along the first direction, a first gap is included between the first pixel circuit and the second pixel circuit, a second gap is included between the second pixel circuit and the third pixel circuit, a third gap is included between the third pixel circuit and the fourth pixel circuit, and a fourth gap is included between the fourth pixel circuit and the pixel circuit adjacent to it in another pixel; wherein, The first data line, the second data line, the first power signal line, and the initialization signal line are each located in one of the first gap, the second gap, the third gap, and the fourth gap.

25. The display panel according to claim 13, characterized in that, The display panel includes pixels, and the pixels include a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel arranged along the first direction; Along the first direction, a first gap is included between the first pixel circuit and the second pixel circuit, a second gap is included between the second pixel circuit and the third pixel circuit, a third gap is included between the third pixel circuit and the fourth pixel circuit, and a fourth gap is included between the fourth pixel circuit and the pixel circuit adjacent to it in another pixel; wherein, At least two of the first data line, the second data line, the first power signal line, and the initialization signal line are located in one of the first gap, the second gap, the third gap, and the fourth gap.

26. The display panel according to claim 12, characterized in that, The first light-emitting element emits red light, the second light-emitting element emits green light, and the third light-emitting element emits blue light. or, The first light-emitting element emits red light, the second light-emitting element emits blue light, and the third light-emitting element emits green light. or, The first light-emitting element emits green light, the second light-emitting element emits blue light, and the third light-emitting element emits red light.

27. The display panel according to claim 13, characterized in that, The first light-emitting element emits red light, the second light-emitting element emits green light, the third light-emitting element emits blue light, and the fourth light-emitting element emits white light; or, The first light-emitting element emits red light, the second light-emitting element emits blue light, the third light-emitting element emits green light, and the fourth light-emitting element emits white light; or, The first light-emitting element emits red light, the second light-emitting element emits white light, the third light-emitting element emits green light, and the fourth light-emitting element emits blue light; or, The first light-emitting element emits blue light, the second light-emitting element emits white light, the third light-emitting element emits red light, and the fourth light-emitting element emits green light; or, The first light-emitting element emits green light, the second light-emitting element emits white light, the third light-emitting element emits red light, and the fourth light-emitting element emits blue light; or, The first light-emitting element emits green light, the second light-emitting element emits blue light, the third light-emitting element emits red light, and the fourth light-emitting element emits white light.

28. The display panel according to claim 12 or 13, characterized in that, The pixel circuits of R sub-pixels arranged along the first direction are connected to the same first power signal line, and the pixel circuits of S sub-pixels arranged along the first direction are connected to the same initialization signal line, where R≥1 and S≥1.

29. The display panel according to claim 28, characterized in that, R=S.

30. The display panel according to claim 28, characterized in that, R < S.

31. The display panel according to claim 28, characterized in that, R > S.

32. The display panel according to claim 28, characterized in that, The pixel circuits of the R sub-pixels are connected to the first power signal line via a first connection line, and the pixel circuits of the S sub-pixels are connected to the initialization signal line via a second connection line.

33. The display panel according to claim 32, characterized in that, In a direction perpendicular to the substrate of the display panel, at least one of the first connecting lines and at least one of the second connecting lines do not overlap.

34. The display panel according to claim 32, characterized in that, In a direction perpendicular to the substrate of the display panel, at least one of the first connecting lines and at least one of the second connecting lines at least partially overlap.

35. The display panel according to claim 32, characterized in that, The width of at least one of the first connecting lines is greater than the width of at least one of the second connecting lines.

36. The display panel according to claim 32, characterized in that, Along the first direction, the first connecting line connected to the first power signal line is located on the same side of the first power signal line, and the second connecting lines connected to the initialization signal line are distributed on both sides of the initialization signal line; or, Along the first direction, the first connecting lines connected to the first power signal line are distributed on both sides of the first power signal line, and the second connecting lines connected to the initialization signal line are located on the same side of the initialization signal line.

37. The display panel according to claim 36, characterized in that, Along the first direction, the number of second connecting lines distributed on both sides of the initialization signal line is equal; or, Along the first direction, the number of the first connecting lines distributed on both sides of the first power signal line is equal.

38. The display panel according to claim 32, characterized in that, Along the first direction, the first connecting line connected to the first power signal line is located on the same side of the first power signal line, and the second connecting line connected to the initialization signal line is located on the same side of the first power signal line; or, Along the first direction, the first connecting lines connected to the first power signal line are distributed on both sides of the first power signal line, and the second connecting lines connected to the initialization signal line are distributed on both sides of the initialization signal line.

39. The display panel according to claim 38, characterized in that, Along the first direction, the number of the first connecting lines distributed on both sides of the first power signal line is equal; or, Along the first direction, the number of second connecting lines distributed on both sides of the initialization signal line is equal.

40. The display panel according to claim 1, characterized in that, The first sub-pixel and the second sub-pixel are arranged along the first direction; The first sub-scan line is connected to the first node of the first pixel circuit, and the second sub-scan line is connected to the first node of the second pixel circuit; Along the second direction, the distance between the first sub-scan line and the first node of the first pixel circuit is D1, and the distance between the second sub-scan line and the first node of the second pixel circuit is D2, where D1≥0, D2≥0, and D1≠D2.

41. The display panel according to claim 1, characterized in that, The first sub-pixel and the second sub-pixel are arranged along the first direction; The first sub-scan line is connected to the first node of the first pixel circuit, and the second sub-scan line is connected to the first node of the second pixel circuit; Along the second direction, the distance between the first sub-scan line and the first node of the first pixel circuit is D1, and the distance between the second sub-scan line and the first node of the second pixel circuit is D2, where D1≥0, D2≥0, and D1=D2.

42. The display panel according to claim 40 or 41, characterized in that, The first scan line is connected to the first transistor of the pixel circuit, and the first node is the gate of the first transistor.

43. The display panel according to claim 40 or 41, characterized in that, The first node in the first pixel circuit is in the same position as the first node in the second pixel circuit.

44. The display panel according to claim 40 or 41, characterized in that, The first pixel circuit includes P1 transistors and Q1 capacitors, and the second pixel circuit includes P2 transistors and Q2 capacitors, where P1≥1, Q1≥1, P2≥1, and Q2≥1. The arrangement of P1 transistors and Q1 capacitors in the first pixel circuit is the same as the arrangement of P2 transistors and Q2 capacitors in the second pixel circuit.

45. The display panel according to claim 40 or 41, characterized in that, The position of the first node in the first pixel circuit is different from that of the first node in the second pixel circuit.

46. ​​The display panel according to claim 40 or 41, characterized in that, The first pixel circuit includes P1 transistors and Q1 capacitors, and the second pixel circuit includes P2 transistors and Q2 capacitors, where P1≥1, Q1≥1, P2≥1, and Q2≥1. The first scan line is connected to the first transistor of the pixel circuit, and the first node is the gate of the first transistor; In the first pixel circuit, the arrangement of at least the first transistor among the P1 transistors and Q1 capacitors is different from that of at least the first transistor among the P2 transistors and Q2 capacitors in the second pixel circuit.

47. The display panel according to claim 40 or 41, characterized in that, Along the second direction, the first sub-scan line is located on the first side of the first node of the first pixel circuit, and the second sub-scan line is located on the second side of the first node of the second pixel circuit. The first side and the second side are opposite sides along the second direction.

48. The display panel according to claim 40 or 41, characterized in that, Along the second direction, the first sub-scan line is located on the first side of the first node of the first pixel circuit, and the second sub-scan line is located on the first side of the first node of the second pixel circuit.

49. The display panel according to claim 40 or 41, characterized in that, The first sub-scan line is connected to the first node of the first pixel circuit through a first transition line, and the second sub-scan line is connected to the first node of the second pixel circuit through a second transition line. Along the second direction, the length of the first transition line is L1, and the length of the second transition line is L2; ​​wherein, L1≥0, L2≥0, and L1 = L2, or L1 ≠ L2.

50. The display panel according to claim 40, characterized in that, The width of the first sub-scan line is W1, and the width of the second sub-scan line is W2; wherein... (D1-D2)×(W1-W2)>0.

51. The display panel according to claim 1, characterized in that, The scan line also includes a second scan line, which is connected to the first pixel circuit, and the second scan line is first connected to the second pixel circuit; or, The scan line also includes a second scan line, which includes a third sub-scan line and a fourth sub-scan line. The third sub-scan line is connected to the first pixel circuit, and the fourth sub-scan line is connected to the second pixel circuit.

52. The display panel according to claim 51, characterized in that, The pixel circuit includes a first transistor and a second transistor; The first scan line is connected to the first transistor; The second scan line is connected to the second transistor.

53. The display panel according to claim 51, characterized in that, The first sub-scan line, the second sub-scan line, the third sub-scan line, and the fourth sub-scan line are arranged along the second direction, and the arrangement order satisfies at least one of the following: The first sub-scan line, the second sub-scan line, the third sub-scan line, and the fourth sub-scan line; or, The first sub-scan line, the third sub-scan line, the second sub-scan line, and the fourth sub-scan line; or, The first sub-scan line, the third sub-scan line, the fourth sub-scan line, and the second sub-scan line.

54. The display panel according to claim 1, characterized in that, The sub-pixel also includes a third sub-pixel, which includes a third pixel circuit and a third light-emitting element. The first light-emitting element, the second light-emitting element, and the third light-emitting element emit different colors of light. The first data line is connected to the third pixel circuit; The first scan line includes a fifth sub-scan line, which is connected to the third pixel circuit.

55. The display panel according to claim 54, characterized in that, The sub-pixel also includes a fourth sub-pixel, which includes a fourth pixel circuit and a fourth light-emitting element. The first light-emitting element, the second light-emitting element, the third light-emitting element, and the fourth light-emitting element emit different colors of light. The first data line is connected to the fourth pixel circuit; The first scan line includes a sixth sub-scan line, which is connected to the fourth pixel circuit.

56. The display panel according to claim 1, characterized in that, The data line provides data signals to the pixel circuit; The scan lines provide scan signals to the pixel circuit; wherein... The first data line provides a first data signal to the first pixel circuit, and the first data line provides a second data signal to the second pixel circuit; The first scan line provides a first scan signal to the pixel circuit. The first scan signal includes a first sub-scan signal and a second sub-scan signal. The first sub-scan line provides the first sub-scan signal to the first pixel circuit, and the second sub-scan line provides the second sub-scan signal to the second pixel circuit.

57. The display panel according to claim 56, characterized in that, Within one screen refresh cycle of the display panel, there is no overlap between the effective pulses of the first sub-scan signal and the effective pulses of the second sub-scan signal.

58. The display panel according to claim 56, characterized in that, After the effective pulse of the first sub-scan signal ends, the data signal on the first data line changes from the first data signal to the second data signal, and then the effective pulse of the second sub-scan signal is turned on.

59. The display panel according to claim 56, characterized in that, During one screen refresh cycle of the display panel, the effective pulses of the first sub-scan signal and the effective pulses of the second sub-scan signal at least partially overlap.

60. The display panel according to claim 59, characterized in that, The effective pulse of the second sub-scan signal is activated before the effective pulse of the first sub-scan signal ends; After the effective pulse of the first sub-scan signal ends, the effective pulse of the second sub-scan signal ends; After the effective pulse of the first sub-scan signal ends, the first data signal changes to the second data signal.

61. The display panel according to claim 56, characterized in that, The display panel includes a T-row of sub-pixel rows arranged along the second direction and multiple first sub-scan lines and multiple second sub-scan lines; Within one screen refresh cycle of the display panel, the effective pulses of the second sub-scan signal on the second sub-scan line connected to the pixel circuit of the i-th sub-pixel row and the effective pulses of the first sub-scan signal on the first sub-scan line connected to the pixel circuit of the j-th sub-pixel row at least partially overlap, 0≤i≤T, 0≤j≤T, and i≠j.

62. The display panel according to claim 56, characterized in that, The display panel includes a T-row of sub-pixel rows arranged along the second direction and multiple first sub-scan lines and multiple second sub-scan lines; Within one screen refresh cycle of the display panel, there is no overlap between the effective pulse of the second sub-scan signal on the second sub-scan line connected to the pixel circuit of the i-th sub-pixel row and the effective pulse of the first sub-scan signal on the first sub-scan line connected to the pixel circuit of the j-th sub-pixel row, 0≤i≤T, 0≤j≤T, and i≠j.

63. The display panel according to claim 56, characterized in that, The display panel includes a T-row of sub-pixel rows arranged along the second direction and multiple first sub-scan lines and multiple second sub-scan lines; Within one screen refresh cycle of the display panel, the start time of the effective pulse of the first sub-scan signal on the first sub-scan line connected to the pixel circuit of the i-th sub-pixel row is earlier than the start time of the effective pulse of the second sub-scan signal on the second sub-scan line connected to the pixel circuit of the i-th sub-pixel row, and the start time of the effective pulse of the first sub-scan signal on the first sub-scan line connected to the pixel circuit of the j-th sub-pixel row is later than the start time of the effective pulse of the second sub-scan signal on the second sub-scan line connected to the pixel circuit of the j-th sub-pixel row, 0≤i≤T, 0≤j≤T, and i≠j.

64. The display panel according to claim 56, characterized in that, The width of the effective pulse of the first sub-scan signal is equal to the width of the effective pulse of the second sub-scan signal.

65. The display panel according to claim 56, characterized in that, The width of the effective pulse of the first sub-scan signal is greater than or less than the width of the effective pulse of the second sub-scan signal.

66. The display panel according to claim 64, characterized in that, The start time of the effective pulse of the first sub-scan signal is earlier than the start time of the effective pulse of the second sub-scan signal; or, The start time of the effective pulse of the first sub-scan signal is later than the start time of the effective pulse of the second sub-scan signal.

67. The display panel according to claim 1, characterized in that, The operation of the display panel includes an initialization phase and a sampling phase; During the initialization phase, an initialization signal is received on the initialization signal line; During the sampling phase, the signal on the initialization signal line is in a floating state.

68. The display panel according to claim 1, characterized in that, The light-emitting element of the display panel includes a first electrode and a second electrode; The first electrode is connected to the pixel circuit, and the second electrode is connected to the second power signal line to receive the second power signal; wherein... The initialization signal line receives the second power signal.

69. The display panel according to claim 67, characterized in that, The display panel also includes a control unit, which is electrically connected to the data line; The control unit includes a storage module and a control module; The storage module stores the mapping relationship between the display parameters of the display panel and the data voltage; The control module is used to retrieve the corresponding data voltage from the storage module according to the display parameters, and provide the data voltage to the data line.

70. The display panel according to claim 1, characterized in that, The pixel circuit includes at least a first transistor, a second transistor, a third transistor, and a first capacitor; The first transistor is connected between the data line and the gate of the third transistor; The second transistor is connected between the initialization signal line and the light-emitting element; The third transistor is connected between the first power signal line and the light-emitting element; The first capacitor is connected between the gate of the third transistor and the light-emitting element, or the first capacitor is connected between the first power signal line and the gate of the third transistor; wherein, The gate of the first transistor is connected to the first scan line; or, The gate of the second transistor is connected to the first scan line.

71. The display panel according to claim 1, characterized in that, The pixel circuit includes at least a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and a first capacitor; The first transistor is connected between the data line and the first electrode of the seventh transistor; The second transistor is connected between the first electrode and the gate of the seventh transistor; The third transistor is connected between the first electrode of the seventh transistor and the light-emitting element; The fourth transistor is connected between the initialization signal line and the light-emitting element; The fifth transistor is connected between the initialization signal line and the gate of the seventh transistor; The sixth transistor is connected between the first power signal line and the second terminal of the seventh transistor; The first capacitor is connected between the gate of the seventh transistor and the light-emitting element; or, the first capacitor is connected between the first power signal line and the gate of the seventh transistor. The gate of the first transistor is connected to the first scan line.

72. A display device, characterized in that, Includes the display panel as described in any one of claims 1-71.

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