Display device, method of driving display device, and electronic device

Abstract

The invention relates to a display device, a method of driving the display device, and an electronic device. The display device includes a display panel including pixels and a display panel driver that outputs a gate signal, a data voltage, and an emission signal to the pixels. The display apparatus determines whether a driving period in a driving sequence is a write period or a hold period, determines a number of hold periods of a current hold period when a plurality of hold periods are repeated in the driving sequence, and determining a transmission off time based on the number of holding cycles of the current holding cycle by adjusting at least one of an end point of an off duration of the transmission signal and a start point of the off duration of the transmission signal according to a set value. The display quality of the display device is improved because the brightness difference between the write period and the latter part of the hold period is reduced.

Description

Technical Field

[0001] Embodiments of the present invention relate to display devices, methods for driving display devices, and electronic devices including display devices. More specifically, embodiments of the present invention relate to display devices, methods for driving display devices, and electronic devices that improve the display quality of display devices by reducing brightness variations at low driving frequencies. Background Technology

[0002] A display device may include a display panel and a display panel driver. The display panel includes multiple gate lines, multiple data lines, multiple emitter lines, and multiple pixels. The display panel driver includes a gate driver, a data driver, an emitter driver, and a drive controller. The gate driver outputs gate signals to the gate lines. The data driver outputs data voltages to the data lines. The emitter driver outputs emitter signals to the emitter lines. The drive controller controls the gate driver, data driver, and emitter driver.

[0003] Display devices can execute driving sequences for displaying images in a display panel at various driving frequencies. A driving sequence may include write cycles and hold cycles. During a write cycle, the display panel receives data voltages from data lines and emits light based on the received data voltages. During a hold cycle, the display panel emits light based on data voltages stored in multiple pixels.

[0004] When a display device drives a display panel at a low drive frequency, the number of hold cycles in a frame can be increased, and the brightness of the display panel can be reduced as the hold cycles repeat. By compensating for brightness variations in the display panel at a low drive frequency, the display quality of the display device is improved. Summary of the Invention

[0005] An embodiment of the present invention provides a display device that adjusts the emission time of a pixel based on determining whether a drive cycle in a drive sequence is a write cycle or a hold cycle and determining the number of hold cycles in the current hold cycle, and selectively adjusting one of the end point and the start point of the off-duration of the transmitted signal to adjust the emission time of the pixel. According to an embodiment, the display device includes a display panel comprising pixels and a display panel driver comprising a gate driver, a data driver, and an emitter driver, wherein the gate driver, data driver, and emitter driver are configured to generate a gate signal, a data voltage, and an emitter signal, respectively, and to provide the gate signal, data voltage, and emitter signal to the display panel, wherein the display panel driver is configured to: determine whether a drive cycle in a drive sequence is a write cycle or a hold cycle, wherein during a write cycle, the display panel is configured to receive a data voltage, write the data voltage to the pixel, and drive the light-emitting element of the pixel to emit light based on the data voltage, and during a hold cycle, the display panel is configured to drive the light-emitting element of the pixel to emit light based on the data voltage stored in the pixel, and when multiple hold cycles are repeated in the drive sequence, determine the hold cycle number of the current hold cycle, and determine the emitter off time based on the hold cycle number of the current hold cycle by adjusting at least one of the end point of the off duration of the emitter signal and the start point of the off duration of the emitter signal according to a set value.

[0006] When the number of hold cycles in the current hold cycle is equal to or greater than the predetermined hold cycle reference number, the display panel driver is configured to advance the end of the off-duty duration of the transmit signal according to a set value and / or reduce the transmit off-duty time by delaying the start of the off-duty duration of the transmit signal according to a set value.

[0007] When the number of hold cycles in the current hold cycle is equal to or greater than a predetermined hold cycle reference number, the display panel driver is configured to increase the bias voltage applied to the drive switching element of the pixel to a value greater than the reference bias voltage.

[0008] When the setting value is the first value, the display panel driver is configured to advance the end of the off-time of the transmitted signal to reduce the off-time, and when the setting value is the second value, the display panel driver is configured to delay the start of the off-time of the transmitted signal to reduce the off-time.

[0009] When the setting is the third value, the display panel driver is configured to advance the end of the transmit signal's off-duration duration and delay the start of the transmit signal's off-duration duration to reduce the transmit off-duration time. The display panel driver also includes: a signal generator configured to generate a vertical start signal and a data enable signal; and a cycle counter configured to determine whether the current drive cycle is a write cycle or a hold cycle based on the vertical start signal and the data enable signal, and the cycle counter is further configured to determine the hold cycle number of the current hold cycle based on the vertical start signal and the data enable signal when multiple hold cycles repeat in the drive sequence.

[0010] When the cycle counter receives the pulse of the data enable signal repeatedly after receiving the vertical start signal, the cycle counter determines the current drive cycle as the write cycle. When the cycle counter does not receive the pulse of the data enable signal after receiving the vertical start signal, the cycle counter determines the current drive cycle as the hold cycle.

[0011] The display panel driver also includes a lookup table configured to store transmit-off times corresponding to the number of hold cycles.

[0012] The display panel driver also includes a register that stores the emit shutdown setting, and the display panel driver is configured to determine the emit shutdown time corresponding to the number of hold cycles based on the emit shutdown setting.

[0013] The display panel driver also includes an emission off-time output circuit configured to receive the hold cycle number of the current hold cycle from a cycle counter and output the emission off-time corresponding to the hold cycle number from a lookup table. The display panel driver also includes: a position setter configured to output a setting value, which the emission driver uses to determine whether to change the end point or the start point of the emission signal's off-time duration; and an emission driver configured to generate an emission signal based on the emission off-time received from the emission off-time output circuit and the setting value received from the position setter, and to provide the emission signal to the pixels. The pixel includes: a driving switch element, including a control electrode of the driving switch element connected to a first node, a first electrode of the driving switch element connected to a second node, and a second electrode of the driving switch element connected to a third node; a bias switch element, including a control electrode of the bias switch element configured to receive a bias gate signal, a first electrode of the bias switch element configured to receive a bias voltage, and a second electrode of the bias switch element connected to a second node; a first transmit switch element, including a control electrode of the first transmit switch element configured to receive a transmit signal, a first electrode of the first transmit switch element configured to receive a first power voltage, and a second electrode of the first transmit switch element connected to a second node; a second transmit switch element, including a control electrode of the second transmit switch element configured to receive a transmit signal, a first electrode of the second transmit switch element connected to a third node, and a second electrode of the second transmit switch element connected to a first electrode of a light-emitting element; and a data write switch element, including a control electrode of the data write switch element configured to receive a bias gate .... The system comprises: a control electrode configured to receive a data write gate signal; a first electrode of a data write switch element configured to receive a data voltage; and a second electrode of the data write switch element connected to a second node; a compensation switch element, comprising a control electrode of the compensation switch element configured to receive a compensation gate signal; a first electrode of the compensation switch element connected to a first node; and a second electrode of the compensation switch element connected to a third node; a data initialization switch element, comprising a control electrode of the data initialization switch element configured to receive a data initialization gate signal; a first electrode of the data initialization switch element configured to receive an initialization voltage; and a second electrode of the data initialization switch element connected to a first node; and a light-emitting element initialization switch element, comprising a control electrode of the light-emitting element initialization switch element configured to receive a bias gate signal; a first electrode of the light-emitting element initialization switch element configured to receive a light-emitting element initialization voltage; and a second electrode of the light-emitting element initialization switch element connected to the first electrode of the light-emitting element.

[0014] The compensation switching element comprises two transistors connected in series with each other, and the data initialization switching element comprises two transistors connected in series with each other. According to an embodiment of a method for driving a display device, the method includes: determining whether a driving cycle in a driving sequence is a write cycle or a hold cycle, wherein during the write cycle, the display device is configured to generate a data voltage and write the data voltage to a pixel, and drive a light-emitting element of the pixel to emit light based on the data voltage, and during the hold cycle, the display device is configured to drive a light-emitting element of the pixel to emit light based on the data voltage stored in the pixel; determining the hold cycle number of the current hold cycle when multiple hold cycles are repeated in the driving sequence; determining a transmission off-time based on the hold cycle number of the current hold cycle by adjusting at least one of the end point of the off-time of the transmission signal and the start point of the off-time of the transmission signal according to a set value; and generating a transmission signal based on the transmission off-time and the set value, and providing the transmission signal to the pixel.

[0015] When the number of hold periods in the current hold period is equal to or greater than the predetermined hold period reference number, the transmission shutdown time is reduced by advancing the end of the transmission signal shutdown duration according to a set value and / or by delaying the start of the transmission signal shutdown duration according to a set value.

[0016] When the number of hold cycles in the current hold cycle is equal to or greater than the predetermined hold cycle reference number, the bias voltage applied to the drive switching element of the pixel is increased to be greater than the reference bias voltage.

[0017] When the setting value is the first value, the end point of the transmission signal shutdown duration is brought forward to reduce the transmission shutdown time, and when the setting value is the second value, the start point of the transmission signal shutdown duration is delayed to reduce the transmission shutdown time.

[0018] Based on the vertical start signal and the data enable signal, it is determined whether the current drive cycle is a write cycle or a hold cycle. When multiple hold cycles are repeated in the drive sequence, the hold cycle number of the current hold cycle is determined based on the vertical start signal and the data enable signal. According to an embodiment of an electronic device, the electronic device includes: a processor configured to input image data and input control signals; a display panel including pixels; and a display panel driver including a gate driver, a data driver, and an emitter driver, wherein the gate driver, data driver, and emitter driver are configured to generate a gate signal, a data voltage, and an emitter signal, respectively, and to provide the gate signal, data voltage, and emitter signal to the pixels, wherein the display panel driver is configured to determine whether a drive cycle in a drive sequence is a write cycle or a hold cycle, wherein during a write cycle, the display panel is configured to receive a data voltage, write the data voltage to the pixel, and drive the light-emitting element of the pixel to emit light based on the data voltage, and during a hold cycle, the display panel is configured not to receive a data voltage and drive the light-emitting element of the pixel to emit light based on the data voltage stored in the pixel; when multiple hold cycles are repeated in the drive sequence, determining the hold cycle number of the current hold cycle; and determining an emitter off time based on the hold cycle number of the current hold cycle by adjusting at least one of the end point of the off duration of the emitter signal and the start point of the off duration of the emitter signal according to a set value.

[0019] The display panel driver is also configured to determine whether a drive cycle is a write cycle or a hold cycle based on input control signals from the processor. Attached Figure Description

[0020] The features and advantages of the present invention will become more apparent from the detailed description of the embodiments with reference to the accompanying drawings, in which:

[0021] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the concept of the present invention;

[0022] Figure 2 It is shown Figure 1 A graph showing the driving frequency of the display panel;

[0023] Figure 3 It is shown Figure 1 The circuit diagram of the pixels of the display panel;

[0024] Figure 4 It is shown Figure 1 A diagram showing the drive sequence of the display panel at various drive frequencies;

[0025] Figure 5 It is shown Figure 1 A diagram showing the drive sequence of the display panel at various drive frequencies;

[0026] Figure 6 This indicates the force applied during the write cycle. Figure 1 Timing diagram of the input signals of the display panel;

[0027] Figure 7 This shows the application during the holding period. Figure 1 Timing diagram of the input signals of the display panel;

[0028] Figure 8A This illustrates when the display device drives the display panel without illumination timing control. Figure 1 Timing diagram of the brightness of the display panel;

[0029] Figure 8B This illustrates when a display device drives a display panel using emissivity timing control. Figure 1 Timing diagram of the brightness of the display panel;

[0030] Figure 9 It is shown Figure 1 A block diagram of the drive controller;

[0031] Figure 10 It is shown Figure 9 A diagram showing the settings of the position setter;

[0032] Figure 11A and Figure 11B This indicates the adjustment Figure 10 Timing diagram of the method for determining the end of the off-duration period of the transmitted signal;

[0033] Figure 12A and Figure 12B This indicates the adjustment Figure 10 Timing diagram of the method for determining the start of the off-duration period of the transmitted signal;

[0034] Figure 13 This diagram illustrates a method for adjusting the transmission shutdown time based on the setting value of the display device's position setter;

[0035] Figure 14A and Figure 14B This indicates the adjustment Figure 13 A timing diagram of the method for determining the start and end points of the shutdown duration of the transmitted signal;

[0036] Figure 15 It is a circuit diagram showing the pixels of the display panel;

[0037] Figure 16 This is a block diagram illustrating an electronic device according to an embodiment of the concept of the present invention;

[0038] Figure 17 It is shown as Figure 16A diagram of an example of an electronic device, such as a smartphone;

[0039] Figure 18 It is shown as Figure 16 A diagram of a monitor, an example of an electronic device; and

[0040] Figure 19 This is a block diagram illustrating an electronic device according to an embodiment of the concept of the present invention. Detailed Implementation

[0041] The concept of the invention will be explained in detail below with reference to the accompanying drawings.

[0042] The display device includes a display panel and a display panel driver. The display panel includes pixels, and the display panel driver outputs gate signals, data voltages, and transmit signals to the pixels. The display device determines whether a drive cycle in a drive sequence is a write cycle or a hold cycle. During a write cycle, the light-emitting elements of the pixels emit light based on data voltages received from the data driver, and during a hold cycle, the light-emitting elements of the pixels emit light based on data voltages stored in the pixels. When a hold cycle repeats in the drive sequence, the hold cycle number of the current hold cycle is determined, and the transmit off time is determined based on the hold cycle number of the current hold cycle by adjusting at least one of the end point of the transmit signal's off duration and the start point of the transmit signal's off duration according to a set value.

[0043] Because the light emission time in the later portion of the hold cycle is increased by adjusting at least one of the end point of the off-time of the transmit signal and the start point of the off-time of the transmit signal, the brightness difference between the write cycle and the later portion of the hold cycle is reduced, and the display quality of the display device is improved.

[0044] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the concept of the present invention.

[0045] Reference Figure 1 The display device includes a display panel 100 and a display panel driver. The display panel 100 includes a plurality of pixels. The display panel driver includes a drive controller 200, a gate driver 300, a gamma reference voltage generator 400, a data driver 500, and a transmit driver 600.

[0046] The display panel 100 has a display area and an adjacent peripheral area. An image is displayed in the display area using multiple pixels, and a display panel driver is provided in the peripheral area.

[0047] The display panel 100 includes a first gate line GWL, a second gate line GIL, a third gate line GCL, and a fourth gate line EBL, multiple data lines DL, multiple emitter lines EML, and multiple pixels electrically connected to the first gate line GWL, the second gate line GIL, the third gate line GCL, the fourth gate line EBL, the data lines DL, and the emitter lines EML. The first gate line GWL, the second gate line GIL, the third gate line GCL, and the fourth gate line EBL can extend in a first direction D1, the data lines DL can extend in a second direction D2 perpendicular to the first direction D1, and the emitter lines EML can extend in the first direction D1.

[0048] The drive controller 200 receives input image data IMG and input control signals CONT from an external device such as an application processor. For example, the input image data IMG may include red image data, green image data, and blue image data. The input image data IMG may also include white image data, magenta image data, yellow image data, and cyan image data. The input control signals CONT may include a master clock signal and a data enable signal. The input control signals CONT may also include a vertical synchronization signal and a horizontal synchronization signal.

[0049] The drive controller 200 can generate a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, and a fourth control signal CONT4 based on the input control signal CONT, and the drive controller 200 can also generate a data signal DATA based on the input image data IMG.

[0050] The drive controller 200 generates a first control signal CONT1 based on the input control signal CONT for controlling the operation of the gate driver 300, and provides the first control signal CONT1 to the gate driver 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0051] The drive controller 200 generates a second control signal CONT2 based on the input control signal CONT for controlling the operation of the data driver 500, and provides the second control signal CONT2 to the data driver 500. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0052] The drive controller 200 generates a data signal DATA based on the input image data IMG and provides the data signal DATA to the data driver 500.

[0053] The drive controller 200 generates a third control signal CONT3 based on the input control signal CONT for controlling the operation of the gamma reference voltage generator 400, and provides the third control signal CONT3 to the gamma reference voltage generator 400.

[0054] The drive controller 200 generates a fourth control signal CONT4 based on the input control signal CONT for controlling the operation of the transmitter driver 600, and provides the fourth control signal CONT4 to the transmitter driver 600.

[0055] In response to the first control signal CONT1 received from the drive controller 200, the gate driver 300 generates first to fourth gate signals for driving the first gate line GWL, the second gate line GIL, the third gate line GCL, and the fourth gate line EBL. The gate driver 300 can provide the first to fourth gate signals to the first gate line GWL, the second gate line GIL, the third gate line GCL, and the fourth gate line EBL, respectively. The first to fourth gate signals can correspond to the data initialization gate signal, the compensation gate signal, the data write gate signal, and the bias gate signal, respectively.

[0056] According to an embodiment, the gate driver 300 can be embedded in the peripheral region of the display panel 100. Alternatively, the gate driver 300 can be mounted as a separate chip in the peripheral region of the display panel 100.

[0057] The gamma reference voltage generator 400 generates a gamma reference voltage VGREF in response to a third control signal CONT3 received from the drive controller 200. The gamma reference voltage generator 400 provides the gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF has a reference value used to determine the level of the data signal DATA.

[0058] The gamma reference voltage generator 400 can be located in the drive controller 200 or embedded in the data driver 500.

[0059] The data driver 500 receives a second control signal CONT2 and a data signal DATA from the drive controller 200, and receives a gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 uses the gamma reference voltage VGREF to convert the data signal DATA into a data voltage of analog type. The data driver 500 provides the data voltage to the data line DL.

[0060] The data driver 500 can be embedded in the peripheral area of ​​the display panel 100. Alternatively, the data driver 500 can be installed as a separate chip in the peripheral area of ​​the display panel 100.

[0061] The transmit driver 600 generates a transmit signal in response to a fourth control signal CONT4 received from the drive controller 200 to drive the transmit line EML. The transmit driver 600 can provide a transmit signal to the transmit line EML.

[0062] According to an embodiment, the transmitter driver 600 can be embedded in the peripheral area of ​​the display panel 100. Alternatively, the transmitter driver 600 can be mounted as a separate chip in the peripheral area of ​​the display panel 100.

[0063] The gate driver 300 can be disposed on a first side of the display panel 100, and the emitter driver 600 can be disposed on a second side of the display panel 100 opposite to the first side. However, the inventive concept is not limited thereto. For example, both the gate driver 300 and the emitter driver 600 can be disposed on the first side of the display panel 100. Alternatively, the gate driver 300 and the emitter driver 600 can be separated and disposed on opposite sides of the display panel 100. Furthermore, the gate driver 300 and the emitter driver 600 can be configured as an integrated circuit block.

[0064] Figure 2 It is shown Figure 1 A diagram showing the driving frequency of the display panel 100.

[0065] Reference Figure 1 and Figure 2 The display device can drive the display panel 100 at various different driving frequencies. For example, the display device can drive the display panel 100 at a first driving frequency during a first frame, at a second driving frequency during a second frame, and at a third driving frequency during a third frame, wherein the first driving frequency to the third driving frequency are different from each other. The first frame FR1 displayed at the first driving frequency may include a first active period AC1 and a first blanking period BL1. The second frame FR2 displayed at the second driving frequency may include a second active period AC2 and a second blanking period BL2. The third frame FR3 displayed at the third driving frequency may include a third active period AC3 and a third blanking period BL3.

[0066] The length of the first activation period AC1 can be substantially the same as the length of the second activation period AC2. However, due to different drive frequencies, the length of the first blanking period BL1 can differ from the length of the second blanking period BL2.

[0067] The length of the second activation period AC2 can be the same as the length of the third activation period AC3. The length of the second blanking period BL2 can be different from the length of the third blanking period BL3.

[0068] For the drive cycle of the drive sequence, the display device can drive the display panel 100 at various different drive frequencies. The drive sequence may include a write cycle and a hold cycle. During the write cycle, the display panel 100 receives a data voltage VDATA from the data driver 500 (see...). Figure 3 The data voltage VDATA is written to the pixel, and the pixel's light-emitting element emits light based on the data voltage VDATA. During the hold period, the display panel 100 stops receiving the data voltage VDATA from the data driver 500, and the pixel's light-emitting element emits light based on the data voltage VDATA previously received in the pixel during the write period. The write period may correspond to a first active period AC1, a second active period AC2, and a third active period AC3, and the hold period may correspond to a first blanking period BL1, a second blanking period BL2, and a third blanking period BL3.

[0069] Figure 3 It is shown Figure 1 Circuit diagram of a display panel with 100 pixels.

[0070] Reference Figures 1 to 3 The pixel may include a light-emitting element EE, a driving switch element T1, and a bias switch element T8. The driving switch element T1 can drive (e.g., apply) a driving current to the light-emitting element EE, and the bias switch element T8 can supply a bias voltage VBIAS to the driving switch element T1. The pixel may also include a first transmit switch element T5, a second transmit switch element T6, a data write switch element T2, a compensation switch element T3, a data initialization switch element T4, and a light-emitting element initialization switch element T7. As the emission time of the pixel increases, the level of the bias voltage VBIAS supplied to the driving switch element T1 increases.

[0071] The driving switch element T1 may include a control electrode connected to a first node N1, a first electrode connected to a second node N2, and a second electrode connected to a third node N3. The bias switch element T8 may include a control electrode receiving a bias gate signal EB, a first electrode receiving a bias voltage VBIAS, and a second electrode connected to the second node N2. The first transmit switch element T5 may include a control electrode receiving a transmit signal EM, a first electrode receiving a first power voltage ELVDD, and a second electrode connected to the second node N2. The second transmit switch element T6 may include a control electrode receiving the transmit signal EM, a first electrode connected to the third node N3, and a second electrode connected to the first electrode of the light-emitting element EE. The data write switch element T2 may include a control electrode receiving a data write gate signal GW, a first electrode receiving a data voltage VDATA, and a second electrode connected to the second node N2. The compensation switch element T3 may include a control electrode receiving a compensation gate signal GC, a first electrode connected to the first node N1, and a second electrode connected to the third node N3. The data initialization switch element T4 may include a control electrode receiving a data initialization gate signal GI, a first electrode receiving an initialization voltage VINT, and a second electrode connected to the first node N1. The light-emitting element initialization switch element T7 may include a control electrode that receives the bias gate signal EB, a first electrode that receives the light-emitting element initialization voltage AINT, and a second electrode that is connected to the first electrode of the light-emitting element EE.

[0072] The pixel may also include a first capacitor C1 and a second capacitor C2. The first capacitor C1 may include a first electrode receiving a first power voltage ELVDD and a second electrode connected to a first node N1, and the first capacitor C1 maintains the level of the data voltage VDATA applied to the first node N1 connected to the control electrode of the drive switching element T1.

[0073] The second capacitor C2 may include a first electrode that receives the first electrical voltage ELVDD and a second electrode connected to the second node N2.

[0074] The second electrical voltage ELVSS can be applied to the second electrode of the light-emitting element EE.

[0075] Each of the drive switch element T1, data write switch element T2, compensation switch element T3, data initialization switch element T4, first emitter switch element T5, second emitter switch element T6, light-emitting element initialization switch element T7, and bias switch element T8 can be a P-type low-temperature polycrystalline silicon (LTPS) thin-film transistor.

[0076] The concept of this invention may not be limited to Figure 3The pixel structure. For example, a pixel may also include additional transistors and / or additional capacitors, and transistors T1 to T8 may be connected to... Figure 3 The pixel structures are connected differently. Transistors T1 to T8 can be implemented in N-type transistors.

[0077] Figure 4 It is shown Figure 1 A diagram showing the drive sequence of the display panel 100 at various drive frequencies.

[0078] Reference Figures 1 to 4 The display device can drive the display panel 100 at various driving frequencies depending on the application. For example, the display device can drive the display panel 100 at a high driving frequency to display moving images. Conversely, the display device can drive the display panel 100 at a low frequency to display static images. Furthermore, the display device can drive the display panel 100 at a high frequency to avoid flicker in the image displayed on the display panel 100, and when the effect of flicker in the image displayed on the display panel 100 is minimal, the display device can drive the display panel 100 at a low frequency.

[0079] According to the embodiments, such as Figure 4 As shown, the maximum driving frequency of the display panel 100 can be 240Hz. However, the inventive concept is not limited to this.

[0080] The driving sequence of the display panel 100 may include a write cycle WR and a hold cycle HL. During the write cycle WR, the display panel 100 receives a data voltage VDATA from the data driver 500 and applies the data voltage VDATA to the first electrode of the drive switching element T1. The drive switching element T1 drives a drive current to the first electrode of the light-emitting element EE, causing the light-emitting element EE to emit light based on the drive current. During the hold cycle HL, the display panel 100 may stop receiving the data voltage VDATA, and the light-emitting element EE emits light based on the data voltage VDATA stored in the second capacitor C2 connected between the first power voltage ELVDD and the first electrode of the drive switching element T1. During the write cycle WR, the gate driver 300 drives the activation level of the data write gate signal GW to the control electrode of the data write switching element T2, causing the data write switching element T2 to conduct, and the data voltage VDATA may be applied to the first electrode of the drive switching element T1. During the hold period HL, the gate driver 300 drives the disable level of the data write gate signal GW to the control electrode of the data write switch element T2 to turn off the data write switch element T2, wherein the data voltage VDATA may not be applied to the first electrode of the drive switch element T1.

[0081] According to the embodiments, such as Figure 4As shown, a frame can be displayed at the maximum drive frequency (e.g., 240Hz) via a single write cycle WR.

[0082] When the display device drives the display panel 100 at a driving frequency of 240Hz, Figure 4 All first cycle periods P1 to eighth cycle periods P8 can be write cycles WR. Each of the first cycle periods P1 to eighth cycle periods P8 can be a single write cycle WR that performs both write and emission operations.

[0083] When the display device drives the display panel 100 at a drive frequency of 120Hz, the ratio between the write cycle WR and the hold cycle HL can be 1:1, where half of the drive cycle can be the write cycle WR and the other half can be the hold cycle HL. For example, the first cycle period P1, the third cycle period P3, the fifth cycle period P5, and the seventh cycle period P7 can be the write cycle WR, and the second cycle period P2, the fourth cycle period P4, the sixth cycle period P6, and the eighth cycle period P8 can be the hold cycle HL. Each of the first cycle period P1 to the eighth cycle period P8 can correspond to one cycle of the drive sequence, where the first cycle period P1 and the second cycle period P2 can form the first frame, the third cycle period P3 and the fourth cycle period P4 can form the second frame, the fifth cycle period P5 and the sixth cycle period P6 can form the third frame, and the seventh cycle period P7 and the eighth cycle period P8 can form the fourth frame.

[0084] When the display device drives the display panel 100 at a drive frequency of 60Hz, the ratio between the write cycle WR and the hold cycle HL can be 1:3, where one-quarter of the drive cycle can be the write cycle WR and three-quarters of the drive cycle can be the hold cycle HL. For example, the first cycle period P1 and the fifth cycle period P5 can be the write cycle WR, and the second cycle period P2, the third cycle period P3, the fourth cycle period P4, the sixth cycle period P6, the seventh cycle period P7, and the eighth cycle period P8 can be the hold cycle HL. Each of the first cycle period P1 to the eighth cycle period P8 corresponds to one cycle of the drive sequence, where the first cycle period P1 to the fourth cycle period P4 can form the first frame, and the fifth cycle period P5 to the eighth cycle period P8 can form the second frame.

[0085] When the display device drives the display panel 100 at a drive frequency of 30Hz, the ratio between the write cycle WR and the hold cycle HL can be 1:7, where one-eighth of the drive cycle can be the write cycle WR, and seven-eighths of the drive cycle can be the hold cycle HL. For example, the first cycle period P1 can be the write cycle WR, and the second cycle period P2, the third cycle period P3, the fourth cycle period P4, the fifth cycle period P5, the sixth cycle period P6, the seventh cycle period P7, and the eighth cycle period P8 can be the hold cycle HL. Each of the first cycle period P1 to the eighth cycle period P8 can correspond to one cycle of the drive sequence, where the first cycle period P1 to the eighth cycle period P8 can form the first frame.

[0086] Figure 5 It is shown Figure 1 The diagram shows the drive sequence of the display panel at various drive frequencies.

[0087] Figure 5 The drive sequence shown can be illustrated as an example of a frame formed by two cycles at a maximum drive frequency of 240Hz.

[0088] When the display device drives the display panel 100 at a maximum driving frequency of 240Hz, the ratio between the write cycle WR and the hold cycle HL can be 1:1, where Figure 5 Half of the drive cycle can be a write cycle (WR), and the other half can be a hold cycle (HL). For example, the first cycle period P1, the third cycle period P3, the fifth cycle period P5, the seventh cycle period P7, and the ninth cycle period P9 can be write cycles (WR), and the second cycle period P2, the fourth cycle period P4, the sixth cycle period P6, the eighth cycle period P8, and the tenth cycle period P10 can be hold cycles (HL). Each of the first cycle period P1 to the tenth cycle period P10 can correspond to one cycle of the drive sequence, where the first cycle period P1 and the second cycle period P2 can form the first frame, the third cycle period P3 and the fourth cycle period P4 can form the second frame, the fifth cycle period P5 and the sixth cycle period P6 can form the third frame, the seventh cycle period P7 and the eighth cycle period P8 can form the fourth frame, and the ninth cycle period P9 and the tenth cycle period P10 can form the fifth frame.

[0089] When the display device drives the display panel 100 at a drive frequency of 120Hz, the ratio between the write cycle WR and the hold cycle HL can be 1:3, where one-quarter of the drive cycle can be the write cycle WR and three-quarters of the drive cycle can be the hold cycle HL. For example, the first cycle period P1, the fifth cycle period P5, and the ninth cycle period P9 can be the write cycle WR, and the second cycle period P2, the third cycle period P3, the fourth cycle period P4, the sixth cycle period P6, the seventh cycle period P7, the eighth cycle period P8, and the tenth cycle period P10 can be the hold cycle HL. Each of the first cycle period P1 to the tenth cycle period P10 can correspond to one cycle of the drive sequence, where the first cycle period P1 to the fourth cycle period P4 can form the first frame, the fifth cycle period P5 to the eighth cycle period P8 can form the second frame, and the ninth cycle period P9 and the tenth cycle period P10 can form part of the third frame.

[0090] When the display device drives the display panel 100 at a drive frequency of 60Hz, the ratio between the write cycle WR and the hold cycle HL can be 1:7, where one-eighth of the drive cycle can be the write cycle WR, and seven-eighths of the drive cycle can be the hold cycle HL. For example, the first cycle period P1 and the ninth cycle period P9 can be the write cycle WR, and the second cycle period P2, the third cycle period P3, the fourth cycle period P4, the fifth cycle period P5, the sixth cycle period P6, the seventh cycle period P7, the eighth cycle period P8, and the tenth cycle period P10 can be the hold cycle HL. Each of the first cycle period P1 to the eighth cycle period P10 can correspond to one cycle of the drive sequence, where the first cycle period P1 to the eighth cycle period P8 can form the first frame, and the ninth cycle period P9 and the tenth cycle period P10 can form part of the second frame.

[0091] When the display device drives the display panel 100 at a drive frequency of 48Hz, the ratio between the write cycle WR and the hold cycle HL can be 1:9, where one-tenth of the drive cycle can be the write cycle WR and nine-tenths of the drive cycle can be the hold cycle HL. For example, the first cycle period P1 can be the write cycle WR, and the second cycle period P2, the third cycle period P3, the fourth cycle period P4, the fifth cycle period P5, the sixth cycle period P6, the seventh cycle period P7, the eighth cycle period P8, the ninth cycle period P9, and the tenth cycle period P10 can be the hold cycle HL. Each of the first cycle period P1 to the tenth cycle period P10 can correspond to one cycle of the drive sequence, where the first cycle period P1 to the tenth cycle period P10 can form the first frame.

[0092] Figure 6This indicates the force applied during the write cycle WR. Figure 1 Timing diagram of the input signals of the display panel 100. Figure 7 This shows the application of [something] during the holding period HL. Figure 1 Timing diagram of the input signals of the display panel 100.

[0093] Reference Figures 1 to 7 During the write cycle WR, the activation pulses of the data initialization gate signal GI, the data write gate signal GW, the compensation gate signal GC, and the bias gate signal EB can be applied sequentially or in parallel. Figure 3 The pixels. The activation pulse for the gate signal can be a logic low level.

[0094] When the activation pulse of the data initialization gate signal GI is applied to the pixel, the data initialization switch element T4 can be turned on, and the initialization voltage VINT can be applied to the first node N1 connected to the control electrode of the drive switch element T1.

[0095] When the activation pulses of the data write gate signal GW and the compensation gate signal GC are applied to the pixel, the data write switch element T2 and the compensation switch element T3 can be turned on. The data voltage VDATA can be applied to the second node N2, which is connected to the first electrode of the drive switch element T1, through the data write switch element T2. Because the compensation switch element T3 is turned on, the drive switch element T1 is connected in the form of a diode, and the data voltage VDATA applied to the second node N2 drives the drive switch element T1. The data voltage VDATA applied to the second node N2 can be applied to the first node N1, which is connected to the control electrode of the drive switch element T1, after being compensated by the threshold voltage of the drive switch element T1.

[0096] When the activation pulse of the bias gate signal EB is applied to the pixel, the light-emitting element initialization switch T7 and the bias switch T8 can be turned on, wherein the light-emitting element initialization voltage AINT can be applied to the first electrode of the light-emitting element EE, and the bias voltage VBIAS can be applied to the second node N2 connected to the first electrode of the drive switch T1.

[0097] exist Figure 7 During the hold period HL, the data initialization gate signal GI, the data write gate signal GW, and the compensation gate signal GC can remain at inactive levels, thus preventing the data voltage VDATA from being applied to the second node N2. However, the activation pulse of the bias gate signal EB can be applied to emit light through the light-emitting element EE. The inactive level of the gate signal can be logic high, and the activation pulse can be logic low.

[0098] During the hold period HL, the data initialization switch element T4 remains off and the voltage level of the first node N1 can be maintained by the first capacitor C1, while the data write switch element T2 remains off and the voltage level of the second node N2 can be maintained by the second capacitor C2. Because the compensation switch element T3 remains off, the diode connection of the drive switch element T1 can be disconnected. However, in response to the activation pulse of the bias gate signal EB during the hold period HL, the light-emitting element initialization switch element T7 and the bias switch element T8 can be turned on. Therefore, the bias operation via the bias switch element T8 and the light-emitting element initialization operation via the light-emitting element initialization switch element T7 can be performed continuously during the hold period HL.

[0099] exist Figure 6 During the write cycle WR, when the activation pulses of the data initialization gate signal GI, the data write gate signal GW, the compensation gate signal GC, and the bias gate signal EB are applied to the pixel, the transmit signal EM can have an inactive level until the next data voltage VDATA received from the data driver 500 is written into the pixel.

[0100] Figure 7 The pulse width of the transmitted signal EM in the hold period HL can be compared with... Figure 6 The pulse width of the transmit signal EM in the write cycle WR is the same.

[0101] Figure 8A This illustrates when the display device drives the display panel 100 without illumination timing control. Figure 1 Timing diagram of the brightness of display panel 100.

[0102] Reference Figure 8A The display panel 100 displays an image during the write cycle WR and hold cycles HL1 to HL7. Frames in the drive sequence may include one write cycle WR and multiple hold cycles HL1 to HL7 at a low drive frequency.

[0103] During the hold period at a low driving frequency, the brightness of the display panel 100 can be gradually reduced. In particular, the brightness of the display panel 100 can be rapidly reduced within a high grayscale range.

[0104] In the role of Figure 8A During the seventh hold cycle HL7 of the final hold cycle, the brightness of the display panel 100 may be lower than the brightness of the display panel 100 during the write cycle WR by a first difference DF1. For a user viewing the display panel 100, this brightness difference can be perceived as flicker.

[0105] Figure 8B This illustrates when the display device drives the display panel 100 using light-emitting timing control. Figure 1 Timing diagram of the brightness of display panel 100.

[0106] Unlike Figure 8A The brightness level shown Figure 8B The brightness level can be slowly reduced during the multiple hold cycles HL1 to HL7, and the flicker of the display panel 100 due to the brightness difference can be reduced.

[0107] Reference Figure 8B The display panel 100 can compensate for brightness reduction by performing emissivity timing control. When the display device drives the display panel 100 at a low drive frequency, emissivity timing control can be performed by increasing the emissivity time in the later portions of the hold cycles among the plurality of hold cycles HL1 to HL7 (e.g., the fifth hold cycle HL5 to the seventh hold cycle HL7). For example, the display device can drive the display panel 100 at a low drive frequency for a first emissivity time OT1 during the earlier portions of the write cycle WR and hold cycles (e.g., the first hold cycle HL1 to the fourth hold cycle HL4). The display device can drive the display panel 100 at a low drive frequency for a second emissivity time OT2, which is longer than the first emissivity time OT1, in the later portions of the hold cycles (e.g., the fifth hold cycle HL5 to the seventh hold cycle HL7).

[0108] The brightness of the later portion of the hold period at a low drive frequency can be increased by increasing the emission time in the later portion of the hold period.

[0109] and Figure 8A Compared to the brightness reduction in the seventh retention period HL7, in the case of... Figure 8B During the seventh hold cycle (HL7) of the final hold cycle, the brightness of the display panel 100 can be reduced less. The brightness of the seventh hold cycle (HL7) can be lower than the brightness of the write cycle (WR) by a second difference (DF2), which is smaller than the first difference (DF1). This is because at low drive frequencies, the light emission time increases in the later portion of the hold cycle, thus... Figure 8A Compared to the first difference DF1, the second difference DF2 between the last hold period and the write period WR after the last hold period can be smaller, and the flicker of the display panel 100 can be reduced.

[0110] Reference Figure 8B During the earlier portion of the write cycle (WR) and hold cycle, the pixel can be in the corresponding... Figure 8AThe pixel emits light during the first emission duration t1 of the first emission time OT1. An earlier portion of the hold period can be a first hold period HL1 to a fourth hold period HL4. Similarly, during a later portion of the hold period, the pixel can emit light during a second emission duration t2 corresponding to the second emission time OT2. A later portion of the hold period can be a fifth hold period HL5 to a seventh hold period HL7. For example, during a write period WR, the pixel can emit light during the first emission duration t1, and during the fifth hold period HL5, the pixel can emit light during the second emission duration t2. The second emission duration t2 can be equal to or greater than the first emission duration t1.

[0111] The second emission duration t2 for each cycle of the later portion of the holding period can correspond to the second emission time OT2. Each cycle of the later portion of the holding period can have the same duration as each other. Alternatively, the second emission duration t2 for each cycle of the later portion of the holding period can be different from the durations of the other cycles of the later portion of the holding period. For example, the emission duration of the fifth holding period HL5 can be different from the emission duration of the sixth holding period HL6. Similarly, the emission duration of the sixth holding period HL6 can be different from the emission duration of the seventh holding period HL7.

[0112] Despite Figure 8B In this invention, the number of the earlier portions of the holding period with the first emission time OT1 is four, and the number of the later portions of the holding period with the second emission time OT2 is three, but the inventive concept is not limited to the number of holding periods.

[0113] Figure 9 It is shown Figure 1 Block diagram of the drive controller 200. Figure 10 It is shown Figure 9 A diagram showing the setting values ​​of the position setter 250. Figure 11A and Figure 11B This indicates the adjustment Figure 10 A timing diagram of the method for determining the end of the off-duration period of the transmitted signal EM. Figure 12A and Figure 12B This indicates the adjustment Figure 10 A timing diagram of the method for determining the start of the off-duration period of the transmitted signal EM.

[0114] Reference Figures 1 to 12BThe drive controller 200 can determine whether the current cycle is a write cycle (WR) or a hold cycle (HL) based on the control signal CONT. During the write cycle (WR), the drive controller 200 controls the data voltage VDATA to be written to the pixel, and controls the pixel's light-emitting element (EE) to emit light based on the data voltage VDATA. During the hold cycle (HL), the drive controller 200 further controls the data voltage VDATA not to be written to the pixel, and controls the pixel's light-emitting element (EE) to emit light based on the data voltage stored in the pixel.

[0115] The drive controller 200 can count the hold cycles HL and determine the hold cycle number of the current hold cycle within the hold cycle HL. For example, the drive controller 200 can determine that the hold cycle number of the first hold cycle HL1 immediately following the write cycle WR is 1, and can determine that the hold cycle number of the fifth hold cycle HL5 within the hold cycle HL is 5.

[0116] Based on the number of hold cycles, the drive controller 200 can determine the transmit start time and transmit stop time (EOF) of the current hold cycle.

[0117] The drive controller 200 can change the transmission off time EOF by adjusting at least one of the end point of the off duration of the transmission signal EM and the start point of the off duration of the transmission signal EM according to the set value SV.

[0118] For example, when the number of hold cycles in the current hold period is determined to be equal to or greater than a predetermined hold cycle reference number, the drive controller 200 can increase the transmit on-time to be longer than the reference transmit on-time. The hold cycle reference number can be a reference value that the drive controller 200 can use to determine whether to maintain the reference transmit on-time or adjust the transmit on-time. When the current number of hold cycles is less than the hold cycle reference number, the drive controller 200 can determine to maintain the reference transmit on-time. When the current number of hold cycles is equal to or greater than the hold cycle reference number, the drive controller 200 can determine to adjust the transmit on-time.

[0119] For example, when in Figure 8B When the predetermined hold period reference number is 5, the drive controller 200 can increase the transmit on-time for the fifth hold period HL5 and the hold periods following the fifth hold period HL5 (e.g., the sixth hold period HL6 and the seventh hold period HL7). Therefore, the transmit on-time from the fifth hold period HL5 to the seventh hold period HL7 can be gradually increased and become longer than the reference transmit on-time until a new write cycle WR begins. The reference transmit on-time can correspond to... Figure 8B The first emission time OT1, and the increased emission on-time can correspond to Figure 8B The second emission time OT2. (Refer to...) Figure 9 The base transmit on time can be adjusted, and the transmit off time (EOF) can be set differently. For example, the transmit off time (EOF) can be set to one cycle minus 15 horizontal cycles (15H). For a transmit on time that is adjusted to an increased hold period, the transmit off time (EOF) can be set to one cycle minus 9 horizontal cycles (9H).

[0120] When the emission time is increased in the later portion of the hold cycle at a low driving frequency, the brightness can be increased due to the hysteresis characteristics of the driving switching element T1 in the low grayscale range. Furthermore, when the number of hold cycles in the current hold cycle is equal to or greater than a predetermined hold cycle reference number, the display panel driver can increase the bias voltage VBIAS applied to the driving switching element T1 of the pixel to a value greater than the reference bias voltage. By increasing the bias voltage VBIAS applied to the driving switching element T1 in the later portion of the hold cycle, the increase in brightness in the low grayscale range due to the hysteresis characteristics of the driving switching element T1 can be compensated.

[0121] The drive controller 200 may include a signal generator 210 that generates a vertical start signal VS and a data enable signal DE, and a cycle counter 230 that determines whether the current cycle is a write cycle WR or a hold cycle HL based on the vertical start signal VS and the data enable signal DE. When the hold cycle HL repeats in the drive sequence, the cycle counter 230 also determines the hold cycle number of the current hold cycle within the hold cycle HL based on the vertical start signal VS and the data enable signal DE.

[0122] For example, when the cycle counter 230 repeatedly receives pulses of the data enable signal DE after receiving the vertical start signal VS, the cycle counter 230 can determine the current period as the write period WR. When the cycle counter 230 does not receive pulses of the data enable signal DE after receiving the vertical start signal VS, the cycle counter 230 can determine the current period as the hold period HL.

[0123] The drive controller 200 may also include a lookup table 240 that stores the transmit off time EOF corresponding to the hold cycle number HCY.

[0124] The drive controller 200 may further include a register 220 storing a transmit shutdown setting CDC, and the register 220 is configured to determine a transmit shutdown time EOF for the hold cycle number HCY based on the transmit shutdown setting CDC. The transmit shutdown setting CDC may include a hold cycle number HCY for selecting the transmit shutdown time EOF corresponding to the hold cycle number HCY in a lookup table 240.

[0125] The drive controller 200 may also include a transmit shutdown time output circuit 260. The transmit shutdown time output circuit 260 can receive the hold period number HCY of the current hold period from the period counter 230, and can output the transmit shutdown time EOF corresponding to the hold period number HCY from the lookup table 240. The transmit shutdown time output circuit 260 can be implemented using a multiplexer.

[0126] The drive controller 200 may also include a position setter 250. The position setter 250 may output a setpoint SV, which allows the transmitter driver 600 to determine whether to change the end point or the start point of the off-duration of the transmitter signal EM.

[0127] The transmit driver 600 can generate a transmit signal EM based on the transmit shutdown time EOF received from the transmit shutdown time output circuit 260 and the set value SV received from the position setter 250, and provide the transmit signal EM to the pixel.

[0128] like Figure 10 As shown, when the set value SV is the first value (e.g., logic low level), the display panel driver can advance the end of the off-time of the luminous signal EM to reduce the emission off-time EOF.

[0129] Reference Figure 11A The reference launch start time can be determined by the reference launch shutdown time EOF1. (Refer to...) Figure 11B The launch-on time can be increased and made longer than the baseline launch-on time, and the increased launch-on time can be determined by the launch-off time EOF2. For example... Figure 11B As shown, the end of the off-duration of the transmit signal EM can be advanced by a first reduction value DEA. The transmit off-duration EOF can be reduced from the reference transmit off-duration EOF1 to the transmit off-duration EOF2, and the transmit on-duration can be increased accordingly.

[0130] When the set value SV is the second value, such as a logic high level, the display panel driver can delay the start of the off-time of the transmit signal EM to reduce the transmit off-time EOF.

[0131] Reference Figure 12A The reference launch start time can be determined by the reference launch shutdown time EOF1. (Refer to...) Figure 12B The launch-on time can be increased and made longer than the baseline launch-on time, and the increased launch-on time can be determined by the launch-off time EOF2. For example... Figure 12BAs shown, the start point of the off-duration of the transmit signal EM can be delayed by a second reduction value DSA. The transmit off-duration EOF can be reduced from the reference transmit off-duration EOF1 to the transmit off-duration EOF2, and the transmit on-duration can be increased accordingly.

[0132] like Figure 11A As shown, the duration between the activation pulse of the bias gate signal EB and the end of the off duration of the transmit signal EM can be referred to as the first bias period BP1, during which the bias voltage VBIAS is applied to the drive switching element T1. Figure 11B In this context, the duration between the activation pulse of the bias gate signal EB and the end of the off duration of the transmit signal EM can be referred to as the second bias period BP2.

[0133] When the end of the off-time of the transmit signal EM is brought forward to reduce the transmit off-time EOF, the duration of the bias period can be reduced from the first bias period BP1 to the second bias period BP2, and the duration of the bias period during which the bias voltage VBIAS is applied to the drive switching element T1 can be reduced.

[0134] To prevent the duration of the offset period from decreasing, the setpoint SV can be set to a second value, and the start point of the off-time of the transmit signal EM can be delayed to reduce the total transmit off-time EOF. For example... Figure 12B As shown, the duration of the bias period can be maintained when the start point of the off-time of the transmit signal EM is delayed to reduce the total transmit off-time EOF.

[0135] According to an embodiment, when the display device drives the display panel 100 at a low driving frequency during the hold period HL, the display device can perform light emission timing control to increase the light emission time in the later part of the hold period HL.

[0136] As the emission time increases in the later portion of the hold cycle (e.g., from the fifth hold cycle HL5 to the seventh hold cycle HL7), the brightness can actually increase due to the hysteresis characteristics of the driving switching element T1 in the low grayscale range, and the duration of the bias period in the later portion of the hold cycle (e.g., from the fifth hold cycle HL5 to the seventh hold cycle HL7), during which the bias voltage VBIAS is applied to the driving switching element T1, can be increased.

[0137] like Figure 11A and Figure 11BAs shown, as the display device performs emission timing control, the duration of the bias period during which the bias voltage VBIAS is applied to the driving switching element T1 can be reduced from a first bias period BP1 to a second bias period BP2. To prevent undesirable effects due to the increased duration of the bias period, when adjusting the emission timing of the pixel, one of the end point of the off-duration of the emission signal EM and the start point of the off-duration of the emission signal EM can be selectively adjusted.

[0138] Therefore, at low driving frequencies, the brightness difference of the display panel 100 can be reduced within a low grayscale range. Consequently, flickering of the display panel 100 due to brightness differences can be prevented or reduced, and the display quality of the display panel 100 can be improved.

[0139] Figure 13 This shows the position setter 250 according to the display device (see...). Figure 9 The diagram shows the method for adjusting the launch shutdown time based on the set value. Figure 14A and Figure 14B This indicates the adjustment Figure 13 A timing diagram showing the start and end points of the shutdown duration of the transmitted signal EM.

[0140] Reference Figure 13 The setting value of the position setter 250 can be compared with... Figure 10 The settings are set differently.

[0141] Reference Figures 1 to 9 and Figure 11 to Figure 14A and Figure 14B The drive controller 200 may include a position setter 250. The position setter 250 may output a setpoint SV, which allows the transmitter driver 600 to determine whether to change the end point or the start point of the off-duration of the transmitter signal EM.

[0142] The transmit driver 600 can generate a transmit signal EM based on the transmit shutdown time EOF received from the transmit shutdown time output circuit 260 and the set value SV received from the position setter 250, and output the transmit signal EM to the pixel.

[0143] like Figure 13 As shown, when the setting value SV is the first value that can be "00", the display panel driver can advance the end of the off-time of the light emission signal EM to reduce the emission off-time EOF.

[0144] Reference Figure 11A The reference launch start time can be determined by the reference launch shutdown time EOF1. (Refer to...) Figure 11BThe launch-on time can be increased and made longer than the baseline launch-on time, and the increase in launch-on time can be determined by the launch-off time EOF2. For example... Figure 11B As shown, the end of the off-duration period of the transmit signal EM can be advanced by a first reduction value DEA. The transmit off-duration EOF can be reduced from the reference transmit off-duration EOF1 to the transmit off-duration EOF2, and the transmit on-duration can be increased accordingly.

[0145] When the setting value SV is a second value that can be "01", the display panel driver can delay the start of the off-time of the transmit signal EM to reduce the transmit off-time EOF.

[0146] Reference Figure 12A The reference launch start time can be determined by the reference launch shutdown time EOF1. (Refer to...) Figure 12B The launch-on time can be increased and made longer than the baseline launch-on time, and the increased launch-on time can be determined by the launch-off time EOF2. For example... Figure 12B As shown, the start point of the off duration of the transmit signal EM can be delayed by a second reduction value DSA, and the transmit off time EOF can be reduced from the reference transmit off time EOF1 to the transmit off time EOF2, and the transmit on time can be increased accordingly.

[0147] like Figure 11A and Figure 11B As indicated in the document, the duration from the activation pulse of the bias gate signal EB to the end of the off duration of the transmit signal EM can be referred to as the first bias period BP1 and the second bias period BP2, respectively, wherein the bias voltage VBIAS is applied to the drive switching element T1.

[0148] When the end of the off-time of the transmit signal EM is brought forward to reduce the transmit off-time EOF, the duration of the bias period can be reduced from the first bias period BP1 to the second bias period BP2, and the duration of the bias period during which the bias voltage VBIAS is applied to the drive switching element T1 can be reduced.

[0149] To prevent undesirable effects due to increased bias duration, the setting value SV can be set to a second value that can be "01", and the start point of the transmit signal EM's off duration can be delayed to reduce the total transmit off time EOF. For example... Figure 12B As shown, the duration of the bias period can be maintained when the start point of the off-time of the transmit signal EM is delayed to reduce the total transmit off-time EOF.

[0150] When the setting value SV is a third value that can be "10", the display panel driver can advance the end of the off duration of the transmit signal EM and delay the start of the off duration of the transmit signal EM to reduce the total transmit off time EOF.

[0151] Reference Figure 13 When the setting value SV is a third value that can be "10", the display panel driver can advance the end of the off duration of the transmit signal EM and delay the start of the off duration of the transmit signal EM to reduce the total transmit off time EOF.

[0152] Reference Figure 14A The reference launch start time can be determined by the reference launch shutdown time EOF1. (Refer to...) Figure 14B The launch-on time can be increased and made longer than the baseline launch-on time, and the increased launch-on time can be determined by the launch-off time EOF2. For example... Figure 14B As shown, the end point of the off duration of the transmit signal EM can be advanced by a third reduction value DEA, and the start point of the off duration of the transmit signal EM can be delayed by a fourth reduction value DSA, and the total transmit off time EOF can be reduced from the reference transmit off time EOF1 to the transmit off time EOF2.

[0153] According to an embodiment, when the display device drives the display panel 100 at a low driving frequency, the display device can perform light emission timing control to increase the light emission time in the later part of the holding period.

[0154] Due to the hysteresis characteristics of the driving switching element T1 in the low grayscale range, the brightness can be increased. When the emission time is increased in the later part of the hold cycle (e.g., the fifth hold cycle HL5 to the seventh hold cycle HL7), the bias voltage VBIAS applied to the driving switching element T1 can be increased in the later part of the hold cycle.

[0155] As the display device performs emission timing control, the duration of the bias period during which the bias voltage VBIAS is applied to the driving switching element T1 can be reduced from the first bias period BP1 to the second bias period BP2, such as... Figure 11A and Figure 11B As shown in the figure. To prevent undesirable effects due to the increased duration of the offset period, the end point and the start point of the off-duration of the transmit signal EM can be adjusted.

[0156] Therefore, at low driving frequencies, the brightness difference of the display panel 100 can be reduced in the low grayscale range, and the flicker of the display panel 100 caused by the brightness difference can be prevented or reduced, thereby improving the display quality of the display panel 100.

[0157] Figure 15 This is a circuit diagram showing the pixels of the display panel 100.

[0158] Display devices may include those different from those used in display devices. Figure 3 The pixel circuit of the pixel circuit.

[0159] Reference Figure 15 The pixel may include a compensation switching element (e.g., a first compensation transistor T3-1 and a second compensation transistor T3-2) connected between a first node N1 connected to the control electrode of the driving switching element T1 and a third node N3 connected to the second electrode of the driving switching element T1.

[0160] The compensation switching element may include a first compensation transistor T3-1 and a second compensation transistor T3-2 connected in series with each other. The first compensation transistor T3-1 may include a control electrode receiving a compensation gate signal GC, a first electrode connected to a first node N1 connected to the control electrode of the driving switching element T1, and a second electrode connected to a first intermediate node connected to the second compensation transistor T3-2. The second compensation transistor T3-2 may include a control electrode receiving the compensation gate signal GC, a first electrode connected to the first intermediate node, and a second electrode connected to a third node N3 connected to the second electrode of the driving switching element T1.

[0161] Because the compensation switching element includes two transistors T3-1 and T3-2 connected in series with each other, the leakage current through the compensation switching element can be reduced compared to the case where the compensation switching element includes a single transistor, and the level of the data voltage VDATA applied to the first node N1 connected to the control electrode of the driving switching element T1 and stored in the first capacitor C1 can be better maintained.

[0162] The pixel may include a data initialization switching element (e.g., a first data initialization transistor T4-1 and a second data initialization transistor T4-2) connected to a first node N1 connected to the control electrode of the driving switching element T1, and applying an initialization voltage VINT to the first node N1 connected to the control electrode of the driving switching element T1.

[0163] More specifically, the data initialization switching element may include a first data initialization transistor T4-1 and a second data initialization transistor T4-2 connected in series with each other. The first data initialization transistor T4-1 may include a control electrode for receiving the data initialization gate signal GI, a first electrode connected to a second intermediate node, and a second electrode connected to a first node N1 connected to the control electrode of the driving switching element T1. The second data initialization transistor T4-2 may include a control electrode for receiving the data initialization gate signal GI, a first electrode for receiving the initialization voltage VINT, and a second electrode connected to the second intermediate node.

[0164] Because the data initialization switching element includes two transistors T4-1 and T4-2 connected in series with each other, the leakage current through the data initialization switching element can be reduced compared to the case where the data initialization switching element includes a single transistor, and the level of the data voltage VDATA applied to the first node N1 connected to the control electrode of the driving switching element T1 and stored in the first capacitor C1 can be better maintained.

[0165] According to an embodiment, when the display device drives the display panel 100 at a low driving frequency during the hold period HL, the display device can perform light emission timing control to increase the light emission time in the later part of the hold period.

[0166] In the low grayscale range, the brightness can actually be increased due to the hysteresis characteristics of the driving switching element T1, because the emission time is increased in the later part of the hold period (e.g., from the fifth hold period HL5 to the seventh hold period HL7), and the duration of the bias period in the later part of the hold period (e.g., from the fifth hold period HL5 to the seventh hold period HL7) in which the bias voltage VBIAS is applied to the driving switching element T1 can be increased.

[0167] To prevent undesirable effects caused by increasing the duration of the bias period of the bias voltage VBIAS applied to the driving switching element T1 through emission time control, one of the end point of the off-duration of the emission signal EM and the start point of the off-duration of the emission signal EM can be selectively adjusted while adjusting the emission time of the pixel.

[0168] Therefore, at low driving frequencies, the brightness difference of the display panel 100 can be reduced in the low grayscale range, and the flicker of the display panel 100 caused by the brightness difference can be prevented or reduced, thereby improving the display quality of the display panel 100.

[0169] Figure 16 This is a block diagram illustrating an electronic device 1000 according to an embodiment of the concept of the present invention. Figure 17 It is shown as Figure 16 A diagram of an example of a smartphone among 1000 electronic devices. Figure 18 It is shown as Figure 16 A diagram of a monitor, representing an example of an electronic device 1000.

[0170] Reference Figures 16 to 18 The electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. The display device 1060 may be... Figure 1 The display device. In addition, the electronic device 1000 may include multiple ports for communicating with video cards, sound cards, memory cards, universal serial bus (USB) devices, and other electronic devices.

[0171] Although smartphones and monitors are illustrated as examples of electronic devices 1000, electronic devices 1000 are not limited to these. For example, electronic devices 1000 may include televisions, cellular phones, video phones, smartboards, smartwatches, tablet PCs, car navigation systems, laptop computers, and head-mounted display (HMD) devices, etc.

[0172] Processor 1010 can perform various computing functions or tasks. Processor 1010 can be a microprocessor, central processing unit (CPU), application processor (AP), etc. Processor 1010 can be coupled to other components via address bus, control bus, and data bus. In addition, processor 1010 can be coupled to an expansion bus (such as a peripheral component interconnect (PCI) bus).

[0173] Processor 1010 can... Figure 1 The drive controller 200 outputs and inputs image data (IMG) (see Figure 1 ) and input control signal CONT (see Figure 1 ).

[0174] The memory device 1020 can store data for the operation of the electronic device 1000. The memory device 1020 may include at least one non-volatile memory device (such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase-change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano-floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, and a ferroelectric random access memory (FRAM) device, etc.) and / or at least one volatile memory device (such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, and a mobile DRAM device, etc.).

[0175] Storage device 1030 may include solid-state drive (SSD) devices, hard disk drive (HDD) devices, and read-only optical disc (CD-ROM) devices. I / O device 1040 may include input devices such as keyboards, keypads, mice, touchpads, and touchscreens, and output devices such as printers and speakers. Display device 1060 may be integrated into I / O device 1040. Power supply 1050 provides power for the operation of electronic device 1000. Display device 1060 may be coupled to other components via a bus or other communication link.

[0176] Figure 19 This is a block diagram illustrating an electronic device 101 according to an embodiment of the concept of the present invention.

[0177] Reference Figures 1 to 19 The electronic device 101 outputs various information through the display module 140 in the operating system. When the processor 110 executes the application stored in the memory 120, the display module 140 provides application information to the user through the display panel 141.

[0178] Processor 110 receives external input via input module 130 or sensor module 161 and executes an application corresponding to the external input. For example, when a user selects the camera icon displayed on display panel 141, processor 110 receives user input via input sensor 161-2 and activates camera module 171. Processor 110 transmits image data corresponding to the captured image obtained by camera module 171 to display module 140. Display module 140 can display the image corresponding to the captured image via display panel 141.

[0179] When personal information authentication is performed in the display module 140, the fingerprint sensor 161-1 obtains the input fingerprint information as input data. The processor 110 compares the input data obtained by the fingerprint sensor 161-1 with the authentication data stored in the memory 120, and executes the application based on the comparison result. The display module 140 can display the information executed according to the application logic through the display panel 141.

[0180] When the music stream icon displayed in the display module 140 is selected, the processor 110 obtains user input through the input sensor 161-2 and activates the music stream application stored in the memory 120. When the music execution command is received by the music stream application, the processor 110 activates the sound output module 163 to provide the user with sound information corresponding to the music execution command.

[0181] Electronic device 101 may include various components for performing the operations described above. Some components of electronic device 101 may be integrated into one component, or one component may be divided into two or more components.

[0182] Electronic device 101 can communicate with external electronic device 102 via a network (e.g., a short-range wireless communication network or a long-range wireless communication network). Electronic device 101 may include processor 110, memory 120, input module 130, display module 140, power module 150, embedded module 160, and external module 170. Some components of electronic device 101 may be optional, and other components not listed above may also be used. Some of the aforementioned components (such as sensor module 161, antenna module 162, or audio output module 163) may be integrated into other components such as display module 140.

[0183] The processor 110 can execute software to control at least one other hardware or software element of the electronic device 101 and perform various data processing or operations on the hardware or software element. According to an embodiment, at least a portion of the data processing or operation can store instructions or data received from other elements such as the input module 130, sensor module 161, or communication module 173 in volatile memory 121, and can process the instructions or data stored in volatile memory 121 and store the processing results in non-volatile memory 122.

[0184] Processor 110 may include a main processor 111 and an auxiliary processor 112. Main processor 111 may include at least one of a central processing unit (CPU) 111-1 and an application processor (AP). Main processor 111 may also include any one or more of a graphics processing unit (GPU) 111-2, a communication processor (CP), and an image signal processor (ISP). Main processor 111 may also include a neural network processing unit (NPU) 111-3. Neural network processing unit 111-3 is a processor specifically designed to process artificial intelligence models. Artificial intelligence models can be generated through machine learning. Artificial intelligence models may include multiple layers of artificial neural networks (artificial neural networks). Artificial neural networks may be one of deep neural networks (DNN), convolutional neural networks (CNN), recurrent neural networks (RNN), restricted Boltzmann machines (RBM), deep belief networks (DBN), bidirectional recurrent deep neural networks (BRDNN), and deep Q-networks, or a combination of two or more of the above. However, artificial neural networks are not limited to the examples above. In addition to hardware architecture, artificial intelligence models may additionally or alternatively include software architecture. At least two of the aforementioned processing units and processors can be implemented as integrated elements, or each can be implemented as a separate element. A single chip may include processing units integrated into a single element, and multiple chips may include processing units implemented in several separate elements.

[0185] The auxiliary processor 112 may include a controller. The controller may include interface conversion circuitry and timing control circuitry. The controller receives image signals from the main processor 111, converts the data format of the image signals to conform to the interface specifications of the display module 140, and outputs the image data. The controller may output various control signals for driving the display module 140.

[0186] The auxiliary processor 112 may further include a data conversion circuit 112-2, a gamma correction circuit 112-3, and a rendering circuit 112-4. The data conversion circuit 112-2 can receive image data from the controller and compensate the image data according to the characteristics of the electronic device 101 or user settings, so that the image is displayed with a desired brightness; or the data conversion circuit 112-2 can convert the image data to reduce power consumption or compensate for afterimages in the image data. The gamma correction circuit 112-3 can convert image data or a gamma reference voltage used to display an image in the electronic device 101 into an image with desired gamma characteristics. The rendering circuit 112-4 can receive image data from the controller and can render the image data based on the pixel arrangement of the display panel 141 included in the electronic device 101. At least one of the data conversion circuit 112-2, the gamma correction circuit 112-3, and the rendering circuit 112-4 may be integrated into another component (e.g., the main processor 111 or the controller). At least one of the data conversion circuit 112-2, the gamma correction circuit 112-3, and the rendering circuit 112-4 can be integrated into the data driver 143.

[0187] The memory 120 may store various data used by at least one element of the electronic device 101 (e.g., processor 110 or sensor module 161), as well as input or output data for commands associated therewith. The memory 120 may include at least one of volatile memory 121 and non-volatile memory 122.

[0188] The input module 130 can receive commands or data from outside the electronic device 101 (e.g., from a user or external electronic device 102), wherein the commands or data can be used by components of the electronic device 101 (e.g., processor 110, sensor module 161, or sound output module 163).

[0189] Input module 130 may include a first input module 131 for receiving commands or data from a user and a second input module 132 for receiving commands or data from an external electronic device 102. The first input module 131 may include a microphone, mouse, keyboard, keys (e.g., buttons), or pen (e.g., a passive or active pen). The second input module 132 may support a specified protocol enabling wired or wireless connection to the external electronic device 102. According to embodiments, the second input module 132 may include a High Definition Multimedia Interface (HDMI), a Universal Serial Bus (USB) interface, a Secure Digital Card (SD) card interface, or an audio interface. The second input module 132 may include a connector (e.g., an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector)) physically connected to the external electronic device 102.

[0190] Display module 140 provides video information to the user. Display module 140 may include display panel 141, scan driver 142, and data driver 143. Display module 140 may also include a window, chassis, and bracket to protect display panel 141.

[0191] Display panel 141 may include a liquid crystal display panel, an organic light-emitting display panel, or an inorganic light-emitting display panel. The type of display panel 141 is not particularly limited. Display panel 141 may be rigid or flexible and capable of being rolled or folded. Display module 140 may also include a support member or heat dissipation member supporting display panel 141.

[0192] The scan driver 142 can be mounted as a driver chip in the display panel 141. Alternatively, the scan driver 142 can be integrated into the display panel 141. For example, the scan driver 142 may include an amorphous silicon thin-film transistor (TFT) gate (ASG) driving circuit, a low-temperature polycrystalline silicon (LTPS) TFT gate driving circuit, or an oxide semiconductor TFT gate (OSG) driving circuit integrated into the display panel 141. The scan driver 142 receives control signals from the controller and outputs scan signals to the display panel 141 in response to the control signals.

[0193] The display module 140 may further include a light-emitting driver. The light-emitting driver outputs a light-emitting control signal to the display panel 141 in response to a control signal received from the controller. The light-emitting driver may be formed independently of the scan driver 142. Alternatively, the light-emitting driver may be integrated into the scan driver 142.

[0194] The data driver 143 receives a control signal from the controller and converts the image data into an analog voltage (e.g., a data voltage), and outputs the data voltage to the display panel 141 in response to the control signal.

[0195] The data driver 143 can be integrated into another component (e.g., a controller). The functions of the interface conversion circuitry and timing control circuitry of the aforementioned controller can be integrated into the data driver 143.

[0196] The display module 140 may also include a voltage generation circuit. The voltage generation circuit can output various voltages for driving the display panel 141.

[0197] Power module 150 supplies power to components of electronic device 101. Power module 150 may include a battery that supplies power voltage. The battery may include a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell. Power module 150 may include a power management integrated circuit (PMIC). The PMIC supplies optimized power to each of the modules described above and later. Power module 150 may include a wireless power transmitting / receiving component electrically connected to the battery. The wireless power transmitting / receiving component may include multiple antenna radiators in the form of coils.

[0198] The electronic device 101 may also include an embedded module 160 and an external module 170. The embedded module 160 may include a sensor module 161, an antenna module 162, and a sound output module 163. The external module 170 may include a camera module 171, an optical module 172, and a communication module 173.

[0199] Sensor module 161 can detect input through the user's body or through the pen in the first input module 131, and generate an electrical signal or data value corresponding to the input. Sensor module 161 may include at least one of fingerprint sensor 161-1, input sensor 161-2, and digitizer 161-3.

[0200] The fingerprint sensor 161-1 can generate data values ​​corresponding to a user's fingerprint. The fingerprint sensor 161-1 may include one of an optical fingerprint sensor and a capacitive fingerprint sensor.

[0201] Input sensor 161-2 can generate data values ​​corresponding to coordinate information of input via the user's body or via a pen. Input sensor 161-2 generates capacitance changes caused by the input as data values. Input sensor 161-2 can detect input via a passive pen, or send data to / receive data from an active pen.

[0202] Input sensor 161-2 can measure biosignals (such as blood pressure, humidity, or body fat). For example, when a user touches a part of his body to the sensor layer or sensing panel for a period of time, input sensor 161-2 can detect biosignals based on changes in the electric field caused by that part of the body, wherein display module 140 can output the corresponding information.

[0203] The digitizer 161-3 can generate data values ​​corresponding to the coordinate information input by the pen. The digitizer 161-3 generates the electromagnetic change caused by this input as a data value. The digitizer 161-3 can detect input through a passive pen, or send data to / receive data from an active pen.

[0204] At least one of the fingerprint sensor 161-1, input sensor 161-2, and digitizer 161-3 can be formed as a sensor layer on / in the display panel 141 via a continuous process. The fingerprint sensor 161-1, input sensor 161-2, and digitizer 161-3 can be disposed on the upper side of the display panel 141. At least one of the fingerprint sensor 161-1, input sensor 161-2, and digitizer 161-3 (e.g., digitizer 161-3) can be disposed on the lower side of the display panel 141.

[0205] At least two of the fingerprint sensor 161-1, input sensor 161-2, and digitizer 161-3 can be integrated into the sensing panel during the process. When at least two of the fingerprint sensor 161-1, input sensor 161-2, and digitizer 161-3 are integrated into the sensing panel, the sensing panel can be positioned between the display panel 141 and a window disposed above the upper surface of the display panel 141. According to an embodiment, the sensing panel can be positioned on the window. The inventive concept is not limited to the location of the sensing panel.

[0206] At least one of the fingerprint sensor 161-1, the input sensor 161-2, and the digitizer 161-3 may be embedded in the display panel 141. For example, at least one of the fingerprint sensor 161-1, the input sensor 161-2, and the digitizer 161-3 may be formed simultaneously with the display panel 141 by a process of forming an element (e.g., a light-emitting element or a transistor) included in the display panel 141.

[0207] Furthermore, sensor module 161 can generate electrical signals or data values ​​corresponding to the internal or external state of electronic device 101. For example, sensor module 161 may also include a gesture sensor, gyroscope sensor, barometric pressure sensor, magnetic sensor, accelerometer, grip sensor, proximity sensor, color sensor, IR (infrared) sensor, biosensor, temperature sensor, humidity sensor, or illuminance sensor.

[0208] Antenna module 162 may include one or more antennas for transmitting or receiving signals or power to or from an external source. Communication module 173 may transmit or receive signals to or from an external electronic device via an antenna suitable for communication. The antenna pattern of antenna module 162 may be integrated with elements of display module 140 (e.g., display panel 141) or input sensor 161-2.

[0209] The sound output module 163 is a means for outputting sound signals to the outside of the electronic device 101. For example, the sound output module 163 may include a speaker for general purposes such as multimedia playback or transcription playback and a receiver specifically for receiving calls. The receiver may be integrated with the speaker or formed separately from the speaker. The sound output pattern (or pattern) of the sound output module 163 may be integrated with the display module 140.

[0210] Camera module 171 can capture still images and moving images. Camera module 171 may include one or more lenses, an image sensor, or an image signal processor. Camera module 171 may also include an infrared camera capable of determining the presence or absence of a user, the user's position, and the user's gaze.

[0211] The optical module 172 can provide light. The optical module 172 may include a light-emitting diode or a xenon lamp. The optical module 172 can operate in conjunction with the camera module 171 or independently.

[0212] Communication module 173 can support the establishment of a wired or wireless communication channel between electronic device 101 and external electronic device 102, and enable communication through the established communication channel. Communication module 173 may include one or both of the following: a wireless communication module such as a cellular communication module, a short-range wireless communication module, or a Global Navigation Satellite System (GNSS) communication module; and a wired communication module such as a Local Area Network (LAN) communication module or a Power Line Communication module. Communication module 173 can communicate with external electronic device 102 via short-range communication networks such as Bluetooth, Wi-Fi Direct, or Infrared Data Association (IrDA), or long-range communication networks such as cellular networks, the Internet, or computer networks (e.g., LANs or Wide Area Networks (WANs)). The various types of communication modules 173 described above can be implemented as a single chip or as separate chips.

[0213] The input module 130, sensor module 161, and camera module 171 can be used in conjunction with the processor 110 to control the operation of the display module 140.

[0214] The processor 110 outputs commands or data to the display module 140, sound output module 163, camera module 171, or optical module 172 based on the input data received from the input module 130. For example, the processor 110 can generate image data corresponding to the input data applied by a mouse or active pen and output the generated image data to the display module 140, or the processor 110 can generate command data corresponding to the input data and output the generated command data to the camera module 171 or optical module 172. When no input data is received from the input module 130 for a specific period of time, the processor 110 switches the operating mode of the electronic device 101 to a low-power mode or a sleep mode, thereby reducing the power consumption of the electronic device 101.

[0215] Processor 110 outputs commands or data to display module 140, sound output module 163, camera module 171, or optical module 172 based on sensing data received from sensor module 161. For example, processor 110 can compare authentication data applied by fingerprint sensor 161-1 with authentication data stored in memory 120, and then execute the application based on the comparison result. Processor 110 can execute commands or output corresponding image data to display module 140 based on sensing data sensed by input sensor 161-2 or digitizer 161-3. When sensor module 161 includes a temperature sensor, processor 110 can receive temperature data for measuring the temperature from sensor module 161, and can perform brightness correction on image data based on the temperature data.

[0216] Processor 110 can receive determined data from camera module 171 regarding the presence or absence of a user, the user's position, and the user's gaze. Processor 110 can further perform brightness correction on the image data based on the determined data. For example, processor 110, which determines the presence or absence of a user based on input from camera module 171, can display image data with brightness corrected by data conversion circuit 112-2 or gamma correction circuit 112-3 to display module 140.

[0217] Some of the aforementioned components can be interconnected to exchange signals (e.g., commands or data) via peripheral communication methods, such as buses, general purpose input / output (GPIO), serial peripheral interfaces (SPI), mobile industrial processor interfaces (MIPI), or ultrapath interconnect (UPI) links. Processor 110 can communicate with display module 140 through a pre-defined interface. For example, processor 110 can communicate with display module 140 using any of the aforementioned communication methods. The invention is not limited to the communication methods described above.

[0218] The electronic device 101 according to the various embodiments disclosed in this disclosure can be of various types. For example, the electronic device 101 may include at least one of portable communication devices (e.g., smartphones), computer devices, portable multimedia devices, portable medical devices, cameras, wearable devices, and home appliances. The electronic device 101 according to the embodiments of this disclosure is not limited to the devices described above.

[0219] For example, Figure 1 The display panel 100 can correspond to Figure 19 Display panel 141. For example, Figure 1 The drive controller 200 can correspond to Figure 19 The controller of the auxiliary processor 112. For example. Figure 1 The gate driver 300 and emitter driver 600 can correspond to Figure 19 The scan driver 142. For example. Figure 1 Data drive 500 can correspond to Figure 19 Data drive 143.

[0220] According to an embodiment of the display device, the display quality of the display panel can be enhanced.

[0221] The foregoing is illustrative of the inventive concept and should not be construed as limiting it. Although several embodiments of the inventive concept have been described, those skilled in the art will readily understand that many modifications are possible in the embodiments without departing from the novel teachings and advantages of the inventive concept in essence. Therefore, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims. In the claims, the device plus function clause is intended to cover structures described herein that perform the functions, and includes not only structural equivalents but also equivalent structures. Therefore, it will be understood that the foregoing is illustrative of the inventive concept and should not be construed as limiting to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The inventive concept is defined by the claims, and equivalents of the claims are included therein.

Claims

1. A display device, wherein, The display device includes: Display panel, including pixels; and A display panel driver includes a gate driver, a data driver, and a transmit driver, wherein the gate driver, the data driver, and the transmit driver are configured to generate a gate signal, a data voltage, and a transmit signal, respectively, and to provide the gate signal, the data voltage, and the transmit signal to the display panel. The display panel driver is configured as follows: Determine whether the driving cycle in the driving sequence is a write cycle or a hold cycle, wherein during the write cycle, the display panel is configured to receive the data voltage and write the data voltage to the pixel, and drive the light-emitting element of the pixel to emit light based on the received data voltage, and during the hold cycle, the display panel is configured to drive the light-emitting element of the pixel to emit light based on the data voltage stored in the pixel; When multiple hold cycles are repeated in the drive sequence, the hold cycle number of the current hold cycle is determined; and The transmission shutdown time is determined based on the number of hold cycles of the current hold cycle by adjusting at least one of the end point of the shutdown duration of the transmission signal and the start point of the shutdown duration of the transmission signal according to a set value.

2. The display device according to claim 1, wherein, When the number of hold cycles of the current hold cycle is equal to or greater than a predetermined hold cycle reference number, the display panel driver is configured to reduce the transmission shutdown time by advancing the end of the shutdown duration of the transmitted signal according to the set value and / or by delaying the start of the shutdown duration of the transmitted signal according to the set value.

3. The display device according to claim 2, wherein, When the number of hold periods of the current hold period is equal to or greater than the predetermined hold period reference number, the display panel driver is configured to increase the bias voltage applied to the drive switching element of the pixel to a value greater than the reference bias voltage.

4. The display device according to claim 1, wherein, When the set value is a first value, the display panel driver is configured to advance the end point of the off duration of the transmitted signal to reduce the transmission off time, and when the set value is a second value, the display panel driver is configured to delay the start point of the off duration of the transmitted signal to reduce the transmission off time.

5. The display device according to claim 4, wherein, When the set value is a third value, the display panel driver is configured to advance the end point of the off-duration of the transmitted signal and delay the start point of the off-duration of the transmitted signal to reduce the transmission off-duration time.

6. The display device according to claim 1, wherein, The display panel driver also includes: The signal generator is configured to generate a vertical start signal and a data enable signal; and A cycle counter is configured to determine whether the current drive cycle is the write cycle or the hold cycle based on the vertical start signal and the data enable signal, and the cycle counter is also configured to determine the number of hold cycles of the current hold cycle based on the vertical start signal and the data enable signal when multiple hold cycles are repeated in the drive sequence.

7. The display device according to claim 6, wherein, When the cycle counter repeatedly receives the pulse of the data enable signal after receiving the vertical start signal, the cycle counter determines the current drive cycle as the write cycle; and when the cycle counter does not receive the pulse of the data enable signal after receiving the vertical start signal, the cycle counter determines the current drive cycle as the hold cycle.

8. The display device according to claim 6, wherein, The display panel driver also includes a lookup table configured to store the transmit off time corresponding to the hold period number.

9. The display device according to claim 8, wherein, The display panel driver also includes a register storing an emit-off setting, and the display panel driver is configured to determine the emit-off time corresponding to the hold cycle number based on the emit-off setting.

10. The display device according to claim 8, wherein, The display panel driver further includes an emit-off-time output circuit configured to receive the hold period number of the current hold period from the period counter and output the emit-off time corresponding to the hold period number from the lookup table.

11. The display device according to claim 10, wherein, The display panel driver also includes: A position setter is configured to output the set value, which the transmit driver uses to determine whether to change the end point of the off-duration of the transmit signal or the start point of the off-duration of the transmit signal; and The transmit driver is configured to generate the transmit signal based on the transmit shutdown time received from the transmit shutdown time output circuit and the set value received from the position setter, and to provide the transmit signal to the pixel.

12. The display device according to claim 1, wherein, The pixels include: A drive switch element includes: a control electrode of the drive switch element connected to a first node, a first electrode of the drive switch element connected to a second node, and a second electrode of the drive switch element connected to a third node; A bias switching element includes: a control electrode of the bias switching element configured to receive a bias gate signal, a first electrode of the bias switching element configured to receive a bias voltage, and a second electrode of the bias switching element connected to the second node. The first transmitting switch element includes: a control electrode of the first transmitting switch element configured to receive the transmitting signal, a first electrode of the first transmitting switch element configured to receive a first power voltage, and a second electrode of the first transmitting switch element connected to the second node. The second transmitting switch element includes: a control electrode of the second transmitting switch element configured to receive the transmitting signal, a first electrode of the second transmitting switch element connected to the third node, and a second electrode of the second transmitting switch element connected to the first electrode of the light-emitting element. A data write switch element includes: a control electrode of the data write switch element configured to receive a data write gate signal, a first electrode of the data write switch element configured to receive the data voltage, and a second electrode of the data write switch element connected to the second node. A compensation switching element includes: a control electrode of the compensation switching element configured to receive a compensation gate signal, a first electrode of the compensation switching element connected to the first node, and a second electrode of the compensation switching element connected to the third node. A data initialization switching element includes: a control electrode configured to receive a data initialization gate signal, a first electrode configured to receive an initialization voltage, and a second electrode connected to the first node. A light-emitting element initialization switch element includes: a control electrode of the light-emitting element initialization switch element configured to receive the bias gate signal, a first electrode of the light-emitting element initialization switch element configured to receive the light-emitting element initialization voltage, and a second electrode of the light-emitting element initialization switch element connected to the first electrode of the light-emitting element.

13. The display device according to claim 12, wherein, The compensation switching element comprises two transistors connected in series with each other, and the data initialization switching element comprises two transistors connected in series with each other.

14. A method for driving a display device, wherein, The method includes: Determine whether the driving cycle in the driving sequence is a write cycle or a hold cycle, wherein during the write cycle, the display device is configured to generate a data voltage and write the data voltage to a pixel, and drive the light-emitting element of the pixel to emit light based on the received data voltage, and during the hold cycle, the display device is configured to drive the light-emitting element of the pixel to emit light based on the data voltage stored in the pixel; When multiple hold cycles are repeated in the drive sequence, the number of hold cycles for the current hold cycle is determined; The transmission shutdown time is determined based on the number of hold cycles of the current hold cycle by adjusting at least one of the end point of the shutdown duration of the transmitted signal and the start point of the shutdown duration of the transmitted signal according to a set value; and The transmission signal is generated based on the transmission shutdown time and the set value, and the transmission signal is provided to the pixel.

15. The method according to claim 14, wherein, When the number of hold periods of the current hold period is equal to or greater than the predetermined number of hold periods, the transmission shutdown time is reduced by advancing the end of the shutdown duration of the transmitted signal according to the set value and / or by delaying the start of the shutdown duration of the transmitted signal according to the set value.

16. The method according to claim 15, wherein, When the number of hold periods of the current hold period is equal to or greater than the predetermined hold period reference number, the bias voltage applied to the drive switching element of the pixel is increased to be greater than the reference bias voltage.

17. The method of claim 14, wherein, When the set value is a first value, the end point of the off duration of the transmitted signal is advanced to reduce the transmission off time, and when the set value is a second value, the start point of the off duration of the transmitted signal is delayed to reduce the transmission off time.

18. The method according to claim 17, wherein, When the set value is the third value, the end point of the off duration of the transmitted signal is brought forward and the start point of the off duration of the transmitted signal is delayed to reduce the transmission off time.

19. The method of claim 14, wherein, The current drive cycle is determined to be either the write cycle or the hold cycle based on the vertical start signal and the data enable signal, and when multiple hold cycles are repeated in the drive sequence, the number of hold cycles of the current hold cycle is determined based on the vertical start signal and the data enable signal.

20. An electronic device, wherein, The electronic device includes: The processor is configured to output input image data and input control signals; Display panel, including pixels; and A display panel driver includes a gate driver, a data driver, and an emitter driver, wherein the gate driver, the data driver, and the emitter driver are configured to generate a gate signal, a data voltage, and an emitter signal, respectively, and to provide the gate signal, the data voltage, and the emitter signal to the pixel. The display panel driver is configured as follows: Determine whether the driving cycle in the driving sequence is a write cycle or a hold cycle, wherein during the write cycle, the display panel is configured to receive the data voltage, write the data voltage to the pixel, and drive the light-emitting element of the pixel to emit light based on the received data voltage, and during the hold cycle, the display panel is configured not to receive the data voltage, and drive the light-emitting element of the pixel to emit light based on the data voltage stored in the pixel; When multiple hold cycles are repeated in the drive sequence, the hold cycle number of the current hold cycle is determined; and The transmission shutdown time is determined based on the number of hold cycles of the current hold cycle by adjusting at least one of the end point and the start point of the shutdown duration of the transmission signal according to a set value. The display panel driver is further configured to determine whether the drive cycle is the write cycle or the hold cycle based on the input control signal from the processor.

Images