Pixel driving circuit, display panel and display device
By introducing a coupling module and AC signal bias adjustment into the pixel driving circuit of OLED display products, the problems of uneven display and image retention caused by leakage current are solved, thereby improving display stability and reducing power consumption.
Patent Information
- Application Number
- CN202511886158.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-12
- Publication Date
- 2026-02-13
AI Technical Summary
In OLED display products, there is a leakage current problem in the pixel driving circuit, which leads to defects such as uneven display and image retention, and existing technologies are difficult to solve effectively.
A coupling module is introduced into the pixel driving circuit. The bias adjustment module, which is connected to the second node through the coupling module, blocks the DC signal and uses the AC signal for bias adjustment. The potential is adjusted by relying on the combination of the data signal and the bias adjustment signal, thereby enhancing the stability of the driving module.
It effectively mitigates the impact of leakage current on pixel driving circuits, enhances the stability and display effect of display products, and reduces static current and power consumption.
Smart Images
Figure CN121528154A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of display technology, and in particular to a pixel driving circuit, a display panel, and a display device. Background Technology
[0002] With the development of display technology, Organic Light-Emitting Diode (OLED) displays have become widely used in various fields due to their advantages such as high brightness, low power consumption, flexibility, and thinness. OLED displays include pixel driving circuits, which typically require specific control signals or voltages to adjust or compensate for the luminous performance of the pixels, thereby improving image quality such as uniformity and brightness stability. However, in some display products, undesirable leakage currents or interference can be introduced into the pixel driving circuits, affecting the retention characteristics of critical signals and potentially leading to defects such as uneven brightness and image retention on the display panel. Summary of the Invention
[0003] To address the aforementioned technical problems, this disclosure provides a pixel driving circuit, a display panel, and a display device to improve the leakage current problem of the pixel driving circuit, thereby improving the display effect of the display product.
[0004] In a first aspect, this disclosure provides a pixel driving circuit for driving a corresponding light-emitting unit, the pixel driving circuit comprising: The drive module has its control terminal connected to the first node, and its first and second terminals connected to the second and third nodes, respectively. The system includes a data writing module and a threshold compensation module. The data writing module is connected to the second node, and the threshold compensation module is connected between the first node and the third node. The bias adjustment module and the coupling module are provided, with the bias adjustment module connected to the second node via the coupling module.
[0005] Secondly, based on the same inventive concept, this disclosure provides a display panel including a pixel driving circuit.
[0006] Thirdly, based on the same inventive concept, this disclosure provides a display device, including a display panel.
[0007] The technical solution provided in this disclosure has the following advantages compared with the prior art: This disclosure provides a pixel driving circuit, a display panel, and a display device. The pixel driving circuit includes a driving module, a data writing module, a threshold compensation module, a bias adjustment module, and a coupling module. The bias adjustment module is connected to a second node through the coupling module. This disclosure sets a coupling module between the second node and the bias adjustment module. The coupling module can block DC signals, effectively blocking the leakage current path. This helps to reduce the impact of leakage current on other modules in the pixel driving circuit, improves the stability of the pixel driving circuit, and thus helps to improve or stabilize the display effect of the display product. Simultaneously, when adjusting the bias of the second node, the bias adjustment can be performed after the data signal is written to the second node, and then through the coupling module. In this case, the potential of the second node depends on the data signal and the bias adjustment signal. That is, the potential of the second node can be biased according to the data signal. Compared with the constant bias voltage in related technologies, this achieves bias adjustment based on the data signals of different light-emitting units, which helps to improve the effect of bias adjustment. Attached Figure Description
[0008] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.
[0009] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0010] Figure 1 The diagram shown is a schematic of a pixel driving circuit in related technologies; Figure 2 The diagram shown is a schematic of a pixel driving circuit provided in an embodiment of this disclosure; Figure 3 The diagram shown is another schematic diagram of the pixel driving circuit provided in an embodiment of this disclosure; Figure 4 The diagram shown is another schematic diagram of the pixel driving circuit provided in an embodiment of this disclosure; Figure 5 The diagram shown is yet another schematic of a pixel driving circuit provided in an embodiment of this disclosure; Figure 6 The figure shown is a timing diagram of a pixel driving circuit provided in an embodiment of this disclosure; Figure 7 The diagram shown is another timing schematic of the pixel driving circuit provided in an embodiment of this disclosure; Figure 8The diagram shown is another timing schematic of the pixel driving circuit provided in an embodiment of this disclosure; Figure 9 The diagram shown is yet another schematic of a pixel driving circuit provided in an embodiment of this disclosure; Figure 10 The diagram shown is another timing schematic of the pixel driving circuit provided in an embodiment of this disclosure; Figure 11 The diagram shown is another timing schematic of the pixel driving circuit provided in an embodiment of this disclosure; Figure 12 The diagram shown is another timing schematic of the pixel driving circuit provided in an embodiment of this disclosure; Figure 13 The diagram shown is yet another schematic of a pixel driving circuit provided in an embodiment of this disclosure; Figure 14 The diagram shown is yet another schematic of a pixel driving circuit provided in an embodiment of this disclosure; Figure 15 The diagram shown is another timing schematic of the pixel driving circuit provided in an embodiment of this disclosure; Figure 16 The image shown is a plan view of a display panel provided in an embodiment of this disclosure; Figure 17 The figure shown is a plan view of a display device provided in an embodiment of this disclosure. Detailed Implementation
[0011] To better understand the above-mentioned objectives, features, and advantages of this disclosure, the solutions disclosed herein will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.
[0012] Numerous specific details are set forth in the following description in order to provide a full understanding of this disclosure, but this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some, and not all, of the embodiments of this disclosure.
[0013] The inventors discovered in their research that in the pixel driving circuits of some display panels, especially in circuit structures that employ internal compensation (such as threshold voltage compensation), a bias voltage node is often set up for optical compensation or brightness adjustment. Figure 1 The diagram shown is a schematic of a pixel driving circuit in related technologies. Please refer to it. Figure 1The pixel driving circuit 000 includes multiple transistors M1' to M8', among which transistor M3' is the driving transistor. The control terminal, first terminal, and second terminal of the driving transistor M3' are connected to the first node N1', the second node N2', and the third node N3', respectively. The threshold voltage of the driving transistor M3' drifts slowly with usage time, temperature, and operating state. Even with the same input data voltage, small differences in threshold voltage between different pixels can lead to different brightness, causing uneven display or image retention in the display product. Transistor M8' is used to transmit a bias adjustment voltage signal DVH' to the second node N2' for bias adjustment, creating a larger voltage difference between the first node N1' and the second node N2', causing the driving transistor M3' to briefly enter a strong conduction or strong shutdown state. For example, inputting a high DC voltage to the second node N2' increases the voltage difference between the first node N1' and the second node N2', causing the driving transistor M3' to briefly enter a strong shutdown state, thereby accelerating the recovery or stabilization of the threshold voltage of the driving transistor M3'. However, in related technologies, transistor M8' is directly connected to the first terminal (second node) of driving transistor M3', causing current to continuously leak to other nodes, such as the gate of driving transistor M3', thus affecting the gate voltage of driving transistor M3' and consequently impacting the display effect. Furthermore, the bias adjustment voltage signal DVH' has a fixed value and cannot be adjusted according to the data voltage, resulting in poor bias adjustment performance.
[0014] In view of this, the present disclosure provides a pixel driving circuit, a display panel, and a display device to improve the leakage current problem of the pixel driving circuit, thereby improving the display effect of the display product.
[0015] Figure 2 The diagram shown is a schematic of a pixel driving circuit provided in an embodiment of this disclosure. Please refer to it. Figure 2 This disclosure provides a pixel driving circuit 100 for driving a corresponding light-emitting unit 110. The pixel driving circuit 100 includes: Drive module 10, the control terminal of drive module 10 is connected to the first node N1, and the first terminal and the second terminal are respectively connected to the second node N2 and the third node N3; The data writing module 20 is connected to the second node N2, and the threshold compensation module 30 is connected between the first node N1 and the third node N3. The bias adjustment module 40 and the coupling module 50 are connected to the second node N2 through the coupling module 50.
[0016] It should be noted that the accompanying drawings in this disclosure only show some modules of the pixel driving circuit 100 and do not represent the actual structure of the pixel driving circuit 100.
[0017] Specifically, this disclosure provides a pixel driving circuit 100, including a driving module 10, a data writing module 20, a threshold compensation module 30, a bias adjustment module 40, and a coupling module 50. The control terminal, first terminal, and second terminal of the driving module 10 are respectively connected to a first node N1, a second node N2, and a third node N3. Other modules in the pixel driving circuit 100 are directly or indirectly connected to their respective nodes and are turned on at corresponding stages to reset or adjust the voltage of each node of the driving module 10, or to transmit corresponding signals to the respective nodes.
[0018] In some optional implementations, the data writing module 20 is connected to the second node N2 and is turned on during the data writing phase to transmit data signals to the drive module 10. During the data writing phase, the threshold compensation module 30 is also turned on to capture the threshold voltage of the drive module 10, thereby performing threshold compensation on the drive module 10. The bias adjustment module 40 is coupled to the second node N2 and is used to adjust the voltage of the second node N2 to generate a more extreme voltage between the first node N1 and the second node N2 than the voltage received during normal operation. That is, by applying an extreme voltage between the control terminal and the first terminal of the drive module 10, an over-bias stress (OBS) is generated inside the drive module 10, thereby causing the drive module 10 to enter an over-biased state. That is, the drive module 10 briefly enters a strong on or strong off state, thereby accelerating the recovery or stabilization of the threshold voltage of the drive module 10. For example, a larger voltage than that during normal operation is transmitted to the second node N2, making the voltage difference between the control terminal and the first terminal of the drive module 10 larger, and the drive module 10 enters a strong shutdown state to help it perform threshold voltage compensation.
[0019] In related technologies, DC signals are directly transmitted to the second node N2. During the conduction phase of the bias adjustment module 40, as long as there is a voltage difference between the bias adjustment module 40 and the second node N2, charge will continuously flow to the second node N2, thereby generating leakage current. In this embodiment, the bias adjustment module 40 is connected to the second node N2 through a coupling module 50, which affects the voltage of the second node N2 through coupling. This disclosure sets a coupling module 50 between the second node N2 and the bias adjustment module 40. The coupling module 50 can block DC signals, which is equivalent to blocking the leakage current path. Therefore, it is beneficial to improve the impact of leakage current on other modules in the pixel driving circuit 100, improve the stability of the pixel driving circuit 100, and thus improve or stabilize the display effect of the display product. Meanwhile, when adjusting the bias of the second node N2, the bias can be adjusted through the coupling module 50 after the data signal DATA is written to the second node N2. At this time, the potential of the second node N2 depends on the data signal DATA and the bias adjustment signal DVH. In other words, the potential of the second node N2 can be adjusted according to the data signal DATA. Compared with the constant bias voltage in related technologies, the bias adjustment is realized according to the data signal DATA of different light-emitting units 110, which is beneficial to improving the effect of bias adjustment.
[0020] Figure 3 The diagram shown is another schematic diagram of the pixel driving circuit provided in this embodiment of the present disclosure. Please refer to [the diagram]. Figure 3 In one optional embodiment of this disclosure, the control terminal of the bias adjustment module 40 is connected to the first control signal terminal S1, the first terminal is connected to the bias adjustment signal terminal DVH, and the second terminal is connected to the coupling module 50; the bias adjustment signal terminal DVH transmits the bias adjustment signal DVH; the bias adjustment module 40 is turned on or off under the control of the first control signal terminal S1. When the bias adjustment module 40 is turned on, it transmits the bias adjustment signal DVH to the coupling module 50; the bias adjustment signal DVH transmitted by the bias adjustment signal terminal DVH is an AC signal.
[0021] It should be noted that the signal terminals and the signals they transmit are illustrated using the same reference numerals in this disclosure. For example, the bias adjustment signal terminal DVH and the bias adjustment signal DVH are illustrated using the same reference numerals. Other signal terminals and corresponding signals are also illustrated in the same way, and repeated details will not be described again.
[0022] Specifically, in the pixel driving circuit 100 provided in this embodiment, the bias adjustment module 40 operates under the control of the first control signal terminal S1, and is turned on during a corresponding time period to adjust the potential of the second node N2. The bias adjustment signal DVH transmitted by the bias adjustment signal terminal DVH is an AC signal. The coupling module 50 transmits voltage changes but does not transmit DC components. When the bias adjustment module 40 is turned on and the bias adjustment signal DVH changes, the coupling module 50 transmits the change in the bias adjustment signal DVH to the second node N2, and the change in the bias adjustment signal DVH affects the potential of the second node N2. In this embodiment, the bias adjustment signal DVH is set as an AC signal, and the change in the bias adjustment signal DVH at the rising or falling edge is coupled and written to the second node N2 through the coupling module 50, thereby affecting the voltage of the second node N2. The aforementioned bias adjustment signal DVH transition effect is instantaneous, not continuous. Compared to the continuous writing of a constant DC signal for a period of time in related technologies, this disclosure is beneficial for cutting off the DC path, improving leakage current, and thus reducing the impact of leakage current on other modules in the pixel driving circuit 100, improving the stability of the pixel driving circuit 100, and therefore improving or stabilizing the display effect of the display product. Furthermore, the bias adjustment effect depends on the transition amplitude of the bias adjustment signal DVH. For example, if the bias adjustment signal DVH transitions from -1V to 1V with an amplitude of 2V, the coupling module 50 transmits the 2V change generated by the bias adjustment signal DVH transition to the second node N2. Compared to the transmission of DC voltage to the second node N2 in related technologies, the reference potential of the bias adjustment signal DVH in this disclosure can be set to a lower value. This setting also helps to reduce the static current and power consumption of the display product.
[0023] Figure 4 The diagram shown is another schematic representation of the pixel driving circuit provided in this embodiment of the present disclosure. Please refer to [the diagram]. Figure 4Optionally, the coupling module 50 includes a first capacitor C1. The first plate of the first capacitor C1 is connected to the second terminal of the bias adjustment module 40, and the second plate of the first capacitor C1 is connected to the second node N2. Specifically, in this embodiment of the present disclosure, the coupling module 50 may select the first capacitor C1 as the coupling device, and the first capacitor C1 is connected between the second node N2 and the bias adjustment module 40. Based on the characteristic of the first capacitor C1 to block DC and pass AC, when the bias adjustment module 40 is turned on and the bias adjustment signal DVH changes, the first capacitor C1 can couple the change in the bias adjustment signal DVH to the second node N2 to realize the bias adjustment of the drive module 10, thereby assisting in the recovery or stabilization of the threshold voltage of the drive module 10. In this embodiment, the change in the bias adjustment signal DVH is coupled to the second node N2 via the first capacitor C1. This effectively blocks the DC path and prevents continuous leakage from the bias adjustment module 40 to the second node N2, thereby reducing the impact of leakage on other modules in the pixel driving circuit 100 and improving the stability of the pixel driving circuit 100. Consequently, this is beneficial for improving or stabilizing the display effect of the display product. Furthermore, when adjusting the bias of the second node N2, the bias adjustment can be performed after the data signal DATA is written to the second node N2, via the coupling module 50. In this case, the potential of the second node N2 depends on the data signal DATA and the bias adjustment signal DVH. That is, the potential of the second node N2 can be adjusted based on the data signal DATA. Compared to the constant bias voltage in related technologies, this achieves bias adjustment based on the data signal DATA of different pixels, which is beneficial for improving the effect of bias adjustment. Furthermore, the bias adjustment effect depends on the jump amplitude of the bias adjustment signal DVH. Compared with the transmission of DC voltage to the second node N2 in related technologies, the reference potential of the bias adjustment signal DVH in this disclosure can be set to a lower value. Such a setting is also beneficial to reduce the static current and power consumption of the display product.
[0024] Please continue to refer to this. Figure 4 Optionally, the capacitance value of the first capacitor C1 is C_C1, and the capacitance value of the parasitic capacitance of the second node N2 is C_N2, where C_C1 > 50%C_N2.
[0025] Specifically, the pixel driving circuit 100 includes multiple modules connected by metal lines. These modules and metal lines generate parasitic capacitance at some nodes. For example, for the second node N2, its parasitic capacitance is affected not only by the coupling of the bias adjustment module 40 but also by interference from signal jumps in surrounding modules or metal lines. The jump amplitude of the bias adjustment signal DVH is limited. If the capacitance value C_C1 of the first capacitor C1 accounts for a small proportion of the parasitic capacitance value C_N2 of the second node N2, the coupling effect of the coupling module 50 has a small impact on the potential of the second node N2, resulting in a poor bias adjustment effect on the driving module 10. If the capacitance value C_C1 of the first capacitor C1 is also small, the change in the bias adjustment signal DVH may be difficult to couple to the second node N2. Therefore, this disclosure sets the capacitance value of the first capacitor C1, C_C1 > 50%C_N2. That is, the capacitance value of the first capacitor C1 is relatively large, and its proportion in the parasitic capacitance of the second node N2 is also relatively large. With this setting, the capacitance value of the first capacitor C1 has a greater impact on the second node N2. When the bias adjustment signal DVH changes, its change more easily affects the potential of the second node N2, which is beneficial for improving the effect and stability of the bias adjustment, and further helps the drive module 10 perform threshold voltage compensation. At the same time, a sufficiently large capacitance value of the first capacitor C1 also facilitates a more complete coupling of the bias adjustment signal DVH to the second node N2. This disclosure provides an optional implementation where the capacitance value of the first capacitor C1 is C_C1 = 60%C_N2; another optional implementation where the capacitance value of the first capacitor C1 is C_C1 = 55%C_N2; and yet another optional implementation where the capacitance value of the first capacitor C1 is C_C1 = 65%C_N2.
[0026] Please continue to refer to this. Figure 4 Optionally, the capacitance value of the first capacitor C1 is C_C1, where C_C1 > 2fF.
[0027] Specifically, when the capacitance value C_C1 of the first capacitor C1 is ≤ 2fF, the capacitance value of the first capacitor C1 is relatively small. On the one hand, the small capacitance of the first capacitor C1 is not conducive to the complete coupling of the change in the bias adjustment signal DVH to the second node N2. On the other hand, the capacitance value of the first capacitor C1 accounts for a small proportion of the capacitance value of the parasitic capacitance of the second node N2. Consequently, the first capacitor C1 has a small influence on the capacitance value of the parasitic capacitance of the second node N2, making it difficult to affect the potential of the second node N2, which is not conducive to bias adjustment. Therefore, in this embodiment, the capacitance value C_C1 of the first capacitor C1 is set to > 2fF. With this setting, the capacitance value of the first capacitor C1 is sufficient, which is conducive to the more complete coupling of the bias adjustment signal DVH to the second node N2. At the same time, the first capacitor C1 has a greater influence on the capacitance value of the parasitic capacitance of the second node N2. When the bias adjustment signal DVH changes, its change is more likely to affect the potential of the second node N2, which is conducive to improving the effect and stability of bias adjustment, and further conducive to helping the drive module 10 perform threshold voltage compensation. This disclosure provides an optional embodiment in which the capacitance value of the first capacitor C1 is C_C1=2fF; another optional embodiment in which the capacitance value of the first capacitor C1 is C_C1=3fF; and yet another optional embodiment in which the capacitance value of the first capacitor C1 is C_C1=4fF.
[0028] Please refer to Figure 3 Optionally, the first control signal terminal S1 transmits a first control signal S1, which includes at least one enable period within one frame of operation. Specifically, the bias adjustment module 40 is turned on or off under the control of the first control signal S1 transmitted from the first control signal terminal S1. When in the enable period of the first control signal S1, the bias adjustment module 40 is turned on and can couple voltage to the second node N2 to achieve bias adjustment of the drive module 10. This disclosure provides an optional implementation where the first control signal S1 includes one enable period within one frame of operation, i.e., bias adjustment is performed once within one frame of operation. This disclosure provides another optional implementation where the first control signal S1 includes two enable periods within one frame of operation, i.e., bias adjustment is performed twice within one frame of operation. It should be noted that this disclosure is only illustrative using the above embodiments as examples and is not limited thereto. The number of bias adjustments performed within one frame of operation can be set according to actual needs.
[0029] Figure 5 The diagram shown is another schematic representation of the pixel driving circuit provided in this embodiment of the present disclosure. Please refer to [the diagram]. Figure 5Optionally, the control terminal of the data writing module 20 is connected to the second control signal terminal S2; the data writing module 20 is turned on or off under the control of the second control signal terminal S2. When the data writing module 20 is turned on, it transmits the data signal DATA to the second node N2. Figure 6 The diagram shown is a timing schematic of a pixel driving circuit provided in an embodiment of this disclosure. Please refer to it. Figure 5 and Figure 6 The enable period of the first control signal S1 includes the first enable period SC1; within one frame of operation, the transition time of the bias adjustment signal DVH is located within the first enable period SC1 of the first control signal S1 and after the enable period of the second control signal S2.
[0030] Specifically, the pixel driving circuit 100 includes a data writing module 20 and a bias adjustment module 40. The bias adjustment module 40 is turned on or off under the control of a first control signal S1 transmitted from the first control signal terminal S1. The enable period of the first control signal S1 includes a first enable period SC1. During the first enable period SC1, the bias adjustment module 40 is turned on, and the bias adjustment signal terminal DVH is connected to the coupling module 50. The data writing module 20 is turned on or off under the control of a second control signal S2 transmitted from the second control signal terminal S2. During the enable period of the second control signal S2, the data writing module 20 is turned on. An optional implementation provided in this disclosure is that within one frame of operation, the transition time of the bias adjustment signal DVH is within the first enable period SC1 of the first control signal S1 and after the enable period of the second control signal S2. In other words, the transition time of the bias adjustment signal DVH is when the bias adjustment module 40 is turned on, and after the data signal DATA is written to the second node N2. With this configuration, the second node N2 has already been written with the data signal DATA before bias adjustment. When bias adjustment is performed after the data is written, the voltage of the second node N2 depends on the changes in the currently written data signal DATA and the bias adjustment signal DVH. The transition of the bias adjustment signal DVH is coupled to the second node N2, affecting its potential. This increases the potential difference between the control terminal (first node N1) and the first terminal (second node N2) of the drive module 10, causing the drive module 10 to be in a strongly on or strongly off state, thereby improving the compensation for the threshold voltage of the drive module 10. Simultaneously, this embodiment of the present disclosure can achieve bias adjustment of the potential of the second node N2 based on the data signal DATA. Compared with the constant bias voltage in related technologies, it achieves bias adjustment based on the data signal DATA of different pixels, which is beneficial to improving the effect of bias adjustment.
[0031] Figure 7 The diagram shown is another timing schematic of the pixel driving circuit provided in an embodiment of this disclosure. Figure 8The diagram shown is another timing schematic of the pixel driving circuit provided in this embodiment of the present disclosure. Please refer to it. Figure 5~Figure 8 In one optional embodiment of this disclosure, the enable period of the second control signal S2 overlaps with the first enable period SC1 of the first control signal S1. That is, the data writing module 20 and the bias adjustment module 40 have a period of simultaneous conduction. With this configuration, the enable period of the second control signal S2 can write the data signal DATA to the second node N2. Before the change in the bias adjustment signal DVH is coupled to the second node N2, the second node N2 has an initial potential, which helps to avoid the second node N2 from floating or being interfered with by residual charge from the previous frame. Therefore, it is more beneficial to improve the bias adjustment effect and the consistency of bias adjustment. Figure 6~Figure 8 The illustration shows three scenarios where the enable period of the second control signal S2 overlaps with the first enable period SC1 of the first control signal S1. The start time of the first enable period SC1 of the first control signal S1 can be earlier than, synchronized with, or later than the start time of the enable period of the second control signal S2. This application does not impose specific limitations and the choice can be made according to actual needs. The overlap between the enable period of the second control signal S2 and the first enable period SC1 of the first control signal S1 shown in this disclosure is merely illustrative and not intended to be limiting.
[0032] It should be noted that this disclosure improves leakage current by blocking the DC path through the coupling module 50. By coupling the change in the bias adjustment signal DVH to the second node N2, the voltage difference between the first node N1 and the second node N2 is increased, causing the drive module 10 to enter a strong conduction or strong shutdown state, thereby achieving bias adjustment of the drive module 10. The coupling module 50 needs to acquire the change in the bias adjustment signal DVH; therefore, the transition time of the bias adjustment signal DVH needs to be within the enable period of the first control signal terminal S1. To ensure that the first capacitor C1 fully acquires the change in the bias adjustment signal DVH, the bias adjustment module 40 can be turned on earlier. Please refer to... Figure 6 In one optional embodiment of this disclosure, within a frame of operation, the start time of the first enable period SC1 of the first control signal S1 is earlier than the start time of the enable period corresponding to the second control signal S2. Please refer to... Figure 7In another optional embodiment of this disclosure, within one frame of operation, the start time of the first enable period SC1 of the first control signal terminal S1 is synchronized with the start time of the enable period corresponding to the second control signal S2. That is, the start time of the first enable period SC1 of the first control signal S1 is earlier or synchronized with the start time of the enable period of the second control signal S2. After the data signal DATA is written to the second node N2, the bias adjustment signal DVH changes again. With this setting, the second node N2 writes the data signal DATA first. Based on the potential of the data signal DATA, the first capacitor C1 can fully obtain the change in the bias adjustment signal DVH and couple it to the second node N2, further raising the potential of the second node N2. This is more conducive to improving the bias adjustment of the drive module 10.
[0033] Figure 9 The diagram shown is yet another schematic representation of a pixel driving circuit provided in an embodiment of this disclosure. Figure 10 The diagram shown is another timing schematic of the pixel driving circuit provided in this embodiment of the present disclosure. Please refer to it. Figure 9 and Figure 10 In one optional embodiment of this disclosure, the pixel driving circuit 100 further includes an initialization module 60, the control terminal of which is connected to an initialization control signal terminal SP1. The initialization module 60 is turned on or off under the control of the initialization control signal terminal SP1. When the initialization module 60 is turned on, it transmits a reset signal VREF to the first node N1. Within one frame of operation, the enable period of the first control signal S1 also includes a second enable period SC2, which is located before the first enable period SC1. The enable period of the initialization control signal SP1 is located within the second enable period SC2 of the first control signal S1.
[0034] Specifically, the pixel driving circuit 100 module further includes an initialization module 60, which is used to reset the first node N1, that is, to reset the control terminal of the driving module 10. In this embodiment, within one frame of operation, the enable period of the first control signal S1 includes a first enable period SC1 and a second enable period SC2, and bias adjustment is performed in the first enable period SC1 and the second enable period SC2, respectively. The second enable period SC2 covers the enable period of the initialization control signal SP1, that is, bias adjustment is performed simultaneously with the reset of the first node N1. The first enable period SC1 overlaps with the enable period of the second control signal S2, and the transition time of the bias adjustment signal DVH is located after the enable period of the second control signal S2, that is, bias adjustment is performed after the data signal DATA is written. During the first bias adjustment (second enable period SC2), the control terminal (first node N1) of the drive module 10 is reset. The second terminal (second node N2) of the drive module 10 maintains the potential of the first power signal PVDD due to the influence of the previous frame display. Based on this, the change in the bias adjustment signal DVH is coupled to the second node N2 through the coupling module 50, increasing the voltage difference between the first node N1 and the second node N2, thus adjusting the bias of the drive module 10 to improve threshold voltage compensation. During the second bias adjustment (first enable period SC1), the second node N2 first writes the data signal DATA, and then the change in the bias adjustment signal DVH is coupled to the second node N2 through the coupling module 50, increasing the voltage difference between the first node N1 and the second node N2, thus adjusting the bias of the drive module 10 to improve threshold voltage compensation. Performing two bias adjustments within one frame's working time is more conducive to improving the bias adjustment effect, thereby enhancing the stability of the pixel drive circuit 100 and improving the display effect of the display product.
[0035] Figure 11 The diagram shown is another timing schematic of the pixel driving circuit provided in this embodiment of the present disclosure. Please refer to it. Figure 9~Figure 11 When resetting the first node N1 and simultaneously performing bias adjustment, the start time of the second enable period SC2 of the first control signal S1 can be earlier than or synchronized with the start time of the enable period corresponding to the initialization control signal SP1. This setting helps the coupling module 50 obtain the transition time of the bias adjustment signal DVH, thereby coupling the change in the bias adjustment signal DVH to the second node N2 to improve the bias adjustment effect. Furthermore, the early activation of the bias adjustment module 40 facilitates earlier completion of bias adjustment, shortening the non-light-emitting time and freeing up more space for the light-emitting stage. This, in turn, helps to increase the maximum brightness or refresh rate, further improving the display effect of the display product. Please refer to [reference needed]. Figure 10In one optional embodiment of this disclosure, within one frame of operation, the start time of the second enable period SC2 of the first control signal terminal S1 is earlier than the start time of the enable period corresponding to the initialization control signal SP1. Please refer to... Figure 11 In another optional embodiment of this disclosure, during a frame of operation, the start time of the first enable period SC1 of the first control signal S1 is synchronized with the start time of the enable period corresponding to the initialization control signal SP1.
[0036] It should be noted that during the enable period of the initialization control signal SP1, the initialization module 60 is turned on to reset the first node N1. After resetting the first node N1, bias adjustment is performed. At this time, the voltage of the first node N1 is initialized, which helps to increase the voltage difference between the first node N1 and the second node N2, thereby improving the bias adjustment effect. Therefore, this disclosure provides an optional embodiment in which the transition time of the bias adjustment signal DVH is located within the enable period of the initialization control signal within one frame of operation. However, this disclosure is not limited to this. In some other optional embodiments, the transition time of the bias adjustment signal DVH is located within the first enable period SC1 of the first control signal S1 and after the enable period of the initialization control signal SP1.
[0037] Figure 12 The diagram shown is another timing schematic of the pixel driving circuit provided in this embodiment of the present disclosure. Please refer to it. Figure 9 and Figure 12 In one optional embodiment of this disclosure, the pixel driving circuit 100 further includes an initialization module 60, the control terminal of which is connected to an initialization control signal terminal SP1. The initialization module 60 is turned on or off under the control of the initialization control signal terminal SP1. When the initialization module 60 is turned on, it transmits a reset signal VREF to the first node N1. The enable period of the first control signal S1 includes a second enable period SC2; the enable period of the initialization control signal SP1 is located within the second enable period SC2 of the first control signal S1.
[0038] Specifically, in this embodiment, a bias adjustment is performed once within one frame of operation, and the bias adjustment is synchronized with the initialization of the first node N1. During the enable period of the initialization control signal SP1, the initialization module 60 is turned on to reset the control terminal (first node N1) of the drive module 10. The second terminal (second node N2) of the drive module 10 maintains the potential of the first power signal PVDD under the influence of the previous frame display. Based on this, the change in the bias adjustment signal DVH is coupled to the second node N2 through the coupling module 50, thereby increasing the voltage difference between the first node N1 and the second node N2, and performing bias adjustment on the drive module 10 to improve the compensation for the threshold voltage.
[0039] Figure 13 The diagram shown is another schematic representation of the pixel driving circuit provided in this embodiment of the present disclosure. Please refer to [the diagram]. Figure 13 In one optional embodiment of this disclosure, the pixel driving circuit 100 further includes a first light-emitting control module 70, a second light-emitting control module 80, a reset module 90, and a storage module 52. The control terminal of the first light-emitting control module 70 is connected to the light-emitting control signal terminal EMIT, its first terminal is connected to the first power signal terminal PVDD, and its second terminal is connected to the second node N2. The control terminal of the second light-emitting control module 80 is connected to the light-emitting control signal terminal EMIT, its first terminal is connected to the third node N3, and its second terminal is connected to the light-emitting unit 110. The control terminal of the reset module 90 is connected to the first control signal terminal S1, its first terminal is connected to the reset signal terminal VREF, and its second terminal is connected to the anode of the light-emitting unit 110. The cathode of the light-emitting unit 110 is connected to the second power signal terminal PVEE. The storage module 52 is connected to the first node N1 and the first terminal of the first light-emitting control module 70.
[0040] Specifically, in this embodiment, the pixel driving circuit 100 includes a driving module 10, an initialization module 60, a storage module 52, a data writing module 20, a threshold compensation module 30, a bias adjustment module 40, a coupling module 50, a first light emission control module 70, a second light emission control module 80, and a reset module 90. The initialization module 60 is connected to the first node N1 and is used to transmit a reset signal VREF to the control terminal (first node N1) of the driving module 10 under the control of the initialization control signal SP1, thereby resetting the control terminal (first node N1) of the driving module 10. The storage module 52 is connected between the first node N1 and the first terminal of the first light emission control module 70, and is used to maintain the potential of the control terminal of the driving module 10. The data writing module 20 is connected to the second node N2 and is used to write the data signal DATA under the control of the second control signal S2. The threshold compensation module 30 is connected between the first node N1 and the third node N3, and is used to perform threshold compensation on the driving module 10 under the control of the second control signal S2. The bias adjustment module 40 is connected to the second node N2 via the coupling module 50, and is used to adjust the bias of the drive module 10 under the control of the first control signal terminal S1 to improve the compensation of the threshold voltage. The first light-emitting control module 70 is connected between the first power supply signal terminal PVDD and the second node N2, and the second light-emitting control module 80 is connected between the third node N3 and the light-emitting unit 110. The first light-emitting control module 70 and the second light-emitting control module 80 are used to be turned on or off under the control of the light-emitting control signal terminal EMIT. The reset module 90 is connected to the anode of the light-emitting unit 110, and is used to reset the anode potential of the light-emitting unit 110 under the control of the first control signal terminal S1.
[0041] Figure 14 The diagram shown is another schematic representation of the pixel driving circuit provided in this embodiment of the present disclosure. Please refer to [the diagram]. Figure 14 This disclosure provides an optional implementation in which the driving module 10 includes a driving transistor M3, the initialization module 60 includes an initialization transistor M5, the storage module 52 includes a storage capacitor Cst, the data writing module 20 includes a data writing transistor M2, the threshold compensation module 30 includes a threshold compensation transistor M4, the bias adjustment module 40 includes a bias adjustment transistor M8, the coupling module 50 includes a first capacitor C1, the first light emission control module 70 includes a first light emission control transistor M1, the second light emission control module 80 includes a second light emission control transistor M6, and the reset module 90 includes an anode reset transistor M7. Figure 15 The diagram shown is another timing schematic of the pixel driving circuit provided in this embodiment of the present disclosure. Please refer to it. Figure 14 and Figure 15 The specific workflow of the pixel driving circuit 100 includes an initialization phase t1, a data writing phase t2, and a light-emitting phase t3. In the initialization phase t1, the initialization transistor M5 is turned on under the control of the initialization control signal SP1. The initialization transistor M5 transmits the reset signal VREF to the control terminal of the driving transistor M3 for initialization, thereby eliminating residual charge from the previous frame and improving the display effect of the display product. In the data writing phase t2, the initialization transistor M5 is turned off, and the data writing transistor M2 and the threshold compensation transistor M4 are turned on under the control of the second control signal S2. The data signal DATA is written to the data writing transistor M2. The threshold compensation transistor M4 is connected between the gate and the second electrode of the driving transistor M3, and can capture the threshold voltage of the driving transistor M3 to its gate to achieve threshold voltage compensation. In the light-emitting phase t3, both the data writing transistor M2 and the threshold compensation transistor M4 are turned off, and the first light-emitting control transistor M1, the second light-emitting control transistor M6, and the driving transistor M3 are all turned on. The driving current is transmitted to the first electrode of the light-emitting unit 110, and the light-emitting unit 110 emits light. The bias adjustment transistor M8 is turned on or off under the control of the first control signal terminal S1. During the bias adjustment phase t0, the bias adjustment transistor M8 is turned on to adjust the bias of the driving transistor M3. The bias adjustment phase t0 overlaps with the data writing phase t2 and / or the initialization phase t1. The anode reset transistor M7 is also turned on or off under the control of the first control signal terminal S1. When the anode reset transistor M7 is turned on, the anode of the light-emitting unit 110 is reset.
[0042] It should be noted that the accompanying drawings in this disclosure are only illustrative of the pixel driving circuit 100 using P-type transistors as an example, and are not intended to limit the scope. In some other embodiments, the transistors in the pixel driving circuit 100 may also be N-type transistors. For example, the threshold compensation transistor M4 and the initialization transistor M5 may be N-type transistors. When the threshold compensation transistor M4 and the initialization transistor M5 are N-type transistors, it is also beneficial to improve the leakage current of the pixel driving circuit. When the driving transistor M3 is a P-type transistor, the transition time of the bias adjustment signal DVH refers to the rising edge of the bias adjustment signal DVH; when the driving transistor M3 is an N-type transistor, the transition time of the bias adjustment signal DVH refers to the falling edge of the bias adjustment signal DVH.
[0043] Based on the same inventive concept, this disclosure provides a display panel. Figure 16 The image shown is a plan view of a display panel provided in an embodiment of this disclosure. Please refer to... Figure 16 The display panel 200 includes a pixel driving circuit 100, which is any pixel driving circuit 100 provided in the embodiments of this disclosure.
[0044] It should be noted that this disclosure Figure 16 The display panel 200 shown is for illustrative purposes only and does not represent the actual structure of the display panel 200. For example, the accompanying drawings of this disclosure only illustrate a rectangular display panel as an example, and are not limited thereto. In some other alternative embodiments, the display panel 200 can also be a circle, a rounded rectangle, or any other feasible shape. For example, Figure 16 The pixel driving circuit 100 is only shown as a partial rectangle and does not represent the actual number and structure of the pixel driving circuit 100. For specific embodiments of the display panel 200, please refer to the specific embodiments of the pixel driving circuit 100 provided in this disclosure; details that are repeated will not be repeated.
[0045] Based on the same inventive concept, this disclosure provides a display device. Figure 17 The diagram shown is a plan view of a display device provided in an embodiment of this disclosure. Please refer to it. Figure 17 The display device 300 includes a display panel 200.
[0046] It should be noted that the display device 300 provided in this disclosure can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, or navigator.
[0047] As can be seen from the above embodiments, the pixel driving circuit, display panel, and display device provided in this disclosure achieve at least the following beneficial effects: This disclosure provides a pixel driving circuit, a display panel, and a display device. The pixel driving circuit includes a driving module, a data writing module, a threshold compensation module, a bias adjustment module, and a coupling module. The bias adjustment module is connected to a second node through the coupling module. This disclosure sets a coupling module between the second node and the bias adjustment module. The coupling module can block DC signals, effectively blocking the leakage current path. This helps to reduce the impact of leakage current on other modules in the pixel driving circuit, improves the stability of the pixel driving circuit, and thus helps to improve or stabilize the display effect of the display product. Simultaneously, when adjusting the bias of the second node, the bias adjustment can be performed after the data signal is written to the second node, and then through the coupling module. In this case, the potential of the second node depends on the data signal and the bias adjustment signal. That is, the potential of the second node can be biased according to the data signal. Compared with the constant bias voltage in related technologies, this achieves bias adjustment based on the data signals of different light-emitting units, which helps to improve the effect of bias adjustment.
[0048] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0049] The above description is merely a specific embodiment of this disclosure, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A pixel driving circuit, characterized in that, The pixel driving circuit, used to drive the corresponding light-emitting unit, includes: The drive module has its control terminal connected to the first node, and its first and second terminals connected to the second and third nodes, respectively. The system includes a data writing module and a threshold compensation module. The data writing module is connected to the second node, and the threshold compensation module is connected between the first node and the third node. The bias adjustment module and the coupling module are provided, with the bias adjustment module connected to the second node via the coupling module.
2. The pixel driving circuit according to claim 1, characterized in that, The control terminal of the bias adjustment module is connected to the first control signal terminal, the first terminal is connected to the bias adjustment signal terminal, and the second terminal is connected to the coupling module; the bias adjustment signal terminal transmits the bias adjustment signal. The bias adjustment module is turned on or off under the control of the first control signal terminal. When the bias adjustment module is turned on, it transmits the bias adjustment signal to the coupling module. The bias adjustment signal transmitted at the bias adjustment signal terminal is an AC signal.
3. The pixel driving circuit according to claim 2, characterized in that, The coupling module includes a first capacitor, the first plate of which is connected to the second end of the bias adjustment module, and the second plate of which is connected to the second node.
4. The pixel driving circuit according to claim 3, characterized in that, The capacitance value of the first capacitor is C_C1, and the capacitance value of the parasitic capacitance of the second node is C_N2, where C_C1 > 50%C_N2.
5. The pixel driving circuit according to claim 3, characterized in that, The capacitance value of the first capacitor is C_C1, where C_C1 > 2fF.
6. The pixel driving circuit according to claim 2, characterized in that, The first control signal terminal transmits a first control signal, and within one frame of working time, the first control signal includes at least one enable period.
7. The pixel driving circuit according to claim 6, characterized in that, The control terminal of the data writing module is connected to the second control signal terminal; the data writing module is turned on or off under the control of the second control signal terminal, and when the data writing module is turned on, it transmits data signals to the second node. The enable period of the first control signal includes a first enable period; within one frame of operation, the transition time of the bias adjustment signal is located within the first enable period of the first control signal and after the enable period of the second control signal.
8. The pixel driving circuit according to claim 7, characterized in that, The enable period of the second control signal overlaps with the first enable period of the first control signal.
9. The pixel driving circuit according to claim 7, characterized in that, Within one frame of operation, the start time of the first enable period of the first control signal terminal is earlier than the start time of the enable period corresponding to the second control signal; or, Within one frame of operation, the start time of the first enable period of the first control signal terminal is synchronized with the start time of the enable period corresponding to the second control signal.
10. The pixel driving circuit according to claim 7, characterized in that, It also includes an initialization module, the control terminal of which is connected to an initialization control signal terminal; the initialization module is turned on or off under the control of the initialization control signal terminal, and when the initialization module is turned on, it transmits a reset signal to the first node; Within one frame of operation, the enable period of the first control signal also includes a second enable period, which is located before the first enable period; the enable period of the initialization control signal is located within the second enable period of the first control signal.
11. The pixel driving circuit according to claim 10, characterized in that, Within one frame of operation, the start time of the second enable period at the first control signal terminal is earlier than the start time of the enable period corresponding to the initialization control signal; or, Within one frame of operation, the start time of the first enable period of the first control signal terminal is synchronized with the start time of the enable period corresponding to the initialization control signal.
12. The pixel driving circuit according to claim 10, characterized in that, Within one frame of operation, the transition time of the bias adjustment signal falls within the enable period of the initialization control signal.
13. The pixel driving circuit according to claim 6, characterized in that, It also includes an initialization module, the control terminal of which is connected to an initialization control signal terminal; the initialization module is turned on or off under the control of the initialization control signal terminal, and when the initialization module is turned on, it transmits a reset signal to the first node; The enable period of the first control signal includes the second enable period; the enable period of the initialization control signal is located within the second enable period of the first control signal.
14. The pixel driving circuit according to claim 1, characterized in that, It also includes a first light-emitting control module, a second light-emitting control module, a reset module, and a storage module; The control terminal of the first light-emitting control module is connected to the light-emitting control signal terminal, the first terminal is connected to the first power signal terminal, and the second terminal is connected to the second node; The control terminal of the second light-emitting control module is connected to the light-emitting control signal terminal, the first terminal is connected to the third node, and the second terminal is connected to the light-emitting unit; The control terminal of the reset module is connected to the first control signal terminal, the first terminal is connected to the reset signal terminal, the second terminal is connected to the anode of the light-emitting unit, and the cathode of the light-emitting unit is connected to the second power signal terminal. The storage module is connected to the first node and the first end of the first light-emitting control module.
15. A display panel, characterized in that, Includes the pixel driving circuit according to any one of claims 1 to 14.
16. A display device, characterized in that, Includes the display panel as described in claim 15.