Display device and driving method thereof

Abstract

A display device and a driving method thereof are disclosed. The display device includes: a display panel including an active area having a plurality of pixels; a source driver configured to divide a gamma reference voltage to generate a data voltage for implementing an image gray level, and to supply the data voltage to a pixel of the plurality of pixels of the active area; and a reset voltage control circuit configured to reset a reset voltage at a scene change time at which an image gradation change amount with respect to at least a partial region of the active region is equal to or greater than a reference value, an anode reset voltage for discharging a light emitting element of a pixel among the plurality of pixels is changed to be different from a first level, and the anode reset voltage is supplied to the pixel of at least a partial region of the active region.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2024-0107814, filed on August 12, 2024, which is incorporated herein by reference as if fully set forth herein. Technical Field

[0003] This invention relates to a display device and its driving method. Background Technology

[0004] The display device includes a plurality of pixels arranged in a matrix, and uses the pixels to achieve image grayscale levels corresponding to image data. Each pixel includes a light-emitting element, and the brightness corresponding to the image grayscale level is achieved based on the amount of light emitted by the light-emitting element.

[0005] Under conditions where the amount of brightness change implemented in a pixel is large (e.g., the scene changetime when the image gray level changes from white gray level to black gray level, or from black gray level to white gray level), the gray level response time of the light-emitting element can be slowed down, thereby allowing the user to perceive blurring. Summary of the Invention

[0006] The present invention provides a display device and its driving method, which can increase the grayscale response time of the light-emitting element during scene change to enhance display quality.

[0007] Furthermore, the present invention provides a display device and its driving method, which can increase the grayscale response time of the light-emitting element during scene change, thereby enhancing display quality and achieving low power consumption.

[0008] As embodied and broadly described herein, in one aspect, a display device includes: a display panel including an active region having a plurality of pixels; a source driver configured to divide a gamma reference voltage to generate a data voltage for implementing image grayscale levels and to provide the data voltage to pixels among the plurality of pixels of the active region; and a reset voltage control circuit configured to, in a scene where the amount of image grayscale change with respect to at least a portion of the active region is equal to or greater than a reference value, change an anode reset voltage for discharging light-emitting elements of the pixels among the plurality of pixels to a level different from a first level and to provide the anode reset voltage to pixels in at least a portion of the active region.

[0009] In another aspect, there is provided a driving method of a display device including an active area including a plurality of pixels, the driving method including: dividing a gamma reference voltage to generate a data voltage for realizing an image gray scale and supplying the data voltage to a pixel of the plurality of pixels of the active area; and at a scene change time at which an amount of change in image gray scale with respect to a first area of the active area is equal to or greater than a reference value, changing an anode reset voltage for discharging a light emitting element of the pixel of the plurality of pixels to be different from a first level, and supplying the anode reset voltage to the pixel of the first area of the active area.

[0010] In still another aspect, there is provided a display device including: a display panel including an active area having a plurality of pixels; a source driver configured to generate a data voltage for realizing an image gray scale and supply the data voltage to a pixel of the plurality of pixels; and a reset voltage control circuit configured to change an anode reset voltage to be supplied to the pixel between different voltage levels based on a change in image gray scale of the data voltage corresponding to the pixel. BRIEF DESCRIPTION OF DRAWINGS

[0011] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the application and, together with the description, serve to explain the principles of the application. In the drawings:

[0012] Figure 1 is a diagram illustrating a display device according to an embodiment of the present application;

[0013] Figure 2 is a diagram illustrating an example of a variable refresh rate (VRR) technique applied to a display device according to an embodiment of the present application;

[0014] Figure 3 is a diagram illustrating a pixel according to an embodiment of the present application;

[0015] Figure 4 is a diagram of a driving waveform of a pixel in a refresh frame;

[0016] Figure 5 is a diagram illustrating a driving waveform of a pixel in a skip frame;

[0017] Figure 6 is a diagram illustrating a relationship between an anode reset voltage of a light emitting element and a gray scale response time at a scene change time;

[0018] Figure 7 is a diagram illustrating an example in which an anode reset voltage is changed to be different from a default level only at a scene change time and the anode reset voltage is maintained at the default level at other times;

[0019] Figure 8 is a graph showing a gray scale down condition of a scene change time, in which the image gray scale is changed from a white image of the Nth frame to a black image of the (N+l)th frame at the scene change time;

[0020] Figure 9 is a graph showing a case in which the anode reset voltage is maintained at a default level in the Nth frame just before the scene change time of Figure 8 ;

[0021] Figure 10 is a graph showing a case in which the anode reset voltage is lowered from the default level to a second level in the (N+l)th frame corresponding to the scene change time of Figure 8 ;

[0022] Figure 11 is a graph showing a gray scale up condition of a scene change time, in which the image gray scale is changed from a black image of the Nth frame to a white image of the (N+l)th frame at the scene change time;

[0023] Figure 12 is a graph showing a case in which the anode reset voltage is maintained at a default level in the Nth frame just before the scene change time of Figure 11 ;

[0024] Figure 13 is a graph showing a case in which the anode reset voltage is raised from the default level to a third level in the (N+l)th frame corresponding to the scene change time of Figure 11 ;

[0025] Figure 14 is a graph showing a case in which a white image pattern is scrolled down by using a background as a black image in one active area at a scene change time;

[0026] Figure 15 is a graph showing an example in which the anode reset voltage is changed to be different from a default level at a gray scale down position and a gray scale up position of a scene change time, and the anode reset voltage is maintained at the default level at other positions;

[0027] Figure 16 is a graph showing a case in which a gray scale down position and a gray scale up position of a scene change time are changed in time based on a scroll down operation of a white image pattern having a black image as a background;

[0028] Figure 17 and Figure 18is a diagram showing an example of changing the anode reset voltage differently at the gray scale drop position and the gray scale rise position based on a downward scroll operation in the Nth frame in the scene change time;

[0029] Figure 19 is a diagram showing a case of changing the anode reset voltage based on the gray scale drop position and the gray scale rise position shifted in pixel behavior units;

[0030] Figure 20 is a diagram showing a configuration of a reset voltage control circuit;

[0031] Figure 21 is a diagram showing a connection configuration between a reset voltage control circuit, a gamma memory, a gamma voltage circuit, and a source driver;

[0032] Figure 22 is a diagram showing a configuration of a gamma memory. DETAILED DESCRIPTION

[0033] Hereinafter, the present application will be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the application are shown. The application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and fully convey the inventive idea to those skilled in the art.

[0034] The advantages and features of the present application and methods of accomplishing the same will be clarified by referring to following embodiments described in detail with reference to the accompanying drawings.

[0035] The shapes, sizes, ratios, angles, numbers, and the like used to describe embodiments of the present application disclosed in the accompanying drawings for describing the embodiments of the present application are merely exemplary and the present application is not limited thereto. Like reference numerals refer to like elements throughout. Throughout the specification, like elements are designated with like reference numerals. As used herein, the terms "comprise", "have", "contain", and the like, imply the possibility that other parts can be added, unless the term "only" is used. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise.

[0036] Even if not explicitly mentioned, elements in various embodiments of the present application should be construed to include an error margin.

[0037] In describing positional relationships, for example, when the positional relationship between two parts is described as "on", "above", "below", and "behind", one or more other parts can be disposed between the two parts, unless "exactly" or "directly" is used.

[0038] It will be understood that, although the terms "first", "second", etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present application.

[0039] In the following description, detailed descriptions of associated known functions or configurations will be omitted when it is determined that such detailed description will unnecessarily obscure the point of the present application. Hereinafter, embodiments of the present application will be described in detail with reference to the accompanying drawings.

[0040] Figure 1 FIG. 1 is a view illustrating a display device according to an embodiment of the present application.

[0041] Referring to Figure 1 The display device according to the embodiment of the present embodiment can be an organic light emitting display device, but is not limited thereto. The display panel 100 can include an active area AA that reproduces an input image. The active area AA can include a pixel array that displays pixel data (hereinafter, referred to as "image data") DATA of the input image. The pixel array can include a plurality of data lines DL, a plurality of gate lines GL that intersect the data lines DL, and a plurality of pixels SP.

[0042] The pixels SP can be arranged on the active area AA in a matrix type defined by intersections between the data lines DL and the gate lines GL. The pixels SP can be arranged on the active area AA in various types such as a stripe type and a diamond type, based on positions of the pixels SP that emit light of the same color.

[0043] The pixel array can include a plurality of pixel columns and a plurality of pixel rows L1 to Ln that intersect the pixel columns. Each pixel column can include pixels SP arranged in a Y-axis direction. The pixel rows can include pixels SP arranged in an X-axis direction. One vertical period can be one frame period required to write image data DATA of one frame in all pixels of the active area. One horizontal period can be a time obtained by dividing one frame period by the number of the pixel rows L1 to Ln. One horizontal period can be a time required to write image data DATA of one pixel row sharing a gate line GL in the pixels SP of one pixel row.

[0044] The pixels SP can include a first pixel that generates red (R) light, a second pixel that generates green (G) light, and a third pixel that generates blue (B) light, for various color combinations. The pixels SP can further include a fourth pixel that generates white (W) light. The first to third pixels or the first to fourth pixels can constitute one unit pixel.

[0045] Each pixel SP can be implemented with a pixel circuit connected to a data line DL and a gate line GL. The pixel circuit can include a light emitting element, a driving transistor, one or more switching transistors, and a capacitor. The light emitting element can be implemented as an organic light emitting diode (OLED). A driving current applied to the light emitting element can be controlled based on a gate-source voltage of the driving transistor. The gate-source voltage of the driving transistor can be determined by a data voltage corresponding to image data DATA. In Figure 1 In the middle, "D1 to D3" shown in the circle can be data lines, and "Gn-2 to Gn" can be gate lines.

[0046] The pixel circuit can sample a threshold voltage of the driving transistor in a pixel programming operation performed in one frame period, and can allow the sampled threshold voltage to be reflected in a gate-source voltage (hereinafter referred to as Vgs) of the driving transistor, and thus can prevent a driving current from being distorted due to a change in the threshold voltage of the driving transistor.

[0047] The pixel circuit can be implemented as a hybrid type. In a hybrid type pixel circuit, the semiconductor layers of some transistors can include low temperature polysilicon (hereinafter referred to as LTPS), and the semiconductor layers of other transistors can be configured with an oxide.

[0048] The pixel circuit can be driven based on a variable refresh rate (VRR) technique. The VRR technique can change a refresh rate of the image data DATA based on properties of an image. According to the VRR technique, as the reduction in the change in the image, the data refresh period can increase, and thus power consumption can be reduced.

[0049] To implement the VRR variable technique, one or more skip frames can be provided between adjacent refresh frames. A data refresh operation can be performed in a refresh frame, and can not be performed in a skip frame. A refresh rate (i.e., a frame frequency) can be determined based on the number of skip frames set between adjacent refresh frames.

[0050] A data refresh operation including pixel initialization and data programming can be performed in a refresh frame. When the data refresh operation is performed, the light emitting element can be turned off, at which time an anode reset operation of initializing the light emitting element to an anode reset voltage can be performed.

[0051] The data refresh operation on the pixel SP can be omitted (or skipped) in a skip frame, and the data refresh conditions (Vgs, driving current, etc.) set in the refresh frame can be maintained. An anode reset operation for turning off the light emitting element can be performed in the skip frame. Thus, the length of time in which the light emitting element is turned on in the skip frame can be substantially equal to the length of time in which the light emitting element is turned on in the refresh frame.

[0052] The pixel SP can be further connected to a reset voltage line RL for anode reset operation, and can be supplied with an anode reset voltage through the reset voltage line RL. The reset voltage line RL can be independently patterned in a unit of pixel behavior. That is, one reset voltage line RL can be connected to a plurality of pixels SP constituting one pixel row. The reset voltage line RL can be independently driven in a unit of pixel behavior.

[0053] In each of the refresh frame and the skip frame, an on-bias stress (OBS) operation can be performed on the driving transistor while the anode reset operation is performed.

[0054] In the hybrid pixel circuit according to the embodiment of the present application, the OBS operation can be used to prevent image quality defects caused by the hysteresis characteristics of the driving transistor. In a scene change time in which the image data DATA is changed from a black gray scale to a white gray scale or rapidly changed from a white gray scale to a black gray scale, the gray scale response time can be increased in a first frame in which a white image (or a black image) is reproduced due to the time required to change the hysteresis characteristics of the driving transistor, and thus, a dim first frame (DFF) phenomenon can occur. At this time, when Vgs of the driving transistor is increased by applying an OBS voltage to one electrode of the driving transistor, the DFF characteristics can be alleviated. This can be referred to as an OBS operation.

[0055] The scene change time in the present application can be defined as a frame in which the amount of change in the image gray scale with respect to at least a partial region of the active area is a reference value or more. Accordingly, in addition to the amount of change between the black gray scale and the white gray scale, the amount of change in the gray scale in a wide range can be used to define the scene change time.

[0056] In the scene change time, the gray scale response time of the light emitting element can be slowed down due to insufficient reset of the parasitic capacitor of the light emitting element, and thus, blurring can be identified. The gray scale response time of the light emitting element can not be compensated for based on the OBS operation. This can be because the OBS operation is used to compensate for the hysteresis characteristics of the driving transistor.

[0057] In order to increase the gray scale response time of the light emitting element, by using the reset voltage control circuit 200 according to the present application, in a scene change time in which the amount of change in the image gray scale with respect to at least a partial region of the active area or the first region is limited to a reference value or more, the anode reset voltage for discharging the light emitting element of the pixel SP can be changed to a level different from a default level or a first level, and thus, the discharging effect on the parasitic capacitor of the light emitting element can be increased. Here, the scene change time can mean a first frame in which rapid gray scale change is performed. This will be described in detail with reference to Figure 6 FIG. 2.

[0058] Because the anode reset voltage control circuit 200 changes the anode reset voltage to a level different from the default level only at the scene change time and restores the anode reset voltage to the default level in frames other than the scene change time, a problem of an increase in power consumption due to a change in the anode reset voltage can be reduced. This will be described in detail with reference to Figures 7 to 20

[0059] A touch sensor can be further provided on the display panel 100. The touch sensor can be arranged as an on-cell or an add-on on the active area AA of the display panel 100, or can be implemented as an in-cell touch sensor embedded in the pixel array. Even without the touch sensor, a touch input can be sensed only through the pixels SP, in which case the touch sensor can be omitted.

[0060] The display panel driver can include a source driver 110 and a gate driver 120. The display panel driver can write image data DATA into the pixels SP of the display panel 100 in synchronization with a gate signal based on the control of a timing controller 130.

[0061] The source driver 110 can convert the image data DATA received from the timing controller 130 into a gamma compensation voltage by using a digital-to-analog converter (DAC) to generate a data voltage. The source driver 110 can provide the data voltage to a data line DL. The data voltage can be provided to the data line DL and can be applied to the gate of the driving transistor through a switching transistor of the pixel SP. The source driver 110 can be implemented with a plurality of source driving integrated circuits (ICs).

[0062] A gamma voltage circuit connected (or integrated) with the DAC of the source driver 110 can be provided. The gamma voltage circuit can generate a gamma tap voltage and can provide the gamma tap voltage to the DAC of the source driver 110. The gamma tap voltage can be a gamma reference voltage. The DAC of the source driver 110 can divide the gamma reference voltage to generate the data voltage.

[0063] The gamma voltage circuit can output the gamma tap voltage applied to the scene change time to be different from the gamma tap voltage applied to frames other than the scene change time, and thus can prevent a problem of a distortion in color coordinates due to a change in the anode reset voltage at the scene change time. This will be described in detail with reference to Figure 21 and 22

[0064] ​​The gate driver 120 can be implemented as a single bank type in which the gate driver 120 is disposed in one side bezel area BZ of the active area AA, or a double bank type in which the gate driver 120 is disposed in both side bezel areas BZ of the active area AA. The single bank type can be relatively more advantageous for implementing a narrow bezel. The double bank type can be relatively more advantageous for reducing RC delay.

[0065] The gate driver 120 can be disposed as a gate-in-panel (GIP) type in a bezel area BZ disposed outside the active area AA of the display panel 100, and can provide a gate signal whose phase is sequentially shifted to the gate line GL of the display panel 100 based on the control of the timing controller 130. The gate driver 120 can output a gate signal required for pixel driving, and can shift the gate signal in a unit of a pixel behavior.

[0066] A pixel row L1 to Ln charged with a data voltage can be selected based on a gate signal. To this end, pixels SP disposed in the corresponding pixel row L1 to Ln can be simultaneously activated based on the gate signal. The gate signal can include a plurality of scan signals that swing between an on level and an off level, and a light emission control signal. The gate driver 120 can include a plurality of scan drivers that generate the plurality of scan signals, and a light emission driver that generates the light emission control signal.

[0067] The timing controller 130 can receive image data DATA and a timing signal synchronized with the image data DATA from a host system (not shown). The timing signal can include a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a clock signal (DCLK), and a data enable signal (DE). The vertical synchronization signal (Vsync) can define a vertical period. The horizontal synchronization signal (Hsync) can define a horizontal period. The data enable signal DE can define a time at which the image data DATA is transmitted in the vertical period or the horizontal period. The vertical period and the horizontal period can be determined by a method of counting the data enable signal (DE), and thus, the vertical synchronization signal (Vsync) and the horizontal synchronization signal (Hsync) can be omitted.

[0068] The timing controller 130 can generate a source timing control signal DDC for controlling the operation timing of the source driver 110 and a gate timing control signal GDC for controlling the operation timing of the gate driver 120 based on the timing signal (Vsync, Hsync, DE) received from the host system. The timing controller 130 can also control the operation timing of the reset voltage control circuit 200 by using the timing signal (Vsync, Hsync, DE).

[0069] The host system can be one of a television (TV), a set-top box, a navigation system, a personal computer (PC), a home theater, a car display system, a mobile device, and a wearable device.

[0070] The level shifter 140 can convert a voltage of the gate timing control signal GDC output from the timing controller 130 into an on-level voltage and an off-level voltage, and can provide the on-level voltage and the off-level voltage to the gate driver 120.

[0071] In the mobile device and the wearable device, the source driver 110, the timing controller 130, the level shifter 140, and the reset voltage control circuit 200 can be integrated into one driving IC.

[0072] Figure 2 FIG. 1 is a diagram illustrating an example of a VRR technique applied to a display device according to an embodiment of the present application.

[0073] Referring to Figure 2 A data refresh period implemented in a pixel of a display panel can vary based on a property of an input image. When a variation amount of an image is large, the data refresh period can decrease, and when the variation amount of the image is small, the data refresh period can increase. As the data refresh period increases, low-speed driving can be performed, and as the data refresh period decreases, high-speed driving can be performed.

[0074] The data refresh period can be 1 / frame frequency. For example, the data refresh period can be 1 / 120 seconds at 120 Hz, 1 / 60 seconds at 60 Hz, 1 / 24 seconds at 24 Hz, and 1 second at 1 Hz.

[0075] A number of skip frames set between two adjacent refresh frames can vary based on a frame frequency. For example, the number of skip frames can be 0 at 120 Hz, 1 at 60 Hz, 4 at 24 Hz, and 119 at 1 Hz.

[0076] Due to a variation in a leakage characteristic occurring in a pixel, a luminance deviation can occur between frames. Such a luminance deviation is more noticeable in low-speed driving in which a data refresh period is long, and thus an anti-flicker characteristic can be degraded (i.e., a flicker amount can increase).

[0077] Figure 3 FIG. 2 is a diagram illustrating a pixel SP(n) disposed in an nth pixel row Ln according to an embodiment of the present application.

[0078] Referring to Figure 3 The pixel SP(n) disposed in the nth pixel row Ln can be implemented with a pixel circuit including a light emitting element OLED, a driving transistor DT, switching transistors (e.g., first to seventh switching transistors) T1 to T7, and a capacitor Cst.

[0079] The driving transistor DT, the switching transistors T1 to T7, and the capacitor Cst can control a driving current flowing in the light emitting element OLED to drive the light emitting element OLED. Each of the driving transistor DT and the switching transistors T1 to T7 can include a first electrode, a second electrode, and a gate electrode. One of the first electrode and the second electrode can be a source electrode, and the other of the first electrode and the second electrode can be a drain electrode.

[0080] Each of the second transistor T2 to the sixth transistor T6 and the driving transistor DT can be implemented as a PMOS type including a semiconductor layer having a good response characteristic of LTPS. On the other hand, the first transistor T1 and the seventh transistor T7 directly connected to the gate electrode of the driving transistor DT can be implemented as an NMOS type including an oxide semiconductor layer having a good cutoff characteristic.

[0081] The on-level voltage of the PMOS type transistor can be a gate low voltage, and the off-level voltage can be a gate high voltage. On the other hand, the on-level voltage of the NMOS type transistor can be a gate high voltage, and the off-level voltage can be a gate low voltage.

[0082] The light emitting element OLED can include an anode (or a pixel electrode), a cathode (or a common electrode), and an organic compound layer (configured with a common layer and a light emitting layer) disposed therebetween. The anode of the light emitting element OLED can be connected to the fourth node N4, and the cathode of the light emitting element OLED can be connected to the second power supply voltage ELVSS.

[0083] The driving transistor DT can include a gate electrode connected to the first node N1, a source electrode connected to the second node N2, and a drain electrode connected to the third node N3. The driving transistor DT can generate a driving current based on a voltage of the first node N1 (or a data voltage stored in the capacitor Cst), and can apply the driving current to the light emitting element OLED.

[0084] The first switching transistor T1 can include a gate electrode receiving a first scan signal SCAN1 through a first scan line SL1, a drain electrode connected to the third node N3, and a source electrode connected to the first node N1. The first switching transistor T1 can be turned on in response to the first scan signal SCAN1, and can short the gate electrode and the drain electrode of the driving transistor DT to each other. Accordingly, the driving transistor DT can operate like a diode while the first switching transistor T1 is turned on.

[0085] The second switch transistor T2 can include a gate receiving a second scan signal SCAN2 through a second scan line SL2, a source connected to a data line (or receiving a data voltage Vdata), and a drain connected to the second node N2. The second switch transistor T2 can be turned on in response to the second scan signal SCAN2, and can transmit the data voltage Vdata to the second node N2.

[0086] The capacitor Cst can be connected between the first node N1 and an input terminal of the first power voltage ELVDD. The capacitor Cst can maintain a voltage of the first node N1.

[0087] The third switch transistor T3 and the fourth switch transistor T4 can be connected between the first power voltage ELVDD and the light emitting diode OLED, and can form a current moving path through which a driving current generated by the driving transistor DT moves.

[0088] The third switch transistor T3 can include a source connected to an input terminal of the first power voltage ELVDD, a drain connected to the second node N2, and a gate receiving an emission control signal EM through an emission control line EL. The fourth switch transistor T4 can include a source connected to the third node N3, a drain connected to the fourth node N4, and a gate receiving the emission control signal EM through the emission control line EL.

[0089] The third switch transistor T3 and the fourth switch transistor T4 can be turned on in response to the emission control signal EM. While the third switch transistor T3 and the fourth switch transistor T4 are turned on, the light emitting element OLED can receive the driving current from the driving transistor DT, and can emit light having a brightness corresponding to the driving current.

[0090] The fifth switch transistor T5 can include a source connected to an input terminal of the OBS voltage Vobs, a drain connected to the second node N2, and a gate receiving a third scan signal SCAN3 through a third scan line SL3. The fifth switch transistor T5 can be turned on based on the third scan signal SCAN3, and can apply the OBS voltage Vobs to the second node N2.

[0091] The sixth switch transistor T6 can include a source connected to an input terminal of the anode reset voltage VAR, a drain connected to the fourth node N4, and a gate receiving the third scan signal SCAN3 through the third scan line SL3. The sixth switch transistor T6 can be turned on based on the third scan signal SCAN3, and can transmit the anode reset voltage VAR to the fourth node N4.

[0092] The seventh switching transistor T7 can include a source connected to an input terminal of the initialization voltage Vini, a second electrode connected to the first node N1, and a gate receiving a fourth scan signal SCAN4 through a fourth scan line SL4. The seventh switching transistor T7 can be turned on based on the fourth scan signal SCAN4, and can apply the initialization voltage Vini to the first node N1.

[0093] Figure 4 is a driving waveform diagram of a pixel in a refresh frame.

[0094] Referring to Figure 4 , the first OBS period Tobs1, the initialization period Ti, the programming period Ts, the second OBS period Tobs2, and the emission period Te can be arranged in series in time in the refresh frame. The gate driver 120 can be configured to generate a scan signal and provide the scan signal to the pixels of the at least partial area within the scene change time. The scan signal can define the first OBS period and the second OBS period with respect to the pixels of the at least partial area. The first OBS period and the second OBS period can overlap with the non-emission period of the pixels of the at least partial area.

[0095] The second scan signal SCAN2 can define the programming period Ts in which the data voltage Vdata is provided. The programming period Ts can be a period of an on level Lon of the second scan signal SCAN2.

[0096] The third scan signal SCAN3 can define the first OBS period Tobs1 before the programming period Ts and the second OBS period Tobs2 after the programming period Ts and before the emission period Te. The first OBS period Tobs1 and the second OBS period Tobs2 can each be a period of an on level Lon of the third scan signal SCAN3.

[0097] The fourth scan signal SCAN4 can define the initialization period Ti arranged between the first OBS period Tobs1 and the programming period Ts. The initialization period Ti can be a period of an on level Lon of the fourth scan signal SCAN4.

[0098] The emission control signal EM can define the emission period Te after the second OBS period Tobs2. The emission period Te can be a period of an on level Lon of the emission control signal EM.

[0099] The first OBS period Tobs1, the initialization period Ti, the programming period Ts, and the second OBS period Tobs2 can be arranged in an "EM off period" which is a period of an off level Loff of the emission control signal EM. An "EM on period" which is a period of an on level Lon of the emission control signal EM can be the emission period Te.

[0100] Referring to Figure 3 and Figure 4 In the first OBS period Tobs1, in response to the third scan signal SCAN3, the fifth switch transistor T5 and the sixth switch transistor T6 can be turned on, and the other switch transistors T1 to T4 and T7 can be turned off.

[0101] In the first OBS period Tobs1, when the fifth switch transistor T5 is turned on, the OBS voltage Vobs can be applied to the second node N2. Based on the OBS voltage Vobs, the drain-source channel of the driving transistor DT can be maximally opened, the driving transistor DT can maintain a stronger saturation state, and thus, the hysteresis characteristics of the driving transistor DT can be improved before data programming.

[0102] In the first OBS period Tobs1, when the sixth switch transistor T6 is turned on, the anode reset voltage VAR can be applied to the fourth node N4. Based on the anode reset voltage VAR, residual charges in a parasitic capacitor formed between the anode and the cathode of the light emitting element OLED can be reset.

[0103] Referring to Figure 3 and Figure 4 In the initialization period Ti, in response to the first scan signal SCAN1 and the fourth scan signal SCAN4, the first switch transistor T1 and the seventh switch transistor T7 can be turned on, and the other switch transistors T2 to T6 can be turned off. When the seventh switch transistor T7 is turned on, the first node N1 can be initialized to the initialization voltage Vini, and when the first switch transistor T1 is turned on, the driving transistor DT can operate like a diode.

[0104] Referring to Figure 3 and Figure 4 In the programming period Ts, when the first switch transistor T1 and the second switch transistor T2 are turned on in response to the first scan signal SCAN1 and the second scan signal SCAN2, respectively, a threshold voltage sampling operation and a data programming operation can be sequentially or simultaneously performed.

[0105] The data voltage Vdata can be applied to the second node N2 through the second switch transistor T2. The data voltage Vdata can be applied to the third node N3 through the driving transistor DT, and then can be applied to the first node N1 through the first switch transistor T1. In a state in which the first switch transistor T1 is turned on, the driving transistor DT can operate like a diode, and a potential at the gate of the driving transistor DT connected to the first node N1 can be programmed as “Vdata-|Vth|”. The threshold voltage Vth can be sampled and reflected in the programming potential at the gate of the driving transistor DT.

[0106] Referring to Figure 3 andFigure 4 In the second OBS period Tobs2, in response to the third scan signal SCAN3, the fifth switch transistor T5 and the sixth switch transistor T6 can be turned on, and the other switch transistors T1 to T4 and T7 can be turned off.

[0107] In the second OBS period Tobs2, when the fifth switch transistor T5 is turned on, the OBS voltage Vobs can be applied to the second node N2. Based on the OBS voltage Vobs, the drain-source channel of the driving transistor DT can be maximally opened, and the driving transistor DT can maintain a stronger saturation state, and thus, the hysteresis characteristic of the driving transistor DT can be re-improved before light emission.

[0108] In the second OBS period Tobs2, when the sixth switch transistor T6 is turned on, the anode reset voltage VAR can be applied to the fourth node N4, and thus, residual charges in the parasitic capacitor of the light emitting element OLED can be re-reset.

[0109] Referring to Figure 3 and Figure 4 In the light emission period Te, in response to the light emission control signal EM, the third switch transistor T3 and the fourth switch transistor T4 can be turned on, and the other switch transistors T1, T2, T5, T6, and T7 can be turned off.

[0110] In the light emission period Te, the driving current provided from the driving transistor DT to the light emitting element OLED can be based on the Vgs of the driving transistor DT set in the programming period Ts. The driving current can be independent of the threshold voltage of the driving transistor DT and can be associated with the data voltage Vdata.

[0111] Figure 5 is a graph showing a driving waveform of a pixel in a skip frame.

[0112] Referring to Figure 5 , the third OBS period Tobs3, the fourth OBS period Tobs4, and the light emission period Te can be arranged in series in time in a skip frame.

[0113] The light emission control signal EM can define the light emission period Te of the skip frame. The light emission period Te can be a turn-on period Lon of the light emission control signal EM. The turn-on period Lon of the light emission control signal EM in the skip frame can be substantially the same as that of a refresh frame.

[0114] The third scan signal SCAN3 can further define the third OBS period Tobs3 and the fourth OBS period Tobs4 arranged in sequence before the light emission period Te in the skip frame. In the skip frame, the third OBS period Tobs3 and the fourth OBS period Tobs4 can each be a turn-on period Lon of the third scan signal SCAN3.

[0115] In addition, the initialization period and the programming period can not be required in the skip frame, and in addition, the third OBS period Tobs3 can be skipped.

[0116] Referring to Figure 3 and Figure 5 The hysteresis characteristic of the driving transistor DT can be re-improved in the third OBS period Tobs3 and the fourth OBS period Tobs4, and thus the hysteresis characteristic deviation between the skip frame and the refresh frame can be reduced.

[0117] The first OBS period Tobs1 and the second OBS period Tobs2 of the refresh frame can be included in the EM cutoff period, and in addition, the third OBS period Tobs3 and the fourth OBS period Tobs4 of the skip frame can be included in the EM cutoff period.

[0118] The EM cutoff period can be set to be equal to each other in the refresh frame and the skip frame, and thus the length of the emission holding time can be equal to each other in the refresh frame and the skip frame.

[0119] Figure 6 is a graph illustrating a relationship between a scene change time, an anode reset voltage of a light emitting element, and a gray scale response time.

[0120] Referring to Figure 6 In the above-described OBS period, the anode reset voltage VAR can be applied to the anode of the light emitting element OLED based on the third scan signal SCAN3. The parasitic capacitor Coled of the light emitting element OLED can be reset by the anode reset voltage VAR. Thus, the anode reset voltage VAR can be a voltage for initializing the parasitic capacitor Coled of the light emitting element OLED.

[0121] In a gray scale down condition in which a display image of the active area changes from a white image to a black image, the scene change time (for example, in a black image frame) can vary according to the level of the anode reset voltage VAR. For example, as Figure 6 shown, the discharge effect on the parasitic capacitor of the light emitting element can increase in the anode reset voltage VAR of -12.6 V compared to the anode reset voltage VAR of -10.6 V, and thus the black gray scale expression can be enhanced. In other words, in the gray scale down condition, as the anode reset voltage VAR is set to be lower, the gray scale response (or the gray scale response time) of the scene change time can be improved.

[0122] On the other hand, in this case, since the second power voltage ELVSS and the anode reset voltage VAR should be lowered together for normal operation, the power consumption in the light emitting element OLED can increase. The description herein provides a method of improving the gray scale response of the scene change time while achieving low power consumption.

[0123] Figure 7 is a graph showing an example in which the anode reset voltage is changed to a different level from the default level only at the scene change time and is kept at the default level at other times.

[0124] Referring to Figure 7 , in the gray scale drop condition in which the display image of the active area changes from a white image to a black image, when the anode reset voltage VAR is kept at the default level VL1, blurring (e.g., a trailing shadow) caused by a low-speed gray scale response at the scene change time SCT can be recognized.

[0125] In order to improve the gray scale response at the scene change time SCT while achieving low power consumption, the reset voltage control circuit according to the present application can lower the anode reset voltage VAR to a second level VL2 lower than the default level VL1 only at the scene change time SCT, and can restore the anode reset voltage VAR to the default level VL1 at other times.

[0126] This will be described additionally with reference to Figures 8 to 10 .

[0127] Figure 8 The gray scale drop condition at the scene change time SCT is shown, at which the image gray scale level changes from a white image of the Nth frame to a black image of the (N+1)th frame. Figure 9 The case in which the anode reset voltage VAR is kept at the default level VL1 in the Nth frame just before the scene change time is shown. Figure 8 The case in which the anode reset voltage VAR is kept at the default level VL1 in the Nth frame just before the scene change time is shown. Figure 10 The case in which the anode reset voltage VAR is lowered from the default level VL1 to the second level VL2 in the (N+1)th frame corresponding to the scene change time SCT is shown. Figure 8 The case in which the anode reset voltage VAR is lowered from the default level VL1 to the second level VL2 in the (N+1)th frame corresponding to the scene change time SCT is shown.

[0128] Referring to Figure 8 and Figure 9 , in the Nth frame just before the scene change time, the anode reset voltage VAR corresponding to all the pixel rows La and Lb can be kept at the default level VL1. In the OBS period overlapping the EM cutoff period, the anode reset voltage VAR of the default level VL1 can be supplied to the pixels of all the pixel rows La and Lb.

[0129] Referring to Figure 8 and Figure 10In the (N+1)th frame corresponding to the scene change time, the anode reset voltage VAR corresponding to all pixel rows La and Lb is shifted from the default level VL1 to the second level VL2, which is ΔV lower than the default level VL1. During the OBS period overlapping with the EM cutoff period, the anode reset voltage VAR of the second level VL2 can be provided to the pixels of all pixel rows La and Lb.

[0130] like Figure 10 As shown, in order to reduce the power consumption of the light-emitting element, it can be reduced in the (N+2)th frame after the scene change time (if the (N+2)th frame is not in the scene change time). Figure 10 (As shown in the figure) the anode reset voltage VAR is restored to the default level VL1.

[0131] Furthermore, changing the anode reset voltage to a different level only during scene change time and restoring it to the default level after scene change time can be implemented for the grayscale decrease condition when the image changes from white to black, and can also be implemented for the grayscale increase condition during scene change time SCT when the image changes from black to white.

[0132] This will refer to Figures 11 to 13 Provide additional descriptions.

[0133] Figure 11 The grayscale increase condition at scene change time (SCT) is shown. At scene change time (SCT), the image grayscale level changes from a black image in frame N to a white image in frame (N+1). Figure 12 Showing exactly at Figure 11 The scenario where the anode reset voltage VAR is kept at the default level VL1 in the Nth frame before the scene change time. Figure 13 Shown in the corresponding Figure 11 The scenario where the anode reset voltage VAR is moved from the default level VL1 to the third level VL3 in the (N+1)th frame of the scene change time SCT.

[0134] Reference Figure 11 and Figure 12 In the Nth frame, exactly before the scene change time, the anode reset voltage VAR corresponding to all pixel rows La and Lb can be maintained at the default level VL1. During the OBS period that overlaps with the EM cutoff period, the anode reset voltage VAR at the default level VL1 can be provided to the pixels of all pixel rows La and Lb.

[0135] Reference Figure 11 and Figure 13In the (N+1)th frame corresponding to the Scene Change Time (SCT), the anode reset voltage VAR corresponding to all pixel rows La and Lb can be shifted from the default level VL1 to a third level VL3, which is ΔV higher than the default level VL1. During the OBS period overlapping with the EM cutoff period, the anode reset voltage VAR of the third level VL3 can be provided to the pixels of all pixel rows La and Lb.

[0136] like Figure 13 As shown, in order to reduce the power consumption of the light-emitting element, it can be reduced in the (N+2)th frame after the scene change time (if the (N+2)th frame is not in the scene change time). Figure 13 (As shown in the figure) the anode reset voltage VAR is restored to the default level VL1.

[0137] Furthermore, the technique of changing the anode reset voltage in time to a different level than the default level can be applied to scrolling images, where grayscale decrease and grayscale increase operations are performed in different parts of the active region, such as... Figures 14 to 19 As shown.

[0138] Reference Figure 14 During a scene change with a black image as the background, a white image pattern can scroll downwards within an active area. The white image pattern can be implemented using pixels from a portion of the active area. Based on the downward scrolling operation, the position of the white image pattern can shift in the direction from the top of the active area towards the bottom. Therefore, a grayscale decrease position and a grayscale increase position on the screen can appear in different areas (e.g., rows) of the active area.

[0139] Reference Figure 15 According to an embodiment of the present invention, the reset voltage control circuit can change the anode reset voltage VAR to a different level VL1 at the grayscale decrease position SCP1 and the grayscale increase position SCP2 during the scene change time, and can restore the anode reset voltage VAR to the default level VL1 at other positions.

[0140] During a scene change period, for example, when a white image corresponding to a pixel in the first active region scrolls down in an active region with a black image corresponding to a pixel in the second active region as a background, the reset voltage control circuit can change the anode reset voltage VAR to a second level VL2 lower than the default level VL1, and then provide the anode reset voltage VAR of the second level VL2 to pixels in some pixel rows (e.g., the first pixel row) or at least some pixels in a region that meet the grayscale decrease condition.

[0141] In a scene change time, for example, when a white image corresponding to a pixel of a first area of the active area is scrolled down in the active area having a black image corresponding to a pixel of a second area of the active area as a background, the reset voltage control circuit can change the anode reset voltage VAR to a third level VL3 higher than the default level VL1, and then can supply the anode reset voltage VAR of the third level VL3 to the pixels of some pixel rows (for example, the second pixel rows) or the pixels of at least a partial area that satisfy the gray level rise condition. Through a plurality of scene change times, the position of the first pixel row to which the anode reset voltage of the second level is supplied and the position of the second pixel row to which the anode reset voltage of the third level is supplied can be configured to be sequentially shifted in units of pixel rows. The anode reset voltage can be configured to return to the default level VL1 in a frame after the plurality of scene change times.

[0142] Referring to Figure 16 , based on a scroll-down operation of a white image pattern having a black image as a background, a gray level drop position Lc and a gray level rise position Ld of a scene change in time.

[0143] The gray level drop position Lc can be implemented in at least one first pixel row. The image gray level implemented in the first pixel row in a scene change time can be changed from a white image to a black image through a scroll-down operation, and thus can satisfy a gray level drop condition.

[0144] The gray level rise position Ld can be implemented in at least one second pixel row. The image gray level implemented in the second pixel row in a scene change time can be changed from a black image to a white image through a scroll-down operation, and thus can satisfy a gray level rise condition.

[0145] Figure 17 and Figure 18 An example in which the anode reset voltage is changed differently at the gray level drop position and the gray level rise position based on a scroll-down operation in an Nth frame in a scene change time is shown.

[0146] Referring to Figure 17 , the reset voltage control circuit can change the anode reset voltage VAR to a second level VL2 lower than the default level VL1 during a second OBS period of a scene change time, and then can supply the anode reset voltage VAR of the second level VL2 to the pixels of the gray level drop position Lc.

[0147] Referring to Figure 17 , the reset voltage control circuit can change the anode reset voltage VAR to a third level VL3 higher than the default level VL1 during a second OBS period of a scene change time, and then can supply the anode reset voltage VAR of the third level VL3 to the pixels of the gray level rise position Ld.

[0148] Referring toFigure 18 The reset voltage control circuit can change the anode reset voltage VAR to a second level VL2 lower than the default level VL1, and then can supply the anode reset voltage VAR at the second level VL2 to the pixels at the gray scale lowering position Lc during the first and second OBS periods of the scene change time.

[0149] Referring to Figure 18 The reset voltage control circuit can change the anode reset voltage VAR to a third level VL3 higher than the default level VL1 during the first and second OBS periods of the scene change time, and then can supply the anode reset voltage VAR at the third level VL3 to the pixels at the gray scale raising position Ld.

[0150] The level of the anode reset voltage VAR just before the start of the EM on period can be significant for improving the gray scale response of the light emitting element at the scene change time. Thus, as shown in FIG. 6, the reset voltage control circuit can supply the anode reset voltage VAR different from the default level VL1 only in the second OBS period, or as shown in FIG. 7, the reset voltage control circuit can supply the anode reset voltage VAR different from the default level VL1 only in the first and second OBS periods. Based on the gray scale lowering / raising positions Lc / Ld, the reset voltage control circuit can restore the anode reset voltage VAR to the default level VL1 at a time after the second OBS period. Figure 17 Figure 18

[0151] Referring to Figure 19 The anode reset voltage VAR can be changed based on the gray scale lowering position Lc and the gray scale raising position Ld shifted in units of pixels.

[0152] Based on the gray scale lowering position Lc, the anode reset voltage VAR can be lowered from the default level VL1 to the second level VL2, and then can be restored to the default level VL1. Also, based on the gray scale raising position Ld, the anode reset voltage VAR can be raised from the default level VL1 to the third level VL3, and then can be restored to the default level VL1.

[0153] To differently express this, the gray scale lowering position Lc at which the anode reset voltage VAR at the second level VL2 is supplied and the gray scale raising position Ld at which the anode reset voltage VAR at the third level VL3 is supplied can be sequentially shifted in units of pixels by a plurality of scene change times. The anode reset voltage VAR can be restored to the default level VL1 in a subsequent frame after the scene change time.

[0154] Figure 20 ​​is a diagram illustrating a configuration of a reset voltage control circuit 200. The reset voltage control circuit 200 can be configured to change an anode reset voltage to be supplied to a pixel between different voltage levels based on a change in an image gray scale of a data voltage corresponding to the pixel to which the data voltage is supplied. The reset voltage control circuit 200 can be configured to change a first anode reset voltage to be supplied to a first pixel of a plurality of pixels to a second level VL2 lower than a default level VL1 when a first image gray scale of a first data voltage of the first pixel is changed from a white image to a black image, and can be configured to change a second anode reset voltage to be supplied to a second pixel of the plurality of pixels to a third level VL3 higher than the default level VL1 when a second image gray scale of a second data voltage of the second pixel is changed from the black image to the white image.

[0155] Referring to Figure 20 , the reset voltage control circuit 200 can include a memory MEM, an image change detector LOG, and a reset voltage output unit LDO.

[0156] The memory MEM can store voltage level information about the default level VL1, the second level VL2 lower than the default level VL1, and the third level VL3 higher than the default level VL1.

[0157] The image change detector LOG can detect an image gray scale change amount with respect to a previous frame based on a horizontal synchronization signal Hsync in units of a target area. The target area can be set to all pixel rows of an active area (case 1), or can be set to one pixel row of the active area (case 2). Figure 20 Figure 20

[0158] The reset voltage output unit LDO can select voltage level information about one of the default level VL1, the second level VL2, and the third level VL3 in units of the target area based on the image gray scale change amount, and can output an anode reset voltage VAR corresponding to the selected voltage level information DIN in units of the target area.

[0159] Figure 21 is a diagram illustrating a connection configuration between the reset voltage control circuit 200, a gamma memory G-MEM, a gamma voltage circuit CRGM, and the source driver 110. Figure 22 is a diagram illustrating a configuration of the gamma memory G-MEM.

[0160] Referring to Figure 21 , the source driver 110 can include a data latch LAT, a digital-to-analog converter DAC, and an output unit OCH.

[0161] The data latch LAT can latch and temporarily store digital image data transferred from a timing controller in units of pixel rows.​​

[0162] A digital-to-analog converter (DAC) can map digital image data input from a data latch (LAT) to a gamma compensation voltage to generate a data voltage having different gray scale values. The digital-to-analog converter (DAC) can divide a gamma reference voltage to generate the gamma compensation voltage. In this case, the gamma reference voltage can be provided to the digital-to-analog converter (DAC) from a gamma voltage circuit (CRGM).

[0163] An output unit (OCH) can output the data voltage to a data line.

[0164] Referring to Figure 21 and Figure 22 , the gamma voltage circuit (CRGM) can generate gamma tap voltages V1, V2, V6, V13...V250 and can provide the gamma tap voltages V1, V2, V6, V13...V250 as a gamma reference voltage to the digital-to-analog converter (DAC). The gamma tap voltages V1, V2, V6, V13...V250 can be about 10 to 16 gamma reference voltages included in 256 gamma compensation voltages representing 0 (black gray scale) to 255 (white gray scale) gray scales.

[0165] The gamma voltage circuit (CRGM) can operate in conjunction with a reset voltage control circuit 200. The reset voltage control circuit 200 can be the same as described in Figure 20 .

[0166] Referring to tap voltage information about the gamma memory (G-MEM), the gamma voltage circuit (CRGM) can generate the gamma tap voltages V1, V2, V6, V13...V250 independently of red (R), green (G), and blue (B), and in this case, the gamma voltage circuit (CRGM) can output the gamma tap voltages V1, V2, V6, V13...V250 applied to a scene change time as different from the gamma tap voltages V1, V2, V6, V13...V250 applied to other frames except for the scene change time. Accordingly, a problem that color coordinates are distorted due to a change in the anode reset voltage (VAR) at the scene change time can be prevented.

[0167] As shown in Figure 22 , the gamma memory (G-MEM) can store tap voltage information including a plurality of first gamma tap voltages RGM1 corresponding to a default condition, a plurality of second gamma tap voltages RGM2 corresponding to a gray scale down condition in which an image gray scale of a target region of an active region is changed from a white image to a black image, and a plurality of third gamma tap voltages RGM3 corresponding to a gray scale up condition in which the image gray scale of the target region of the active region is changed from the black image to the white image.

[0168] When the anode reset voltage VAR_Normal of the default level VL1 matches the target region of the active region under the default condition, the gamma voltage circuit CRGM can generate a first gamma tap voltage RGM1 and can output the first gamma tap voltage RGM1 as a gamma reference voltage to the digital-to-analog converter DAC.

[0169] When the anode reset voltage VAR_Falling of the second level VL2 lower than the default level VL1 matches the target region of the active region under the falling gray condition, the gamma voltage circuit CRGM can generate a second gamma tap voltage RGM2 and can output the second gamma tap voltage RGM2 as a gamma reference voltage to the digital-to-analog converter DAC.

[0170] When the anode reset voltage VAR_Rising of the third level VL3 higher than the default level VL1 matches the target region of the active region under the rising gray condition, the gamma voltage circuit CRGM can generate a third gamma tap voltage RGM3 and can output the third gamma tap voltage RGM3 as a gamma reference voltage to the digital-to-analog converter DAC.

[0171] The image gray level can include a low gray range (e.g., a first gray range including a first gray level) and other gray ranges (e.g., a second gray range including a second gray level greater than the first gray level) other than the low gray range, wherein the low gray range includes a determined low gray level (the low gray level can be determined or set dynamically or experimentally). Thus, the problem that the color coordinates are distorted due to the change of the anode reset voltage VAR at the scene change time can be further deteriorated in the low gray range.

[0172] To solve such a problem, the level of one of the first gamma tap voltages RGM1, the level of one of the second gamma tap voltages RGM2, and the level of one of the third gamma tap voltages RGM3 corresponding to the same color and the same gray level can be differently set in the low gray range in the gamma memory G-MEM. For example, the gamma tap voltages V1 and A of RGM1 of red, A' of RGM2, and A" of RGM3 corresponding to Figure 22 Figure 22 Figure 22

[0173] ​​​On the other hand, the levels of one of the first gamma tap voltages RGM1, one of the second gamma tap voltages RGM2, and one of the third gamma tap voltages RGM3 corresponding to the same color and the same gray scale can be identically set in the gamma memory G-MEM in a gray scale range other than the low gray scale range. For example, the gamma tap voltages V250 and X of RGM1, X' of RGM2, and X" of RGM3 corresponding to red, respectively, can be set to have the same amplitude, the gamma tap voltages V250 and Y of RGM1, Y' of RGM2, and Y" of RGM3 corresponding to blue, respectively, can be set to have the same amplitude, and the gamma tap voltages V250 and Z of RGM1, Z' of RGM2, and Z" of RGM3 corresponding to green, respectively, can be set to have the same amplitude. Figure 22 The gamma tap voltages V250 and X of RGM1, X' of RGM2, and X" of RGM3 corresponding to red, respectively, can be set to have the same amplitude, the gamma tap voltages V250 and Y of RGM1, Y' of RGM2, and Y" of RGM3 corresponding to blue, respectively, can be set to have the same amplitude, and the gamma tap voltages V250 and Z of RGM1, Z' of RGM2, and Z" of RGM3 corresponding to green, respectively, can be set to have the same amplitude. Figure 22 The gamma tap voltages V250 and X of RGM1, X' of RGM2, and X" of RGM3 corresponding to red, respectively, can be set to have the same amplitude, the gamma tap voltages V250 and Y of RGM1, Y' of RGM2, and Y" of RGM3 corresponding to blue, respectively, can be set to have the same amplitude, and the gamma tap voltages V250 and Z of RGM1, Z' of RGM2, and Z" of RGM3 corresponding to green, respectively, can be set to have the same amplitude. Figure 22 The gamma tap voltages V250 and X of RGM1, X' of RGM2, and X" of RGM3 corresponding to red, respectively, can be set to have the same amplitude, the gamma tap voltages V250 and Y of RGM1, Y' of RGM2, and Y" of RGM3 corresponding to blue, respectively, can be set to have the same amplitude, and the gamma tap voltages V250 and Z of RGM1, Z' of RGM2, and Z" of RGM3 corresponding to green, respectively, can be set to have the same amplitude.

[0174] The present application can achieve the following effects.

[0175] In the present application, the anode reset voltage for discharging the light emitting element of the pixel can be changed to be different from a default level at a scene change time in which the amount of change in image gray scale with respect to at least a part of the active area is a reference value or more, so that the discharging effect of the parasitic capacitor of the light emitting element can be increased, thereby enhancing the display quality of the light emitting element and improving the gray scale response time.

[0176] In the present application, since the anode reset voltage is changed to be different from the default level only at the scene change time, and the anode reset voltage is restored to the default level in frames other than the scene change time, the problem of increased power consumption due to the change in the anode reset voltage can be reduced.

[0177] In the present application, the gamma tap voltage applied to the scene change time can be output to be different from the gamma tap voltage applied to the frames other than the scene change time, so that the problem of color coordinate distortion due to the change in the anode reset voltage at the scene change time can be prevented.

[0178] The effects according to the present application are not limited to the above-described examples, and other various effects can be included in the present specification.

[0179] Although the present application has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details can be made therein without departing from the spirit and scope of the present application including those further set forth in the following claims.

[0180] The various embodiments described above can be combined to provide further embodiments. Various aspects of embodiments can be modified if necessary to employ concepts of the various embodiments to provide yet further embodiments.

[0181] These and other changes can be made to the embodiments in light of the above Specific Description. In general, the selected terminology is used to describe the embodiments, but a person skilled in the art will recognize that equivalents can be used in place of the selected terminology. The description is thus to be regarded as illustrative instead of restrictive on the described embodiments.

Claims

1. A display device, comprising: The display panel includes an active area having a plurality of pixels; A source driver is configured to divide a gamma reference voltage to generate a data voltage for implementing image grayscale levels and to provide the data voltage to pixels among a plurality of pixels in the active region; as well as A reset voltage control circuit is configured to, during a scene change time with respect to at least a portion of the active region, change the anode reset voltage used to discharge the light-emitting elements of the pixels among the plurality of pixels to a level different from a first level, and provide the anode reset voltage to the pixels of at least a portion of the active region.

2. The display device according to claim 1, wherein the reset voltage control circuit restores the anode reset voltage to the first level in a subsequent frame after the scene change time.

3. The display device of claim 1, further comprising a gate driver configured to generate a scan signal and provide the scan signal to pixels in the at least partial region during the scene change time. The scan signal defines a first OBS period and a second OBS period for pixels in the at least partial region. The first OBS time period and the second OBS time period overlap with the non-emitting time periods of the pixels in the at least part of the region. During the second OBS period, the modified anode reset voltage is provided to the pixels in at least a portion of the region. The first OBS time period is scheduled before the data voltage provision time for pixels in the at least partial region. The second OBS time period is arranged between the data voltage provision time of the pixels with respect to the at least partial region and the emission time of the pixels with respect to the at least partial region.

4. The display device according to claim 1, wherein, Under the condition that the image grayscale level of the data voltage provided to the pixels of the at least partial region decreases from the grayscale level of the white image in the previous frame to the grayscale level of the black image at the scene change time, the reset voltage control circuit is configured to shift the anode reset voltage to a second level lower than the first level, and after shifting the anode reset voltage to the second level, provide the anode reset voltage of the second level to the pixels of the at least partial region during the scene change time.

5. The display device of claim 1, wherein, under the condition that the image grayscale level of the data voltage provided to the pixels of the at least partial region shifts from the grayscale level of the black image of the previous frame to the grayscale level of the white image at the scene change time, the reset voltage control circuit is configured to shift the anode reset voltage to a third level higher than the first level, and after shifting the anode reset voltage to the third level, provide the anode reset voltage of the third level to the pixels of the at least partial region during the scene change time.

6. The display device of claim 4, wherein the reset voltage control circuit is configured to provide the second-level anode reset voltage to the pixels of the entire active region including the at least partial region during the scene change time. The anode reset voltage is configured to return to the first level in a frame after the scene change time.

7. The display device of claim 5, wherein the reset voltage control circuit is configured to provide the third-level anode reset voltage to the pixels of the entire active region including the at least partial region during the scene change time. The anode reset voltage is configured to return to the first level in a frame after the scene change time.

8. The display device as claimed in claim 1, wherein, When the scene changes, and a white image corresponding to a pixel in the first region of the active region scrolls downwards in an active region having a black image corresponding to a pixel in the second region of the active region as a background, the reset voltage control circuit is configured to: The anode reset voltage is shifted to a second level lower than the first level, and after shifting the anode reset voltage to the second level, the second level anode reset voltage is provided to the pixels of the first pixel row for the grayscale reduction condition. The anode reset voltage is shifted to a third level higher than the first level, and after shifting the anode reset voltage to the third level, the anode reset voltage of the third level is provided to the pixels of the second pixel row for the grayscale increase condition. in: The image grayscale levels implemented in the first pixel row are configured to shift from the white image to the black image by scrolling down in response to the grayscale decrease condition. The image grayscale level implemented in the second pixel row is configured to shift from the black image to the white image by scrolling down in response to the grayscale increase condition.

9. The display device according to claim 8, wherein, Change time through multiple scenarios. The positions of the first pixel row to which the second-level anode reset voltage is provided and the positions of the second pixel rows to which the third-level anode reset voltage is provided are configured to be shifted sequentially on a pixel-row basis. The anode reset voltage is configured to return to the first level in frames following the multiple scene change times.

10. The display device according to claim 1, wherein the reset voltage control circuit comprises: A memory configured to store voltage level information regarding the first level, a second level below the first level, and a third level above the first level; An image change detector, configured to detect the amount of grayscale change in the current frame relative to the previous frame, on a target region basis; as well as A reset voltage output unit is configured to select voltage level information about one of the first level, the second level, and the third level based on the image grayscale change in a unit of the target area, and output an anode reset voltage corresponding to the selected voltage level information in a unit of the target area.

11. The display device according to claim 1, further comprising: A gamma memory configured to store tap voltage information, the tap voltage information including a plurality of first gamma tap voltages corresponding to a default condition, a plurality of second gamma tap voltages corresponding to a grayscale decrease condition, and a plurality of third gamma tap voltages corresponding to a grayscale increase condition, wherein in the grayscale decrease condition, the image grayscale level of the target area of ​​the active region shifts from a white image to a black image, and in the grayscale increase condition, the image grayscale level of the target area of ​​the active region shifts from the black image to the white image; as well as A gamma voltage circuit is configured to generate the plurality of first gamma tap voltages and output the plurality of first gamma tap voltages as gamma reference voltages to the source driver when the anode reset voltage of the first level matches the target region of the active region under the default conditions. When the anode reset voltage at a second level lower than the first level matches the target region of the active region under the grayscale decrease condition, the plurality of second gamma tap voltages are generated and the plurality of second gamma tap voltages are output to the source driver as the gamma reference voltage. Furthermore, when the anode reset voltage at a third level higher than the first level matches the target region of the active region under the grayscale increase condition, the plurality of third gamma tap voltages are generated and the plurality of third gamma tap voltages are output to the source driver as the gamma reference voltage.

12. The display device according to claim 10, wherein, The target area is set to all pixel rows of the active area, or to one pixel row of the active area.

13. The display device according to claim 11, wherein the image grayscale level includes a first grayscale range including a first grayscale level and a second grayscale range including a second grayscale level, the second grayscale level being larger than the first grayscale level. The levels of one of the plurality of first gamma tap voltages, one of the plurality of second gamma tap voltages, and one of the plurality of third gamma tap voltages, corresponding to the same color and the same grayscale level, are different in the first grayscale range.

14. The display device according to claim 13, wherein, The levels of one of the plurality of first gamma tap voltages, one of the plurality of second gamma tap voltages, and one of the plurality of third gamma tap voltages corresponding to the same color and the same grayscale level are equal to each other within the second grayscale range.

15. A driving method for a display device, the display device including an active region, the active region including a plurality of pixels, the driving method comprising: The gamma reference voltage is divided to generate data voltages for achieving image grayscale levels, and the data voltages are provided to pixels in a plurality of pixels in the active region; as well as During a scene change time when the image grayscale change of the first region of the active region is equal to or greater than a reference value, the anode reset voltage used to discharge the light-emitting element of the pixel among the plurality of pixels is changed to a different level than the first level, and the anode reset voltage is provided to the pixel of the first region of the active region.

16. The driving method according to claim 15, further comprising: The anode reset voltage is restored to the first level in a frame after the scene change time.

17. A display device, comprising: The display panel includes an active area having a plurality of pixels; A source driver configured to generate a data voltage for implementing image grayscale levels and to provide the data voltage to a pixel among the plurality of pixels; and A reset voltage control circuit is configured to change the anode reset voltage to be supplied to the pixel between different voltage levels based on the change in the image grayscale level of the data voltage corresponding to the pixel.

18. The display device of claim 17, wherein the reset voltage control circuit is configured to change the anode reset voltage to a first level lower than the default level when the image grayscale level of the data voltage changes from a white image to a black image.

19. The display device of claim 17, wherein the reset voltage control circuit is configured to change the anode reset voltage to a second level higher than the default level when the image grayscale level of the data voltage changes from a black image to a white image.

20. The display device of claim 17, wherein the reset voltage control circuit is configured to change the first anode reset voltage to be provided to the first pixel to a first level lower than the default level when the first image grayscale level of the first data voltage of the first pixel in the plurality of pixels changes from a white image to a black image, and is configured to change the second anode reset voltage to be provided to the second pixel to a second level higher than the default level when the second image grayscale level of the second data voltage of the second pixel in the plurality of pixels changes from a black image to a white image.

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