Quadrature clock correction circuit, chip and electronic equipment

Abstract

The embodiment of the invention discloses an orthogonal clock correction circuit, a chip and electronic equipment. An original phase delay line, a reverse phase delay line and a trigger subunit are arranged in an orthogonal clock correction circuit, a rising edge of an initial orthogonal clock signal is delayed based on the original phase delay line, and a falling edge of the initial orthogonal clock signal is delayed based on the reverse phase delay line and the trigger subunit. According to the embodiment of the invention, on the premise that the cost is not increased too much, the duty ratio correction of the transmitted orthogonal clock signal can be realized, and meanwhile, the correction precision of the duty ratio of the transmitted orthogonal clock signal can be ensured.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of clock correction, and more particularly, to a quadrature clock correction circuit, a chip and an electronic device. BACKGROUND

[0002] In a system such as an interconnection chip and a high bandwidth memory (HBM) high-speed interface, due to problems such as driving asymmetry, channel loss, reflection and power supply noise in the transmission process, the duty cycle of the clock signal will deviate from the ideal value when it is transmitted to the required circuit, which will lead to the decline of the efficiency and stability of the system. And in this process, since the quadrature clock signal is usually used as the basis for correcting other clock signals, the duty cycle correction of the transmitted quadrature clock signal is particularly important. However, the existing quadrature clock correction circuit is difficult to realize the duty cycle correction of the transmitted quadrature clock signal without increasing the cost too much, and it is also difficult to ensure the correction accuracy of the duty cycle of the transmitted quadrature clock signal. SUMMARY

[0003] Therefore, the embodiments of the present application provide a quadrature clock correction circuit, a chip and an electronic device to realize the duty cycle correction of the transmitted quadrature clock signal without increasing the cost too much, and ensure the correction accuracy of the duty cycle of the transmitted quadrature clock signal.

[0004] In a first aspect, the embodiments of the present application aim to provide a quadrature clock correction circuit, which comprises: two duty cycle adjustment units, respectively used for adjusting the duty cycle of the first clock signal and the second clock signal corresponding thereto, wherein the first clock signal and the second clock signal are initial quadrature clock signals having a 90-degree phase difference with respect to each other, the duty cycle adjustment unit comprises an inverting selector, a non-inverting delay line, an inverting delay line and a trigger sub-unit, the inverting selector is used to output an inverted signal of a selected signal from a plurality of received signals, the plurality of received signals at least include a corresponding clock signal, the non-inverting delay line is used to delay the rising edge of the corresponding clock signal, the inverting delay line is used to delay the rising edge of the inverted signal, and the trigger sub-unit is used to generate a corresponding clock adjustment signal based on the signals output by the non-inverting delay line and the inverting delay line, the rising edge and the falling edge of the clock adjustment signal are triggered based on the rising edges of the signals output by the non-inverting delay line and the inverting delay line, respectively; a duty cycle detection unit arranged at the end of a clock transmission path, used for detecting the duty cycle of the signals output by the two duty cycle adjustment units at the end of the clock transmission path; and a control unit configured to set a delay parameter of the non-inverted delay line and / or the inverted delay line based on a delay setting signal.

[0005] In a second aspect, an embodiment of the present application aims to provide a chip, which comprises: The orthogonal clock correction circuit as claimed in the first aspect.

[0006] In a third aspect, an embodiment of the present application aims to provide an electronic device, which comprises: The chip as claimed in the second aspect.

[0007] The orthogonal clock correction circuit of the embodiment of the present application comprises two duty cycle adjustment units, a duty cycle detection unit and a control unit. The two duty cycle adjustment units are respectively configured to adjust the duty cycle of a first clock signal and a second clock signal. The first clock signal and the second clock signal are initial orthogonal clock signals having a 90-degree phase difference with respect to each other. The duty cycle adjustment unit comprises an inverted selector, a non-inverted delay line, an inverted delay line and a trigger sub-unit. The inverted selector is configured to output an inverted signal of a selected signal from a plurality of received signals. The plurality of received signals at least comprises a corresponding clock signal. The non-inverted delay line is configured to delay a rising edge of the corresponding clock signal. The inverted delay line is configured to delay a rising edge of the inverted signal. The trigger sub-unit is configured to generate a corresponding clock adjustment signal based on the signals output by the non-inverted delay line and the inverted delay line. The rising edge and the falling edge of the clock adjustment signal are triggered based on the rising edges of the signals output by the non-inverted delay line and the inverted delay line, respectively. The duty cycle detection unit is configured to detect the duty cycles of the signals output by the two duty cycle adjustment units at the end of a clock transmission path. The control unit is configured to set the delay parameters of the non-inverted delay line and the inverted delay line based on a delay setting signal.

[0008] Thus, by setting the non-inverted delay line, the inverted delay line and the trigger sub-unit in the orthogonal clock correction circuit, and delaying the rising edge of the initial orthogonal clock signal based on the non-inverted delay line and delaying the falling edge of the initial orthogonal clock signal based on the inverted delay line and the trigger sub-unit, the embodiment of the present application can correct the duty cycle of the transmitted orthogonal clock signal without increasing the cost too much, and can also ensure the correction accuracy of the duty cycle of the transmitted orthogonal clock signal. BRIEF DESCRIPTION OF DRAWINGS

[0009] The above and other objects, features and advantages of the present application will become more apparent from the following description of embodiments of the present application taken in conjunction with the accompanying drawings, in which: Figure 1 FIG. 1 is a schematic diagram of an orthogonal clock correction circuit according to an embodiment of the present application; Figure 2 FIG. 2 is a schematic diagram of the waveforms of various signals in the orthogonal clock correction circuit according to an embodiment of the present application. Figure 3 a schematic diagram of another orthogonal clock correction circuit according to an embodiment of the present application; Figure 4 a schematic diagram of a trigger subunit according to an embodiment of the present application; Figure 5 a schematic diagram of signal waveforms in a trigger subunit according to an embodiment of the present application; Figure 6 a schematic diagram of a rising edge detection module according to an embodiment of the present application; Figure 7 a schematic diagram of a combinational logic module according to an embodiment of the present application; Figure 8 a schematic diagram of a duty cycle detection unit according to an embodiment of the present application; Figure 9 a schematic diagram of another orthogonal clock correction circuit according to an embodiment of the present application. DETAILED DESCRIPTION

[0010] The present application is described below based on embodiments, but the present application is not limited to these embodiments. In the following detailed description of the present application, some specific details are described in detail. The present application can also be fully understood without the description of these details by those skilled in the art. In order to avoid confusion of the essence of the present application, well-known methods, processes, procedures, elements and circuits are not described in detail.

[0011] In addition, those of ordinary skill in the art will understand that the drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.

[0012] At the same time, it should be understood that in the following description, "circuit" refers to a conductive loop composed of at least one element or sub-circuit through electrical or electromagnetic connection. When an element or circuit is said to be "connected to" another element or said to be "connected between" two nodes, it can be directly coupled or connected to another element or there can be intermediate elements between the elements, and the connection between the elements can be physical, logical, or a combination thereof. On the contrary, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there is no intermediate element between the two.

[0013] Unless the context clearly requires otherwise, throughout the present application, the words "comprise", "comprises", and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is to say, in the sense of "including, but not limited to".

[0014] In the description of the present application, it should be understood that the terms "first", "second", etc. are only for the purpose of description and cannot be understood as indicating or implying relative importance. In addition, in the description of the present application, unless otherwise stated, the meaning of "multiple" is two or more.

[0015] It is to be noted that the quadrature clock signals can refer to a pair of clock signals having a 90-degree phase difference with respect to each other. In the following description, for the sake of distinction, the two clock signals in the initial quadrature clock signals will be referred to as a first clock signal clk_0P and a second clock signal clk_90P, respectively.

[0016] Figure 1 A schematic diagram of a quadrature clock correction circuit according to an embodiment of the present application is shown in FIG. 1. As shown in FIG. 1, the quadrature clock correction circuit 1 can include a duty cycle adjustment unit 11, a duty cycle adjustment unit 12, a duty cycle detection unit 13, and a control unit 14. Figure 1

[0017] In the embodiment of the present application, the duty cycle adjustment unit 11 and the duty cycle adjustment unit 12 can correspond to the first clock signal clk_0P and the second clock signal clk_90P, respectively. The duty cycle adjustment unit 11 and the duty cycle adjustment unit 12 can be configured to adjust the duty cycle of the corresponding first clock signal clk_0P and the second clock signal clk_90P, respectively.

[0018] Further, the duty cycle adjustment unit 11 can be configured to include an inverter selector 111, a non-inverted delay line 112, an inverted delay line 113, and a trigger subunit 114. The inverter selector 111 can be configured to output an inverted signal of a selected signal from a plurality of received signals. Here, the plurality of received signals of the inverter selector 111 can be configured to include at least the first clock signal clk_0P corresponding to the duty cycle adjustment unit 11. In the current embodiment, the first clock signal clk_0P is specifically taken as the selected signal. The non-inverted delay line 112 can be configured to delay the rising edge of the first clock signal clk_0P corresponding to the duty cycle adjustment unit 11 to output a signal clk_lead. The inverted delay line 113 can be configured to delay the rising edge of the inverted signal output by the inverter selector 111 to output a signal clk_lag. The trigger subunit 114 can be configured to generate a corresponding clock adjustment signal based on the signals clk_lead and clk_lag output by the non-inverted delay line 112 and the inverted delay line 113. Here, the rising edge and the falling edge of the clock adjustment signal can be triggered based on the rising edges of the signals clk_lead and clk_lag output by the non-inverted delay line 112 and the inverted delay line 113, respectively. The clock adjustment signal can be output as an output signal clk_dca_0P of the duty cycle adjustment unit 11.

[0019] Figure 2 A schematic diagram of the waveforms of various signals in the quadrature clock correction circuit according to an embodiment of the present application is shown in FIG. 2. As shown in FIG. 2, the quadrature clock correction circuit 1 can include a duty cycle adjustment unit 11, a duty cycle adjustment unit 12, a duty cycle detection unit 13, and a control unit 14. Figure 2 ​As shown, for the first clock signal clk_0P, after being input into the duty cycle adjustment unit 11 corresponding thereto, the first clock signal clk_0P can be transmitted to the non-inverted delay line 112 and the inverter selector 111 at the same time. Upon receiving the first clock signal clk_0P, the non-inverted delay line 112 can delay the rising edge of the first clock signal clk_0P to output a signal clk_lead. Also, upon receiving the first clock signal clk_0P, the inverter selector 111 can take the first clock signal clk_0P as a selected signal, and output an inverted signal of the first clock signal clk_0P to the inverted delay line 113. The inverted delay line 113 can delay the rising edge of the inverted signal to output a signal clk_lag. Further, the signal clk_lead and the signal clk_lag are transmitted to the trigger sub-unit 114. The trigger sub-unit 114 can perform rising edge triggering based on the rising edge of the signal clk_lead, and falling edge triggering based on the rising edge of the signal clk_lag, thereby outputting a corresponding clock adjustment signal. Finally, the clock adjustment signal will be output as the output signal clk_dca_0P of the duty cycle adjustment unit 11.

[0020] Further, the duty cycle adjustment unit 12 can be configured to include an inverter selector 121, a non-inverted delay line 122, an inverted delay line 123, and a trigger sub-unit 124. The inverter selector 121 can be configured to output an inverted signal of a selected signal from a plurality of received signals. Here, the plurality of received signals of the inverter selector 121 can be configured to include at least the second clock signal clk_90P corresponding to the duty cycle adjustment unit 12. In the current embodiment, the second clock signal clk_90P is specifically taken as the selected signal. The non-inverted delay line 122 can be configured to delay the rising edge of the second clock signal clk_90P corresponding to the duty cycle adjustment unit 12 to output a signal clk_lead'. The inverted delay line 123 can be configured to delay the rising edge of the inverted signal output by the inverter selector 121 to output a signal clk_lag'. The trigger sub-unit 124 can be configured to generate a corresponding clock adjustment signal based on the signals clk_lead' and clk_lag' output by the non-inverted delay line 122 and the inverted delay line 123. Here, the rising edge and the falling edge of the clock adjustment signal can be triggered based on the rising edges of the signals clk_lead' and clk_lag' output by the non-inverted delay line 122 and the inverted delay line 123, respectively. The clock adjustment signal can be output as the output signal clk_dca_90P of the duty cycle adjustment unit 12.

[0021] As Figure 2As shown, for the second clock signal clk_90P, after being input into the corresponding duty cycle adjustment unit 12, the second clock signal clk_90P can be transmitted to the non-inverted delay line 122 and the inverting selector 121 at the same time. Upon receiving the second clock signal clk_90P, the non-inverted delay line 122 can delay the rising edge of the second clock signal clk_90P to output the signal clk_lead'. Also, upon receiving the second clock signal clk_90P, the inverting selector 121 can take the second clock signal clk_90P as the selected signal, and output the inverted signal of the second clock signal clk_90P to the inverted delay line 123. The inverted delay line 123 can delay the rising edge of the inverted signal to output the signal clk_lag'. Further, the signal clk_lead' and the signal clk_lag' can be transmitted to the trigger sub-unit 124. The trigger sub-unit 124 can perform rising edge triggering based on the rising edge of the signal clk_lead', and perform falling edge triggering based on the rising edge of the signal clk_lag', thereby outputting the corresponding clock adjustment signal. Finally, the clock adjustment signal will be output as the output signal clk_dca_90P of the duty cycle adjustment unit 12.

[0022] In the embodiment of the present application, the signals clk_dca_0P and clk_dca_90P output by the duty cycle adjustment unit 11 and the duty cycle adjustment unit 12 can be transmitted to the required circuits via the clock transmission path 15. It is intended to distinguish the signals output by the duty cycle adjustment unit 11 and the duty cycle adjustment unit 12 before and after being transmitted by the clock transmission path 15. Before being transmitted by the clock transmission path 15, the signals output by the duty cycle adjustment unit 11 and the duty cycle adjustment unit 12 will be represented as the signals clk_dca_0P and clk_dca_90P. After being transmitted by the clock transmission path 15, the signals output by the duty cycle adjustment unit 11 and the duty cycle adjustment unit 12 will be represented as the signals clk_dca_0P_d and clk_dca_90P_d. The duty cycle detection unit 13 can be arranged at the end of the clock transmission path 15, which can be used to detect the duty cycles of the signals clk_dca_0P_d and clk_dca_90P_d output by the duty cycle adjustment unit 11 and the duty cycle adjustment unit 12 at the end of the clock transmission path 15. Alternatively, the clock transmission path 15 can be any clock transmission path including clock tree, and the present application does not make too many limitations on this.

[0023] In the embodiment of the present application, the control unit 14 can be configured to set the delay parameters of the non-inverting delay lines (including the non-inverting delay line 112 in the duty cycle adjustment unit 11 and the non-inverting delay line 122 in the duty cycle adjustment unit 12) and / or the inverting delay lines (including the inverting delay line 113 in the duty cycle adjustment unit 11 and the inverting delay line 123 in the duty cycle adjustment unit 12) based on the delay setting signals (such as the signals dca_0P, dca_180P, dca_90P and dca_270P).

[0024] Optionally, as an implementation manner, the delay setting signals can be set and output to the control unit 14 by a relevant person or a software program according to the detection results output by the duty cycle detection unit 13. Alternatively, as another implementation manner, the delay setting signals can also be determined by the control unit 14 according to the detection results and the pre-set duty cycle requirement value after the detection results are output to the control unit 14 by the duty cycle detection unit 13, and the present application does not limit this.

[0025] In Figure 1 In the orthogonal clock correction circuit shown in FIG. 1, the correction process of the duty cycle adjustment units on the signals clk_dca_0P_d and clk_dca_90P_d can be essentially regarded as a process of delaying the rising edge of the initial orthogonal clock signal by using the non-inverting delay line and delaying the falling edge of the initial orthogonal clock signal by using the inverting delay line and the trigger sub-unit. Based on setting the delay parameters of the non-inverting delay line and / or the inverting delay line, the embodiment of the present application can realize the duty cycle correction of the signals clk_dca_0P_d and clk_dca_90P_d in different scenarios, so that the duty cycles of the signals clk_dca_0P_d and clk_dca_90P_d meet the ideal value (for example, 50%).

[0026] It is intended to be explained that, Figure 2 and Figure 3 The signal waveform diagram shown in FIG. 2 can be the waveform diagram at each end point in the circuit after the duty cycle correction of the signals clk_dca_0P_d and clk_dca_90P_d is completed, so that the duty cycles of the signals clk_dca_0P_d and clk_dca_90P_d meet the ideal value (that is, the two signals have a 90-degree phase difference relative to each other, and the duty cycles of the two signals are both 50%). Meanwhile, it is intended to be explained that, Figure 2 The signal waveform diagram given in FIG. 2 is only for illustration. In actual application process, since different clock transmission paths have different influences on the duty cycle and phase of the transmitted signals, the signal waveform diagrams corresponding to the different clock transmission paths are also different.

[0027] Optionally, at the end of the clock transmission path 15, due to problems such as drive asymmetry, channel loss, reflection, and power supply noise that exist in the clock transmission path 15 during the transmission of clock signals, the phase of signals clk_dca_0P_d and clk_dca_90P_d may no longer satisfy the 90-degree phase difference, and there may also be a phase difference between signals clk_dca_0P_d and clk_dca_90P_d (for example, the duty cycle of signal clk_dca_0P_d is 65%, and the duty cycle of signal clk_dca_90P_d is 60%).

[0028] In this embodiment of the invention, in order to correct the duty cycle and phase of signals clk_dca_0P_d and clk_dca_90P_d so that their duty cycle and phase meet ideal values, the delay parameters of the pre-phase delay line and the anti-phase delay line can be set sequentially as a correction method. Specifically, by uniformly or separately setting the delay parameters of the pre-phase delay lines in the two duty cycle adjustment units, the two duty cycle adjustment units can uniformly or separately delay the rising edge of the initial quadrature clock signal, thereby ensuring that the phase difference between signals clk_dca_0P_d and clk_dca_90P_d meets a 90-degree difference, and initially adjusting the duty cycle of signals clk_dca_0P_d and clk_dca_90P_d. Furthermore, by uniformly or separately setting the delay parameters of the inverting delay lines in the two duty cycle adjustment units, the two duty cycle adjustment units can uniformly or separately delay the falling edge of the initial quadrature clock signal, thereby ensuring that the duty cycles of signals clk_dca_0P_d and clk_dca_90P_d ultimately meet the ideal value.

[0029] For example, in the initial state (that is, when the delay parameters of both the inverting delay line and the non-inverting delay line are set to default parameters), if the signal clk_dca_0P_d is detected to be 70 degrees ahead of clk_dca_90P_d, this embodiment can first have the control unit output the corresponding signal dca_0P or dca_90P to individually set the delay parameter of the inverting delay line in the duty cycle adjustment unit corresponding to the first clock signal clk_0P, or to individually set the delay parameter of the inverting delay line in the duty cycle adjustment unit corresponding to the second clock signal clk_90P, so that the signal clk_dca_0P_d is 90 degrees ahead of clk_dca_90P_d.

[0030] Further, the embodiment can output corresponding signals dca_0P and dca_90P by the control unit to synchronously adjust the delay parameters of the non-inverted delay line in the duty cycle adjustment unit corresponding to the first clock signal clk_0P and the delay parameters of the non-inverted delay line in the duty cycle adjustment unit corresponding to the second clock signal clk_90P, so that the duty cycles of the signals clk_dca_0P_d and clk_dca_90P_d are preliminarily corrected to approximately 50% on the premise that the 90-degree phase difference is maintained unchanged.

[0031] Finally, the embodiment can output corresponding signals dca_180P and / or dca_270P by the control unit to set the delay parameters of the inverted delay line in the duty cycle adjustment unit corresponding to the first clock signal clk_0P and / or the delay parameters of the inverted delay line in the duty cycle adjustment unit corresponding to the second clock signal clk_90P, so that the duty cycles of the signals clk_dca_0P_d and clk_dca_90P_d are accurately corrected to 50%.

[0032] It is intended to be explained that when the non-inverted delay lines in the two duty cycle adjustment units have the same delay parameters, the two duty cycle adjustment units are equivalent to delaying the first clock signal clk_0P and the second clock signal clk_90P by the same value, and this delay operation actually does not introduce additional duty cycle deviation or phase deviation for the quadrature clock signal. Therefore, on the basis of the above characteristics, in order to enable the two duty cycle adjustment units to adjust the phase and duty cycle of clk_dca_0P_d and clk_dca_90P_d by reducing the delay value (i.e., reducing the delay parameter on the basis of the default parameter), the default parameter can be set to a corresponding reasonable value. It should be understood that in some embodiments, the default parameter can also be set to 0.

[0033] Optionally, in the actual correction process, after the delay parameters of the non-inverted delay lines in the two duty cycle adjustment units are uniformly set or respectively set, the duty cycles and phases of the signals clk_dca_0P_d and clk_dca_90P_d can have met the ideal values, at this time, in order to avoid triggering the sub-unit to introduce additional signal delay (compared with the actively set delay, the delay here is the delay that inevitably occurs in the signal conversion process of the triggering sub-unit, such as Figure 2As shown, clk_lead, clk_lag, signal clk_lead' and clk_lag' will all generate corresponding delay after being converted into corresponding clock adjustment signals by the trigger subunit), the duty cycle adjustment unit can also be configured to include an output selector. The output selector can be used to receive a selection signal, and output the clock adjustment signal output by the trigger subunit as the output signal of the duty cycle adjustment unit, or output the signal output by the original phase delay line as the output signal of the duty cycle adjustment unit based on the selection signal.

[0034] Figure 3 The figure is a schematic diagram of another orthogonal clock correction circuit of an embodiment of the present application. As shown, in addition to the inverting selector 311, the original phase delay line 312, the inverting delay line 313 and the trigger subunit 314, the duty cycle adjustment unit 31 also includes an output selector 315. In addition to the inverting selector 321, the original phase delay line 322, the inverting delay line 323 and the trigger subunit 324, the duty cycle adjustment unit 32 also includes an output selector 325. Figure 3

[0035] Among them, the output selector 315 and the output selector 325 can be respectively arranged between the trigger subunit and the clock transmission path 45 of the duty cycle adjustment unit where they are located. The output selector 315 can be used to receive a selection signal, and output the clock adjustment signal output by the trigger subunit 314 as the output signal of the duty cycle adjustment unit 31, or output the signal clk_lead output by the original phase delay line 312 as the output signal of the duty cycle adjustment unit 31 based on the selection signal. The output selector 325 can be used to receive a selection signal, and output the clock adjustment signal output by the trigger subunit 324 as the output signal of the duty cycle adjustment unit 32, or output the signal clk_lead output by the original phase delay line 322 as the output signal of the duty cycle adjustment unit 32 based on the selection signal. Alternatively, the selection information can be specifically set by relevant personnel according to the actual correction situation and the correction demand for the signal clk_dca_0P_d and clk_dca_90P_d, which is not limited in the present application.

[0036] Alternatively, in the actual correction process, to support the correction flexibility of the signal dca_180P or dca_270P, the multiple receiving signals of the inverting selector can also be configured to include the signal output by the original phase delay line.

[0037] As shown, Figure 3 ​As shown, the inverting selector 311 in the duty cycle adjustment unit 31 can be connected with the output terminal of the non-inverting delay line 312 in addition to the input terminal of the first clock signal clk_0P. At this time, the signals received by the inverting selector 311 can include the first clock signal clk_0P and the signal clk_lead simultaneously. The inverting selector 311 can output the inverted signal of the selected signal among the first clock signal clk_0P and the signal clk_lead. Also, the inverting selector 321 in the duty cycle adjustment unit 32 can be connected with the output terminal of the non-inverting delay line 322 in addition to the input terminal of the second clock signal clk_90P. At this time, the signals received by the inverting selector 321 can include the second clock signal clk_90P and the signal clk_lead' simultaneously. The inverting selector 311 can output the inverted signal of the selected signal among the second clock signal clk_90P and the signal clk_lead'. It should be understood that the inverting selector 311 and the inverting selector 321 can determine the selected signal based on the corresponding selection information (such as the information dca_fcode_sel and dca_fcode_sel') received. Alternatively, the selection information can be set by the relevant personnel according to the actual correction situation and the correction requirement of the signals clk_dca_0P_d and clk_dca_90P_d, which is not limited in the present application.

[0038] Alternatively, as an implementation manner, the trigger subunit can be implemented by setting corresponding rising edge detection modules and combination logic modules.

[0039] Figure 4 A schematic diagram of the trigger subunit of the embodiment of the present application is shown in FIG. 4. As shown in FIG. 4, the trigger subunit 41 can be a trigger subunit (such as the trigger subunit 114 shown in FIG. 1 and the trigger subunit 314 shown in FIG. 3) set in the duty cycle adjustment unit corresponding to the first clock signal. Figure 4 As shown in FIG. 4, the trigger subunit 41 can be a trigger subunit (such as the trigger subunit 114 shown in FIG. 1 and the trigger subunit 314 shown in FIG. 3) set in the duty cycle adjustment unit corresponding to the first clock signal. Figure 1 As shown in FIG. 4, the trigger subunit 41 can be a trigger subunit (such as the trigger subunit 114 shown in FIG. 1 and the trigger subunit 314 shown in FIG. 3) set in the duty cycle adjustment unit corresponding to the first clock signal. Figure 3 As shown in FIG. 4, the trigger subunit 41 can be a trigger subunit (such as the trigger subunit 114 shown in FIG. 1 and the trigger subunit 314 shown in FIG. 3) set in the duty cycle adjustment unit corresponding to the first clock signal. Figure 1 As shown in FIG. 4, the trigger subunit 41 can be a trigger subunit (such as the trigger subunit 114 shown in FIG. 1 and the trigger subunit 314 shown in FIG. 3) set in the duty cycle adjustment unit corresponding to the first clock signal. Figure 3 As shown in FIG. 4, the trigger subunit 41 can be a trigger subunit (such as the trigger subunit 114 shown in FIG. 1 and the trigger subunit 314 shown in FIG. 3) set in the duty cycle adjustment unit corresponding to the first clock signal.

[0040] In the embodiment of the present application, the trigger subunit 41 can be used to generate the corresponding clock adjustment signal based on the signal clk_lead and the signal clk_lag. The trigger subunit 42 can be used to generate the corresponding clock adjustment signal based on the signal clk_lead' and the signal clk_lag'.

[0041] Furthermore, the trigger subunit 41 may include a rising edge detection module 411, a rising edge detection module 412, and a combinational logic module 413. The rising edge detection modules 411 and 412 can be connected to the in-phase delay line and the out-of-phase delay line within their respective duty cycle adjustment units to receive the signals clk_lead and clk_lag. The rising edge detection modules 411 and 412 can be used to detect the rising edges of the signals clk_lead and clk_lag, respectively, to output a first pulse sequence and a second pulse sequence. The combinational logic module 413 can be used to output a clock adjustment signal based on the first and second pulse sequences.

[0042] It should be noted that, in the embodiments of the present invention, both the first pulse sequence and the second pulse sequence include multiple pulse signals. Each pulse signal in the first pulse sequence can be used to characterize a corresponding rising edge in the signal output by the original phase delay line, while each pulse signal in the second pulse sequence can be used to characterize a corresponding rising edge in the signal output by the inverting phase delay line.

[0043] Figure 5 This is a schematic diagram of the signal waveforms within the trigger subunit of an embodiment of the present invention. For example... Figure 5 As shown, for the signal clk_lead, the signal clk_lead can be input to the rising edge detection module 411. Upon receiving the signal clk_lead, the rising edge detection module 411 can perform rising edge detection on the signal clk_lead to output a first pulse sequence set_pulse. Each pulse signal in the first pulse sequence set_pulse can be used to characterize the corresponding rising edge in the signal clk_lead. For the signal clk_lag, the signal clk_lag can be input to the rising edge detection module 412. Upon receiving the signal clk_lag, the rising edge detection module 412 can perform rising edge detection on the signal clk_lag to output a second pulse sequence reset_pulse. Each pulse signal in the second pulse sequence reset_pulse can be used to characterize the corresponding rising edge in the signal clk_lag. Furthermore, the first pulse sequence set_pulse and the second pulse sequence reset_pulse can be output uniformly to the combinational logic module 413. The combinational logic module 413 can then output a clock adjustment signal (as shown by the signal clk_dca_0P) based on the first pulse sequence and the second pulse sequence.

[0044] Furthermore, the trigger subunit 42 may include a rising edge detection module 421, a rising edge detection module 422, and a combinational logic module 423. The rising edge detection module 421 and rising edge detection module 422 can be connected to the in-phase delay line and the out-of-phase delay line within the duty cycle adjustment unit, respectively, to receive the signals clk_lead' and clk_lag'. The rising edge detection module 421 and rising edge detection module 422 can be used to perform rising edge detection on the signals clk_lead' and clk_lag', respectively, to output a first pulse sequence and a second pulse sequence.

[0045] like Figure 5 As shown, for the signal clk_lead', the signal clk_lead' can be input to the rising edge detection module 421. Upon receiving the signal clk_lead', the rising edge detection module 421 can perform rising edge detection on the signal clk_lead' to output a first pulse sequence set_pulse'. Each pulse signal in the first pulse sequence set_pulse' can be used to characterize the corresponding rising edge in the signal clk_lead'. For the signal clk_lag', the signal clk_lag' can be input to the rising edge detection module 422. Upon receiving the signal clk_lag', the rising edge detection module 422 can perform rising edge detection on the signal clk_lag' to output a second pulse sequence reset_pulse'. Each pulse signal in the second pulse sequence reset_pulse' can be used to characterize the corresponding rising edge in the signal clk_lag'. Furthermore, the first pulse sequence set_pulse' and the second pulse sequence reset_pulse' can be uniformly output to the combinational logic module 423. The combinational logic module 423 can output a clock adjustment signal (as shown by the signal clk_dca_90P) based on the first pulse sequence and the second pulse sequence.

[0046] Alternatively, as one implementation, the rising edge detection module can be implemented by a data trigger, a delay buffer, and a reset signal generator.

[0047] Figure 6 This is a schematic diagram of the rising edge detection module according to an embodiment of the present invention. It is intended to illustrate that... Figure 6 The rising edge detection module shown can specifically be Figure 4 The rising edge detection module 411 is used here. Since all rising edge detection modules have the same structure, this rising edge detection module will be used as an example to provide a unified explanation of the structure of each rising edge detection module. Figure 6 As shown, the rising edge detection module may include a data trigger 61, a delay buffer D, and a reset signal generator 62.

[0048] In the embodiment, the CLK terminal of the data trigger 61 can be connected with a leading-edge delay line in the duty cycle adjustment unit to receive a signal output by the leading-edge delay line, such as the signal clk_lead. The D terminal of the data trigger 61 can be connected with a high-level signal source tieh to provide a threshold voltage signal for the data trigger 61. The Q terminal of the data trigger 61 can be connected with the positive terminal of the delay buffer D. The negative terminal of the delay buffer D can be connected with the combinational logic module to serve as an output terminal of the rising edge detection module. Meanwhile, the negative terminal of the delay buffer D and the RST terminal of the data trigger 61 can be connected with the reset signal generator 62, which can provide a reset signal for the data trigger 61.

[0049] Specifically, in the rising edge detection module, the data trigger 61 can output a threshold voltage signal when detecting a rising edge of a received signal, such as the signal clk_lead. The delay buffer D can delay the threshold voltage signal output by the data trigger 61. The reset signal generator 62 can output a reset signal to the data trigger 61 in response to the threshold voltage signal collected from the output terminal of the delay buffer D. The data trigger 61 can stop outputting the threshold voltage signal when receiving the reset signal.

[0050] Thus, the data trigger 61 can output threshold voltage signals at intervals to form a first pulse sequence. Each pulse signal in the first pulse sequence can be used to represent a corresponding rising edge of the received signal.

[0051] It is to be noted that, in the rising edge detection module, the voltage value of the threshold voltage signal output by the data trigger can depend on the level of the high-level signal source tieh connected with the D terminal of the data trigger. The width of a single pulse signal output by the data trigger can depend on the delay time of the delay buffer D for the data trigger output signal. The above parameters can be set by relevant personnel according to actual needs, and the present application does not make too many limitations on this.

[0052] Optionally, as an implementation manner, the reset signal generator 62 can include an inverter and a signal generator. The inverter can convert the collected signal into an inverted signal. The signal generator can generate a reset signal based on the inverted signal. Further optionally, the working state of the signal generator can be controlled based on the signal rst_n.

[0053] Optionally, as an implementation manner, the combinational logic module can be implemented by a data trigger, a delay buffer and a reset signal generator.

[0054] Figure 7 Fig. 1 is a schematic diagram of a combinational logic module according to an embodiment of the present application. It is to be understood that, Figure 7 the combinational logic module shown in Fig. 1 can be the combinational logic module 413 in Fig. 4, Figure 4 herein, as the structures of the combinational logic modules are the same, the structure of the combinational logic module will be described uniformly by taking the combinational logic module as an example. As shown in Fig. 1, Figure 7 the combinational logic module can include a field effect transistor M1, a field effect transistor M2, a field effect transistor M3, a field effect transistor M4, a field effect transistor N1, a field effect transistor N2, an inverter D1 and an inverter D2. The series-connected field effect transistor M1 and field effect transistor M2 and the series-connected field effect transistor M3 and field effect transistor M4 can be connected in parallel between a high-level signal source tieh and a low-level signal source tiel. The parallel-connected inverter D1 and inverter D2 can be connected between a common terminal a of the field effect transistor M1 and field effect transistor M2 and a common terminal b of the field effect transistor M3 and field effect transistor M4. The field effect transistor N1 can be connected between the common terminal a and the high-level signal source tieh, and the field effect transistor N2 can be connected between the common terminal b and the low-level signal source tiel. Further, the common terminal b can be taken as an output terminal of the combinational logic module to output a signal clk_dca_0P.

[0055] It is to be understood that the field effect transistor N1 and field effect transistor N2 can be used to determine the working state of the combinational logic module under the control of a signal rst_n. When the combinational logic module is in the working state, the field effect transistor N1 and field effect transistor N2 can be equivalent to open circuit. Further optionally, the working state of the inverter D1 and inverter D2 can also be controlled based on the signal rst_n.

[0056] Optionally, the field effect transistor M1, field effect transistor M2, field effect transistor M3, field effect transistor M4 and field effect transistor N2 can be N-type MOS transistors, and the field effect transistor N1 can be a P-type MOS transistor.

[0057] In the above description, Figure 7In the combinational logic module shown, when in operation, through the cooperation of the field-effect transistors and inverters, when `set_pulse` is low and `reset_pulse` is high, the combinational logic module can output a corresponding low-level signal. When `set_pulse` is high and `reset_pulse` is low, the combinational logic module can output a corresponding high-level signal. When both `set_pulse` and `reset_pulse` are low, the combinational logic module can maintain its previous output. Therefore, the combinational logic module can output a corresponding clock adjustment signal based on the received first and second pulse sequences. The rising and falling edges of the clock adjustment signal can be triggered by the rising edges of the first and second pulse sequences, respectively.

[0058] Alternatively, as one implementation, the duty cycle detection unit may include a signal distribution subunit and a detection subunit.

[0059] Figure 8 This is a schematic diagram of the duty cycle detection unit according to an embodiment of the present invention. Figure 8 As shown, Figure 8 As shown, the duty cycle detection unit may include a signal distribution subunit 81 and a detection subunit 82.

[0060] In this embodiment of the invention, the signal distribution subunit 81 can be used to receive the signals output by the two duty cycle adjustment units, perform parallel-to-serial conversion on the signals output by the two duty cycle adjustment units to generate a high-speed clock signal, and transmit the signals output by the two duty cycle adjustment units and the high-speed clock signal.

[0061] Further, the signal distribution subunit 81 can include a transmission module 811, a transmission module 812 and a parallel-to-serial conversion module 813. The transmission module 811 can receive the signal clk_dca_0P_d output by the duty cycle adjustment unit corresponding to the first clock signal. After receiving the signal clk_dca_0P_d, the transmission module 811 can output the signal clk_dca_0P_d to the subsequent detection subunit 82, and simultaneously output the signal clk_dca_0P_d to the parallel-to-serial conversion module 813. It should be understood that, in order to distinguish the signal clk_dca_0P_d before and after transmission, the signal clk_dca_0P_d transmitted by the transmission module 811 will be referred to as the signal clk_dcm_0P. The transmission module 812 can receive the signal clk_dca_90P_d output by the duty cycle adjustment unit corresponding to the second clock signal to the parallel-to-serial conversion module 813. After receiving the signal clk_dca_90P_d, the transmission module 812 can output the signal clk_dca_90P_d to the subsequent detection subunit 82, and simultaneously output the signal clk_dca_90P_d to the parallel-to-serial conversion module 813. It should be understood that, in order to distinguish the signal clk_dca_90P_d before and after transmission, the signal clk_dca_90P_d transmitted by the transmission module 811 will be referred to as the signal clk_dcm_90P. When receiving the signals clk_dca_0P_d and clk_dca_90P_d transmitted by the transmission module 811 and the transmission module 812, the parallel-to-serial conversion module 813 can perform parallel-to-serial conversion on the signals clk_dca_0P_d and clk_dca_90P_d to generate a high-speed clock signal clk_dcm_p2s, and output the high-speed clock signal clk_dcm_p2s to the subsequent detection subunit 82.

[0062] Optionally, as an implementation manner, the transmission module 811 and the transmission module 812 can be single-ended differential modules. The signals transmitted by the transmission module 811 and the transmission module 812 to the parallel-to-serial conversion module 813 can be differential signal pairs determined based on the respective received signals. The signals transmitted by the transmission module 811 and the transmission module 812 to the detection subunit 82 can be positive differential signals in the differential signal pairs.

[0063] In the embodiment of the application, the detection subunit 82 can be configured to receive the signals transmitted by the signal distribution subunit, and perform duty cycle detection on the selected signal in the signals transmitted by the signal distribution subunit based on the selection signal to generate a duty cycle detection result dcm_out.

[0064] Further, the detection subunit 82 can include a detection selector 821, a common mode level detector 822 and a comparator 823. The detection selector 821 can receive the transmitted signal of the signal distribution subunit 81 and output a corresponding selected signal in the received signal based on a selection signal (e.g., dcm_sel). The common mode level detector 822 can detect the common mode level of the selected signal output by the detection selector 821. The comparator 823 can compare the common mode level with a preset voltage threshold signal (e.g., Vref) to generate a duty cycle detection result dcm_out (which is used to represent whether the current detection signal duty cycle meets the ideal value). Optionally, the selection signal can be set by relevant personnel according to actual correction conditions and correction requirements of the signals clk_dca_0P_d and clk_dca_90P_d, which is not limited in the present application.

[0065] Optionally, in the embodiment of the present application, the initial quadrature clock signal can be provided by an external circuit to the quadrature clock correction circuit, or can be generated by the quadrature clock correction circuit itself, which is not limited in the present application. When the initial quadrature clock signal is generated by the quadrature clock correction circuit itself, the quadrature clock correction circuit can include a signal generation unit.

[0066] Figure 9 Another schematic diagram of the quadrature clock correction circuit in the embodiment of the present application is shown in FIG. 9. As shown in FIG. 9, in addition to including the duty cycle adjustment unit, the duty cycle adjustment unit, the duty cycle detection unit and the control unit, the quadrature clock correction circuit can include a signal generation unit 91. Figure 9

[0067] In the embodiment of the present application, the signal generation unit 91 can be used to receive a data clock signal clk_in and generate a first clock signal and a second clock signal based on the data clock signal clk_in.

[0068] Further, the signal generation unit 91 can include a first frequency divider and a second frequency divider. As a kind of initial quadrature clock signal generation method, the signal generation unit 91 can specifically generate the first clock signal by performing frequency division processing on the data clock signal clk_in in a rising edge trigger manner through the first frequency divider, and generate the second clock signal by performing frequency division processing on the data clock signal clk_in in a falling edge trigger manner through the second frequency divider.

[0069] ​The quadrature clock correction circuit of this invention includes two duty cycle adjustment units, a duty cycle detection unit, and a control unit. The two duty cycle adjustment units are used to adjust the duty cycles of corresponding first and second clock signals, respectively. The first and second clock signals are initial quadrature clock signals with a 90-degree phase difference relative to each other. Each duty cycle adjustment unit includes an inverting selector, a pre-phase delay line, an inverting delay line, and a trigger subunit. The inverting selector outputs an inverted signal of the selected signal from multiple received signals, including at least the corresponding clock signal. The pre-phase delay line delays the rising edge of the corresponding clock signal, and the inverting delay line delays the rising edge of the inverted signal. The trigger subunit generates a corresponding clock adjustment signal based on the signals output by the pre-phase and inverting delay lines. The rising and falling edges of the clock adjustment signal are triggered based on the rising edges of the signals output by the pre-phase and inverting delay lines, respectively. The duty cycle detection unit detects the duty cycle of the signals output by the two duty cycle adjustment units at the end of the clock transmission path. The control unit is used to set the delay parameters of the in-phase delay line and the out-of-phase delay line based on the delay setting signal.

[0070] Therefore, by setting up a pre-phase delay line, an inverting delay line, and a trigger sub-unit in the quadrature clock correction circuit, and delaying the rising edge of the initial quadrature clock signal based on the pre-phase delay line, and delaying the falling edge of the initial quadrature clock signal based on the inverting delay line and the trigger sub-unit, the embodiments of the present invention can achieve duty cycle correction of the transmitted quadrature clock signal without significantly increasing costs, while also ensuring the accuracy of the duty cycle correction of the transmitted quadrature clock signal.

[0071] Another embodiment of the present invention relates to a chip. This chip may include the quadrature clock correction circuit described in the above embodiments. Optionally, the chip may be any type of chip, and this application is not limited thereto. By providing the quadrature clock correction circuit, the chip can utilize the quadrature clock correction circuit to provide required quadrature clock signals to other internal circuit modules.

[0072] Another embodiment of the present invention relates to an electronic device. This electronic device may be an electronic device equipped with the aforementioned chip. Optionally, the electronic device may be any type of electronic device, and this application does not impose any limitations on it.

[0073] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A quadrature clock correction circuit, characterized in that, The circuit includes: Two duty cycle adjustment units are used to adjust the duty cycle of the corresponding first clock signal and second clock signal, respectively. The first clock signal and the second clock signal are initial quadrature clock signals with a 90-degree phase difference relative to each other. Each duty cycle adjustment unit includes an inverting selector, a pre-phase delay line, an inverting delay line, and a trigger subunit. The inverting selector is used to output the inverted signal of the selected signal from a plurality of received signals, the plurality of received signals including at least the corresponding clock signal. The pre-phase delay line is used to delay the rising edge of the corresponding clock signal, the inverting delay line is used to delay the rising edge of the inverted signal, and the trigger subunit is used to generate a corresponding clock adjustment signal based on the signals output by the pre-phase delay line and the inverting delay line. The rising edge and falling edge of the clock adjustment signal are triggered based on the rising edges of the signals output by the pre-phase delay line and the inverting delay line, respectively. A duty cycle detection unit, located at the end of the clock transmission path, is used to detect the duty cycle of the signals output by the two duty cycle adjustment units at the end of the clock transmission path; and The control unit is used to set the delay parameters of the original phase delay line and / or the inverting phase delay line based on the delay setting signal.

2. The quadrature clock correction circuit according to claim 1, characterized in that, The plurality of received signals also includes the signal output by the original phase delay line.

3. The quadrature clock correction circuit according to claim 1, characterized in that, The duty cycle adjustment unit further includes: An output selector is used to receive a selection signal and, based on the selection signal, output the clock adjustment signal output by the trigger subunit as the output signal of the duty cycle adjustment unit, or output the signal output by the original phase delay line as the output signal of the duty cycle adjustment unit.

4. The quadrature clock correction circuit according to claim 1, characterized in that, The duty cycle detection unit includes: The signal distribution subunit is used to receive the signals output by the two duty cycle adjustment units, perform parallel-to-serial conversion on the signals output by the two duty cycle adjustment units to generate a high-speed clock signal, and transmit the signals output by the two duty cycle adjustment units and the high-speed clock signal. The detection subunit is used to receive the signal transmitted by the signal distribution subunit and perform duty cycle detection on the selected signal in the signal transmitted by the signal distribution subunit based on the selection signal, so as to generate a duty cycle detection result.

5. The quadrature clock correction circuit according to claim 4, characterized in that, The detection subunit includes: A detection selector is used to receive the signal transmitted by the signal distribution subunit and output the corresponding selected signal from the received signals based on the selection signal; A common-mode level detector is used to detect the common-mode level of the selected signal output by the detection selector; A comparator is used to compare the common-mode level with a preset voltage threshold signal to generate the duty cycle detection result.

6. The quadrature clock correction circuit according to claim 4, characterized in that, The delay setting signal is received by the control unit, or the delay setting signal is generated by the control unit based on the duty cycle detection result.

7. The quadrature clock correction circuit according to claim 1, characterized in that, The triggering subunit includes: Two rising edge detection modules are used to detect the rising edge of the signal output by the prephase delay line and the signal output by the inverting delay line, respectively, so as to output a first pulse sequence and a second pulse sequence. Each pulse signal in the first pulse sequence is used to characterize the corresponding rising edge in the signal output by the prephase delay line, and each pulse signal in the second pulse sequence is used to characterize the corresponding rising edge in the signal output by the inverting delay line. A combinational logic module is used to output the clock adjustment signal based on the first pulse sequence and the second pulse sequence.

8. The quadrature clock correction circuit according to claim 7, characterized in that, The rising edge detection module includes: A data trigger is used to output a threshold voltage signal when a rising edge of a received signal is detected, and to stop outputting the threshold voltage signal when a reset signal is received; A delay buffer is used to delay the signal output by the data trigger; A reset signal generator is used to output the reset signal to the data trigger in response to the threshold voltage signal acquired from the output of the delay buffer.

9. The quadrature clock correction circuit according to claim 1, characterized in that, The circuit also includes: A signal generation unit is used to receive a data clock signal and generate a first clock signal and a second clock signal based on the data clock signal.

10. The quadrature clock correction circuit according to claim 9, characterized in that, The signal generation unit includes: A first frequency divider is used to divide the data clock signal in a rising-edge triggered manner to generate the first clock signal; and The second frequency divider is used to divide the data clock signal in a falling edge triggered manner to generate the second clock signal.

11. The quadrature clock correction circuit according to claim 1, characterized in that, The clock transmission path includes a clock tree.

12. A chip, characterized in that, The chip includes: Clock transmission path; and The quadrature clock correction circuit as described in any one of claims 1-11.

13. An electronic device, characterized in that, The device includes: The chip as described in claim 12.

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