Magnetic core random access memory read reference circuit architecture design method and system

Abstract

The invention provides a magnetic core random access memory read reference circuit architecture design method and system, and relates to the technical field of circuit architectures.The method comprises the steps that a high-resistance reference unit column and a low-resistance reference unit column are arranged in each storage array, and each high-resistance reference unit column and the corresponding low-resistance reference unit column respectively comprise a transistor and polycrystalline silicon resistor series structure; configuring a reference bit line, adjusting the line width to enable the square resistance to be equal to that of a common bit line, and reading the number of transistors in a path to be the same as that of target units; obtaining a target reading current and a high-low resistance reference current in the reading operation; calculating a high-low resistance reference current intermediate value as a dynamic reference current, wherein the current is adaptively adjusted along with the change of parasitic resistance on a path; and comparing the target read current with the dynamic reference current through a sensitive amplifier to judge the data of the storage unit. According to the invention, the reading reliability and the fault-tolerant capability of the magnetic core random access memory system are improved.

Description

Technical Field

[0001] This invention relates to the field of circuit architecture technology, and in particular to a method and system for designing a read reference circuit architecture for a magnetic core random access memory. Background Technology

[0002] Magnetic core random access memory (MRAM) is a non-volatile memory technology that stores information through magnetic tunnel junctions (MTJs). It offers advantages such as high speed, low power consumption, high durability, and non-volatility. In an MRAM system, data is read by detecting the resistance state of the magnetic tunnel junction. The magnetic tunnel junction can be in a high-resistance state or a low-resistance state, each representing a different logic value.

[0003] In the MRAM read process, the design of the reference circuit is crucial, as it directly affects the reliability and accuracy of the read operation. Traditional MRAM read circuits typically use a fixed reference current or voltage to compare with the read current or voltage of the memory cell to determine the logic state of the memory cell.

[0004] However, existing MRAM reference circuit designs have the following defects and shortcomings: First, traditional reference circuits are sensitive to process variations and operating conditions. Under different temperature and voltage conditions, or due to manufacturing process fluctuations, the reference value may deviate significantly, leading to read errors. Especially in large-scale memory arrays, this deviation may amplify with the increase in array size, severely affecting read reliability.

[0005] Secondly, existing reference generation circuits are often unable to effectively handle variations in parasitic resistance and transistor on-resistance in the read path. These parasitic factors change with the operating environment, causing instability in the comparison results between the read signal and the reference signal, thus affecting read accuracy. Summary of the Invention

[0006] The present invention provides a method and system for designing a read reference circuit architecture for a magnetic core random access memory, which can solve the problems in the prior art.

[0007] A first aspect of this invention provides a method for designing a read reference circuit architecture for a magnetic core random access memory (RAM). The method is applied to a RAM system comprising multiple memory arrays, each memory array comprising multiple rows and columns of memory cells, and each memory cell comprising a transistor connected in series with a magnetic tunnel junction. Each memory array includes a high-resistance reference cell column and a low-resistance reference cell column. The high-resistance reference cell column comprises a transistor connected in series with a first polysilicon resistor, and the low-resistance reference cell column comprises a transistor connected in series with a second polysilicon resistor. The resistance of the first polysilicon resistor is equivalent to the high-resistance state resistance of the magnetic tunnel junction, and the resistance of the second polysilicon resistor is equivalent to the low-resistance state resistance of the magnetic tunnel junction. High-resistance reference bit lines and low-resistance reference bit lines are respectively configured for the high-resistance reference cell column and the low-resistance reference cell column. By adjusting the metal line width of the high-resistance reference bit lines and the low-resistance reference bit lines, the sheet resistance of the two reference bit lines is made equal to the sheet resistance of the ordinary bit lines, and the number of transistors in the read path of the two reference bit lines is made equal to the number of transistors in the read path of the target memory cell. During the read operation, the resistance values ​​of the target memory cell, the high-impedance reference cell, and the low-impedance reference cell are read simultaneously to obtain the target read current, the high-impedance reference current, and the low-impedance reference current. The intermediate value between the high-resistance reference current and the low-resistance reference current is calculated by a differential operational circuit and used as a dynamic reference current. The dynamic reference current is adaptively adjusted according to the parasitic resistance and transistor on-resistance on the paths of the high-resistance reference cell and the low-resistance reference cell. The target read current is compared with the dynamic reference current by a sensitive amplifier to determine whether data is stored in the target storage unit.

[0008] Setting up high-impedance reference cell columns and low-impedance reference cell columns in each memory array includes: Batch resistance characteristic tests were performed on the magnetic tunnel junctions in the memory array. The resistance distribution curves of the magnetic tunnel junctions in the antiparallel magnetization state and the parallel magnetization state were measured under multiple process angles and temperature conditions. The statistical median and standard deviation of the resistance distribution curves were extracted. The nominal resistance value of the first polysilicon resistor is determined based on the statistical median value under the antiparallel magnetization state, and the nominal resistance value of the second polysilicon resistor is determined based on the statistical median value under the parallel magnetization state.

[0009] By adjusting the metal line widths of the high-resistivity reference bit line and the low-resistivity reference bit line, including: Measure the metal layer thickness and material resistivity of a common bit line, and calculate the sheet resistance of the common bit line based on the metal layer thickness and material resistivity; The metal line widths of the high-resistance reference bit line and the low-resistance reference bit line are adjusted so that the deviation between their sheet resistance and the sheet resistance of the ordinary bit line is within the minimum tolerance range allowed by the manufacturing process. The high-resistance reference bit line, the low-resistance reference bit line and the ordinary bit line adopt the same metal layer and the same routing topology to achieve matching between the parasitic resistance of the high-resistance reference bit line and the low-resistance reference bit line and the parasitic resistance of the ordinary bit line.

[0010] Ensuring that the number of transistors in both reference bit lines in the read path is equal to the number of transistors in the read path of the target memory cell includes: A first gate transistor is connected in series between the high-resistance reference bit line and the high-resistance reference cell column, and a second gate transistor is connected in series between the low-resistance reference bit line and the low-resistance reference cell column. The size, threshold voltage, and bias conditions of the first and second gate transistors are the same as those of the gate transistors connecting the ordinary bit line and the target memory cell in the target memory cell read path, so that the on-resistance of the transistors in the high-resistance reference bit line read path and the drift characteristics of the transistors with process, voltage, and temperature are consistent with those of the target memory cell read path.

[0011] The intermediate value between the high-impedance reference current and the low-impedance reference current is calculated using a differential operational circuit as the dynamic reference current, including: A high-impedance reference current is input to the first current input terminal of the differential operational circuit, and a low-impedance reference current is input to the second current input terminal of the differential operational circuit. In the differential operation circuit, a first current mirror branch and a second current mirror branch are set up. The first current mirror branch mirrors and copies the high-impedance reference current and multiplies it by a first weighting coefficient. The second current mirror branch mirrors and copies the low-impedance reference current and multiplies it by a second weighting coefficient. The first weighting coefficient and the second weighting coefficient are determined based on the tunnel reluctance ratio of the magnetic tunnel junction. The tunnel reluctance ratio is calculated by measuring the average resistance of the magnetic tunnel junction in the antiparallel magnetization state and the average resistance in the parallel magnetization state. Based on the tunnel reluctance ratio, the first weighting coefficient is set as the ratio of the tunnel reluctance ratio to the sum of the tunnel reluctance ratio and one. The second weighting coefficient is set as the difference between one and the first weighting coefficient. The weighted high-resistance reference current output from the first current mirror branch and the weighted low-resistance reference current output from the second current mirror branch are converged to a summing node. The weighted high-resistance reference current and the weighted low-resistance reference current are summed in the current domain through the summing node to obtain the dynamic reference current.

[0012] In a differential operational circuit, a first current mirror branch and a second current mirror branch are set up, including: In the first current mirror branch, a first reference transistor and a first mirror transistor are configured. The drain of the first reference transistor is connected to the first current input terminal to receive a high-impedance reference current. The gate and drain of the first reference transistor are shorted to form a diode connection structure. The gate of the first mirror transistor is connected to the gate of the first reference transistor. The source of the first mirror transistor and the source of the first reference transistor are connected to the power supply voltage. A second reference transistor and a second mirror transistor are configured in the second current mirror branch. The drain of the second reference transistor is connected to the second current input terminal to receive a low-impedance reference current. The gate and drain of the second reference transistor are shorted to form a diode connection structure. The gate of the second mirror transistor is connected to the gate of the second reference transistor. The source of the second mirror transistor and the source of the second reference transistor are connected to the power supply voltage.

[0013] A second aspect of the present invention provides a magnetic core random access memory read reference circuit architecture design system, the method being applied to: The first unit is used to set a high-resistance reference cell column and a low-resistance reference cell column in each memory array. The high-resistance reference cell column includes a transistor and a first polysilicon resistor connected in series. The low-resistance reference cell column includes a transistor and a second polysilicon resistor connected in series. The resistance value of the first polysilicon resistor is equivalent to the high-resistance state resistance value of the magnetic tunnel junction, and the resistance value of the second polysilicon resistor is equivalent to the low-resistance state resistance value of the magnetic tunnel junction. The second unit is used to configure high-resistance reference bit lines and low-resistance reference bit lines for the high-resistance reference cell column and the low-resistance reference cell column, respectively. By adjusting the metal line width of the high-resistance reference bit lines and the low-resistance reference bit lines, the sheet resistance of the two reference bit lines is made equal to the sheet resistance of the ordinary bit lines, and the number of transistors in the read path of the two reference bit lines is made equal to the number of transistors in the read path of the target memory cell. The third unit is used to simultaneously read the resistance values ​​of the target memory cell, the high-impedance reference cell, and the low-impedance reference cell during a read operation, thereby obtaining the target read current, the high-impedance reference current, and the low-impedance reference current. The fourth unit is used to calculate the intermediate value between the high-resistance reference current and the low-resistance reference current through a differential operation circuit as a dynamic reference current. The dynamic reference current is adaptively adjusted according to the parasitic resistance and transistor on-resistance on the paths of the high-resistance reference unit and the low-resistance reference unit. The fifth unit is used to compare the target read current with the dynamic reference current through a sensitive amplifier to determine whether data is stored in the target storage unit.

[0014] A third aspect of the present invention, An electronic device is provided, comprising: processor; Memory used to store processor-executable instructions; The processor is configured to invoke instructions stored in the memory to execute the aforementioned method.

[0015] Fourth aspect of the embodiments of the present invention, A computer-readable storage medium is provided, having stored thereon computer program instructions that, when executed by a processor, implement the aforementioned method.

[0016] The beneficial effects of this application are as follows: By setting up high-resistance and low-resistance reference cells and using polysilicon resistors to equivalently simulate the high and low resistance states of the magnetic tunnel junction, a stable and reliable reference reference is achieved, solving the problem of unstable reference current caused by process fluctuations in traditional reference circuits. By adjusting the metal line width of the reference bit line to make its sheet resistance equal to that of the ordinary bit line, and by making the number of transistors in the reference path equal to the number of transistors in the memory cell read path, the parasitic resistance of the read path is effectively balanced, and the read accuracy is improved. A differential operational circuit is used to calculate the intermediate value between the high-resistance reference current and the low-resistance reference current as a dynamic reference current. This enables adaptive adjustment of the reference current, allowing it to dynamically adjust according to changes in the parasitic resistance and transistor on-resistance on the paths of the high-resistance and low-resistance reference cells. This effectively eliminates the influence of factors such as process deviations, temperature changes, and power supply fluctuations on the readout decision. Attached Figure Description

[0017] Figure 1 This is a flowchart illustrating the design method of the magnetic core random access memory read reference circuit architecture according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the novel magnetic core random access memory read reference circuit array architecture of the present invention; Figure 3 This is a schematic diagram of the circuitry on both sides of the sensitive amplifier. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] The technical solution of the present invention will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0020] Figure 1 This is a flowchart illustrating the design method of the magnetic core random access memory read reference circuit architecture according to an embodiment of the present invention, as shown below. Figure 1 As shown, the method includes: Each memory array includes a high-resistance reference cell column and a low-resistance reference cell column. The high-resistance reference cell column comprises a transistor connected in series with a first polysilicon resistor, and the low-resistance reference cell column comprises a transistor connected in series with a second polysilicon resistor. The resistance of the first polysilicon resistor is equivalent to the high-resistance state resistance of the magnetic tunnel junction, and the resistance of the second polysilicon resistor is equivalent to the low-resistance state resistance of the magnetic tunnel junction. High-resistance reference bit lines and low-resistance reference bit lines are respectively configured for the high-resistance reference cell column and the low-resistance reference cell column. By adjusting the metal line width of the high-resistance reference bit lines and the low-resistance reference bit lines, the sheet resistance of the two reference bit lines is made equal to the sheet resistance of the ordinary bit lines, and the number of transistors in the read path of the two reference bit lines is made equal to the number of transistors in the read path of the target memory cell. During the read operation, the resistance values ​​of the target memory cell, the high-impedance reference cell, and the low-impedance reference cell are read simultaneously to obtain the target read current, the high-impedance reference current, and the low-impedance reference current. The intermediate value between the high-resistance reference current and the low-resistance reference current is calculated by a differential operational circuit and used as a dynamic reference current. The dynamic reference current is adaptively adjusted according to the parasitic resistance and transistor on-resistance on the paths of the high-resistance reference cell and the low-resistance reference cell. The target read current is compared with the dynamic reference current by a sensitive amplifier to determine whether data is stored in the target storage unit.

[0021] In one optional implementation, setting up high-impedance reference cell columns and low-impedance reference cell columns in each memory array includes: Batch resistance characteristic tests were performed on the magnetic tunnel junctions in the memory array. The resistance distribution curves of the magnetic tunnel junctions in the antiparallel magnetization state and the parallel magnetization state were measured under multiple process angles and temperature conditions. The statistical median and standard deviation of the resistance distribution curves were extracted. The nominal resistance value of the first polysilicon resistor is determined based on the statistical median value under the antiparallel magnetization state, and the nominal resistance value of the second polysilicon resistor is determined based on the statistical median value under the parallel magnetization state.

[0022] When manufacturing magnetic random access memory (MRAM), the first step is to perform batch resistance characteristic tests on the magnetic tunnel junctions (MTJs) in the memory array. These tests are typically conducted over multiple process corners and temperature conditions to ensure the device functions correctly in various environments.

[0023] Batch resistance characteristic testing first requires placing the MTJ components in both antiparallel magnetization and parallel magnetization states. In the antiparallel magnetization state, the magnetic moments of the free and fixed layers are in opposite directions, resulting in a high resistance state for the MTJ. In the parallel magnetization state, the magnetic moments of the free and fixed layers are in the same direction, resulting in a low resistance state for the MTJ.

[0024] During testing, a small bias voltage, typically between 100 mV and 500 mV, is applied to each MTJ element, and the current flowing through the MTJ is measured. The resistance value of the MTJ is then calculated using Ohm's law. In a typical MRAM array, it may be necessary to test tens of thousands of MTJ elements, forming a huge dataset.

[0025] The tests need to be conducted under different process corner conditions, including typical conditions (TT), fast conditions (FF), slow conditions (SS), and fast N / slow P (FS) and slow N / fast P (SF) conditions. In addition, tests need to be conducted at multiple temperature points, typically including low temperature (e.g., -40°C), room temperature (approximately 25°C), and high temperature (e.g., 125°C).

[0026] The collected resistance data is used to generate resistance distribution curves. One resistance distribution curve is plotted for the antiparallel magnetization state (high resistance state); another resistance distribution curve is plotted for the parallel magnetization state (low resistance state). These distribution curves typically exhibit an approximately Gaussian distribution.

[0027] Next, statistical analysis is performed on these distribution curves to extract the statistical median and standard deviation. The statistical median represents the central location of the resistance distribution, while the standard deviation reflects the degree of dispersion of the resistance values. A smaller standard deviation indicates that the resistance values ​​of the MTJ component are more concentrated, which usually means a more stable manufacturing process.

[0028] Based on the extracted statistical median value under antiparallel magnetization, the nominal resistance value of the first polysilicon resistor is determined. This polysilicon resistor will serve as the high-resistance reference cell column. Similarly, based on the statistical median value under parallel magnetization, the nominal resistance value of the second polysilicon resistor is determined and served as the low-resistance reference cell column.

[0029] When determining the nominal resistance value of polysilicon resistors, a certain margin needs to be considered. For example, the resistance value of the high-resistance reference cell column can be set between 95% and 105% of the statistical median of the antiparallel magnetization state, while the resistance value of the low-resistance reference cell column can be set between 95% and 105% of the statistical median of the parallel magnetization state. This setting ensures that the reference cell columns accurately represent the high and low resistance states of the actual MTJ components.

[0030] In practice, polysilicon resistors are typically fabricated using doping control. By adjusting the doping concentration, the resistivity of the polysilicon can be precisely controlled. For example, high-resistivity reference cell columns can use polysilicon with a lower doping concentration, while low-resistivity reference cell columns use polysilicon with a higher doping concentration. Furthermore, the resistance value can be further fine-tuned by adjusting the geometry of the polysilicon resistor (such as its length and width).

[0031] The fabricated polycrystalline silicon reference resistor needs to undergo verification testing to ensure that its resistance value meets design requirements. Verification testing typically includes resistance measurement, temperature coefficient measurement, and long-term stability testing.

[0032] These reference cells play a crucial role in MRAM read operations. When reading a memory cell, the cell's resistance value is compared with high-resistance and low-resistance reference cells. If the cell's resistance value is closer to the high-resistance reference value, it is determined to be in a "1" state; if it is closer to the low-resistance reference value, it is determined to be in a "0" state.

[0033] The high-resistance reference cell column and low-resistance reference cell column set by the above method can accurately reflect the resistance characteristics of the actual MTJ component under two magnetization states, thereby improving the read reliability and read margin of MRAM, reducing the read error rate, and ultimately improving the overall performance of MRAM.

[0034] In one optional implementation, adjusting the metal line widths of the high-resistivity reference bit line and the low-resistivity reference bit line includes: Measure the metal layer thickness and material resistivity of a common bit line, and calculate the sheet resistance of the common bit line based on the metal layer thickness and material resistivity; The metal line widths of the high-resistance reference bit line and the low-resistance reference bit line are adjusted so that the deviation between their sheet resistance and the sheet resistance of the ordinary bit line is within the minimum tolerance range allowed by the manufacturing process. The high-resistance reference bit line, the low-resistance reference bit line and the ordinary bit line adopt the same metal layer and the same routing topology to achieve matching between the parasitic resistance of the high-resistance reference bit line and the low-resistance reference bit line and the parasitic resistance of the ordinary bit line.

[0035] First, the properties of the metal layer are measured to obtain the thickness and resistivity of the metal layer in a typical bitline. A four-probe method is used to measure the metal layer sample. Test probes are placed on the surface of the metal layer, and a constant current is applied through the two outer probes while the voltage drop between the two inner probes is measured simultaneously. Based on Ohm's law and the known distance between the probes, the resistivity of the metal layer is calculated. The thickness of the metal layer can be measured by cross-sectional observation using a scanning electron microscope or an atomic force microscope.

[0036] When designing high-resistivity reference bit lines, a narrower linewidth should be chosen while minimizing the deviation between the sheet resistance and that of ordinary bit lines. Assuming the minimum linewidth allowed by the process is 0.18 micrometers, and the linewidth of ordinary bit lines is 0.5 micrometers, then the high-resistivity reference bit line can be designed to be 0.18 to 0.2 micrometers wide. In this way, the total resistance of the high-resistivity reference bit line is approximately 2.5 to 2.8 times that of the ordinary bit line, while maintaining consistency in sheet resistance.

[0037] Accordingly, when designing low-resistance reference bit lines, a wider linewidth is selected, such as 0.8 to 1 micrometer, so that its total resistance is approximately 0.5 to 0.625 times that of ordinary bit lines. Circuit simulation verification ensures that the designed linewidth can control the deviation of the sheet resistance of high-resistance and low-resistance reference bit lines from that of ordinary bit lines within ±5%, meeting the minimum tolerance requirements allowed by the process.

[0038] During the placement and routing phase, ensure that high-resistance reference bit lines, low-resistance reference bit lines, and normal bit lines use the same metal layer. For example, if normal bit lines use the Metal 3 layer, then high-resistance and low-resistance reference bit lines must also use the Metal 3 layer. Furthermore, ensure that the three types of bit lines have the same routing topology, including similar number of turns, turn angles, and crossover patterns with other metal layers.

[0039] In practical implementation, a "serpentine" routing method can be used to design the three bit lines, ensuring they have the same number of 90-degree turns within the same area. For example, within a 4 square millimeter area, each bit line can be designed with four 90-degree turns, forming a "U"-shaped routing structure. This ensures consistency in parasitic capacitance and inductance between bit lines, further enhancing matching performance.

[0040] By precisely adjusting the widths of the high-impedance and low-impedance reference bit lines and ensuring they have the same metal hierarchy and routing topology as the ordinary bit lines, the parasitic resistances of the three bit lines can be highly matched. In practical applications, such as differential amplifier design, this method can control mismatch errors to within 1%, significantly improving circuit performance.

[0041] To verify the design effectiveness, parasitic parameters after actual routing can be extracted using post-simulation tools, and the parasitic resistance ratio between different bit lines can be calculated. Ideally, the parasitic resistance ratio between the high-resistance reference bit line and the ordinary bit line should be close to the design value of 2.5 to 2.8, and the parasitic resistance ratio between the low-resistance reference bit line and the ordinary bit line should be close to the design value of 0.5 to 0.625. If the actual extracted values ​​deviate from the design target by more than 10%, the line width parameters need to be readjusted.

[0042] This method achieves parasitic resistance matching among high-resistance reference bit lines, low-resistance reference bit lines, and ordinary bit lines while ensuring the consistency of sheet resistance, providing effective support for high-precision design of integrated circuits.

[0043] In one optional implementation, ensuring that the number of transistors in both reference bit lines in the read path is equal to the number of transistors in the target memory cell read path includes: A first gate transistor is connected in series between the high-resistance reference bit line and the high-resistance reference cell column, and a second gate transistor is connected in series between the low-resistance reference bit line and the low-resistance reference cell column. The size, threshold voltage, and bias conditions of the first and second gate transistors are the same as those of the gate transistors connecting the ordinary bit line and the target memory cell in the target memory cell read path, so that the on-resistance of the transistors in the high-resistance reference bit line read path and the drift characteristics of the transistors with process, voltage, and temperature are consistent with those of the target memory cell read path.

[0044] With the development of memory chip technology, efficient read path structures are needed to ensure the reliability and stability of memory reads. This embodiment provides a method to ensure that the number of transistors in the read path of both reference bit lines is equal to the number of transistors in the read path of the target memory cell.

[0045] In actual memory read operations, it is typically necessary to compare the resistance value of the target memory cell with that of a reference resistance value to determine the logic state of the memory cell. The reference resistance value is usually provided by a high-resistance reference cell and a low-resistance reference cell. To ensure the accuracy of the comparison, it is necessary to ensure that the target memory cell read path and the reference bit line read path have the same electrical characteristics.

[0046] During the memory architecture design phase, the structure of the read path for the target memory cell is determined. The target memory cell is connected to the ordinary bit line via a gating transistor, which controls whether the target memory cell is selected for a read operation. The number and type of transistors in the read path of the target memory cell directly affect the magnitude and stability of the read current.

[0047] Design a high-impedance reference bit line read path. Connect a first gating transistor in series between the high-impedance reference bit line and the high-impedance reference cell column. The design of the first gating transistor must ensure that its size, threshold voltage, and bias conditions are identical to the gating transistor in the target memory cell read path. The high-impedance reference cell is typically programmed to a high-resistance state, representing a stored logic value (such as logic "1").

[0048] Simultaneously, a low-resistance reference bit line read path is designed. A second gating transistor is connected in series between the low-resistance reference bit line and the low-resistance reference cell column. The size, threshold voltage, and bias conditions of the second gating transistor must also be consistent with the gating transistor in the target memory cell read path. The low-resistance reference cell is typically programmed to a low-resistance state, representing another logic value (such as logic "0").

[0049] To ensure the consistency of the gating transistors, the same process parameters and mask patterns are used during transistor manufacturing. Key parameters such as the gate width, length, and channel doping concentration of the transistors must be strictly controlled to ensure that the gating transistors in the three readout paths have the same electrical characteristics.

[0050] In terms of bias design, the same gate and drain voltages are provided for the gating transistors in all three read paths. For example, during a read operation, the gate voltage of the gating transistor can be set to the positive supply voltage VDD, while the source voltage can be set to near ground potential, ensuring that the transistor operates in the linear or saturation region, depending on the memory design requirements.

[0051] The above design ensures that the transistor on-resistance and drift characteristics with process, voltage, and temperature in the high-resistance and low-resistance reference bit line read paths are consistent with those in the target memory cell read path. This consistency is crucial for the memory's read margin and effectively reduces read errors caused by process variations, voltage fluctuations, or temperature changes.

[0052] In practical applications, during a read operation, the target memory cell read path, the high-impedance reference bit line read path, and the low-impedance reference bit line read path are activated simultaneously. By comparing the current generated by the target memory cell with the current generated by the two reference paths, the logic state of the target memory cell can be determined. Since the number of transistors in the three read paths is equal and their characteristics are consistent, any deviations caused by process, voltage, or temperature variations will be reflected consistently in all three paths, thus ensuring the accuracy of the read decision.

[0053] Furthermore, to further improve the matching of read paths, a common centroid layout technique can be adopted during the layout design stage. This involves placing transistors in close proximity across the three read paths, using the same orientation and surrounding environment, thus minimizing transistor characteristic deviations caused by differences in layout location.

[0054] During the testing and verification phase, the effectiveness of the design can be verified using corner analysis. The electrical characteristics of the three reading paths are tested under different process corners (e.g., fast corner, typical corner, slow corner), different supply voltages (e.g., minimum voltage, typical voltage, maximum voltage), and different temperature conditions (e.g., minimum operating temperature, room temperature, maximum operating temperature) to ensure they maintain good compatibility under various conditions.

[0055] The read path design implemented by the above method can effectively improve the read reliability of the memory, enhance the stability of the memory under different operating conditions, and ultimately improve the overall performance and yield of the memory chip.

[0056] In one optional implementation, the intermediate value between the high-impedance reference current and the low-impedance reference current is calculated using a differential operational circuit as the dynamic reference current, including: A high-impedance reference current is input to the first current input terminal of the differential operational circuit, and a low-impedance reference current is input to the second current input terminal of the differential operational circuit. In the differential operation circuit, a first current mirror branch and a second current mirror branch are set up. The first current mirror branch mirrors and copies the high-impedance reference current and multiplies it by a first weighting coefficient. The second current mirror branch mirrors and copies the low-impedance reference current and multiplies it by a second weighting coefficient. The first weighting coefficient and the second weighting coefficient are determined based on the tunnel reluctance ratio of the magnetic tunnel junction. The tunnel reluctance ratio is calculated by measuring the average resistance of the magnetic tunnel junction in the antiparallel magnetization state and the average resistance in the parallel magnetization state. Based on the tunnel reluctance ratio, the first weighting coefficient is set as the ratio of the tunnel reluctance ratio to the sum of the tunnel reluctance ratio and one. The second weighting coefficient is set as the difference between one and the first weighting coefficient. The weighted high-resistance reference current output from the first current mirror branch and the weighted low-resistance reference current output from the second current mirror branch are converged to a summing node. The weighted high-resistance reference current and the weighted low-resistance reference current are summed in the current domain through the summing node to obtain the dynamic reference current.

[0057] In magnetic tunnel junction (MTJ) sensing applications, the design of the reference current is crucial for readout accuracy and reliability. This invention proposes a method for calculating the intermediate value between a high-impedance reference current and a low-impedance reference current using a differential operational circuit as a dynamic reference current. The specific implementation process is as follows: First, a high-impedance reference current is input to the first current input terminal of the differential operational circuit. This high-impedance reference current is typically generated by a reference MTJ cell in an antiparallel magnetization state (AP state), where the MTJ exhibits high resistance. Simultaneously, a low-impedance reference current is input to the second current input terminal of the differential operational circuit. This low-impedance reference current is generated by a reference MTJ cell in a parallel magnetization state (P state), where the MTJ exhibits low resistance.

[0058] The differential operational circuit has two key current mirror branches: a first current mirror branch and a second current mirror branch. The first current mirror branch mainly consists of a pair of PMOS transistors, with their gates connected to the high-impedance reference current input, their sources connected to the power supply voltage, and their drains outputting the mirrored current. By adjusting the aspect ratio of the mirror transistors, the first current mirror branch mirrors the high-impedance reference current and multiplies it by a first weighting coefficient. In specific implementation, if the aspect ratio of the reference transistor is (W / L)1 and the aspect ratio of the mirror transistor is (W / L)2, then the current amplification factor, i.e., the first weighting coefficient, is (W / L)2 / (W / L)1.

[0059] The second current mirror branch adopts a similar structure, mainly composed of pairs of NMOS transistors. Their gates are connected to the low-impedance reference current input, their sources are grounded, and their drains output the mirrored current. By adjusting the aspect ratio of the mirror transistors, the second current mirror branch mirrors the low-impedance reference current and multiplies it by a second weighting coefficient.

[0060] A crucial step is determining the first and second weighting coefficients based on the tunnel magnetoresistance ratio (TMR) of the magnetic tunnel junctions (MTJs). First, MTJ characteristics are measured by taking the resistance values ​​of multiple MTJs in antiparallel magnetization and calculating their average value, RAP. Similarly, the resistance values ​​of these MTJs in parallel magnetization are measured and their average value, RP, is calculated. The tunnel magnetoresistance ratio (TMR) is defined as the ratio of RAP to RP, i.e., TMR = RAP / RP.

[0061] Based on the measured TMR value, the first weighting coefficient α is set as the ratio of the sum of TMR and (TMR+1), i.e., α = TMR / (TMR+1). For example, if the measured TMR = 2, then α = 2 / (2+1) = 2 / 3. Correspondingly, the second weighting coefficient β is set as the difference between 1 and the first weighting coefficient, i.e., β = 1 - α = 1 / (TMR+1). In the above example, β = 1 - 2 / 3 = 1 / 3.

[0062] This weighting factor setting makes the dynamic reference current closer to the theoretically optimal reference point, effectively improving the sensing margin. Specifically, when the resistance value of MTJ exhibits a non-linear distribution between RAP and RP, the above weighting method can obtain a more optimized reference point position.

[0063] After setting the weighting coefficients, the weighted high-impedance reference current output from the first current mirror branch and the weighted low-impedance reference current output from the second current mirror branch are converged to a summing node. This summing node is typically a common connection point within the differential operational circuit, such as the drain connection point of the two mirror circuits. At this node, the weighted high-impedance reference current and the weighted low-impedance reference current are naturally summed in the current domain, i.e., Iref_dynamic = α·Iref_high + β·Iref_low, where Iref_high is the high-impedance reference current and Iref_low is the low-impedance reference current.

[0064] In practical implementation, a simple current buffer can be added after the differential operation circuit to provide sufficient drive capability and ensure that the dynamic reference current can be stably supplied to the subsequent comparator circuit. The current buffer can be implemented using a simple current mirror circuit to keep the output current proportional to the dynamic reference current.

[0065] To improve system stability, a temperature compensation circuit can be added to the differential operational circuit to counteract the effect of temperature changes on the MTJ resistance value. The compensation circuit typically includes a bandgap reference circuit and a temperature-coefficient adjustable current source, which can dynamically adjust the weighting coefficients according to temperature changes, ensuring that the dynamic reference current remains at its optimal position over a wide temperature range.

[0066] The dynamic reference current obtained by the above method can effectively adapt to the changes in the characteristics of MTJ devices under different process and temperature conditions, thereby improving the read stability and reliability of magnetic random access memory (MRAM).

[0067] In one optional implementation, a first current mirror branch and a second current mirror branch are provided in the differential operational circuit, including: In the first current mirror branch, a first reference transistor and a first mirror transistor are configured. The drain of the first reference transistor is connected to the first current input terminal to receive a high-impedance reference current. The gate and drain of the first reference transistor are shorted to form a diode connection structure. The gate of the first mirror transistor is connected to the gate of the first reference transistor. The source of the first mirror transistor and the source of the first reference transistor are connected to the power supply voltage. A second reference transistor and a second mirror transistor are configured in the second current mirror branch. The drain of the second reference transistor is connected to the second current input terminal to receive a low-impedance reference current. The gate and drain of the second reference transistor are shorted to form a diode connection structure. The gate of the second mirror transistor is connected to the gate of the second reference transistor. The source of the second mirror transistor and the source of the second reference transistor are connected to the power supply voltage.

[0068] The method of setting up current mirror branches in differential operational circuits is relevant to the field of analog integrated circuit design, particularly the design of high-precision differential amplifiers. In this embodiment, a first current mirror branch and a second current mirror branch are first set up in the differential operational circuit to achieve accurate current replication and matching.

[0069] In the first current mirror branch, a first reference transistor and a first mirror transistor are configured. The first reference transistor is a PMOS transistor, with its drain connected to the first current input terminal to receive a high-impedance reference current. This high-impedance reference current typically originates from a bandgap reference circuit or other stable current source circuit. The gate and drain of the first reference transistor are shorted to form a diode connection structure. This connection allows the transistor to operate in the saturation region, generating a gate-source voltage proportional to the current. The first mirror transistor is also a PMOS transistor with a size matching that of the first reference transistor, and its gate is connected to the gate of the first reference transistor, sharing the same gate-source voltage. The source of the first mirror transistor and the source of the first reference transistor are connected to the power supply voltage VDD, ensuring that the two transistors have the same source potential.

[0070] In the second current mirror branch, a second reference transistor and a second mirror transistor are configured. The second reference transistor is a PMOS transistor, with its drain connected to the second current input terminal to receive a low-impedance reference current. This low-impedance reference current can come from a resistor bias network or other low-impedance current source. The gate and drain of the second reference transistor are shorted to form a diode connection structure, ensuring that the transistor operates in the saturation region. The second mirror transistor also uses a PMOS transistor with a size matching that of the second reference transistor, and its gate is connected to the gate of the second reference transistor, sharing the same gate-source voltage. The source of the second mirror transistor and the source of the second reference transistor are both connected to the power supply voltage VDD.

[0071] After setting up the current mirror branch, precise current replication is performed. In the first current mirror branch, when the high-impedance reference current flows through the first reference transistor, a voltage is established between its gate and source. This voltage is simultaneously applied between the gate and source of the first mirror transistor. Since the two transistors share the same gate-source voltage and have the same size ratio, the first mirror transistor will generate a mirror current proportional to the high-impedance reference current. The magnitude of this mirror current depends on the size ratio of the two transistors; if they are exactly the same size, the mirror current equals the reference current.

[0072] Similarly, in the second current mirror branch, when the low-resistance reference current flows through the second reference transistor, a voltage is established between its gate and source, which is simultaneously applied between the gate and source of the second mirror transistor. The second mirror transistor will generate a mirror current proportional to the low-resistance reference current.

[0073] To improve the accuracy of the current mirror, the channel length and width of the transistor can be adjusted. In practical implementations, choosing a longer channel length can reduce channel modulation effects and increase output impedance, thereby improving the accuracy of the current mirror. For example, a transistor with a channel length of 2μm or longer can be selected, while adjusting the channel width to meet the required current level.

[0074] To address the impact of temperature variations on current mirror accuracy, a common-centroid layout technique can be employed during transistor placement to ensure a symmetrical distribution of the temperature gradient across the reference and mirror transistors. Furthermore, a guard ring can be added around the transistors to reduce the impact of parasitic interactions on current mirror accuracy.

[0075] In practical applications, it may be necessary to adjust the current ratio between the first current mirror branch and the second current mirror branch. Different mirror ratios can be achieved by changing the width-to-length ratio of the mirror transistor and the reference transistor. For example, if the current of the first mirror transistor needs to be twice that of the first reference transistor, the width-to-length ratio of the first mirror transistor can be designed to be twice that of the first reference transistor.

[0076] After the current mirror branch is established, it needs to be connected to the other parts of the differential operational circuit. The drain of the first mirror transistor can be connected to the first load resistor of the differential operational circuit, and the drain of the second mirror transistor can be connected to the second load resistor of the differential operational circuit. This connection method can provide a matched bias current for the differential operational circuit, improving its common-mode rejection ratio and power supply rejection ratio.

[0077] For high-precision applications, the current mirror branch can be further optimized. By adding a cascaded transistor between the first reference transistor and the first mirror transistor, the output impedance can be increased, reducing the impact of drain voltage variations on the mirror current. Similarly, a cascaded transistor can also be added between the second reference transistor and the second mirror transistor.

[0078] In practical circuits, to prevent the current mirror branch from being affected by power supply noise, a decoupling capacitor can be added between the power supply voltage VDD and the connection point of the first and second current mirror branches to filter out power supply noise and improve the stability of the current mirror.

[0079] This application also provides another specific embodiment: refer to Figure 2 and Figure 3 ,like Figure 2 As shown, the novel array architecture proposed in this invention includes a memory array, a dedicated reference cell column, and a sensitive amplifier. The core innovation of this architecture lies in equipping each memory array with an additional dedicated reference cell column to provide a stable reference current during read operations.

[0080] Specifically, the memory array adopts a conventional 1T1R (one transistor, one resistor) structure, with each memory cell including a MOSFET and a magnetic tunnel junction (MTJ). The drain of the MOSFET in the memory cell is connected to one end of the MTJ, and the other end of the MTJ in each column of memory cells is connected through a bit line (BL). The source of the MOSFET in each column of memory cells is connected through a source line (SL). The reference cell column is connected to the node between the drain of the MOSFET and the MTJ using a reference bit line (REFBL), and the reference source line (REFSL) is connected to the source of the MOSFET in each memory cell.

[0081] The structural design of the reference unit column is as follows: Implementation of the reference resistor: To avoid initialization difficulties caused by using the MTJ as the reference resistor, the reference resistor in this design is implemented entirely with a polysilicon resistor. The resistance value of the reference resistor is set between the high-resistance state and the low-resistance state of the MTJ to ensure accurate differentiation between the two memory states of the memory cell.

[0082] Reference bit line (REFBL) connection: The reference bit line is connected to the node between the drain of the MOS transistor and the MTJ of all cells in the reference cell column. During a read operation, the reference bit line is directly connected to the reference source line through a MOS transistor in the reference array, which depends on which word line is selected.

[0083] The original bit lines (BLR) of the reference cell column are set to a floating state and do not participate in the current path of the read operation, thereby avoiding interference with the reference signal.

[0084] Reference source line (REFSL) connection: The reference source line is grounded through a MOSFET M2, which is consistent with the grounding method of the conventional source line.

[0085] like Figure 3 As shown in the figure, this diagram illustrates the detailed structure of the circuitry on both sides of the sensitive amplifier, including the memory cell side and the reference cell side. During a read operation, one input of the sensitive amplifier is connected to the bit line of the target memory cell, and the other input is connected to the reference bit line.

[0086] Circuit path analysis: The read path of the target memory cell is: MOS transistor → Bit line (BL) → MTJ → MOS transistor → Source line (SL) → MOS transistor → Ground. The total resistance in this path includes: bit line parasitic resistance RBL, MOS transistor on-resistance, MTJ resistance, and source line parasitic resistance RSL.

[0087] The read path for the reference cell is: MOSFET → Reference Bit Line (REFBL) → MOSFET → MTJ → Reference Source Line (SL) → MOSFET → Ground. The total resistance along this path includes: reference bit line parasitic resistance RREFBL, MOSFET on-resistance, reference resistance (RREF), and reference source line parasitic resistance RREFSL.

[0088] Parasitic resistance matching design: The key technical feature of this invention lies in adjusting the metal line width of the reference bit line (REFBL) to ensure its resistance per unit length (i.e., sheet resistance) is consistent with that of the ordinary bit line (BL). Simultaneously, the length of the reference bit line is designed to be the same as the length of the bit line containing the target cell. In this way, the parasitic line resistances (RREFBL, RREFSL) on the reference resistance path can be precisely matched with the parasitic resistances (RBL, RSL) on the target cell read path.

[0089] Furthermore, the number of MOSFETs traversed in both paths is exactly the same: the target cell path passes through the MOSFETs in the memory cell, and the reference path also passes through the MOSFETs in the reference cell and MOSFET M2. By appropriately setting the dimensions of the MOSFETs, the total on-resistance of the MOSFETs in both paths can be kept consistent.

[0090] Read operation process: When a memory cell needs to be read, it is first selected via the word line, turning on its internal MOSFET; simultaneously, the MOSFET in the corresponding row of the reference cell column is selected. Then, a read voltage is applied to the bit line and the reference bit line, and read current flows through the target cell and the reference cell, respectively. Because the parasitic resistance and the MOSFET's on-resistance are matched, the currents on both sides are only affected by process technology and temperature on the MTJ and poly resistors, causing fluctuations. By comparing the two currents with a sensitive amplifier, it can be determined whether the memory cell stores "0" or "1".

[0091] With the above design, regardless of whether the target memory cell is located near or far of the array, the parasitic resistance on the reference path remains consistent with that of the target path, thereby eliminating near-far cell read window deviation caused by the difference in parasitic resistance between the bit line and the source line. Simultaneously, because the number and size of the MOSFETs on both paths are perfectly matched, even when process, voltage, and temperature (PVT) conditions change, the drift in the MOSFET on-resistance occurs synchronously on both paths, without affecting the stability of the read window, thus significantly reducing the read error rate.

[0092] The present invention provides a magnetic core random access memory read reference circuit architecture design system, comprising: The first unit is used to set a high-resistance reference cell column and a low-resistance reference cell column in each memory array. The high-resistance reference cell column includes a transistor and a first polysilicon resistor connected in series. The low-resistance reference cell column includes a transistor and a second polysilicon resistor connected in series. The resistance value of the first polysilicon resistor is equivalent to the high-resistance state resistance value of the magnetic tunnel junction, and the resistance value of the second polysilicon resistor is equivalent to the low-resistance state resistance value of the magnetic tunnel junction. The second unit is used to configure high-resistance reference bit lines and low-resistance reference bit lines for the high-resistance reference cell column and the low-resistance reference cell column, respectively. By adjusting the metal line width of the high-resistance reference bit lines and the low-resistance reference bit lines, the sheet resistance of the two reference bit lines is made equal to the sheet resistance of the ordinary bit lines, and the number of transistors in the read path of the two reference bit lines is made equal to the number of transistors in the read path of the target memory cell. The third unit is used to simultaneously read the resistance values ​​of the target memory cell, the high-impedance reference cell, and the low-impedance reference cell during a read operation, thereby obtaining the target read current, the high-impedance reference current, and the low-impedance reference current. The fourth unit is used to calculate the intermediate value between the high-resistance reference current and the low-resistance reference current through a differential operation circuit as a dynamic reference current. The dynamic reference current is adaptively adjusted according to the parasitic resistance and transistor on-resistance on the paths of the high-resistance reference unit and the low-resistance reference unit. The fifth unit is used to compare the target read current with the dynamic reference current through a sensitive amplifier to determine whether data is stored in the target storage unit.

[0093] A third aspect of the present invention provides an electronic device, comprising: processor; Memory used to store processor-executable instructions; The processor is configured to invoke instructions stored in the memory to execute the aforementioned method.

[0094] A fourth aspect of the present invention provides a computer-readable storage medium having stored thereon computer program instructions that, when executed by a processor, implement the aforementioned method.

[0095] This invention can be a method, apparatus, system, and / or computer program product. The computer program product may include a computer-readable storage medium having computer-readable program instructions loaded thereon for performing various aspects of the invention.

[0096] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for designing a read reference circuit architecture for a magnetic core random access memory, characterized in that, The method is applied to a magnetic core random access memory system comprising multiple memory arrays, each memory array comprising multiple rows and columns of memory cells, each memory cell comprising a transistor and a magnetic tunnel junction connected in series, including: Each memory array includes a high-resistance reference cell column and a low-resistance reference cell column. The high-resistance reference cell column comprises a transistor connected in series with a first polysilicon resistor, and the low-resistance reference cell column comprises a transistor connected in series with a second polysilicon resistor. The resistance of the first polysilicon resistor is equivalent to the high-resistance state resistance of the magnetic tunnel junction, and the resistance of the second polysilicon resistor is equivalent to the low-resistance state resistance of the magnetic tunnel junction. High-resistance reference bit lines and low-resistance reference bit lines are respectively configured for the high-resistance reference cell column and the low-resistance reference cell column. By adjusting the metal line width of the high-resistance reference bit lines and the low-resistance reference bit lines, the sheet resistance of the two reference bit lines is made equal to the sheet resistance of the ordinary bit lines, and the number of transistors in the read path of the two reference bit lines is made equal to the number of transistors in the read path of the target memory cell. During the read operation, the resistance values ​​of the target memory cell, the high-impedance reference cell, and the low-impedance reference cell are read simultaneously to obtain the target read current, the high-impedance reference current, and the low-impedance reference current. The intermediate value between the high-resistance reference current and the low-resistance reference current is calculated by a differential operational circuit and used as a dynamic reference current. The dynamic reference current is adaptively adjusted according to the parasitic resistance and transistor on-resistance on the paths of the high-resistance reference cell and the low-resistance reference cell. The target read current is compared with the dynamic reference current by a sensitive amplifier to determine whether data is stored in the target storage unit.

2. The method according to claim 1, characterized in that, Setting up high-impedance reference cell columns and low-impedance reference cell columns in each memory array includes: Batch resistance characteristic tests were performed on the magnetic tunnel junctions in the memory array. The resistance distribution curves of the magnetic tunnel junctions in the antiparallel magnetization state and the parallel magnetization state were measured under multiple process angles and temperature conditions. The statistical median and standard deviation of the resistance distribution curves were extracted. The nominal resistance value of the first polysilicon resistor is determined based on the statistical median value under the antiparallel magnetization state, and the nominal resistance value of the second polysilicon resistor is determined based on the statistical median value under the parallel magnetization state.

3. The method according to claim 1, characterized in that, By adjusting the metal line widths of the high-resistivity reference bit line and the low-resistivity reference bit line, including: Measure the metal layer thickness and material resistivity of a common bit line, and calculate the sheet resistance of the common bit line based on the metal layer thickness and material resistivity; The metal line widths of the high-resistance reference bit line and the low-resistance reference bit line are adjusted so that the deviation between their sheet resistance and the sheet resistance of the ordinary bit line is within the minimum tolerance range allowed by the manufacturing process. The high-resistance reference bit line, the low-resistance reference bit line and the ordinary bit line adopt the same metal layer and the same routing topology to achieve matching between the parasitic resistance of the high-resistance reference bit line and the low-resistance reference bit line and the parasitic resistance of the ordinary bit line.

4. The method according to claim 3, characterized in that, Ensuring that the number of transistors in both reference bit lines in the read path is equal to the number of transistors in the read path of the target memory cell includes: A first gate transistor is connected in series between the high-resistance reference bit line and the high-resistance reference cell column, and a second gate transistor is connected in series between the low-resistance reference bit line and the low-resistance reference cell column. The size, threshold voltage, and bias conditions of the first and second gate transistors are the same as those of the gate transistors connecting the ordinary bit line and the target memory cell in the target memory cell read path, so that the on-resistance of the transistors in the high-resistance reference bit line read path and the drift characteristics of the transistors with process, voltage, and temperature are consistent with those of the target memory cell read path.

5. The method according to claim 1, characterized in that, The intermediate value between the high-impedance reference current and the low-impedance reference current is calculated using a differential operational circuit as the dynamic reference current, including: A high-impedance reference current is input to the first current input terminal of the differential operational circuit, and a low-impedance reference current is input to the second current input terminal of the differential operational circuit. In the differential operation circuit, a first current mirror branch and a second current mirror branch are set up. The first current mirror branch mirrors and copies the high-impedance reference current and multiplies it by a first weighting coefficient. The second current mirror branch mirrors and copies the low-impedance reference current and multiplies it by a second weighting coefficient. The first weighting coefficient and the second weighting coefficient are determined based on the tunnel reluctance ratio of the magnetic tunnel junction. The tunnel reluctance ratio is calculated by measuring the average resistance of the magnetic tunnel junction in the antiparallel magnetization state and the average resistance in the parallel magnetization state. Based on the tunnel reluctance ratio, the first weighting coefficient is set as the ratio of the tunnel reluctance ratio to the sum of the tunnel reluctance ratio and one. The second weighting coefficient is set as the difference between one and the first weighting coefficient. The weighted high-resistance reference current output from the first current mirror branch and the weighted low-resistance reference current output from the second current mirror branch are converged to a summing node. The weighted high-resistance reference current and the weighted low-resistance reference current are summed in the current domain through the summing node to obtain the dynamic reference current.

6. The method according to claim 5, characterized in that, In a differential operational circuit, a first current mirror branch and a second current mirror branch are set up, including: In the first current mirror branch, a first reference transistor and a first mirror transistor are configured. The drain of the first reference transistor is connected to the first current input terminal to receive a high-impedance reference current. The gate and drain of the first reference transistor are shorted to form a diode connection structure. The gate of the first mirror transistor is connected to the gate of the first reference transistor. The source of the first mirror transistor and the source of the first reference transistor are connected to the power supply voltage. A second reference transistor and a second mirror transistor are configured in the second current mirror branch. The drain of the second reference transistor is connected to the second current input terminal to receive a low-impedance reference current. The gate and drain of the second reference transistor are shorted to form a diode connection structure. The gate of the second mirror transistor is connected to the gate of the second reference transistor. The source of the second mirror transistor and the source of the second reference transistor are connected to the power supply voltage.

7. A magnetic core random access memory read reference circuit architecture design system for implementing the method as described in any one of claims 1-6, characterized in that, include: The first unit is used to set a high-resistance reference cell column and a low-resistance reference cell column in each memory array. The high-resistance reference cell column includes a transistor and a first polysilicon resistor connected in series. The low-resistance reference cell column includes a transistor and a second polysilicon resistor connected in series. The resistance value of the first polysilicon resistor is equivalent to the high-resistance state resistance value of the magnetic tunnel junction, and the resistance value of the second polysilicon resistor is equivalent to the low-resistance state resistance value of the magnetic tunnel junction. The second unit is used to configure high-resistance reference bit lines and low-resistance reference bit lines for the high-resistance reference cell column and the low-resistance reference cell column, respectively. By adjusting the metal line width of the high-resistance reference bit lines and the low-resistance reference bit lines, the sheet resistance of the two reference bit lines is made equal to the sheet resistance of the ordinary bit lines, and the number of transistors in the read path of the two reference bit lines is made equal to the number of transistors in the read path of the target memory cell. The third unit is used to simultaneously read the resistance values ​​of the target memory cell, the high-impedance reference cell, and the low-impedance reference cell during a read operation, thereby obtaining the target read current, the high-impedance reference current, and the low-impedance reference current. The fourth unit is used to calculate the intermediate value between the high-resistance reference current and the low-resistance reference current through a differential operation circuit as a dynamic reference current. The dynamic reference current is adaptively adjusted according to the changes in parasitic resistance and transistor on-resistance on the paths of the high-resistance reference unit and the low-resistance reference unit. The fifth unit is used to compare the target read current with the dynamic reference current through a sensitive amplifier to determine whether data is stored in the target storage unit.

8. An electronic device, characterized in that, include: processor; Memory used to store processor-executable instructions; The processor is configured to invoke instructions stored in the memory to execute the method according to any one of claims 1 to 6.

9. A computer-readable storage medium having computer program instructions stored thereon, characterized in that, When the computer program instructions are executed by the processor, they implement the method described in any one of claims 1 to 6.

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