Switching control method, chip and energy storage system

Abstract

The embodiment of the invention discloses a switching control method, a chip and an energy storage system, and the method comprises the steps: sorting state parameter groups of all energy storage modules in the energy storage system, and obtaining a plurality of first state parameter groups after in-group sorting; performing at least one level of merging sorting on each first state parameter group after sorting in the group to obtain each state parameter after merging sorting; determining a to-be-switched-out energy storage module and a to-be-input energy storage module in the current control period from the energy storage modules based on the merged and sorted state parameters; and based on the to-be-switched-out energy storage module and the to-be-input energy storage module, performing switching control on each energy storage module.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of energy storage technology, and particularly to a switching control method, chip, device, and energy storage system. Background Technology

[0002] In systems such as flexible DC and direct-connected energy storage, control equipment needs to calculate the number of switching modules based on voltage commands, and then generate switching commands to ultimately control the number of modules switched. To optimally select suitable target switching modules, the control equipment needs to sort them according to capacitor voltage or battery state. Because such control equipment has a short execution cycle, it generally uses a Field Programmable Gate Array (FPGA), a chip with parallel data processing capabilities, to accelerate the sorting. In related technologies, merge sort is used to sort capacitors, voltages, or battery states, which consumes significant logic resources. Summary of the Invention

[0003] In view of this, the present disclosure provides at least one switching control method, chip, and energy storage system.

[0004] The technical solution of this disclosure embodiment is implemented as follows:

[0005] This disclosure provides a switching control method applied to an FPGA-based switching control chip, the method comprising:

[0006] The state parameters of each energy storage module in the energy storage system are sorted to obtain multiple first state parameter groups after sorting within each group.

[0007] Perform at least one level of merge sort on each of the sorted first state parameter groups within the group to obtain each state parameter after merge sorting.

[0008] Based on the merged and sorted state parameters, determine the energy storage modules to be switched out and the energy storage modules to be put into operation in the current control cycle from each energy storage module.

[0009] Based on the energy storage modules to be switched out and the energy storage modules to be put into operation, the switching control of each energy storage module is performed.

[0010] In the above embodiments, firstly, the state parameters of each energy storage module in the energy storage system are grouped, and the grouped state parameters are sorted within each group to obtain multiple first state parameter groups after sorting within each group. Secondly, each first state parameter group is subjected to at least one level of merge sorting to obtain merged and sorted state parameters. Based on the merged and sorted state parameters, the energy storage modules to be switched out and to be put into operation in the current control cycle are determined. Finally, the switching control of the energy storage modules to be switched out and to be put into operation is performed. In this way, sorting the state parameters of each energy storage module group can improve the parallelism of the sorting process. Furthermore, it fully utilizes the extremely low data processing latency and strong parallel processing capability of the FPGA-based switching control chip, which can quickly sort the state parameters of each energy storage module and perform switching control of each energy storage module according to the sorted state parameters, thereby enabling stable switching control of each energy storage module within one control cycle.

[0011] In some embodiments, sorting the state parameter groups of each energy storage module in the energy storage system to obtain multiple sorted first state parameter groups within the group includes: storing the state parameter groups of each energy storage module into multiple first memories in the switching control chip; storing one first state parameter group in each first memory; and sorting the first state parameter groups stored in each first memory in parallel, and storing the sorted first state parameter groups within the group into the first memory.

[0012] In the above embodiments, the state parameters of each energy storage module are divided into multiple first state parameter groups, and each first memory stores one first state parameter group. The first state parameter groups stored in each first memory are sorted in parallel, and the sorted first state parameter groups within each group are then stored in the first memory. This parallel sorting of the first state parameter groups stored in the first memory fully utilizes the parallel processing capabilities of the FPGA-based switching control chip, accelerating the sorting speed and improving sorting efficiency.

[0013] In some embodiments, performing at least one level of merge sorting on each sorted first state parameter group within the group to obtain each merge sorted state parameter includes: performing at least one level of merge sorting on each sorted first state parameter group stored in each first memory, and storing each merge sorted state parameter into the first target memory in the switching control chip.

[0014] In the above embodiments, at least one level of merge sorting is performed on each first state parameter group, and the merged and sorted state parameters are stored in the first target memory in the switching control chip. This allows for flexible control of the number of first state parameters in each first state parameter group, thereby enabling multi-level merge sorting of each first state parameter group and improving the speed of merge sorting.

[0015] In some embodiments, performing at least one level of merge sorting on the sorted first state parameter groups stored in each first memory, and storing the merged and sorted state parameters in the first target memory of the switching control chip, includes: performing a parallel merge sorting on each pair of the sorted first state parameter groups stored in each first memory to obtain multiple sorted second state parameter groups, storing each second state parameter group in the corresponding second target memory of the switching control chip; performing at least one level of merge sorting on the second state parameter groups stored in each second target memory, and storing the merged and sorted state parameters in the first target memory.

[0016] In the above embodiments, the sorted first state parameter groups stored in each first memory are merged and sorted pairwise in parallel to obtain multiple sorted second state parameter groups. Each second state parameter group is then stored in the corresponding second target memory in the switching control chip. Furthermore, at least one level of merge sorting is performed on the second state parameter groups stored in each second target memory in parallel, and the merged and sorted state parameters are stored in the first target memory. This utilizes the high concurrency characteristics of the FPGA-based switching control chip to improve the sorting speed of each state parameter through parallel processing. Additionally, the customizable development features of the FPGA-based switching control chip allow for multi-level merge sorting of each first state parameter group, further enhancing the sorting speed of each state parameter.

[0017] In some embodiments, the second target memory is one of a plurality of first memories, and the second target memory includes a first storage area for storing a corresponding first state parameter group and a second storage area for storing a corresponding second state parameter group; storing each second state parameter group into the corresponding second target memory in the switching control chip includes: storing each second state parameter group into the second storage area of ​​the corresponding second target memory.

[0018] In the above embodiments, the second target memory includes a first storage area for storing corresponding first state parameter groups and a second storage area for storing corresponding second state parameter groups; each second state parameter group is stored in the corresponding second storage area of ​​the second target memory. This partitioning and reuse of the second target memory—that is, storing the corresponding first state parameter group in the first storage area and the corresponding second state parameter group in the second storage area—reduces the consumption of memory resources.

[0019] In some embodiments, the first memory includes multiple storage units, each storage unit including a first bit range and a second bit range; storing the state parameters of each energy storage module in groups into multiple first memories in the switching control chip includes: for each energy storage module, storing the module identifier and state parameters of the energy storage module into the first bit range and the second bit range of a storage unit in the corresponding first memory, respectively; storing the sorted first state parameter group within the group into the first memory includes: binding each state parameter in the sorted first state parameter group within the group with the corresponding module identifier and storing it in the corresponding storage unit in the first memory; storing the merged and sorted state parameters into the first target memory includes: binding each merged and sorted state parameter with the corresponding module identifier and storing it in the corresponding storage unit in the first target memory.

[0020] In the above embodiments, the first memory includes multiple storage units, each storage unit including a first bit range and a second bit range. The module identifier and status parameters of each energy storage module are stored respectively in the first bit range and the second bit range of a corresponding storage unit in the first memory. Each status parameter in the sorted first state parameter group is bound to its corresponding module identifier and stored in its corresponding storage unit in the first memory. Finally, each merged and sorted state parameter is bound to its corresponding module identifier and stored in its corresponding storage unit in the first target memory. In this way, after sorting each state parameter, the sorting of the module identifiers of each energy storage module can be completed simultaneously, reducing the difficulty of development, simulation, and debugging.

[0021] In some embodiments, determining the energy storage modules to be switched out and the energy storage modules to be put into operation in the current control cycle from each energy storage module based on the merged and sorted state parameters includes: obtaining the sorted module identifiers from the first target memory based on the merged and sorted state parameters; determining the energy storage modules corresponding to the top number of module identifiers in the sorted order as the energy storage modules to be put into operation in the current control cycle, and determining the other energy storage modules in each energy storage module besides the energy storage modules to be put into operation as the energy storage modules to be switched out.

[0022] In the above embodiments, based on the merged and sorted state parameters, the sorting result of each module identifier is determined; the energy storage modules corresponding to the top-ranked target number of module identifiers are identified as the energy storage modules to be put into operation in the current control cycle, and the other energy storage modules besides those to be put into operation are identified as energy storage modules to be cut off. In this way, the energy storage modules corresponding to the top-ranked target number of module identifiers are put into operation, while the other energy storage modules are cut off, improving energy efficiency and optimizing the performance of the energy storage system.

[0023] In some embodiments, the state parameter group is stored in the third storage area of ​​the corresponding first memory, and the state parameters are sorted in descending order; sorting the first state parameter group stored in the first memory and storing the sorted first state parameter group in the first memory includes: sequentially performing the following operations for each storage address in the third storage area of ​​the first memory: reading the first state parameter in the storage address and the second state parameter in the next address of the storage address; comparing the first state parameter and the second state parameter; if the first state parameter is less than the second state parameter, writing the second state parameter and the first state parameter into the storage address and the next address of the storage address, respectively.

[0024] In the above embodiments, for each first memory, the first state parameter in the storage address and the second state parameter in the next address are read. If the first state parameter is less than the second state parameter, the storage addresses of the first state parameter and the second state parameter are swapped, and the first state parameter and the second state parameter are written into the corresponding storage addresses respectively. In this way, by comparing the size of the state parameters in adjacent storage addresses in the first memory in turn, the state parameters are written into the corresponding storage addresses, which reduces the consumption of additional memory resources and saves memory resources.

[0025] In some embodiments, the first memory includes a first read interface and a second read interface, as well as a first write interface and a second write interface; reading a first status parameter in a storage address and a second status parameter in the next address of the storage address includes: using the first read interface and the second read interface to read the first status parameter in the storage address and the second status parameter in the next address of the storage address in parallel; writing the second status parameter and the first status parameter to the storage address and the next address of the storage address respectively includes: using the first write interface and the second write interface to write the second status parameter and the first status parameter to the storage address and the next address of the storage address respectively in parallel.

[0026] In the above embodiments, the first read interface and the second read interface in the first memory are used to read the first status parameter in the storage address and the second status parameter in the next address of the storage address in parallel; the first write interface and the second write interface in the first memory are used to write the second status parameter and the first status parameter in parallel to the storage address and the next address of the storage address, respectively. In this way, the characteristics of dual-port storage are fully utilized to read and write each status parameter in parallel, which improves the efficiency of reading and writing each status parameter, thereby improving the efficiency of sorting each status parameter.

[0027] This disclosure provides an FPGA-based switching control chip, comprising: a first sorting module, a second sorting module, a determining module, and a control module, wherein:

[0028] The first sorting module is used to sort the state parameters of each energy storage module in the energy storage system to obtain multiple first state parameter groups after sorting within the group.

[0029] The second sorting module is used to perform at least one level of merge sorting on each of the sorted first state parameter groups within the group to obtain each state parameter after merge sorting.

[0030] The determination module is used to determine the energy storage modules to be cut out and the energy storage modules to be put into operation in the current control cycle based on the merged and sorted state parameters.

[0031] The control module is used to control the switching of each energy storage module based on the energy storage modules to be switched out and the energy storage modules to be put into operation.

[0032] In the above embodiments, firstly, the state parameters of each energy storage module in the energy storage system are grouped, and the grouped state parameters are sorted within each group to obtain multiple first state parameter groups after sorting within each group. Secondly, each first state parameter group is subjected to at least one level of merge sorting to obtain merged and sorted state parameters. Based on the merged and sorted state parameters, the energy storage modules to be switched out and to be put into operation in the current control cycle are determined. Finally, the switching control of the energy storage modules to be switched out and to be put into operation is performed. In this way, sorting the state parameters of each energy storage module group can improve the parallelism of the sorting process. Furthermore, it fully utilizes the extremely low data processing latency and strong parallel processing capability of the FPGA-based switching control chip, which can quickly sort the state parameters of each energy storage module and perform switching control of each energy storage module according to the sorted state parameters, thereby enabling stable switching control of each energy storage module within one control cycle.

[0033] In some embodiments, the switching control chip further includes a plurality of first memories, and the first sorting module includes: a first storage unit, used to group and store the state parameters of each energy storage module into the plurality of first memories in the switching control chip; each first memory stores a first state parameter group; and a first sorting unit, used to sort the first state parameter groups stored in each first memory in parallel, and store the sorted first state parameter groups within the group into the first memory.

[0034] In the above embodiments, the state parameters of each energy storage module are divided into multiple first state parameter groups, and each first memory stores one first state parameter group. The first state parameter groups stored in each first memory are sorted in parallel, and the sorted first state parameter groups within each group are then stored in the first memory. This parallel sorting of the first state parameter groups stored in the first memory fully utilizes the parallel processing capabilities of the FPGA-based switching control chip, accelerating the sorting speed and improving sorting efficiency.

[0035] In some embodiments, the switching control chip further includes a first target memory, and the second sorting module includes a second sorting unit, which is used to perform at least one level of merge sorting on the sorted first state parameter groups stored in each of the first memories, and to store the merged and sorted state parameters in the first target memory of the switching control chip.

[0036] In the above embodiments, at least one level of merge sorting is performed on each first state parameter group, and the merged and sorted state parameters are stored in the first target memory in the switching control chip. This allows for flexible control of the number of first state parameters in each first state parameter group, thereby enabling multi-level merge sorting of each first state parameter group and improving the speed of merge sorting.

[0037] In some embodiments, the switching control chip further includes a second target memory, and the second sorting unit includes: a first sorting subunit, which is further configured to perform a parallel merge sort on each pair of sorted first state parameter groups stored in each first memory to obtain a plurality of sorted second state parameter groups, and store each second state parameter group in the corresponding second target memory in the switching control chip; and a first storage subunit, which is further configured to perform at least one level of merge sort on each second state parameter group stored in each second target memory, and store each merge sorted state parameter in the first target memory.

[0038] In the above embodiments, the sorted first state parameter groups stored in each first memory are merged and sorted pairwise in parallel to obtain multiple sorted second state parameter groups. Each second state parameter group is then stored in the corresponding second target memory in the switching control chip. Furthermore, at least one level of merge sorting is performed on the second state parameter groups stored in each second target memory in parallel, and the merged and sorted state parameters are stored in the first target memory. This utilizes the high concurrency characteristics of the FPGA-based switching control chip to improve the sorting speed of each state parameter through parallel processing. Additionally, the customizable development features of the FPGA-based switching control chip allow for multi-level merge sorting of each first state parameter group, further enhancing the sorting speed of each state parameter.

[0039] In some embodiments, the second target memory is one of a plurality of first memories. The second target memory includes a first storage area for storing a corresponding first state parameter group and a second storage area for storing a corresponding second state parameter group. The first storage sub-unit is further used to store each second state parameter group into the second storage area in the corresponding second target memory.

[0040] In the above embodiments, the second target memory includes a first storage area for storing corresponding first state parameter groups and a second storage area for storing corresponding second state parameter groups; each second state parameter group is stored in the corresponding second storage area of ​​the second target memory. This partitioning and reuse of the second target memory—that is, storing the corresponding first state parameter group in the first storage area and the corresponding second state parameter group in the second storage area—reduces the consumption of memory resources.

[0041] In some embodiments, the first memory includes a plurality of storage units, each storage unit including a first bit range and a second bit range; the first storage unit includes a second storage subunit, used for storing the module identifier and status parameters of the energy storage module into the first bit range and the second bit range of a corresponding storage unit in the first memory for each energy storage module; the first sorting unit includes a third storage subunit, used for binding each status parameter in the first state parameter group after sorting within the group with the corresponding module identifier and storing it in the corresponding storage unit in the first memory; the second sorting unit includes a fourth storage subunit, used for binding each merged and sorted status parameter with the corresponding module identifier and storing it in the corresponding storage unit in the first target memory.

[0042] In the above embodiments, the first memory includes multiple storage units, each storage unit including a first bit range and a second bit range. The module identifier and status parameters of each energy storage module are stored respectively in the first bit range and the second bit range of a corresponding storage unit in the first memory. Each status parameter in the sorted first state parameter group is bound to its corresponding module identifier and stored in its corresponding storage unit in the first memory. Finally, each merged and sorted state parameter is bound to its corresponding module identifier and stored in its corresponding storage unit in the first target memory. In this way, after sorting each state parameter, the sorting of the module identifiers of each energy storage module can be completed simultaneously, reducing the difficulty of development, simulation, and debugging.

[0043] In some embodiments, the determining module includes: an acquisition unit, configured to acquire sorted module identifiers from a first target memory based on the merged and sorted state parameters; and a determining unit, configured to determine the energy storage modules corresponding to the top number of module identifiers in the sorted order as the energy storage modules to be put into operation in the current control cycle, and to determine the other energy storage modules among the energy storage modules besides the energy storage modules to be put into operation as the energy storage modules to be cut off.

[0044] In the above embodiments, based on the merged and sorted state parameters, the sorting result of each module identifier is determined; the energy storage modules corresponding to the top-ranked target number of module identifiers are identified as the energy storage modules to be put into operation in the current control cycle, and the other energy storage modules besides those to be put into operation are identified as energy storage modules to be cut off. In this way, the energy storage modules corresponding to the top-ranked target number of module identifiers are put into operation, while the other energy storage modules are cut off, improving energy efficiency and optimizing the performance of the energy storage system.

[0045] In some embodiments, the state parameter group is stored in the third storage area of ​​the corresponding first memory, and the state parameters are sorted in descending order; the first sorting unit is further configured to perform the following operations for each storage address in the third storage area of ​​the first memory in turn: read the first state parameter in the storage address and the second state parameter in the next address of the storage address; compare the first state parameter and the second state parameter; if the first state parameter is less than the second state parameter, write the second state parameter and the first state parameter into the storage address and the next address of the storage address, respectively.

[0046] In the above embodiments, for each first memory, the first state parameter in the storage address and the second state parameter in the next address are read. If the first state parameter is less than the second state parameter, the storage addresses of the first state parameter and the second state parameter are swapped, and the first state parameter and the second state parameter are written into the corresponding storage addresses respectively. In this way, by comparing the size of the state parameters in adjacent storage addresses in the first memory in turn, the state parameters are written into the corresponding storage addresses, which reduces the consumption of additional memory resources and saves memory resources.

[0047] In some embodiments, the first memory includes a first read interface and a second read interface, as well as a first write interface and a second write interface; the first sorting unit is further configured to use the first read interface and the second read interface to read in parallel a first status parameter in a storage address and a second status parameter in the next address of the storage address; the first sorting unit is further configured to use the first write interface and the second write interface to write the second status parameter and the first status parameter in parallel to the storage address and the next address of the storage address, respectively.

[0048] In the above embodiments, the first read interface and the second read interface in the first memory are used to read the first status parameter in the storage address and the second status parameter in the next address of the storage address in parallel; the first write interface and the second write interface in the first memory are used to write the second status parameter and the first status parameter in parallel to the storage address and the next address of the storage address, respectively. In this way, the characteristics of dual-port storage are fully utilized to read and write each status parameter in parallel, which improves the efficiency of reading and writing each status parameter, thereby improving the efficiency of sorting each status parameter.

[0049] This disclosure provides an energy storage system, including at least one energy storage module and the aforementioned switching control chip.

[0050] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory, and are not intended to limit the technical solutions of this disclosure. Attached Figure Description

[0051] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the specification, serve to illustrate the technical solutions of this disclosure.

[0052] Figure 1 A schematic diagram illustrating the implementation flow of a switching control method provided in this embodiment of the present disclosure;

[0053] Figure 2 A schematic diagram of the composition structure of a second target memory provided in an embodiment of this disclosure;

[0054] Figure 3 A schematic diagram of the composition structure of a first memory provided in an embodiment of this disclosure. Figure 1 ;

[0055] Figure 4 A schematic diagram of the composition structure of an FPGA-based switching control chip provided in this embodiment of the present disclosure. Figure 1 ;

[0056] Figure 5 A schematic diagram of the composition structure of an FPGA-based switching control chip provided in this embodiment of the present disclosure. Figure 2 ;

[0057] Figure 6 A schematic diagram of the composition structure of an FPGA-based switching control chip provided in this embodiment of the present disclosure. Figure 3 ;

[0058] Figure 7 A schematic diagram of the composition structure of an FPGA-based switching control chip provided in this embodiment of the present disclosure. Figure 4 ;

[0059] Figure 8 A schematic diagram of the composition structure of a first memory provided in an embodiment of this disclosure. Figure 2 ;

[0060] Figure 9 This is a schematic diagram of the composition structure of an energy storage system provided in an embodiment of the present disclosure;

[0061] Figure 10 This is a schematic diagram of an overall scheme for a sorting algorithm provided in an embodiment of the present disclosure;

[0062] Figure 11 This is a schematic diagram of a partition reuse provided in an embodiment of the present disclosure;

[0063] Figure 12 This is a schematic diagram illustrating the repackaging and storage of module serial numbers and module voltage values, provided in an embodiment of this disclosure. Detailed Implementation

[0064] To make the objectives, technical solutions, and advantages of this disclosure clearer, the technical solutions of this disclosure are further described in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limitations on this disclosure. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0065] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0066] The terms “first / second / third” are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that “first / second / third” may be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0067] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. The terminology used herein is for descriptive purposes only and is not intended to limit the scope of this disclosure.

[0068] In view of this, this disclosure provides a schematic flowchart of a switching control method, applied to an FPGA-based switching control chip. Figure 1 This is a schematic diagram illustrating the implementation flow of a geometric processing method provided in an embodiment of this disclosure, as shown below. Figure 1 As shown, the method includes the following steps S101 to S104:

[0069] Step S101: Sort the state parameters of each energy storage module in the energy storage system to obtain multiple first state parameter groups after sorting within each group;

[0070] Here, energy storage systems are a technology that uses various physical or chemical processes to convert energy into other forms of energy for storage and restore it to its original form of energy when needed.

[0071] Here, a Field-Programmable Gate Array (FPGA) is a semi-custom integrated circuit that allows users to program and configure at the hardware level to implement specific logic functions.

[0072] In some implementations, this switching control method is applied to FPGA-based switching control chips.

[0073] In some implementations, the FPGA-based switching control chip has the same advantages as the FPGA, such as at least one of the following: high flexibility, strong parallel processing capability, low latency, customizable development, high performance and low power consumption, high reliability and stability.

[0074] In some implementations, the energy storage system includes multiple energy storage modules. The state parameters of the multiple energy storage modules are divided into multiple first state parameter groups, and the state parameters in the multiple first state parameter groups are sorted in parallel within each group to obtain multiple sorted first state parameter groups.

[0075] In some implementations, the method for sorting the state parameters within a plurality of first state parameter groups may include at least one of insertion sort, selection sort, bubble sort, etc.

[0076] In some implementations, the state parameters may include, but are not limited to, at least one of voltage, capacitance, state of charge, and activation time.

[0077] Step S102: Perform at least one level of merge sort on each of the sorted first state parameter groups within the group to obtain each state parameter after merge sorting.

[0078] In some implementations, the first state parameter groups after sorting within the group are merged and sorted in pairs to obtain multiple second state parameter groups. The multiple second state parameter groups are then merged and sorted in pairs until the final merged and sorted state parameters are obtained.

[0079] Step S103: Based on the merged and sorted state parameters, determine the energy storage modules to be switched out and the energy storage modules to be put into operation in the current control cycle from each energy storage module;

[0080] In some implementations, based on the merged and sorted state parameters, a target number of energy storage modules are selected as the energy storage modules to be put into operation, and the other energy storage modules are selected as the energy storage modules to be switched out. That is, the energy storage modules with the highest state parameters are selected as the energy storage modules to be put into operation, and the other energy storage modules are selected as the energy storage modules to be switched out.

[0081] Step S104: Based on the energy storage modules to be switched out and the energy storage modules to be put into operation, perform switching control on each energy storage module.

[0082] In some implementations, based on the determined energy storage modules to be cut out and energy storage modules to be put into operation, the switching control chip cuts out the corresponding energy storage module to be cut out in the energy storage system and puts into operation the corresponding energy storage module to be put into operation.

[0083] In this embodiment, the state parameters of each energy storage module in the energy storage system are first grouped, and then sorted within each group to obtain multiple first state parameter groups. Next, each first state parameter group undergoes at least one level of merge sorting to obtain merged and sorted state parameters. Based on these merged and sorted state parameters, the energy storage modules to be switched out and to be put into operation within the current control cycle are determined. Finally, switching control is applied to the energy storage modules to be switched out and to be put into operation. This grouping and sorting of the state parameters of each energy storage module improves the parallelism of the sorting process. Furthermore, it fully utilizes the extremely low data processing latency and strong parallel processing capabilities of the FPGA-based switching control chip, enabling rapid sorting of the state parameters of each energy storage module and, based on the sorted state parameters, switching control of each energy storage module can be performed stably within one control cycle.

[0084] In some embodiments, the sorting of the state parameters of each energy storage module in the energy storage system to obtain multiple sorted first state parameter groups within the group, as described in step S101 above, may include the following steps S111 and S112:

[0085] Step S111: The status parameters of each energy storage module are grouped and stored in multiple first memories in the switching control chip; each first memory stores one group of first status parameters.

[0086] Here, the switching control chip may include multiple first memories.

[0087] In some embodiments, the first memory may be random access memory (RAM).

[0088] In some embodiments, the multiple grouped first state parameter groups are stored one-to-one into multiple first memories.

[0089] Step S112: For each first memory, sort the first state parameter group stored in the first memory in parallel, and store the sorted first state parameter group in the first memory.

[0090] In some embodiments, the state parameters in each first memory are sorted in parallel, and the sorted state parameters are stored in the corresponding first memory.

[0091] In this embodiment, the state parameters of each energy storage module are divided into multiple first state parameter groups, and one first state parameter group is stored in each first memory. The first state parameter groups stored in each first memory are sorted in parallel, and the sorted first state parameter groups within each group are stored in the first memory. In this way, the first state parameter groups stored in the first memory are sorted in parallel, which makes full use of the parallel processing capability of the FPGA-based switching control chip, speeds up the sorting process, and improves the sorting efficiency.

[0092] In some embodiments, the step S102 above, which involves performing at least one level of merge sorting on each of the sorted first state parameter groups within the group to obtain each state parameter after merge sorting, may include the following step S121:

[0093] Step S121: Perform at least one level of merge sorting on the sorted first state parameter groups stored in each first memory, and store the merged and sorted state parameters in the first target memory of the switching control chip.

[0094] Here, the switching control chip may include a first target memory.

[0095] In some implementations, the first target memory can be one of a plurality of first memories. If there is a first memory among the plurality of first memories with remaining space greater than the memory size occupied by the merged and sorted state parameters to be stored, that first memory is determined as the first target memory. This can reduce the consumption of memory resources.

[0096] In some implementations, the first target memory can be a second memory different from the first memory. When the remaining space in multiple first memories is less than the memory size occupied by the merged and sorted state parameters to be stored, the second memory is determined as the first target memory.

[0097] In this embodiment, at least one level of merge sorting is performed on each first state parameter group, and the merged and sorted state parameters are stored in the first target memory of the switching control chip. This allows for flexible control of the number of first state parameters in each first state parameter group, thereby enabling multi-level merge sorting of each first state parameter group and improving the speed of merge sorting.

[0098] In some embodiments, the step S121 above, which involves performing at least one level of merge sorting on the sorted first state parameter groups stored in each first memory and storing the merged and sorted state parameters in the first target memory of the switching control chip, may include the following steps S131 and S132:

[0099] Step S131: Using a parallel approach, merge and sort the sorted first state parameter groups stored in each first memory pairwise to obtain multiple sorted second state parameter groups, and store each second state parameter group in the corresponding second target memory in the switching control chip.

[0100] Here, the switching control chip may include a first target memory.

[0101] In some implementations, taking the merging and sorting of the first group of first state parameter groups and the second group of first state parameter groups as an example, the state parameters are read sequentially from the first storage address in the first memory storing the first group of first state parameter groups and the first storage address in the first memory storing the second group of first state parameter groups; the size relationship between the state parameters of the first group of first state parameter groups and the state parameters of the second group of first state parameter groups is compared sequentially; and the state parameters of the larger first state parameter group are stored in the corresponding second target memory in the switching control chip.

[0102] In some implementations, all the first state parameter groups are merged and sorted in pairs to obtain multiple sorted second state parameter groups.

[0103] In some implementations, every two first state parameter groups in each first state parameter group are merged and sorted in parallel to obtain multiple second state parameter groups. This leverages the high concurrency of the FPGA-based switching control chip to improve the sorting speed of the state parameters.

[0104] In some implementations, the second target memory may be one of a plurality of first memories, or it may be a third memory that is different from each of the first memories.

[0105] In some implementations, where both the first target memory and the second target memory are one of the first memory, the first target memory is different from the second memory.

[0106] Step S132: Perform at least one level of merge sorting on the second state parameter groups stored in each second target memory, and store the merged and sorted state parameters into the first target memory.

[0107] In some implementations, multiple first state parameter groups are merged and sorted in multiple levels until the final merged and sorted state parameters are obtained.

[0108] In this embodiment, the sorted first state parameter groups stored in each first memory are merged and sorted pairwise in parallel to obtain multiple sorted second state parameter groups. Each second state parameter group is then stored in the corresponding second target memory in the switching control chip. Furthermore, at least one level of merge sorting is performed on the second state parameter groups stored in each second target memory in parallel, and the merged and sorted state parameters are stored in the first target memory. This leverages the high concurrency of the FPGA-based switching control chip to improve the sorting speed of each state parameter through parallel processing. Additionally, the customizable development features of the FPGA-based switching control chip allow for multi-level merge sorting of each first state parameter group, further enhancing the sorting speed.

[0109] In some embodiments, such as Figure 2 As shown, the second target memory 201 is one of a plurality of first memories. The second target memory 201 includes a first storage area 202 for storing the corresponding first state parameter group and a second storage area 203 for storing the corresponding second state parameter group.

[0110] The step S131 above, which involves storing each second state parameter group into the corresponding second target memory in the switching control chip, may include the following step S141:

[0111] Step S141: Store each second state parameter group into the second storage area in the corresponding second target memory.

[0112] In some implementations, the second target memory can be divided into a first storage area and a second storage area, where the first storage area is used to store the corresponding first state parameter group and the second storage area is used to store the corresponding second state parameter group.

[0113] In some implementations, the storage address of the second target memory 201 may include address 0 to address 1023, the first storage range 202 may include address 0 to address 511, and the second storage range 203 may include address 512 to address 1023.

[0114] In some implementations, the starting address of the second state parameter group in the second target memory can be determined based on the ending address of the first state parameter group in the second target memory 201.

[0115] In this embodiment, the second target memory includes a first storage area for storing corresponding first state parameter groups and a second storage area for storing corresponding second state parameter groups; each second state parameter group is stored in the corresponding second storage area of ​​the second target memory. This partitioning and reuse of the second target memory—that is, storing the corresponding first state parameter group in the first storage area and the corresponding second state parameter group in the second storage area—reduces the consumption of memory resources.

[0116] In some embodiments, such as Figure 8 As shown, the first memory 301 includes a plurality of memory cells 801, and each memory cell 801 includes a first bit range 802 and a second bit range 803.

[0117] The step S111 above, which involves grouping and storing the state parameters of each energy storage module into multiple first memories in the switching control chip, may include the following step S151:

[0118] Step S151: For each energy storage module, store the module identifier and status parameters of the energy storage module into the first bit range and the second bit range of a storage cell in the corresponding first memory.

[0119] The step S112 described above, which involves storing the sorted first state parameter group within the group into the first memory, may include the following step S152:

[0120] Step S152: Bind each state parameter in the sorted first state parameter group and its corresponding module identifier to the corresponding storage unit in the first memory.

[0121] The step S121 above, which involves storing the merged and sorted state parameters into the first target memory in the switching control chip, may include the following step S153:

[0122] Step S153: Bind and store each merged and sorted state parameter with its corresponding module identifier into the corresponding storage unit in the first target memory.

[0123] In some embodiments, the first memory 301 includes a plurality of memory cells 801, each memory cell 801 may correspond to a memory address, and each memory cell 801 includes a first bit range 802 and a second bit range 803. The first bit range 802 is used to store the module identifier of the energy storage module, and the second bit range 803 is used to store the status parameters of the energy storage module.

[0124] In some implementations, the module identifier can be a module sequence number.

[0125] In some implementations, the module identifier and status parameters of the energy storage module are stored in the first bit range 802 and the second bit range 803 of a storage cell 801 in the corresponding first memory 301, respectively. For example, a storage cell 801 may include 24 bits, with the first bit range 802 consisting of bits 23 to 16 and the second bit range 803 consisting of bits 15 to 0. Therefore, the module identifier of the energy storage module is stored in bits 23 to 16, and the status parameters of the energy storage module are stored in bits 15 to 0.

[0126] In some implementations, each storage unit 801 stores the module identifier and status parameters of an energy storage module.

[0127] In some implementations, the fundamental purpose of sorting the state parameters of each energy storage module is to sort them according to the magnitude of the state parameters, obtain the module identifier of each sorted energy storage module, and finally control the switching of each energy storage module through the module identifier of each energy storage module.

[0128] In some implementations, the module identifier and status parameters are stored independently, and then stored again according to the merged and sorted results. This method is quite complex and causes great trouble for simulation and debugging.

[0129] In some implementations, this disclosure combines the module identifier and status parameters into a new data element, making full use of the FPGA's ease of bit manipulation. The module identifier is stored in the first bit interval 802, and the status parameters are stored in the second bit interval 803. After the status parameters of each energy storage module are sorted, the module identifier can be stored synchronously, which greatly reduces the difficulty of development, simulation, and debugging.

[0130] In this embodiment, the first memory includes multiple storage units, each storage unit including a first bit range and a second bit range. The module identifier and status parameters of each energy storage module are stored in the first bit range and second bit range of a corresponding storage unit in the first memory, respectively. Each status parameter in the sorted first state parameter group is bound to its corresponding module identifier and stored in its corresponding storage unit in the first memory. Finally, each merged and sorted state parameter is bound to its corresponding module identifier and stored in its corresponding storage unit in the first target memory. In this way, after sorting each state parameter, the sorting of the module identifiers of each energy storage module can be completed simultaneously, reducing the difficulty of development, simulation, and debugging.

[0131] In some embodiments, the step S103 above, which involves determining the energy storage modules to be switched out and the energy storage modules to be put into operation within the current control cycle based on the merged and sorted state parameters, may include the following steps S161 and S162:

[0132] Step S161: Based on the state parameters after merging and sorting, obtain the sorted module identifiers from the first target memory;

[0133] In some implementations, since the module identifier and status parameters of each energy storage module are stored in the same storage unit, the sorted module identifiers can also be obtained after completing the status parameters of each energy storage module.

[0134] Step S162: Identify the energy storage modules corresponding to the top-ranked target number of modules as the energy storage modules to be put into operation in the current control cycle, and identify the other energy storage modules in each energy storage module besides the energy storage modules to be put into operation as the energy storage modules to be cut off.

[0135] In some implementations, the target quantity is determined by the energy storage system based on actual needs.

[0136] In some implementations, during the operation of the energy storage system, within the current control cycle, the target number of target module identifiers with the highest ranking are selected according to the sorted module identifiers; based on each target module identifier, the energy storage modules to be put into operation are determined, and the other energy storage modules in each energy storage module, excluding the energy storage modules to be put into operation, are determined as energy storage modules to be cut off.

[0137] In some implementations, the state parameters of each energy storage module are sorted in each control cycle.

[0138] In this embodiment, based on the merged and sorted state parameters, the sorting result of each module identifier is determined. The energy storage modules corresponding to the top-ranked target number of module identifiers are identified as the energy storage modules to be put into operation in the current control cycle, and the other energy storage modules besides those to be put into operation are identified as energy storage modules to be cut off. In this way, the energy storage modules corresponding to the top-ranked target number of module identifiers are put into operation, and the other energy storage modules are cut off, which improves energy efficiency and optimizes the performance of the energy storage system.

[0139] In some embodiments, the state parameter group is stored in the third storage area of ​​the corresponding first memory, and the state parameters are sorted in descending order;

[0140] The above step S112, which involves sorting the first state parameter group stored in the first memory and storing the sorted first state parameter group into the first memory, may include the following step S171:

[0141] Step S171: For each memory address in the third memory region of the first memory, perform the following operations in sequence: read the first state parameter in the memory address and the second state parameter in the next memory address; compare the first state parameter and the second state parameter; if the first state parameter is less than the second state parameter, write the second state parameter and the first state parameter into the memory address and the next memory address, respectively.

[0142] In some implementations, bubble sort can be used to sort the first set of state parameters stored in the first memory.

[0143] In some implementations, the third storage area is the storage area in the first memory that stores the state parameter group.

[0144] In some implementations, the status parameters in each storage address of the third storage region are read from the beginning. If the first status parameter in the storage address is less than the second status parameter in the next storage address, the storage addresses of the first and second status parameters are swapped, that is, the second and first status parameters are written to the storage address and the next address of the storage address, respectively. If the first status parameter in the storage address is not less than the second status parameter in the next storage address, the storage addresses of the first and second status parameters remain unchanged, that is, the first and second status parameters are written to the storage address and the next address of the storage address, respectively.

[0145] In this embodiment of the present disclosure, for each first memory, a first state parameter in the storage address and a second state parameter in the next address are read. If the first state parameter is less than the second state parameter, the storage addresses of the first state parameter and the second state parameter are swapped, and the first state parameter and the second state parameter are written into their respective storage addresses. In this way, by comparing the size of the state parameters in adjacent storage addresses in the first memory in turn, the state parameters are written into their respective storage addresses, which reduces the consumption of additional memory resources and saves memory resources.

[0146] In some embodiments, such as Figure 3 As shown, the first memory 301 includes a first read interface 302 and a second read interface 303, as well as a first write interface 304 and a second write interface 305.

[0147] The step S171 described above, which involves reading the first status parameter in the storage address and the second status parameter in the next address of the storage address, may include the following step S181:

[0148] Step S181: Using the first read interface and the second read interface, read the first status parameter in the storage address and the second status parameter in the next address of the storage address in parallel.

[0149] The step S171 above, which involves writing the second state parameter and the first state parameter to the storage address and the next address of the storage address, respectively, may include the following step S182:

[0150] Step S182: Using the first write interface and the second write interface, write the second state parameter and the first state parameter to the storage address and the next address of the storage address in parallel.

[0151] In some implementations, the first memory 301 is a dual-port RAM, that is, it has two read interfaces and two write interfaces, which can read the status parameters of two memory addresses in parallel, and can write the two status parameters into the two memory addresses in parallel.

[0152] In some implementations, when sorting the first state parameter group stored in the first memory 301, the first state parameter in the storage address and the second state parameter in the next address of the storage address are read in parallel using the first read interface 302 and the second read interface 303; the second state parameter and the first state parameter are written in parallel using the first write interface 304 and the second write interface 305 to the storage address and the next address of the storage address, respectively.

[0153] In some implementations, for example, during the first clock cycle, the first status parameter in the storage address and the second status parameter in the next address of the storage address are read in parallel using the first read interface 302 and the second read interface 303. In the next clock cycle, the second status parameter and the first status parameter are written in parallel using the first write interface 304 and the second write interface 305 to the storage address and the next address of the storage address, respectively.

[0154] In this embodiment, the first read interface and the second read interface in the first memory are used to read the first status parameter in the storage address and the second status parameter in the next address of the storage address in parallel. The first write interface and the second write interface in the first memory are used to write the second status parameter and the first status parameter in parallel to the storage address and the next address of the storage address, respectively. This fully utilizes the characteristics of dual-port storage, enabling parallel reading and writing of each status parameter, improving the efficiency of reading and writing each status parameter, and thus improving the efficiency of sorting the status parameters.

[0155] This disclosure provides an FPGA-based switching control chip. Figure 4 A schematic diagram of the composition structure of an FPGA-based switching control chip provided in this embodiment of the present disclosure. Figure 1 ,like Figure 4As shown, the switching control chip 400 includes: a first sorting module 401, a second sorting module 402, a determination module 403, and a control module 404, wherein:

[0156] The first sorting module 401 is used to sort the state parameter groups of each energy storage module in the energy storage system to obtain multiple first state parameter groups after sorting within the group.

[0157] The second sorting module 402 is used to perform at least one level of merge sorting on each of the sorted first state parameter groups within the group to obtain each state parameter after merge sorting.

[0158] The determination module 403 is used to determine the energy storage modules to be cut out and the energy storage modules to be put into operation in the current control cycle based on the state parameters after merging and sorting.

[0159] The control module 404 is used to control the switching of each energy storage module based on the energy storage modules to be switched out and the energy storage modules to be put into operation.

[0160] In this embodiment, the state parameters of each energy storage module in the energy storage system are first grouped, and then sorted within each group to obtain multiple first state parameter groups. Next, each first state parameter group undergoes at least one level of merge sorting to obtain merged and sorted state parameters. Based on these merged and sorted state parameters, the energy storage modules to be switched out and to be put into operation within the current control cycle are determined. Finally, switching control is applied to the energy storage modules to be switched out and to be put into operation. This grouping and sorting of the state parameters of each energy storage module improves the parallelism of the sorting process. Furthermore, it fully utilizes the extremely low data processing latency and strong parallel processing capabilities of the FPGA-based switching control chip, enabling rapid sorting of the state parameters of each energy storage module and, based on the sorted state parameters, switching control of each energy storage module can be performed stably within one control cycle.

[0161] In some embodiments, such as Figure 5 As shown, the switching control chip 400 also includes multiple first memories 301, and the first sorting module 401 includes:

[0162] The first storage unit is used to group and store the status parameters of each energy storage module into multiple first memories in the switching control chip; each first memory stores one group of first status parameters.

[0163] The first sorting unit is used to sort the first state parameter groups stored in the first memory in parallel for each first memory, and store the sorted first state parameter groups in the first memory.

[0164] In this embodiment, the state parameters of each energy storage module are divided into multiple first state parameter groups, and one first state parameter group is stored in each first memory. The first state parameter groups stored in each first memory are sorted in parallel, and the sorted first state parameter groups within each group are stored in the first memory. In this way, the first state parameter groups stored in the first memory are sorted in parallel, which makes full use of the parallel processing capability of the FPGA-based switching control chip, speeds up the sorting process, and improves the sorting efficiency.

[0165] In some embodiments, such as Figure 6 As shown, the switching control chip 400 also includes a first target memory 601, and the second sorting module 402 includes:

[0166] The second sorting unit is used to perform at least one level of merge sorting on the sorted first state parameter groups stored in each first memory, and to store the merged and sorted state parameters into the first target memory in the switching control chip.

[0167] In this embodiment, at least one level of merge sorting is performed on each first state parameter group, and the merged and sorted state parameters are stored in the first target memory of the switching control chip. This allows for flexible control of the number of first state parameters in each first state parameter group, thereby enabling multi-level merge sorting of each first state parameter group and improving the speed of merge sorting.

[0168] In some embodiments, such as Figure 7 As shown, the switching control chip 400 also includes a second target memory 201, and the second sorting unit includes:

[0169] The first sorting subunit is also used to merge and sort the sorted first state parameter groups stored in each first memory in a parallel manner to obtain multiple sorted second state parameter groups, and store each second state parameter group in the corresponding second target memory in the switching control chip.

[0170] The first storage subunit is also used to perform at least one level of merge sorting on the second state parameter groups stored in each second target memory, and store the merged and sorted state parameters into the first target memory.

[0171] In this embodiment, the sorted first state parameter groups stored in each first memory are merged and sorted pairwise in parallel to obtain multiple sorted second state parameter groups. Each second state parameter group is then stored in the corresponding second target memory in the switching control chip. Furthermore, at least one level of merge sorting is performed on the second state parameter groups stored in each second target memory in parallel, and the merged and sorted state parameters are stored in the first target memory. This leverages the high concurrency of the FPGA-based switching control chip to improve the sorting speed of each state parameter through parallel processing. Additionally, the customizable development features of the FPGA-based switching control chip allow for multi-level merge sorting of each first state parameter group, further enhancing the sorting speed.

[0172] In some embodiments, the second target memory is one of a plurality of first memories, and the second target memory includes a first storage area for storing a corresponding first state parameter group and a second storage area for storing a corresponding second state parameter group, wherein:

[0173] The first storage sub-unit is also used to store each second state parameter group into the second storage area in the corresponding second target memory.

[0174] In this embodiment, the second target memory includes a first storage area for storing corresponding first state parameter groups and a second storage area for storing corresponding second state parameter groups; each second state parameter group is stored in the corresponding second storage area of ​​the second target memory. This partitioning and reuse of the second target memory—that is, storing the corresponding first state parameter group in the first storage area and the corresponding second state parameter group in the second storage area—reduces the consumption of memory resources.

[0175] In some embodiments, such as Figure 8 As shown, the first memory 301 includes a plurality of memory cells 801, and each memory cell 801 includes a first bit range 802 and a second bit range 803.

[0176] The first storage unit includes a second storage subunit, which is used to store the module identifier and status parameters of the energy storage module into the first bit range 802 and the second bit range 803 of a storage unit in the corresponding first memory 301 for each energy storage module.

[0177] The first sorting unit includes a third storage subunit, which is used to bind and store each state parameter in the sorted first state parameter group with the corresponding module identifier to the corresponding storage unit 601 in the first memory 301.

[0178] The second sorting unit includes a fourth storage subunit, which is used to bind and store the merged and sorted state parameters with the corresponding module identifiers in the corresponding storage unit 801 in the first target memory.

[0179] In this embodiment, the first memory includes multiple storage units, each storage unit including a first bit range and a second bit range. The module identifier and status parameters of each energy storage module are stored in the first bit range and second bit range of a corresponding storage unit in the first memory, respectively. Each status parameter in the sorted first state parameter group is bound to its corresponding module identifier and stored in its corresponding storage unit in the first memory. Finally, each merged and sorted state parameter is bound to its corresponding module identifier and stored in its corresponding storage unit in the first target memory. In this way, after sorting each state parameter, the sorting of the module identifiers of each energy storage module can be completed simultaneously, reducing the difficulty of development, simulation, and debugging.

[0180] In some embodiments, the determining module includes:

[0181] The acquisition unit is used to acquire the sorted module identifiers from the first target memory based on the merged and sorted state parameters.

[0182] The determination unit is used to identify the energy storage modules corresponding to the top-ranked target number of modules as the energy storage modules to be put into operation in the current control cycle, and to identify the other energy storage modules in each energy storage module besides the energy storage modules to be put into operation as the energy storage modules to be cut off.

[0183] In this embodiment, based on the merged and sorted state parameters, the sorting result of each module identifier is determined. The energy storage modules corresponding to the top-ranked target number of module identifiers are identified as the energy storage modules to be put into operation in the current control cycle, and the other energy storage modules besides those to be put into operation are identified as energy storage modules to be cut off. In this way, the energy storage modules corresponding to the top-ranked target number of module identifiers are put into operation, and the other energy storage modules are cut off, which improves energy efficiency and optimizes the performance of the energy storage system.

[0184] In some embodiments, the state parameter group is stored in the third storage area of ​​the corresponding first memory, and the state parameters are sorted in descending order;

[0185] The first sorting unit is also configured to perform the following operations sequentially for each storage address in the third storage area of ​​the first memory: read the first state parameter in the storage address and the second state parameter in the next address of the storage address; compare the first state parameter and the second state parameter; if the first state parameter is less than the second state parameter, write the second state parameter and the first state parameter into the storage address and the next address of the storage address, respectively.

[0186] In this embodiment of the present disclosure, for each first memory, a first state parameter in the storage address and a second state parameter in the next address are read. If the first state parameter is less than the second state parameter, the storage addresses of the first state parameter and the second state parameter are swapped, and the first state parameter and the second state parameter are written into their respective storage addresses. In this way, by comparing the size of the state parameters in adjacent storage addresses in the first memory in turn, the state parameters are written into their respective storage addresses, which reduces the consumption of additional memory resources and saves memory resources.

[0187] In some embodiments, the first memory includes a first read interface and a second read interface, as well as a first write interface and a second write interface;

[0188] The first sorting unit is also used to read the first status parameter in the storage address and the second status parameter in the next address of the storage address in parallel using the first read interface and the second read interface.

[0189] The first sorting unit is also used to write the second state parameter and the first state parameter to the storage address and the next address of the storage address in parallel using the first write interface and the second write interface.

[0190] In this embodiment, the first read interface and the second read interface in the first memory are used to read the first status parameter in the storage address and the second status parameter in the next address of the storage address in parallel. The first write interface and the second write interface in the first memory are used to write the second status parameter and the first status parameter in parallel to the storage address and the next address of the storage address, respectively. This fully utilizes the characteristics of dual-port storage, enabling parallel reading and writing of each status parameter, improving the efficiency of reading and writing each status parameter, and thus improving the efficiency of sorting the status parameters.

[0191] This disclosure provides an energy storage system, such as... Figure 9 As shown, the energy storage system 900 includes at least one energy storage module 901 and the aforementioned switching control chip 400.

[0192] The following describes the application of the embodiments of this disclosure in real-world scenarios.

[0193] Sorting algorithms are a common and fundamental data processing method. Without considering time overhead, they are usually implemented using a Central Processing Unit (CPU) or Microcontroller Unit (MCU). However, with the advent of the big data era, using CPU / MCU to sort large amounts of data will consume a lot of CPU resources and limit product performance.

[0194] Taking flexible DC and direct-connected energy storage systems as examples, the control equipment needs to calculate the number of switching modules based on voltage commands, and then generate switching commands to ultimately control the number of switching modules. To optimally select suitable target switching modules, the control equipment needs to sort them according to a comprehensive index of capacitor voltage or cell state (State of X, SOX). Since the execution cycle of such control equipment is short, typically less than 50 microseconds (µs), chips with parallel data processing capabilities, such as FPGAs, are generally used to accelerate the sorting process.

[0195] Related technologies provide a merge sort method based on pipelined processes and a valve control device using this method. This method is an efficient parallel algorithm based on the merge operation. Merge sort is the operation of merging two sorted arrays into one sorted array. It compares the elements in the two arrays, placing the smaller element into a third array, and repeats this process. If one array reaches its end first, the remaining part of the other array is placed into the third array, ultimately merging the two different arrays into a single sorted array. By utilizing pipelined technology, the critical path in the algorithm is shortened. Even with the increase in IGBT sub-modules in each bridge arm, it ensures the speed of capacitor voltage sorting, consumes fewer resources, and improves chip utilization.

[0196] However, the sorting methods in related technologies require approximately 1022 * 16 = 16k register resources for 512 data points (16 bits wide per data point), which is a significant register consumption. Firstly, this leads to considerable difficulties in FPGA placement and routing. Secondly, due to the large resource overhead, the chip selection requirements become more stringent, reducing the versatility of the solution. Finally, the code size becomes exceptionally large, making development, simulation, and maintenance difficult, and troubleshooting will be challenging. Therefore, fundamentally, the sorting methods in related technologies are only suitable for data sizes of up to 50 points; implementation becomes difficult beyond this range.

[0197] Based on the above description, this disclosure provides an FPGA sorting algorithm for multiple voltage levels in the field of energy storage valves.

[0198] The overall scheme of the sorting algorithm provided in this disclosure is as follows: Figure 10 As shown, the algorithm is divided into three levels from left to right. The first level uses bubble sort, and the second and third levels use merge sort. Taking four RAM blocks (RAM1, RAM2, RAM3, and RAM4) and 16 points to be sorted as an example, the basic workflow of the algorithm provided in this disclosure embodiment is illustrated. The basic workflow may include steps S1001 and S1003:

[0199] Step S1001: Distribute the 16 data points evenly into the four RAM blocks of the first level, with each RAM block containing four data points. The state machine controls the four RAM blocks to begin bubble sorting in parallel.

[0200] Here, the state machine can be as follows: Figure 4 The first sorting module 401 shown.

[0201] Taking the sorting of data in RAM1 as an example, first, retrieve the data at address 0 and address 1 in RAM1. If the value at address 0 is smaller, swap the data at address 0 and address 1. Then, retrieve the data at address 1 and address 2. If the value at address 1 is smaller, swap the data at address 1 and address 2. And so on, to complete the sorting of all four data items in RAM1 from largest to smallest.

[0202] Step S812: Merge the data in RAM1 and RAM2, and write the merged result into RAM1; merge the data in RAM3 and RAM4, and write the merged result into RAM3;

[0203] RAM1 and RAM2 are grouped together. Data is read from address 0. The data in RAM1 and RAM2 is compared. The larger data is stored in RAM1 at the third level, while the smaller data waits for the next comparison. This process continues until all data is compared and written to the third level.

[0204] RAM3 and RAM4 are grouped together. Data is read from address 0. Then the data in RAM3 and RAM4 are compared. The larger data is stored in RAM3 at the third level, and the smaller data waits for the next comparison. This process continues until all data is compared and written to the third level.

[0205] Step S813: Merge the data in RAM1 and RAM3, and write the merged result into RAM2.

[0206] RAM1 and RAM3 are grouped together. Data is read from address 0. The data size of RAM1 and RAM3 is compared. The larger data is stored in the last level RAM2, and the smaller data waits for the next comparison. This process continues until all data is compared and written to the third level.

[0207] In order to accelerate the speed of bubble sort in the first stage, this embodiment of the disclosure makes full use of the characteristics of true dual-port RAM, that is, reading data from both ports simultaneously, for example, in the first clock cycle, such as... Figure 3 As shown, the first read interface 302 reads address 0, and the second read interface 303 reads address 1. By comparison, if the value of address 0 is less than the value of address 1, the data at addresses 0 and 1 are swapped, and in the second clock cycle, the data is rewritten back to the corresponding address of the block RAM through the first write interface 304 and the second write interface 305.

[0208] To reduce the overhead of block RAM resources, this embodiment of the disclosure employs a partitioning and multiplexing method for block RAM, such as... Figure 11 As shown, the entire block RAM region is divided into an upper half 1101 and a lower half 1102, as follows: Figure 10 When performing merge sort from the second level to the third level, the merge sort result is written to the lower half of RAM1, 1102, thus saving the number of RAM blocks; the final sorting result is written to the lower half of RAM2, 1102.

[0209] The fundamental purpose of the sorting algorithm used for submodule switching control in this embodiment is to sort the modules according to their voltage values ​​and ultimately obtain the submodule serial numbers. That is, the module voltage values ​​are the sorting logic, and the sorted module serial numbers are the final output results of the sorting.

[0210] In related technologies, the module voltage value and module serial number are stored independently, and the module serial number is stored again according to the sorting result. This method is relatively complex to implement and causes great trouble for simulation and debugging.

[0211] This embodiment combines the module serial number and module voltage value into a new data element, fully utilizing the FPGA's ease of bit manipulation, such as... Figure 12 As shown, the module voltage values ​​of bits 15 to 0 are used for sorting, and the module serial numbers of bits 23 to 16 are used as the sorting result for storage. After sorting based on all module voltage values, the module serial numbers can be stored simultaneously, which greatly reduces the difficulty of development, simulation and debugging.

[0212] This paper compares the resource overhead of a pipeline-based sorting method with that of the present disclosure. As shown in Table 1, register resources are the number of registers multiplied by a data width of 16, and block RAM resources are the number of block RAMs used. In the embodiments of this disclosure, each block RAM has a space of 1024 and a data width of 16 bits.

[0213] In Table 1, when the number of data items is 32, the register resources consumed by pipelined sorting are 992 and the block RAM resources are 0, while the register resources consumed by this disclosure are 832 and the block RAM resources are 16; when the number of data items is 256, the register resources consumed by pipelined sorting are 8160 and the block RAM resources are 0, while the register resources consumed by this disclosure are 832 and the block RAM resources are 16; when the number of data items is 512, the register resources consumed by pipelined sorting are 16352 and the block RAM resources are 0, while the register resources consumed by this disclosure are 832 and the block RAM resources are 16.

[0214] As shown in Table 1, this disclosure consumes 832 register resources and 16 block RAM resources when the number of data items is between 32 and 512.

[0215] Table 1 Comparison of Logical Resource Consumption

[0216]

[0217] As shown in Table 1, pipelined sorting consumes an enormous amount of register resources as the number of data items increases. However, in this invention, the overhead of register resources and block RAM resources does not change with the increase of the number of data items, and the overall overhead is very small. Therefore, this invention solves the problem of excessive logic resource consumption and thus has greater versatility.

[0218] In this embodiment, the voltage values ​​of each energy storage module are grouped, and bubble sort is used to sort the voltage values ​​within each group. Then, a multi-level merge sort is performed on each pair of sorted voltage values ​​to obtain the sorted result of the voltage values ​​of each energy storage module. This method is easy to implement on an FPGA and reduces the consumption of logic resources. It utilizes the characteristics of dual-port RAM, employing dual-port parallel read and write operations to improve algorithm performance. Furthermore, it fully leverages the ease of bit manipulation on FPGAs, using bits 15-0 of the module voltage values ​​for sorting and bits 23-16 of the module sequence number as the sorting result storage. After sorting all module voltage values, the module sequence number can be stored synchronously, greatly reducing the difficulty of development, simulation, and debugging.

[0219] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above steps / processes do not imply a sequential order of execution; the execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above embodiments of this disclosure are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0220] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0221] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed may be through some interfaces, and the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0222] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units. They may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0223] Furthermore, in the various embodiments of this disclosure, all functional units can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in a combination of hardware and software functional units. Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, read-only memory (ROM), magnetic disks, or optical disks.

[0224] Alternatively, if the integrated units described above are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this disclosure, or the part that contributes to related technologies, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods described in the various embodiments of this disclosure. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, ROM, magnetic disks, or optical disks.

[0225] The above description is merely an embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A switching control method, characterized in that, The method, applied to FPGA-based switching control chips, includes: The state parameters of each energy storage module in the energy storage system are sorted to obtain multiple first state parameter groups after sorting within each group. Perform at least one level of merge sorting on each of the first state parameter groups after sorting within the group to obtain each of the state parameters after merge sorting. Based on the merged and sorted state parameters, determine the energy storage modules to be switched out and the energy storage modules to be put into operation in the current control cycle from each energy storage module. Based on the energy storage modules to be switched out and the energy storage modules to be put into operation, the switching control of each energy storage module is performed.

2. The switching control method according to claim 1, characterized in that, The process of sorting the state parameters of each energy storage module in the energy storage system yields multiple first state parameter groups after sorting within each group, including: The status parameters of each energy storage module are grouped and stored in multiple first memories in the switching control chip; each first memory stores one group of first status parameters. In parallel, for each of the first memories, the first state parameter groups stored in the first memory are sorted, and the sorted first state parameter groups within the group are stored in the first memory.

3. The switching control method according to claim 2, characterized in that, The step of performing at least one level of merge sort on each of the first state parameter groups after sorting within the group to obtain each of the merge sorted state parameters includes: Perform at least one level of merge sorting on the sorted first state parameter groups stored in each of the first memories, and store the merged and sorted state parameters in the first target memory of the switching control chip.

4. The switching control method according to claim 3, characterized in that, The step of performing at least one level of merge sorting on the sorted first state parameter groups stored in each of the first memories, and storing the merged and sorted state parameters into the first target memory in the switching control chip, includes: In a parallel manner, the sorted first state parameter groups stored in each of the first memories are merged and sorted in pairs to obtain multiple sorted second state parameter groups. Each second state parameter group is then stored in the corresponding second target memory in the switching control chip. Perform at least one level of merge sorting on the second state parameter groups stored in each of the second target memories, and store the merged and sorted state parameters in the first target memory.

5. The switching control method according to claim 4, characterized in that, The second target memory is one of the plurality of first memories, and the second target memory includes a first storage area for storing the corresponding first state parameter group and a second storage area for storing the corresponding second state parameter group; The step of storing each of the second state parameter groups into the corresponding second target memory in the switching control chip includes: Each of the second state parameter groups is stored in the second storage area of ​​the corresponding second target memory.

6. The switching control method according to claim 3, characterized in that, The first memory includes multiple storage cells, and each storage cell includes a first bit range and a second bit range; The step of grouping and storing the status parameters of each energy storage module into multiple first memories in the switching control chip includes: for each energy storage module, storing the module identifier and status parameters of the energy storage module into the first bit range and the second bit range of a storage cell in the corresponding first memory; The step of storing the sorted first state parameter group into the first memory includes: binding each state parameter in the sorted first state parameter group into the corresponding module identifier and storing it into the corresponding storage unit of the first memory; The step of storing the merged and sorted state parameters into the first target memory in the switching control chip includes: binding the merged and sorted state parameters with their corresponding module identifiers and storing them in the corresponding storage units in the first target memory.

7. The switching control method according to claim 6, characterized in that, The step of determining the energy storage modules to be switched out and the energy storage modules to be put into operation within the current control cycle based on the merge sorted state parameters includes: Based on the merged and sorted state parameters, the sorted module identifiers are obtained from the first target memory; The energy storage modules corresponding to the top-ranked target number of module identifiers are identified as the energy storage modules to be put into operation in the current control cycle, and the other energy storage modules in each energy storage module, excluding the energy storage modules to be put into operation, are identified as the energy storage modules to be cut off.

8. The switching control method according to any one of claims 2 to 7, characterized in that, The state parameter group is stored in the third storage area of ​​the corresponding first memory, and the state parameters are sorted in descending order. The step of sorting the first state parameter group stored in the first memory and storing the sorted first state parameter group into the first memory includes: For each memory address in the third memory region of the first memory, the following operations are performed sequentially: read the first status parameter in the memory address and the second status parameter in the next address of the memory address; compare the first status parameter and the second status parameter; if the first status parameter is less than the second status parameter, write the second status parameter and the first status parameter into the memory address and the next address of the memory address, respectively.

9. The switching control method according to claim 8, characterized in that, The first memory includes a first read interface and a second read interface, as well as a first write interface and a second write interface; The step of reading the first status parameter in the storage address and the second status parameter in the next address of the storage address includes: Using the first read interface and the second read interface, the first status parameter in the storage address and the second status parameter in the next address of the storage address are read in parallel. The step of writing the second state parameter and the first state parameter to the storage address and the next address of the storage address, respectively, includes: Using the first write interface and the second write interface, the second status parameter and the first status parameter are written in parallel to the storage address and the next address of the storage address, respectively.

10. A switching control chip based on FPGA, characterized in that, include: The system comprises a first sorting module, a second sorting module, a determining module, and a control module, wherein: The first sorting module is used to sort the state parameter groups of each energy storage module in the energy storage system to obtain multiple first state parameter groups after sorting within the group. The second sorting module is used to perform at least one level of merge sorting on each of the first state parameter groups after sorting within the group, to obtain each of the state parameters after merge sorting. The determining module is used to determine, based on the merged and sorted state parameters of each energy storage module, the energy storage modules to be cut out and the energy storage modules to be put into operation in the current control cycle. The control module is used to control the switching of each energy storage module based on the energy storage module to be switched out and the energy storage module to be put into operation.

11. The switching control chip according to claim 10, characterized in that, The switching control chip further includes multiple first memories, and the first sorting module includes: The first storage unit is used to group and store the status parameters of each energy storage module into multiple first memories in the switching control chip; each first memory stores one group of first status parameters. The first sorting unit is used to sort the first state parameter groups stored in the first memory in parallel for each of the first memories, and store the sorted first state parameter groups in the first memory.

12. The switching control chip according to claim 11, characterized in that, The switching control chip further includes a first target memory, and the second sorting module includes: The second sorting unit is used to perform at least one level of merge sorting on the sorted first state parameter groups stored in each of the first memories, and to store the merged and sorted state parameters into the first target memory in the switching control chip.

13. The switching control chip according to claim 12, characterized in that, The switching control chip further includes a second target memory, and the second sorting unit includes: The first sorting subunit is also used to perform a parallel sorting of the sorted first state parameter groups stored in each of the first memories to obtain multiple sorted second state parameter groups, and store each of the second state parameter groups in the corresponding second target memory in the switching control chip. The first storage subunit is further configured to perform at least one level of merge sorting on the second state parameter groups stored in each of the second target memories, and store the merged and sorted state parameters into the first target memory.

14. The switching control chip according to claim 13, characterized in that, The second target memory is one of the plurality of first memories, and the second target memory includes a first storage area for storing the corresponding first state parameter group and a second storage area for storing the corresponding second state parameter group, wherein: The first storage subunit is further configured to store each of the second state parameter groups into a second storage area in the corresponding second target memory.

15. The switching control chip according to claim 12, characterized in that, The first memory includes multiple storage cells, and each storage cell includes a first bit range and a second bit range; The first storage unit includes a second storage subunit, which is used to store the module identifier and status parameters of each energy storage module into the first bit range and the second bit range of a storage unit in the corresponding first memory for each energy storage module. The first sorting unit includes a third storage subunit, which is used to bind and store each state parameter in the first state parameter group after sorting within the group with the corresponding module identifier to the corresponding storage unit in the first memory; The second sorting unit includes a fourth storage subunit, which is used to bind and store the merged and sorted state parameters with their corresponding module identifiers in the corresponding storage unit of the first target memory.

16. The switching control chip according to claim 15, characterized in that, The determining module includes: The acquisition unit is used to acquire the sorted module identifiers from the first target memory based on the merged and sorted state parameters. The determining unit is used to determine the energy storage modules corresponding to the top-ranked target number of module identifiers as the energy storage modules to be put into operation in the current control cycle, and to determine the other energy storage modules among the energy storage modules besides the energy storage modules to be put into operation as energy storage modules to be cut off.

17. The switching control chip according to any one of claims 11 to 16, characterized in that, The state parameter group is stored in the third storage area of ​​the corresponding first memory, and the state parameters are sorted in descending order. The first sorting unit is further configured to perform the following operations sequentially for each storage address in the third storage interval of the first memory: read a first status parameter in the storage address and a second status parameter in the next address of the storage address; compare the first status parameter and the second status parameter; and if the first status parameter is less than the second status parameter, write the second status parameter and the first status parameter into the storage address and the next address of the storage address, respectively.

18. The switching control chip according to claim 17, characterized in that, The first memory includes a first read interface and a second read interface, as well as a first write interface and a second write interface; The first sorting unit is also used to read the first status parameter in the storage address and the second status parameter in the next address of the storage address in parallel using the first read interface and the second read interface; The first sorting unit is further configured to use the first write interface and the second write interface to write the second status parameter and the first status parameter to the storage address and the next address of the storage address in parallel.

19. An energy storage system, characterized in that, It includes at least one energy storage module and a switching control chip as described in any one of claims 10 to 18.

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