Full-band low-phase-noise small-step phase shifting system and method and storage medium

Abstract

The invention belongs to the field of signal processing. The invention provides a full-band low-phase-noise small-stepping phase shift system. The full-band low-phase-noise small-stepping phase shift system comprises a control signal input module, a signal input port, an orthogonal decomposition and attenuation module, an output signal synthesis module and a signal output port, the signal input port is connected with the orthogonal decomposition and attenuation module, the orthogonal decomposition and attenuation module is respectively connected with the control signal input module and the output signal synthesis module, and the output signal synthesis module is connected with the signal output port; the orthogonal decomposition and attenuation module is used for performing orthogonal decomposition on an input signal transmitted through a signal input port and performing amplitude adjustment on the decomposed orthogonal signal; the control signal input module is used for providing an external control signal for the orthogonal decomposition and attenuation module; and the output signal synthesis module is used for synthesizing the orthogonal signal after amplitude adjustment to obtain a phase shift signal, and outputting the phase shift signal through a signal output port.

Description

Technical Field

[0001] This invention belongs to the field of signal processing, and particularly relates to a full-band low phase noise small-step phase shifting system, method, and storage medium. Background Technology

[0002] Phase shifters are widely used in radio frequency circuits. There are generally two methods of phase shifting: one is digital phase shifters, such as... Figure 1 As shown, one type is an analog phase shifter, such as... Figure 2 As shown.

[0003] Digital phase shifters achieve phase changes by switching the delay line through which the signal passes using a switch. The delay line can be a transmission line. This phase shifting method offers high temperature stability and high phase shift accuracy. However, due to the miniaturization requirements of integrated circuits, the number of delay line segments cannot be too large, resulting in a large phase shift step, typically divided into 6 segments. The phase shift amounts for each segment are 5.625°, 11.25°, 22.5°, 45°, 90°, and 180°, respectively. Furthermore, the frequency cannot be too low; otherwise, the increased wavelength would lead to excessively long delay lines. Typically, the frequency is ≥1GHz.

[0004] An analog phase shifter internally contains an LC network, which can be of the Γ-type, π-type, or other forms. Some capacitors in the network are replaced with varactor diodes. An external VCTR voltage is applied in reverse to the varactor diodes. When the VCTR voltage changes, the capacitance of the varactor diodes also changes, thus changing the phase shift of the LC network and achieving the purpose of signal phase shifting. This phase shifting method has a small phase shift step; theoretically, as long as the control voltage accuracy is high enough, the phase shift is continuous. However, due to the use of varactor diodes, temperature stability deteriorates. Furthermore, the nonlinear characteristics of varactor diodes cause the signal phase noise to deteriorate rapidly. Additionally, it is not suitable for high-frequency signals. As the signal frequency increases, the magnitude of the capacitance and inductance in the LC network decreases, requiring extremely high precision and making implementation very difficult. Summary of the Invention

[0005] This invention addresses the problem that existing phase shifters cannot achieve high-precision 0°–360° phase shifting, and provides a full-band low-phase-noise small-step phase shifting system, including a control signal input module, a signal input port, an orthogonal decomposition and attenuation module, an output signal synthesis module, and a signal output port; the signal input port is connected to the orthogonal decomposition and attenuation module, the orthogonal decomposition and attenuation module is connected to both the control signal input module and the output signal synthesis module, and the output signal synthesis module is connected to the signal output port;

[0006] The orthogonal decomposition and attenuation module is used to orthogonally decompose the input signal transmitted through the signal input port, and adjust the amplitude of the decomposed orthogonal signals respectively.

[0007] The control signal input module is used to provide external control signals to the orthogonal decomposition and attenuation module;

[0008] The output signal synthesis module is used to synthesize the amplitude-adjusted quadrature signals to obtain a phase-shifted signal, which is then output through the signal output port.

[0009] In some embodiments, the orthogonal decomposition and attenuation module includes a 90° bridge, a first 180° bridge, a second 180° bridge, a first switch SW1, a second switch SW2, a first voltage-controlled attenuator, a second voltage-controlled attenuator, a third switch SW3, and a fourth switch SW4.

[0010] The signal input port is connected to a 90° bridge, which is connected to a first 180° bridge and a second 180° bridge. The first 180° bridge is connected to a first voltage-controlled attenuator via a first switch SW1. The first voltage-controlled attenuator is connected to a third switch SW3, which is connected to the output signal synthesis module. The first switch SW1, the third switch SW3, and the first voltage-controlled attenuator are each connected to the control signal input module.

[0011] The second 180° bridge is connected to the second voltage-controlled attenuator via the second switch SW2. The second voltage-controlled attenuator is connected to the fourth switch SW4. The fourth switch SW4 is connected to the output signal synthesis module. The second switch SW2, the fourth switch SW4, and the second voltage-controlled attenuator are respectively connected to the control signal input module.

[0012] The first switch SW1 and the second switch SW2 are single-pole double-throw switches; the third switch SW3 and the fourth switch SW4 are single-pole single-throw switches.

[0013] In some embodiments, the control signal input module includes an external serial port control signal input terminal, a serial port driver module, an FPGA module, a first RC low-pass filter, a first operational amplifier, a second RC low-pass filter, and a second operational amplifier;

[0014] After the external control command is input via the external serial port control signal input terminal, it is sent to the FPGA by the serial port driver module to generate the first pulse width modulation signal, the second pulse width modulation signal, the first switch control signal, the second switch control signal, the third switch control signal, and the fourth switch control signal;

[0015] The first pulse width modulation signal passes sequentially through a first RC low-pass filter and a first operational amplifier, and is used to control the first voltage-controlled attenuator.

[0016] The second pulse width modulation signal passes sequentially through the second RC low-pass filter and the second operational amplifier, and is used to control the connection of the second voltage-controlled attenuator;

[0017] The first switch control signal is used to control the first switch SW1;

[0018] The second switch control signal is used to control the second switch SW2;

[0019] The third switch control signal is used to control the third switch SW3;

[0020] The fourth switch control signal is used to control the fourth switch SW4.

[0021] In some embodiments, the 90° bridge, the first 180° bridge, and the second 180° bridge are microstrip bridges or balun bridges.

[0022] In some embodiments, the first voltage-controlled attenuator and the second voltage-controlled attenuator have the same circuit structure, including a voltage-controlled attenuator input terminal RFIN, a first DC blocking coupling capacitor C1, a first diode D1, a first resistor R1, a first phase shifting module, a second diode D2, a third resistor R3, a first choke coil L1, a third filter capacitor C3, a second phase shifting module, a second DC blocking coupling capacitor C2, a third diode D3, a second resistor R2, a control voltage input terminal, and a voltage-controlled attenuator output terminal RFOUT;

[0023] The first switch SW1 is connected to one end of the first DC blocking coupling capacitor C1 via the input terminal RFIN of the voltage-controlled attenuator. The other end of the first DC blocking coupling capacitor C1 is connected to one end of the first diode D1 and the input terminal of the first phase shifting module. The other end of the first diode D1 is connected to one end of the first resistor R1, and the other end of the first resistor R1 is grounded. The output terminal of the first phase shifting module is connected to one end of the second diode D2, the input terminal of the second phase shifting module, and one end of the third resistor R3. The other end of the second diode D2 is grounded, and the other end of the third resistor R3 is connected to the first choke coil L. One end of the first choke coil L1 is connected to the control voltage input terminal and the other end of the third filter capacitor C3. The other end of the third filter capacitor C3 is grounded. The control voltage input terminal is connected to the control signal input module. The output terminal of the second phase shift module is connected to one end of the second DC blocking coupling capacitor C2 and one end of the third diode D3. The other end of the third diode D3 is connected to one end of the second resistor R2. The other end of the second resistor R2 is grounded. The other end of the second DC blocking coupling capacitor C2 is connected to the third switch SW3 via the output terminal RFOUT of the voltage-controlled attenuator.

[0024] In some embodiments, the first phase shifting module and the second phase shifting module are each a 1 / 4 wavelength transmission line.

[0025] In some embodiments, the first phase shift module and the second phase shift module have the same circuit structure, including an input terminal, a fourth resistor R4, a fourth capacitor C4, a second inductor L2, a fifth capacitor C5, a third inductor L3, a sixth capacitor C6, a fifth resistor R5, and an output terminal.

[0026] The input terminal is connected to one end of the fourth resistor R4, one end of the fourth capacitor C4, and one end of the second inductor L2, respectively. The other end of the fourth resistor R4 and the other end of the fourth capacitor C4 are grounded. The other end of the second inductor L2 is connected to one end of the third inductor L3 and one end of the fifth capacitor C5, respectively. The other end of the fifth capacitor C5 is grounded. The other end of the third inductor L3 is connected to one end of the sixth capacitor C6, one end of the fifth resistor R5, and the output terminal, respectively. The other end of the sixth capacitor C6 and the other end of the fifth resistor R5 are grounded.

[0027] In some embodiments, the output signal synthesis module is a passive resistor adder.

[0028] This invention also provides a full-band low-phase-noise small-step phase shifting method, comprising the following steps:

[0029] Step 1: Decompose the input signal Acosωt into Bcosωt and Bsinωt orthogonally using a 90° bridge;

[0030] Step 2: Use a 180° bridge to perform orthogonal decomposition on Bcosωt and Bsinωt to obtain Bcosωt, -Bcosωt, Bsinωt, and -Bsinωt respectively;

[0031] Step 3: Select the polarity of Bcosωt and send it to the first voltage-controlled attenuator; select the polarity of Bsinωt and send it to the second voltage-controlled attenuator.

[0032] Step 4: Use external control signals to control the first voltage-controlled attenuator and the second voltage-controlled attenuator respectively, so that the amplitude of the output signal is adjusted to Ccosφcosωt and Csinφsinωt respectively, where φ is the phase shift.

[0033] Step 5: Add Ccosφcosωt and Csinφsinωt together using an adder to obtain the phase-shifted signal Dcos(ωt-φ).

[0034] The present invention also provides a computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, it implements the full-band low phase noise small-step phase shifting method as described above.

[0035] The beneficial effects of the present invention are as follows: the phase shifting system of the present invention has a simple structure, can be used for phase shifting in all frequency bands from 0° to 360°, and the phase is continuously adjustable, with high precision and minimal impact on signal phase noise. Attached Figure Description

[0036] Figure 1 The principle of digital phase shifters in the background technology of this invention.

[0037] Figure 2 The principle of a simulated phase shifter in the background technology of this invention.

[0038] Figure 3 The structure diagram of the full-band low phase noise small step phase shift circuit in this embodiment of the invention.

[0039] Figure 4 The circuit diagram of the voltage-controlled attenuator in this embodiment of the invention.

[0040] Figure 5 The LC circuit in the embodiments of the present invention.

[0041] Figure 6 Simulation diagram of the LC90-degree phase shift circuit in the embodiment of the present invention.

[0042] Figure 7 The internal resistance characteristic curve of MA4P290 in the embodiment of the present invention.

[0043] Figure 8 The internal resistance characteristic curve of MA4P7455 in the embodiment of the present invention.

[0044] Figure 9 The equivalent circuit diagram of the LC circuit when the control voltage is 2mV or 10V in the embodiments of the present invention.

[0045] Figure 10 The simulation results of the equivalent circuit of the LC circuit when the control voltage is 2mV in the embodiment of the present invention.

[0046] Figure 11 The simulation results of the equivalent circuit of the LC circuit when the control voltage is 10V in the embodiment of the present invention.

[0047] Figure 12 The adder circuit diagram in the embodiment of the present invention.

[0048] Figure 13 Simulation results of the adder in the embodiments of the present invention. Detailed Implementation

[0049] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0050] Example

[0051] This example uses the 0° to 360° phase shift requirement of a 100MHz signal to specifically describe the present invention.

[0052] The specific structure of the full-band low-phase-noise, small-step phase-shifting system in this example is as follows: Figure 3 As shown, in the control signal input module, external control commands are input via the external serial port control signal input terminal and then sent by the serial port driver module to the FPGA to generate a first pulse width modulation signal PWM1, a second pulse width modulation signal PWM2, a first switch control signal, a second switch control signal, a third switch control signal, and a fourth switch control signal. The first pulse width modulation signal PWM1 passes through a first RC low-pass filter and a first operational amplifier in sequence, and is used to control a first voltage-controlled attenuator (voltage-controlled attenuator in the figure); the second pulse width modulation signal PWM2 passes through a second RC low-pass filter and a second operational amplifier in sequence, and is used to control the connection of a second voltage-controlled attenuator (voltage-controlled attenuator in the figure); the first switch control signal is used to control the first switch SW1; the second switch control signal is used to control the second switch SW2; the third switch control signal is used to control the third switch SW3; and the fourth switch control signal... The switch control signal is used to control the fourth switch SW4. A 100MHz input signal is input through the signal input port and connected to a 90° bridge. The 90° bridge is connected to both the first and second 180° bridges (shown in the diagram). The first 180° bridge is connected to the first voltage-controlled attenuator (VCO) via the first switch SW1. The first VCO is connected to the third switch SW3, which is connected to a resistor adder. The first and third switches SW1 and SW3, along with the first VCO, are connected to the control signal input module. The second 180° bridge is connected to the second VCO via the second switch SW2. The second VCO is connected to the fourth switch SW4, which is connected to the output signal synthesis module. The second and fourth switches SW2 and SW4, along with the second VCO, are connected to the resistor adder. The first and second switches SW1 and SW2 are single-pole double-throw switches; the third and fourth switches SW3 and SW4 are single-pole single-throw switches. A resistor adder adds quadrature signals with varying amplitudes to obtain a phase-shifted signal.

[0053] The 100MHz input signal Acosωt is orthogonally decomposed into Bcosωt and Bsinωt by a 90° bridge circuit. After passing through a 180° bridge circuit and a selector switch, it is fed into a voltage-controlled attenuator. The FPGA generates two PWM pulse signals, which are converted into voltage signals after passing through an RC low-pass filter. These signals are then driven by an operational amplifier to control the voltage-controlled attenuator, causing the amplitude of the output signal to become Ccosφcosωt and Csinφsinωt, where φ is the phase shift. The orthogonal signals with changed amplitudes are then added together using an adder to obtain the output signal Dcos(ωt-φ), which has a phase shift of φ relative to the input signal, and its amplitude changes from A to D.

[0054] For higher frequency signals, microstrip bridges can be used. In this example, the signal is 100MHz, so a balun design can be employed. Because the balun contains magnetic material, the input signal power should not be too high to prevent magnetic saturation and nonlinearity. In practical designs, the input signal power is ≤0dBm, and the insertion loss of the two-stage bridge is 6dB.

[0055] Specifically, the voltage-controlled attenuator includes an input terminal RFIN, a first DC blocking capacitor C1, a first diode D1, a first resistor R1, a first phase-shifting module, a second diode D2, a third resistor R3, a first choke coil L1, a third filter capacitor C3, a second phase-shifting module, a second DC blocking capacitor C2, a third diode D3, a second resistor R2, a control voltage input terminal, and an output terminal RFOUT. A first switch SW1 is connected to one end of the first DC blocking capacitor C1 via the input terminal RFIN. The other end of the first DC blocking capacitor C1 is connected to one end of the first diode D1 and the input terminal of the first phase-shifting module. The other end of the first diode D1 is connected to one end of the first resistor R1, and the other end of the first resistor R1 is grounded. The first phase-shifting module... The output terminal is connected to one end of the second diode D2, the input terminal of the second phase shift module, and one end of the third resistor R3, respectively. The other end of the second diode D2 is grounded. The other end of the third resistor R3 is connected to one end of the first choke coil L1. The other end of the first choke coil L1 is connected to the control voltage input terminal and one end of the third filter capacitor C3, respectively. The other end of the third filter capacitor C3 is grounded. The control voltage input terminal is connected to the control signal input module. The output terminal of the second phase shift module is connected to one end of the second DC blocking coupling capacitor C2 and one end of the third diode D3, respectively. The other end of the third diode D3 is connected to one end of the second resistor R2, and the other end of the second resistor R2 is grounded. The other end of the second DC blocking coupling capacitor C2 is connected to the third switch SW3 via the output terminal RFOUT of the voltage-controlled attenuator.

[0056] The control voltage, after being filtered by capacitor C3 and choke coil L1, is applied to the anode of PIN diode D2. The current in D2 increases with the increase of the control voltage VCTR, while its internal resistance decreases. A higher internal resistance in D2 results in a higher impedance to ground at point A, leading to lower signal insertion loss and thus less attenuation. Conversely, a lower internal resistance in D2 results in a lower impedance to ground at point A, leading to higher signal insertion loss and thus greater attenuation. In summary, a lower control voltage VCTR results in less attenuation, while a higher control voltage VCTR results in greater attenuation.

[0057] When the first phase-shifting module and the second phase-shifting module are each a 1 / 4 wavelength transmission line, the circuit is as follows: Figure 4 As shown, there are quarter-wavelength transmission lines before and after diode D2. The other ends of these transmission lines are connected to two PIN diodes, D1 and D2, respectively. These two PIN diodes are identical to D2, also controlled by the control voltage VCTR, except that the cathodes of D1 and D2 are each connected to ground with a 50Ω resistor. The quarter-wavelength transmission line has a 90° phase shift effect on the signal. Therefore, when the signal is reflected back to the input end of the transmission line, its phase has changed by 180°, exactly opposite to the input signal and thus canceled out. Therefore, the quarter-wavelength transmission line isolates D1, D2, and D3. The 50Ω resistors connected to D1 and D2, when the control voltage is at its maximum, can force the impedance of the input and output terminals to match to 50Ω, ensuring port matching.

[0058] In this example, the signal is 100MHz. Using a transmission line design would result in an excessively large size. Therefore, an LC circuit can be used to design the first and second phase-shifting modules, such as... Figure 5 As shown, the input terminal is connected to one end of the fourth resistor R4, one end of the fourth capacitor C4, and one end of the second inductor L2, respectively. The other ends of the fourth resistor R4 and the fourth capacitor C4 are grounded. The other end of the second inductor L2 is connected to one end of the third inductor L3 and one end of the fifth capacitor C5, respectively. The other end of the fifth capacitor C5 is grounded. The other end of the third inductor L3 is connected to one end of the sixth capacitor C6, one end of the fifth resistor R5, and the output terminal, respectively. The other ends of the sixth capacitor C6 and the fifth resistor R5 are grounded. The simulation results are as follows. Figure 6 As shown, the circuit is an LC low-pass circuit with a cutoff frequency of 150MHz. At 100MHz, the signal phase is offset by 90°.

[0059] Specifically, in this example, the PIN diodes used are MA4P290 and MA4P7455, with parallel capacitances of 0.3pF and 0.35pF respectively. The relationship between forward current and internal resistance is as follows: Figure 7 , 8As shown. The current-limiting resistor R3 is selected as 100Ω. When the current is 100mA and the control voltage is 10V, the corresponding resistance values ​​are 3Ω and 0.8Ω respectively. When the current is 0.02mA and the control voltage is 2mV, the corresponding resistance values ​​are 3000Ω and 200Ω respectively. The minimum phase shift is 1°, the attenuation coefficient sin1°≈0.01745, and the corresponding attenuation is 20lg(0.01745)≈-35.16dB. When the control voltage is 2mV, the equivalent circuit is as follows. Figure 9 As shown, the simulation results are as follows: Figure 10 As shown, when the control voltage is 10V, the equivalent circuit is as follows: Figure 9 As shown, the simulation results are as follows: Figure 11 As shown, the voltage-controlled attenuation range is between 1.5dB and 41dB, which meets the requirement of a minimum phase shift step of 1°.

[0060] Specifically, in the control signal input module, the values ​​of cosφ and sinφ range from [-1, +1]. The PWM pulses generated by the FPGA, after RC filtering, are positive voltages. Driven by the operational amplifier, they can only control the amplitude of the quadrature signal, varying it between 0 and 1 times, but not between -1 and 0 times. Therefore, the polarity of the quadrature signal needs to be adjusted according to the value of φ. The solution uses four switches, SW1 to SW4, for adjustment.

[0061] When 0°<φ<90°, cosφ>0, sinφ>0, SW1 selects pin 1 to conduct, SW2 selects pin 1 to conduct, SW3 and SW4 conduct, and the signals entering the attenuator are Bcosωt and Bsinωt respectively;

[0062] When 90°<φ<180°, cosφ<0, sinφ>0, SW1 selects pin 2 to conduct, SW2 selects pin 1 to conduct, SW3 and SW4 conduct, and the signals entering the attenuator are -Bcosωt and Bsinωt, respectively.

[0063] When 180°<φ<270°, cosφ<0, sinφ<0, SW1 selects pin 2 to conduct, SW2 selects pin 2 to conduct, SW3 and SW4 conduct, and the signals entering the attenuator are -Bcosωt and -Bsinωt, respectively.

[0064] When 180°<φ<360°, cosφ>0, sinφ<0, SW1 selects pin 1 to conduct, SW2 selects pin 2 to conduct, SW3 and SW4 conduct, and the signals entering the attenuator are Bcosωt and -Bsinωt, respectively.

[0065] By controlling the conduction states of SW1 and SW2, the output quadrature signals can be made Ccosφcosωt and Csinφsinωt respectively when φ∈(0°,90°)∪(90°,180°)∪(180°,270°)∪(270°,360°). Then, according to the trigonometric formula, the signal after the adder is Dcos(ωt-φ), and the signal is phase-shifted by φ.

[0066] When φ = 0°, cosφ = 1, sinφ = 0, SW1 selects pin 1 to conduct, SW2 conducts on any pin, SW3 conducts, SW4 is cut off, the output signal is Ccosωt, and the phase shift is 0°;

[0067] When φ = 90°, cosφ = 0, sinφ = 1, any pin of SW1 is turned on, pin 1 of SW2 is turned on, SW3 is turned off, SW4 is turned on, and the output signal is Csinωt = cos(ωt - 90°), with a phase shift of 90°.

[0068] When φ = 180°, cosφ = -1, sinφ = 1, SW1 selects pin 2 to conduct, SW2 selects any pin to conduct, SW3 conducts, SW4 is cut off, and the output signal is -Ccosωt = cos(ωt - 180°), with a phase shift of 180°.

[0069] When φ = 270°, cosφ = 1, sinφ = 0, any pin of SW1 is turned on, pin 2 of SW2 is turned on, SW3 is turned off, SW4 is turned on, and the output signal is -Csinωt = cos(ωt - 270°), with a phase shift of 270°.

[0070] The settings are the same when φ = 360° and when φ = 0°.

[0071] In summary, after being controlled by the PWM1 and PWM2 pulses generated by the FPGA and the control signals of SW1 to SW4, when φ∈[0°,360°], the input signal Acosωt will become Dcos(ωt-φ) after passing through the phase shift circuit, which is exactly a phase shift of φ.

[0072] Preferably, in this example, the adder uses a passive resistor network design, which will not cause phase degradation. Let the input voltages be V1 and V2, the input resistance be R11, the compensation resistor be R22, and the port impedance be 50Ω. Figure 12 As shown.

[0073] Looking at the input impedance from V1, Zin = R11 + [(R11 + 50) / / (R22 + 50)]. Looking at the output impedance from RF_OUT, Zout = (R11 + 50) / / (R11 + 50) + R22. Zin = Zout = 50Ω. Solving the system of equations, we get R11 = R22 = 16.66Ω. In actual design, a 33Ω parallel connection is selected. The simulation results are as follows... Figure 13 As shown, the insertion loss is 6dB.

[0074] The insertion loss is as follows:

[0075] The insertion loss of a single bridge circuit is 3dB, the insertion loss of a single switch is 1dB, and the insertion loss of an adder is 6dB, so the total insertion loss is 14dB. Taking into account line loss and the insertion loss of the attenuator, the insertion loss of the phase shifting circuit in the patent is about 16dB. For different frequencies, the output power has a normal fluctuation of about ±1dB.

[0076] The phase noise is as follows:

[0077] In the phase-shifting circuit, only the electrically adjustable attenuator is an active circuit on the channel. The linearity of the electrically adjustable attenuator directly affects the phase noise of the phase shifter. Because the PIN diode in the electrically adjustable attenuator operates in a forward-biased state, its junction capacitance is low and its response speed is fast, resulting in high linearity and negligible impact on phase noise.

[0078] This differs from the diodes in an electrically tunable phase shifter, where the diodes operate in reverse bias, their junction capacitance changes with voltage, resulting in low linearity and a significant impact on phase noise.

[0079] In summary, this invention adjusts the amplitude of quadrature signals by using an FPGA to generate PWM1 and PWM2 control voltages to control the attenuation of the attenuator. The amplitude of the cosine signal is adjusted to Bcosφ, and the amplitude of the sine signal is adjusted to Bsinφ. After passing through an adder, a phase shift effect of 0° to 90° is produced. After the input signal is orthogonally decomposed using a 90° bridge, it is further decomposed using a 180° bridge. The polarity of the quadrature signal is selected by switches SW1 and SW2, allowing the phase shift to extend from 0° to 90° to 90° to 180°, 180° to 270°, and 270° to 360°. SW3 and SW4 extend the four special phase shift points of 0°, 90°, 180°, and 270° into the phase shift circuit, ultimately achieving full-phase phase shift of [0°, 360°]. The attenuator topology using a PIN diode design ensures input-output port matching. In this patent, the control voltage can also be generated by an FPGA-controlled DAC, which can significantly improve the phase shift accuracy.

[0080] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0081] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It should be understood that flowchart illustrations and / or block diagrams of computer program products can be used to describe them. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0082] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0083] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0084] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0085] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0086] In a typical configuration, a computing device includes one or more processors (CPUs), input / output interfaces, network interfaces, and memory. Memory may include non-persistent memory in computer-readable media, random access memory (RAM), and / or non-volatile memory such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media. Computer-readable media includes both permanent and non-persistent, removable and non-removable media that can store information by any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transfer medium that can be used to store information that can be accessed by the computing device. As defined in this article, computer-readable media do not include transient media, such as modulated data signals and carrier waves.

[0087] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0088] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A full-band low-phase-noise, small-step phase-shifting system, characterized in that, It includes a control signal input module, a signal input port, an orthogonal decomposition and attenuation module, an output signal synthesis module, and a signal output port; the signal input port is connected to the orthogonal decomposition and attenuation module, the orthogonal decomposition and attenuation module is connected to the control signal input module and the output signal synthesis module respectively, and the output signal synthesis module is connected to the signal output port. The orthogonal decomposition and attenuation module is used to orthogonally decompose the input signal transmitted through the signal input port, and adjust the amplitude of the decomposed orthogonal signals respectively. The control signal input module is used to provide external control signals to the orthogonal decomposition and attenuation module; The output signal synthesis module is used to synthesize the amplitude-adjusted quadrature signals to obtain a phase-shifted signal, which is then output through the signal output port.

2. The full-band low-phase-noise small-step phase-shifting system according to claim 1, characterized in that, The orthogonal decomposition and attenuation module includes a 90° bridge, a first 180° bridge, a second 180° bridge, a first switch SW1, a second switch SW2, a first voltage-controlled attenuator, a second voltage-controlled attenuator, a third switch SW3, and a fourth switch SW4. The signal input port is connected to a 90° bridge, which is connected to a first 180° bridge and a second 180° bridge. The first 180° bridge is connected to a first voltage-controlled attenuator via a first switch SW1. The first voltage-controlled attenuator is connected to a third switch SW3, which is connected to the output signal synthesis module. The first switch SW1, the third switch SW3, and the first voltage-controlled attenuator are each connected to the control signal input module. The second 180° bridge is connected to the second voltage-controlled attenuator via the second switch SW2. The second voltage-controlled attenuator is connected to the fourth switch SW4. The fourth switch SW4 is connected to the output signal synthesis module. The second switch SW2, the fourth switch SW4, and the second voltage-controlled attenuator are respectively connected to the control signal input module. The first switch SW1 and the second switch SW2 are single-pole double-throw switches; the third switch SW3 and the fourth switch SW4 are single-pole single-throw switches.

3. The full-band low-phase-noise small-step phase-shifting system according to claim 2, characterized in that, The control signal input module includes an external serial port control signal input terminal, a serial port driver module, an FPGA module, a first RC low-pass filter, a first operational amplifier, a second RC low-pass filter, and a second operational amplifier; After the external control command is input via the external serial port control signal input terminal, it is sent to the FPGA by the serial port driver module to generate the first pulse width modulation signal, the second pulse width modulation signal, the first switch control signal, the second switch control signal, the third switch control signal, and the fourth switch control signal; The first pulse width modulation signal passes sequentially through a first RC low-pass filter and a first operational amplifier, and is used to control the first voltage-controlled attenuator. The second pulse width modulation signal passes sequentially through the second RC low-pass filter and the second operational amplifier, and is used to control the connection of the second voltage-controlled attenuator; The first switch control signal is used to control the first switch SW1; The second switch control signal is used to control the second switch SW2; The third switch control signal is used to control the third switch SW3; The fourth switch control signal is used to control the fourth switch SW4.

4. The full-band low-phase-noise small-step phase-shifting system according to claim 3, characterized in that, The 90° bridge, the first 180° bridge, and the second 180° bridge are microstrip bridges or balun bridges.

5. The full-band low-phase-noise small-step phase-shifting system according to claim 4, characterized in that, The first voltage-controlled attenuator and the second voltage-controlled attenuator have the same circuit structure, including the voltage-controlled attenuator input terminal RFIN, the first DC blocking coupling capacitor C1, the first diode D1, the first resistor R1, the first phase shifting module, the second diode D2, the third resistor R3, the first choke coil L1, the third filter capacitor C3, the second phase shifting module, the second DC blocking coupling capacitor C2, the third diode D3, the second resistor R2, the control voltage input terminal, and the voltage-controlled attenuator output terminal RFOUT; The first switch SW1 is connected to one end of the first DC blocking coupling capacitor C1 via the input terminal RFIN of the voltage-controlled attenuator. The other end of the first DC blocking coupling capacitor C1 is connected to one end of the first diode D1 and the input terminal of the first phase shifting module. The other end of the first diode D1 is connected to one end of the first resistor R1, and the other end of the first resistor R1 is grounded. The output terminal of the first phase shifting module is connected to one end of the second diode D2, the input terminal of the second phase shifting module, and one end of the third resistor R3. The other end of the second diode D2 is grounded, and the other end of the third resistor R3 is connected to the first choke coil L. One end of the first choke coil L1 is connected to the control voltage input terminal and the other end of the third filter capacitor C3. The other end of the third filter capacitor C3 is grounded. The control voltage input terminal is connected to the control signal input module. The output terminal of the second phase shift module is connected to one end of the second DC blocking coupling capacitor C2 and one end of the third diode D3. The other end of the third diode D3 is connected to one end of the second resistor R2. The other end of the second resistor R2 is grounded. The other end of the second DC blocking coupling capacitor C2 is connected to the third switch SW3 via the output terminal RFOUT of the voltage-controlled attenuator.

6. The full-band low-phase-noise small-step phase-shifting system according to claim 5, characterized in that, The first phase shifting module and the second phase shifting module are both 1 / 4 wavelength transmission lines.

7. The full-band low-phase-noise small-step phase-shifting system according to claim 5, characterized in that, The first phase shift module and the second phase shift module have the same circuit structure, including an input terminal, a fourth resistor R4, a fourth capacitor C4, a second inductor L2, a fifth capacitor C5, a third inductor L3, a sixth capacitor C6, a fifth resistor R5, and an output terminal; The input terminal is connected to one end of the fourth resistor R4, one end of the fourth capacitor C4, and one end of the second inductor L2, respectively. The other end of the fourth resistor R4 and the other end of the fourth capacitor C4 are grounded. The other end of the second inductor L2 is connected to one end of the third inductor L3 and one end of the fifth capacitor C5, respectively. The other end of the fifth capacitor C5 is grounded. The other end of the third inductor L3 is connected to one end of the sixth capacitor C6, one end of the fifth resistor R5, and the output terminal, respectively. The other end of the sixth capacitor C6 and the other end of the fifth resistor R5 are grounded.

8. The full-band low-phase-noise small-step phase-shifting system according to claim 6 or 7, characterized in that, The output signal synthesis module is a passive resistor adder.

9. A full-band low-phase-noise, small-step phase-shifting method, characterized in that, Includes the following steps: Step 1: Decompose the input signal Acosωt into Bcosωt and Bsinωt orthogonally using a 90° bridge; Step 2: Use a 180° bridge to perform orthogonal decomposition on Bcosωt and Bsinωt to obtain Bcosωt, -Bcosωt, Bsinωt, and -Bsinωt respectively; Step 3: Select the polarity of Bcosωt and send it to the first voltage-controlled attenuator; select the polarity of Bsinωt and send it to the second voltage-controlled attenuator. Step 4: Use external control signals to control the first voltage-controlled attenuator and the second voltage-controlled attenuator respectively, so that the amplitude of the output signal is adjusted to Ccosφcosωt and Csinφsinωt respectively, where φ is the phase shift. Step 5: Add Ccosφcosωt and Csinφsinωt together using an adder to obtain the phase-shifted signal Dcos(ωt-φ).

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the full-band low phase noise small-step phase shifting method as described in claim 9.

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