Data processing method and device, equipment, storage medium and program product

Abstract

The invention provides a data processing method and device, equipment, a storage medium and a program product, and relates to the technical field of communication. According to the method, the data read-write address is generated by adopting the preset read-write address generation rule, so that the write-in and read-out sequence of the data is effectively arranged, the data of each time slot can be read according to the continuous arrangement of the data of each beam, and the effective recombination processing of the multi-beam uplink data in the single cache module is realized. Therefore, the data processing efficiency is improved, the waste of cache resources in a traditional double-cache scheme is avoided, and the consumption of hardware resources is remarkably reduced, for example, the use number of BRAMs is reduced, so that the hardware cost and power consumption of the base station are reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of communication, in particular to a data processing method and device, equipment, storage medium and program product. BACKGROUND

[0002] In modern wireless communication systems such as satellite communication and 5G mobile communication, multi-beam technology can significantly improve system capacity and spectrum utilization by forming multiple independent directional beams. In the physical layer (PHY) processing of these systems, the Low PHY (bottom layer physical layer) undertakes the signal preprocessing function close to the radio frequency side, and its performance and efficiency are directly related to the performance of the entire system.

[0003] In a typical satellite payload or base station system, the signals received by the uplink usually contain data of multiple beams. These data are sampled in a beam-interleaved manner in the time domain, that is, the sampling sequence is each sampling point of beam 0, beam 1, …, and beam M-1 in turn, and then this mode is repeated cyclically. However, the subsequent Low PHY core processing modules (such as Fast Fourier Transform (FFT), beamforming, etc.) usually require the input data to be arranged continuously by beam, that is, all sampling points of a beam are processed first, and then the next beam is processed. Therefore, before the Low PHY core processing, a preprocessing procedure of “data sequence transformation” or “data reorganization” must be performed to convert the interleaved format data into continuous format.

[0004] The prior art generally adopts a data reorganization scheme based on double buffering. The core architecture of this scheme includes two buffer areas of the same capacity (for example, implemented by Bipolar Random Access Memory (BRAM) in FPGA (Field Programmable Gate Array)). The working process is as follows: while the first buffer area (buffer A) is writing interleaved data of the current time slot, the second buffer area (buffer B) is used to read the continuous data of the previous time slot that has been reorganized; when the time slot switches, the roles of the two buffer areas are interchanged, that is, buffer B is used to write new data and buffer A is used to read old data, and this alternation is performed.

[0005] Taking a four-beam system as an example, each beam contains 28672 sampling points per time slot, and the bit width of a single sampling point is 32 bits. The storage capacity required for a single buffer area is 4 × 28672 × 32 bits. It is calculated that about 101.5 BRAM resources are required to implement this single buffer in FPGA. Since the double-buffering scheme requires two such buffer areas to work alternately, a total of about 203 BRAMs are required.

[0006] Therefore, the storage resource (BRAM) required by the existing scheme is doubled compared with the single cache scheme. This will sharply consume the valuable storage resource of the FPGA in a system with a large number of channels and a high sampling rate, and become a major bottleneck for system integration and cost control. SUMMARY

[0007] Embodiments of the present application aim to provide a data processing method, device, equipment, storage medium and program product, to improve the problem that a large amount of storage resource is consumed in the existing scheme for implementing data reorganization by using a double cache scheme.

[0008] In a first aspect, embodiments of the present application provide a data processing method applied to a base station, comprising: obtaining i-th current uplink data sampled in j-th time slot wherein m represents the serial number of the m-th beam, n represents the serial number of the n-th sampling data of the m-th beam, and the uplink data of each time slot is sampled in a beam interleaving manner; obtaining a current data write address and a current data read address generated according to a preset read-write address generation rule, wherein the preset read-write address generation rule comprises: the data write address of the j-th time slot is the same as the data read address of the j-1-th time slot, and the data read out according to the data read address of each time slot is arranged continuously according to the data of each beam; writing the i-th current uplink data into a cache module according to the current data write address, and reading data from the cache module according to the current data read address.

[0009] In the above implementation process, the data read-write address is generated by using the preset read-write address generation rule, which effectively arranges the writing and reading order of the data, so that the data of each time slot can be read in a continuous arrangement of the data of each beam, and the effective reorganization processing of the multi-beam uplink data in the single cache module is realized. This not only improves the efficiency of data processing and avoids the waste of cache resources in the traditional double cache scheme, but also significantly reduces the consumption of hardware resources, such as reducing the number of BRAM used, thereby reducing the hardware cost and power consumption of the base station.

[0010] Optionally, the preset read-write address generation rule comprises a write address generation rule and a read address generation rule; the write address generation rule is to generate a data write address based on a previous data write address and an address step corresponding to the j-1-th time slot; the read address generation rule is to generate a data read address based on a previous data read address and an address step corresponding to the j-th time slot; The address step corresponding to the jth time slot is the value of the (M+1)th data write address of the (j-1)th time slot, M represents the number of beams, and the starting addresses of the data write address and the data read address of each time slot are both 0.

[0011] In the implementation process, the write address generation rule and the read address generation rule can ensure correct writing and reading of data, optimize the data processing flow by dynamically adjusting the address step, avoid read-write conflicts, simplify the control logic, and improve system stability and reliability.

[0012] Optionally, the write address generation rule is represented by the following expression: wherein, , The address step corresponding to the (j-1)th time slot is represented by Q, Q represents the total number of sampling points of the M beams in the jth time slot, and mod represents the modulo operation. The read address generation rule is represented by the following expression: wherein, , The address step corresponding to the jth time slot is represented by Q, Q represents the total number of sampling points of the M beams in the jth time slot, and mod represents the modulo operation. wherein, .

[0013] In the implementation process, the write address generation rule is based on the previous write address and the address step of the previous time slot, and the modulo operation is used to ensure that the address is within the cache range and to avoid address overflow. The read address generation rule is generated based on the previous read address and the address step of the current time slot, and the modulo operation is also used to ensure the validity of the address. This design not only reduces the demand for cache resources, reduces hardware cost and power consumption, but also realizes complex address management through simple mathematical operations, simplifying the control logic.

[0014] Optionally, the method further comprises: After writing all the uplink data of the first time slot to the cache module, a read enable signal is generated, which is used to control reading the data of the first time slot.

[0015] In the implementation process, the read enable signal is generated after all the uplink data of the first time slot is written to the cache module, realizing accurate control of the data reading process. This mechanism ensures the integrity and accuracy of the data, avoiding the situation where data is read before it is completely written to the cache, thereby preventing data loss or errors.

[0016] Optionally, the method further comprises: After the uplink data of the first time slot is completely written into the cache module and the first uplink data sampled in the second time slot is obtained, a read enable signal is generated, which is used to control reading the data of the first time slot.

[0017] In the above implementation process, by generating the read enable signal after the uplink data of the first time slot is completely written into the cache module and the first uplink data sampled in the second time slot is obtained, accurate timing control of the data reading process is realized. This mechanism not only ensures that the data of the first time slot is read only after being written, avoiding data conflicts and errors, but also optimizes the pipeline operation of data processing by synchronizing with the sampling of the second time slot data. This method effectively improves the efficiency of the system and reduces the processing delay.

[0018] Optionally, the method further comprises: In the process of writing the uplink data of the first time slot into the cache module, a read enable signal is generated at a specified time of the first time slot, which is used to control reading the data of the first time slot.

[0019] In the above implementation process, by generating the read enable signal at the specified time in the process of writing the uplink data of the first time slot into the cache module, accurate timing control of the data reading is realized. This mechanism allows the reading operation to start during the data writing process, thereby optimizing the pipeline efficiency of data processing and reducing the processing delay. At the same time, by generating the read enable signal at the specified time, the accuracy and stability of the reading operation are ensured, avoiding data conflicts and errors.

[0020] Optionally, the specified time is later than or equal to the time of 3 / 4 of the time slot length of the first time slot. In this way, it can be ensured that most of the data has been written into the cache module before reading the data of the first time slot. This design avoids the problem of data coverage caused by the reading operation starting too early, while fully utilizing the storage capacity of the cache module and improving the efficiency of data processing.

[0021] Optionally, the capacity of the cache module is determined based on the total number of sampling points of M beams sampled in one time slot. This design ensures that the cache module can exactly accommodate all data of one time slot, avoiding unnecessary resource waste, while reducing hardware cost and power consumption.

[0022] In a second aspect, the embodiments of the present application provide a data processing device applied to a base station, comprising: The control module is configured to obtain the i-th current uplink data sampled in the j-th time slot wherein m represents the serial number of the mth beam, n represents the serial number of the n th sampling data of the mth beam, and the uplink data of each time slot is sampled in a beam interleaving manner; The read-write address generation module is configured to generate a current data write address and a current data read address according to a preset read-write address generation rule, wherein the preset read-write address generation rule comprises: the data write address of the jth time slot is the same as the data read address of the (j-1)th time slot, and the data read out according to the data read address of each time slot is arranged continuously according to each beam. The control module is further configured to write the ith current uplink data into the cache module according to the current data write address, and read data from the cache module according to the current data read address. The control module is further configured to write the ith current uplink data into the cache module according to the current data write address, and read data from the cache module according to the current data read address.

[0023] Optionally, the read-write address generation module comprises: The read address register is configured to store the data read address. The write address register is configured to store the data write address. The write address adder is configured to perform addition operation on the previous data write address and the address step corresponding to the previous time slot to obtain a first sum value, and input the first sum value into the write address operator. The write address operator is configured to perform modulo operation on the first sum value and a value obtained by subtracting 1 from the total sampling point number of the M beams in the current time slot to obtain the current data write address. The read address adder is configured to perform addition operation on the previous data read address and the address step corresponding to the current time slot to obtain a second sum value, and input the second sum value into the read address operator. The read address operator is configured to perform modulo operation on the second sum value and a value obtained by subtracting 1 from the total sampling point number of the M beams in the current time slot to obtain the current data read address.

[0024] In the above implementation process, the process of read-write address generation involves addition and subtraction operation, and the control logic mainly detects the completion of time slot data collection and latches the address step, so the complexity is low and the implementation is convenient.

[0025] In a third aspect, an embodiment of the present application provides a data processing device, which comprises a cache module and the data processing apparatus provided in the second aspect.

[0026] In a fourth aspect, an embodiment of the present application provides a computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to run the steps in the method provided in the first aspect.

[0027] In a fifth aspect, an embodiment of the present application provides a computer program product, comprising computer program instructions, which, when read and executed by a processor, perform the steps in the method according to the first aspect.

[0028] Other features and advantages of the present application will be set forth in the following description, and in part will become apparent to those skilled in the art upon examination of the following or can be learned by practice of the application. The objects and other advantages of the application can be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings. BRIEF DESCRIPTION OF DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments of the present application. It should be understood that the following drawings only show some of the embodiments of the present application, and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0030] Figure 1 A flow chart of a data processing method provided by an embodiment of the present application; Figure 2 An architecture schematic diagram of a single cache module provided by an embodiment of the present application; Figure 3 A read-write timing schematic diagram provided by an embodiment of the present application; Figure 4 A structure block diagram of a data processing device provided by an embodiment of the present application; Figure 5 A detailed architecture schematic diagram of an address generation module provided by an embodiment of the present application; Figure 6 A structure schematic diagram of a data processing device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0031] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application.

[0032] It should be noted that the terms "system" and "network" in the embodiments of the present application can be used interchangeably. "Multiple" means two or more, and therefore, "multiple" in the embodiments of the present application can also be understood as "at least two". "And / or" describes the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B can represent the following three cases: A exists alone, A and B exist together, and B exists alone. In addition, the character " / ", if not specially stated, generally represents an "or" relationship between the associated objects before and after it.

[0033] It should be further noted that all the actions of obtaining signals, information or data in the present application are carried out in accordance with the corresponding data protection regulations and policies of the country where the device is located, and with the authorization given by the owner of the corresponding device.

[0034] The satellite payload system mentioned in the present solution is arranged in a satellite, and the satellite payload system is a functional unit directly performing a communication task on the satellite, which refers to a collection of all devices and subsystems on the satellite for receiving, processing, converting and retransmitting electromagnetic wave signals.

[0035] The satellite can also be a satellite base station or a network side device carried on the satellite.

[0036] The satellite base station can be used to support terminal access, for example, it can be a base transceiver station (BTS) and a base station controller (BSC) in a 2G access technology communication system, a node B (Node B) and a radio network controller (RNC) in a 3G access technology communication system, an evolved node B (eNB) in a 4G access technology communication system, a next generation node B (gNB) in a 5G access technology communication system, a transmission reception point (TRP), a relay node, an access point (AP) and the like ground equipment, and can also be a non-ground equipment: a high-altitude base station, for example, a hot air balloon and the like equipment, a low-orbit satellite, a medium-orbit satellite, a high-orbit satellite and the like, which can provide wireless access function for terminals. For convenience of description, all the devices providing wireless communication function for terminals in the embodiments of the present application are collectively referred to as base stations.

[0037] The data processing method of the present solution can be applied to a LowPHY preprocessing module in a base station. The uplink sampling data needs to be processed by the LowPHY preprocessing module first, and then the data sequence between different beams is transformed, and then the data can enter the LowPHY module and subsequent modules for processing.

[0038] Please refer to Figure 1 , Figure 1 A flowchart of a data processing method provided by the embodiments of the present application is shown in the figure, and the method comprises the following steps: Step S110: obtaining the i-th current uplink data S obtained by sampling the j-th time slot m,n .

[0039] The time slot refers to a fixed time unit in a communication system, and in the present scheme, one complete data acquisition is completed in each time slot, that is, data acquisition of all beams. For example, in a satellite communication scenario, the subcarrier spacing is 30KHz, the bandwidth is 40M, and the data amount of one beam in one time slot is 28672. Therefore, the input of the sampling data of one time slot of four beams is S m,n The sampling time sequence is as follows: ; Wherein, m represents the serial number of the mth beam, and n represents the serial number of the nth sampling data of the mth beam.

[0040] In the present scheme, the uplink data of each time slot is sampled in a beam interleaving manner. It can be understood that, instead of sequentially collecting all data of one beam and then collecting the next one, the data is collected in a beam unit in a cycle, such as collecting data in an alternating manner according to the beam serial number, such as the first data of beam 0, the first data of beam 1, the first data of beam 2, the first data of beam 3, the second data of beam 0, and so on. In practical applications, each beam is independently sampled at a sampling clock of 61.44M, and then the data of beams 1 to 4 is sequentially transmitted to the LowPHY preprocessing module at a sampling rate of 4 times (245.76M) (such as collecting one data point of four beams at the same time, and a total of four data points are obtained). The manner of sequentially transmitting the data points of four beams can be understood as sampling the uplink data in a beam interleaving manner.

[0041] j represents the time slot serial number, which is counted from 1, and i represents the sampling point serial number in the current time slot. After receiving the digital sampling signal from the radio frequency front end, the satellite payload system samples according to the beam interleaving sequence. For example, each time slot can contain 28672 sampling points / beam*4 beams=114688 total sampling points.

[0042] For example, assuming that the current time slot is the second time slot (j=2), and the tenth uplink data (i=10) is collected, according to the interleaving rule: i=10, m=10 mod 4=2 (corresponding to beam 2), n=floor (10 / 4)=2, which means that the second uplink data of the second beam is sampled.

[0043] After sampling the uplink data, the radio frequency front end can input the sampled uplink data to the LowPHY preprocessing module for processing to realize reorganization of the data in a beam sequence.

[0044] Step S120: obtaining a current data write address and a current data read address generated according to a preset read-write address generation rule.

[0045] The principle of the pre-processing by the LowPHY pre-processing module is to continuously output the data of the beams in sequence according to the beam-interleaved sampling, that is, to output all the data of a beam in sequence and then output the data of the next beam. For example, the output data sequence of the LowPHY pre-processing module is as follows: .

[0046] In order to save the cache resources, a cache module is used in the present scheme to pre-process the uplink data, to realize the continuous output of the uplink data in the beam sequence, and the overall implementation block diagram can be shown as in FIG. 1. Figure 2 The cache module is used to store the uplink sampling data, and the type thereof is, for example, RAM or BRAM. On the cache resource, the cache of the data of one time slot of four beams is 114688*32 bits, which occupies 101.5 BRAMs, and can save 50% of the storage resources compared with the double cache scheme.

[0047] The preset read-write address generation rule includes that the data write address of the jth time slot is the same as the data read address of the (j-1)th time slot, and the data read out according to the data read address of each time slot is arranged in sequence according to the data of each beam.

[0048] The above-described preset read-write address generation rule can ensure that, when using one cache module to process the data, the old data written will not be covered by the new data, and the written data can be read out in time and in the beam sequence.

[0049] For example, the data write address of the 2nd time slot is the data read address of the 1st time slot, that is, when processing the uplink data of the 2nd time slot, the data corresponding to the data write address has been read out, so that the data will not be covered when writing the data, and the data read address is read according to the sequence of the output data sequence of the above-described LowPHY pre-processing module.

[0050] For example, the data write address of the 1st time slot is 0, 1, 2, 3,..., 114687, and since the data of one beam needs to be read out continuously, the data read address of the 1st time slot is 0, 4, 8, 12,..., 114687. In this way, in the 2nd time slot, the data write address of the 2nd time slot is 0, 4, 8, 12,..., 114687, and at this time, when writing the data of the 2nd time slot, the data corresponding to the address has been read out, so that the correct writing of the data can be ensured.

[0051] In some embodiments, the uplink data of the first time slot can be written into the cache module according to the data write address described above, and after the data of the first time slot is collected, the read enable signal can be generated, that is, the data is read from the cache module according to the data read address of the first time slot, for example, the data at address 0 is read first, and at the same time, the first data of the second time slot is received, and then written into address 0, and then the data at address 4 is read, and the second data of the second time slot is written into address 4. In this way, the data is read before being written, so that data overwrite does not occur, and the data read first is the continuous data corresponding to beam 0 (addresses 0, 4, 8, 12,..., 114687 are the data corresponding to beam 0).

[0052] It can be understood that after the i-th current uplink data S is obtained, the current data write address and the current data read address can be generated in real time, and the corresponding addresses are generated according to the preset read-write address generation rule.

[0053] In some other embodiments, the data write address and the data read address of one or two time slots (a small number of time slots) can also be stored in advance, so that after an uplink data is obtained, the data write address and the data read address corresponding to the index can be obtained according to the serial number of m and n, so that real-time address calculation is not required.

[0054] Step S130: write the i-th current uplink data S m,n into the cache module according to the current data write address, and read data from the cache module according to the current data read address.

[0055] According to the obtained current data write address, the i-th current uplink data S m,n obtained at present can be written into the cache module at this address, and after the writing of data is completed, the address generation module is updated to the next write address.

[0056] According to the obtained current data read address, data is read from the corresponding position in the cache module, and the read data is directly output to the subsequent processing module, and after the reading is completed, the address generation module is updated to the next read address.

[0057] In the above implementation process, the data read-write address is generated by using the preset read-write address generation rule, the writing and reading order of the data is effectively arranged, so that the data of each time slot can be read in a continuous arrangement according to the data of each beam, and the effective reorganization processing of the multi-beam uplink data in the single cache module is realized. This not only improves the efficiency of data processing, avoids the waste of cache resources in the traditional double cache scheme, but also significantly reduces the consumption of hardware resources, such as reducing the number of BRAMs used, thereby reducing the hardware cost and power consumption of the base station.

[0058] On the basis of the above embodiment, the preset read-write address generation rule includes a write address generation rule and a read address generation rule. The write address generation rule is that a data write address is generated based on a previous data write address and an address step corresponding to a j-1th time slot. The read address generation rule is that a data read address is generated based on a previous data read address and an address step corresponding to a jth time slot, where the address step corresponding to the jth time slot is a value of an M+1th data write address of the j-1th time slot, M represents a beam quantity, and a starting address of each time slot is 0.

[0059] Here, the address step can be understood as an increment of each new address relative to a previous address when generating a read-write address sequence.

[0060] When generating a data write address, the data write address is generated based on a previous data write address and an address step of a previous time slot. When generating a data read address, the data read address is generated based on a previous data read address and an address step of a current time slot. The address step is related to a beam quantity.

[0061] For example, in a scenario where the beam quantity M=4, when j=1, a data write address of a 1st time slot is generated with an address step 1, such as 0, 1, 2, 3, 4,..., 114687. A data read address of the 1st time slot is generated with an address step 4, such as 0, 4, 8, 12,...

[0062] When j=2, a data write address of a 2nd time slot is generated with a step 4, such as 0, 4, 8, 12,... A data read address of the 2nd time slot is generated with an address step 16, such as 0, 16, 32, 48,...

[0063] When j=3, a data write address of a 3rd time slot is generated with an address step 16, such as 0, 16, 32, 48,... A data read address of the 3rd time slot is generated with an address step 64, such as 0, 64, 128, 192,...

[0064] That is, the 1st time slot: The write address step is 1, and the read address step is 4; The data write address is 0, 1, 2, 3,... The data read address is 0, 4, 8, 12,... The 2nd time slot: The write address step is 4, and the read address step is 16; Data write address: 0, 4, 8, 12,...; Data read address: 0, 16, 32, 48,...; The 3rd time slot: The write address step is 16, and the read address step is 64; Data write address: 0, 16, 32, 48,...; Data read address: 0, 64, 128, 192,....

[0065] As can be seen, except for the 1st time slot, for the data write address of a time slot, it is equal to the data read address of the previous time slot, so that when the data is written, the data at the corresponding address is read out, so the data can be successfully written, and according to the above address step setting, the data read out each time is continuous data of the same beam. For example, when reading the data of the 1st time slot, the data read address is 0, 4, 8, 12,..., which exactly traverses all the addresses where the data of beam 0 is located, thereby continuously outputting all the sample data of beam 0, and after reading the data of beam 0, the data of beams 1, 2 and 3 will be read out with the same step, realizing the transformation from interleaving to continuity.

[0066] In the 2nd time slot, continuous sample points of the same beam are written into positions with a physical address interval of 4, for example, sample points S 0,0 , 0,1 , 0,2 ... of beam 0 are written into addresses 0, 4, 8,..., which are exactly the addresses of the last data read out, so that when the data is written in the next time slot, it can be written into the addresses of the empty data.

[0067] In this way, the data of all time slots of beam 0 can be read first, and then according to the same rule, after a certain number of times, the read and write addresses and the address step will return to the starting state of the 1st time, that is, the data of all time slots of other beams will be read.

[0068] In the above implementation process, the write address generation rule and the read address generation rule can ensure correct writing and reading of data, and through dynamic adjustment of the address step, the data processing flow is optimized, read-write conflicts are avoided, the control logic is simplified, and the system stability and reliability are improved.

[0069] On the basis of the above embodiment, the write address generation rule can be represented by the following expression: wherein, , indicates the address step corresponding to the j-1th time slot, Q indicates the total number of sample points of the M beams in the jth time slot, and mod indicates the modulo operation.

[0070] The read address generation rule can be characterized by the following expression: wherein, , represents the address step corresponding to the jth time slot, Q represents the total number of sampling points of the M beams in the jth time slot, and mod represents the modulo operation.

[0071] wherein, .

[0072] Referring to the above example, if the number of beams is 4, the total number of sampling points of the 4 beams in each time slot is 114688, so Q can be 114688.

[0073] In generating the data write address, each new data write address is based on the previous write address plus an address step value, forming an arithmetic sequence, and then performing a modulo operation with Q-1, mainly to ensure that the address circulates within the cache space to avoid overflow.

[0074] The system can latch the previous data write address, then read out the previous data write address and add an address step value, and then perform a modulo operation with Q-1, to obtain the current data write address, which can be latched again for the next data write address operation.

[0075] In generating the data read address, each new data read address is based on the previous read address plus an address step value, and then performing a modulo operation with Q-1.

[0076] The system can also latch the previous data read address, then read out the previous data read address and add an address step value, and then perform a modulo operation with Q-1, to obtain the current data read address, which can be latched again for the next data read address operation.

[0077] In the read address generation mode, through the designed address step value, continuous data can be extracted from the out-of-order stored sampling data, and when the read step and the write step satisfy a certain relationship, the read operation can reorganize the data in the order of continuous beams.

[0078] The read and write addresses generated by the above rule can ensure that the read and write operations are interleaved in different time slots, and in the same time slot, the read and write operations access different regions of the cache module, and the read and write do not access the same position, avoiding conflicts.

[0079] In order to avoid data read-write conflict, the generation rule of the address step can be: , , which realizes the dynamic change of the address step.

[0080] In the implementation process, the write address generation rule is based on the last write address and the address step of the previous time slot, and the address is ensured to be within the cache range by using the modulo operation to avoid address overflow. The read address generation rule is generated based on the last read address and the address step of the current time slot, and the effectiveness of the address is also ensured by using the modulo operation. This design not only reduces the demand for cache resources, reduces hardware cost and power consumption, but also simplifies the control logic through simple mathematical operations to achieve complex address management.

[0081] Optionally, in this application, with the increase of the time slot number, the data write address sequence, the data read address sequence and the address step value show periodic changes. Specifically, after a certain number of time slots, these sequences and values will return to the initial state of the time slot, and a new cycle will begin.

[0082] Based on the above embodiment, in order to avoid read-write conflict, the present scheme can also limit the read-write timing in several implementation ways, and the specific read-write timing diagram can be as shown in Figure 3 .

[0083] Method 1: After writing all the uplink data of the first time slot to the cache module, a read enable signal is generated, which is used to control reading the data of the first time slot.

[0084] In writing data, the control module in the LowPHY preprocessing module can generate a write enable signal and a read enable signal, and the address generation module is used to generate data read-write addresses according to the above rules. The address generation module inputs the current data write address to the write port of the cache module, and the control module generates a write enable signal and inputs it to the write enable port of the cache module at the same time. The control module synchronously transmits the current uplink data to the cache module, and the cache module stores the received current uplink data in the storage unit corresponding to the data write address after receiving the write enable signal.

[0085] The write enable signal can be high active and can last for a complete time slot. After all the data of the first time slot is written to the cache module, the control module can generate a write completion flag, which can be generated when the last sampling point in the first time slot is written to the cache module. The control module can generate a read enable signal after detecting the presence of the write completion flag. The read enable signal can also be high active and can last for a complete reading time of a time slot.

[0086] The address generation module can synchronously generate the current data read address and input it to the cache module after detecting the write completion flag. The current data read address at this time is used to read the first data of the first time slot. The cache module receives the read enable signal, reads the data from the corresponding address according to the current data read address, and outputs it to the subsequent processing module.

[0087] The subsequent write enable signal and read enable signal can be valid all the time, so that after collecting data of one time slot, data reading and writing can be performed synchronously and no conflict occurs.

[0088] In the above implementation process, the read enable signal is generated after the uplink data of the first time slot is completely written into the cache module, so that the data reading process is accurately controlled. This mechanism ensures the integrity and accuracy of the data, avoids the situation that the data is read before it is completely written into the cache, and thus prevents data loss or errors.

[0089] In mode 2, the read enable signal is generated after the uplink data of the first time slot is completely written into the cache module and the first uplink data sampled in the second time slot is obtained, and the read enable signal is used to control reading of the data of the first time slot.

[0090] The implementation mode is similar to the implementation process of mode 1 described above, except that in mode 2, the control module can generate a write completion flag when the first uplink data of the second time slot is written, the current data read address can be generated by the read address generation module after the write completion flag is detected, and the control module synchronously generates the read enable signal.

[0091] In some embodiments, in modes 1 and 2, the amount of data written can be detected by a sampling counter, for example, in mode 1, when the sampling counter reaches the maximum value (114687), it indicates that the data of the first time slot has been completely written into the cache module, the control module and the address generation module can monitor the value of the sampling counter in real time, at this time the control module can synchronously generate the read enable signal, and the address generation module generates the current data read address.

[0092] During the writing of the data of the first time slot, the read enable signal remains low or is not output. After the writing of the data of the first time slot is completed, the control module can generate a write completion flag, which can be used to indicate that the writing of the data of the first time slot is completed. At this time, the sampling counter is cleared and re-counted. When the control module and the address generation module detect the write completion flag and the value of the sampling counter is 1, it indicates that the first uplink data of the second time slot has been written. At this time, the read enable signal can be generated, and the address generation module can synchronously generate the current data read address. At this time, the current data read address is used to read the first data of the first time slot. Subsequently, data writing and data reading are performed at every clock of the system.

[0093] In the above implementation process, the read enable signal is generated after the uplink data of the first time slot is completely written into the cache module and the first uplink data sampled in the second time slot is obtained, so that the accurate timing control of the data reading process is realized. This mechanism not only ensures that the data of the first time slot is read only after the writing is completed, avoiding data conflict and error, but also optimizes the pipeline operation of data processing by synchronizing with the sampling of the second time slot data. This method effectively improves the efficiency of the system and reduces the processing delay.

[0094] In mode 3, the read enable signal is generated at a specified time of the first time slot during the writing of the uplink data of the first time slot into the cache module, and the read enable signal is used to control the reading of the data of the first time slot.

[0095] In this implementation mode, the reading operation is started at a preset time point during the time slot writing, so that it can be ensured that the reading address will not exceed the minimum time interval of the writing address.

[0096] It should be noted that the above mode 1, mode 2 and mode 3 all need to meet timing constraints to ensure the correctness of data reading and writing in a single cache module. These constraints are applicable to all time slots, including: 1) Read operation delay constraint: the read operation of the data of the jth time slot must be delayed in time relative to the write operation of the data of the jth time slot.

[0097] 2) Read operation latest start constraint: the read operation of the data of the j-1th time slot at least starts at a time not later than the write operation of the jth time slot.

[0098] 3) Read operation earliest start constraint: the read operation of the data of the j-1th time slot should not be earlier than the progress of the write operation of the j-1th time slot to a certain proportion of time, for example, not earlier than 3 / 4 of the write time slot.

[0099] In some embodiments, the specified time can be detected by a timer, such as starting the timer before writing the first uplink data of the first time slot. The duration of a time slot is fixed, so the control module can generate the read enable signal and the address generation module can generate the current data read address to start reading the data in the first time slot after the timer reaches the specified time.

[0100] In some other embodiments, the specified time can also be detected by the sampling counter in the above-mentioned mode. The data is written in sequence according to the timing, so the sampling counter can be used to record the amount of data written into the cache module. When the amount of data reaches a specified amount, it is considered that the specified time has been reached, and the control module can be triggered to generate the read enable signal and the address generation module can generate the current data read address.

[0101] In some embodiments, the specified time is later than or equal to the time of 3 / 4 of the length of the first time slot, so as to avoid the problem that the burst read operation may be faster than the write data and cause conflict of data read and write. Moreover, before reading the data of the first time slot, most of the data has been written into the cache module. This design avoids the problem of data overwrite caused by too early start of the read operation, and fully utilizes the storage capacity of the cache module, thereby improving the efficiency of data processing.

[0102] For example, if the length of one time slot is 100 ms, then the length of 3 / 4 of the time slot is 75 ms, and the specified time can be later than or equal to 75 ms. In the implementation of the timer, the control module can generate the read enable signal and the address generation module can generate the current data read address when the timer counts to 75 ms or later.

[0103] Alternatively, in the implementation of the sampling counter, the amount of data written at the time of 3 / 4 can be determined by calculating the amount of data that can be written in 75 ms. For example, 114688 samples of data need to be written in 100 ms, so the amount of data written at the time of 3 / 4 should be 114688*3 / 4=86016. Therefore, the control module can generate the read enable signal and the address generation module can generate the current data read address when it is detected that the count of the sampling counter reaches 86016 or more.

[0104] In the above implementation process, the read enable signal is generated at the specified time during the writing of the uplink data of the first time slot into the cache module, so as to realize accurate timing control of data reading. This mechanism allows the read operation to be prepared during the data writing process, thereby optimizing the pipeline efficiency of data processing and reducing the processing delay. At the same time, the generation of the read enable signal at the specified time ensures the accuracy and stability of the read operation, and avoids data conflict and errors.

[0105] On the basis of the above embodiment, the capacity of the cache module is determined based on the total sampling points of M beams sampled in one time slot.

[0106] That is, the capacity of the cache module can be greater than or equal to the total sampling points of M beams sampled in one time slot. In this way, the data of different time slots can reuse the same physical storage space, which can effectively save storage resources. This design ensures that the cache module can accommodate all data of one time slot, avoids unnecessary waste of resources, and reduces hardware cost and power consumption.

[0107] Please refer to Figure 4 , Figure 4 A structural block diagram of a data processing apparatus 200 provided by the embodiments of the present application is shown in FIG. 1. The data processing apparatus 200 comprises: The control module 210 is configured to acquire i-th current uplink data sampled in j-th time slot wherein m represents a serial number of the m-th beam, n represents a serial number of n-th sampling data of the m-th beam, and uplink data of each time slot is sampled in a beam interleaving manner; The read-write address generation module 220 is configured to generate a current data write address and a current data read address according to a preset read-write address generation rule, wherein the preset read-write address generation rule comprises: a data write address of j-th time slot is the same as a data read address of j-1-th time slot, and data read out according to the data read address of each time slot is arranged continuously according to data of each beam. The control module 210 is further configured to write the i-th current uplink data into the cache module according to the current data write address, and read data from the cache module according to the current data read address. The control module 210 is further configured to write the i-th current uplink data into the cache module according to the current data write address, and read data from the cache module according to the current data read address.

[0108] The data processing device 200 can be understood as the LowPHY preprocessing module in the satellite payload system, and the control module 210 can be implemented by using a CPU, a microcontroller or the like. Figure 5 The address generation module 220 can include the following hardware: a read address register, a write address register, a write address adder, a write address operator, a read address adder and a read address operator, and the detailed architecture can be referred to the drawing.

[0109] The read address register is configured to store the data read address, and the write address register is configured to store the data write address.

[0110] The read address adder is configured to perform addition operation on the previous data read address and the address step corresponding to the current time slot, and input a second sum value obtained by the addition operation into the read address operator.

[0111] In the initial state, the write address register is cleared, the control module provides an initial write step value of 1, at each clock arrival, the write address adder receives the current value of the write address register and the write address step value, the write address adder calculates a first sum, the write address operator performs a modulo operation on the first sum and a value of Q-1, to obtain a new write address, the new write address is latched into the write address register as the current data write address of the next period, and the write address is sent to the write address port of the cache module. After a time slot ends, the control module can generate a reset signal to clear the write address register, and update the write address step value.

[0112] In the initial state, the read address register is cleared, the control module provides an initial read address step value of 4, when the read enable is valid, the read address adder receives the current value of the read address register and the read address step value, the read address adder calculates a second sum, the read address operator performs a modulo operation on the second sum and a value of Q-1, to obtain a new read address, the new read address is latched into the read address register as the current data read address of the next period, and the read address is sent to the read address port of the cache module. After a time slot ends, the control module can generate a reset signal to clear the read address register, and update the read address step value.

[0113] In the above implementation process, the process of generating read and write addresses involves addition and subtraction operations, the control logic mainly detects the completion of time slot data collection and latches the address step of the time slot, so the complexity is low and easy to implement.

[0114] It can be understood that the data processing apparatus described above can also be a module, a program segment or code on a data processing device. It should be understood that the apparatus corresponds to the method embodiments described above, and can perform each step involved in the method embodiments. The specific functions of the apparatus can be referred to the description in the foregoing description, and the detailed description is appropriately omitted here to avoid repetition.

[0115] It should be noted that those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the apparatus described above can refer to the corresponding process in the foregoing method embodiments, which will not be described here again.

[0116] Please refer to Figure 6 , Figure 6A structural schematic diagram of a data processing device provided in the embodiment is shown in FIG. 3. The data processing device 300 can be understood as a satellite payload device, which further comprises the cache module 310 and the data processing apparatus 200 as described above. The data processing apparatus 200 refers to Low PHY preprocessing, which can be used to execute the method as described above. The cache module 310 is used for storing data. The cache module 310 can be a high-speed RAM memory, or a non-volatile memory such as at least one disk memory. The cache module 310 can alternatively be at least one storage device located away from the aforementioned control module.

[0117] It can be understood that, Figure 6 The structure shown is only schematic. The data processing device 300 can further comprise more or less components than those shown in FIG. 3, or have a different configuration than that shown in FIG. 3. Figure 6 The components shown in FIG. 3 can be implemented in hardware, software or a combination thereof. Figure 6 Figure 6 The components shown in FIG. 3 can be implemented in hardware, software or a combination thereof.

[0118] The embodiment provides a computer readable storage medium, which stores a computer program. When the computer program is executed by a processor, the method executed by the data processing apparatus in the method embodiment is executed.

[0119] The embodiment discloses a computer program product, which comprises a computer program stored on a non-transitory computer readable storage medium. The computer program comprises program instructions, which, when executed by a computer, enable the computer to execute the method provided in each method embodiment, for example, comprising: obtaining i-th current uplink data obtained by j-th time slot sampling wherein m represents the serial number of the m-th beam, n represents the serial number of the n-th sampling data of the m-th beam, and the uplink data of each time slot is sampled in a beam interleaved manner; obtaining a current data write address and a current data read address generated according to a preset read-write address generation rule, wherein the preset read-write address generation rule comprises that the data write address of the j-th time slot is the same as the data read address of the j-1-th time slot, and the data read out according to the data read address of each time slot is arranged continuously according to the data of each beam; writing the i-th current uplink data into the cache module according to the current data write address, and reading data from the cache module according to the current data read address.

[0120] ​​In conclusion, the embodiment of the present application provides a data processing method, device, equipment, storage medium and program product. The method generates data read-write addresses by using a preset read-write address generation rule, effectively arranges the data writing and reading order, enables the data of each time slot to be read in a continuous arrangement according to the data of each beam, and realizes effective reorganization processing of the multi-beam uplink data in a single cache module. This not only improves the data processing efficiency, avoids the waste of cache resources in the traditional double cache scheme, but also significantly reduces the consumption of hardware resources, such as reducing the number of BRAMs used, thereby reducing the hardware cost and power consumption of the base station.

[0121] In the embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other manners. The above-described device embodiments are only schematic. For example, the division of the units is only a logical function division. There can be another division manner for the actual implementation, for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections between the units can be indirect couplings or communication connections through some interfaces, devices or units, and can be electrical, mechanical or in other forms.

[0122] In addition, the units described as separate components can or can not be physically separate, and the components displayed as units can or can not be physical units, that is, they can be located in one place, or can be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purposes of the embodiments of the present application.

[0123] In addition, the functional modules in the various embodiments of the present application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0124] In this paper, the relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations.

[0125] The above only describes the embodiments of the present application and is not used to limit the protection scope of the present application. For those skilled in the art, the present application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A data processing method, characterized in that, Applied to a base station, the method includes: Obtain the i-th current uplink data obtained from the j-th time slot sampling. Where m represents the sequence number of the m-th beam, and n represents the sequence number of the n-th sampled data of the m-th beam. The uplink data of each time slot is sampled in a beam interleaving manner. Obtain the current data write address and current data read address generated according to the preset read / write address generation rules, wherein the preset read / write address generation rules include: the data write address of the j-th time slot is the same as the data read address of the (j-1)-th time slot, and the data read from each time slot according to the data read address of each time slot is arranged continuously according to the data of each beam; Based on the current data write address, the i-th current uplink data The data is written into the cache module, and then read from the cache module according to the current data read address.

2. The method according to claim 1, characterized in that, The preset read / write address generation rules include write address generation rules and read address generation rules; The write address generation rule is as follows: the data write address is generated step by step based on the previous data write address and the address corresponding to the (j-1)th time slot; The read address generation rule is as follows: the data read address is generated step by step based on the previous data read address and the address corresponding to the j-th time slot; The address step corresponding to the j-th time slot is the value of the M+1-th data write address of the (j-1)-th time slot, where M represents the number of beams. The starting address of the data write address and data read address for each time slot is 0.

3. The method according to claim 2, characterized in that, The write address generation rule is characterized by the following expression: ,in, , This represents the address step corresponding to the (j-1)th time slot, Q represents the total number of sampling points for the M beams in the jth time slot, and mod represents the modulo operation; The read address generation rule is characterized by the following expression: ,in, , This represents the address step corresponding to the j-th time slot, Q represents the total number of sampling points for the M beams in the j-th time slot, and mod represents the modulo operation; in, .

4. The method according to claim 1, characterized in that, The method further includes: After all the uplink data of the first time slot is written to the cache module, a read enable signal is generated. The read enable signal is used to control the reading of data from the first time slot.

5. The method according to claim 1, characterized in that, The method further includes: After all the uplink data of the first time slot is written to the cache module and the first uplink data sampled in the second time slot is obtained, a read enable signal is generated. The read enable signal is used to control the reading of data in the first time slot.

6. The method according to claim 1, characterized in that, The method further includes: During the process of writing the uplink data of the first time slot into the cache module, a read enable signal is generated at a specified time in the first time slot. The read enable signal is used to control the reading of data in the first time slot.

7. The method according to claim 6, characterized in that, The specified time is later than or equal to 3 / 4 of the length of the first time slot.

8. The method according to any one of claims 1-7, characterized in that, The capacity of the buffer module is determined based on the total number of sampling points of M beams sampled in one time slot.

9. A data processing apparatus, characterized in that, The data processing device, applied to a base station, includes: The control module is used to acquire the i-th current uplink data obtained from the j-th time slot sampling. Where m represents the sequence number of the m-th beam, and n represents the sequence number of the n-th sampled data of the m-th beam. The uplink data of each time slot is sampled in a beam interleaving manner. The read / write address generation module is used to generate the current data write address and the current data read address according to a preset read / write address generation rule. The preset read / write address generation rule includes: the data write address of the j-th time slot is the same as the data read address of the (j-1)-th time slot, and the data read from the data read address of each time slot is arranged continuously according to the data of each beam. The control module is further configured to write the i-th current uplink data according to the current data write address. The data is written into the cache module, and then read from the cache module according to the current data read address.

10. The apparatus according to claim 9, characterized in that, The read / write address generation module includes: The read address register is used to store the data read address; Write address register, used to store the write address of data; The write address adder is used to add the previous data write address and the address step corresponding to the previous time slot, and the first sum is input into the write address arithmetic unit. The write address arithmetic unit is used to perform a modulo operation on the first sum and the value of the total number of sampling points of the M beams in the current time slot minus 1 to obtain the current data write address; The read address adder performs an addition operation on the previous data read address and the address step corresponding to the current time slot, and inputs the second sum value into the read address arithmetic unit. The read address arithmetic unit is used to perform a modulo operation on the second sum and the value of the M beams minus 1 in the current time slot to obtain the current data read address.

11. A data processing device, characterized in that, The data processing device includes a cache module and the data processing apparatus according to any one of claims 9-10.

12. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it performs the method as described in any one of claims 1-8.

13. A computer program product, characterized in that, It includes computer program instructions, which, when read and executed by a processor, perform the method as described in any one of claims 1-8.

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