Manufacturing method of three-dimensional structure electrode of silicon capacitor and silicon capacitor
By employing carbon nanotube patterning transfer and atomic layer deposition processes to form an alternating stacked structure of multilayer carbon nanotubes and alumina dielectric layers in silicon capacitors, the problems of high etching process requirements and difficult trench filling were solved, enabling the manufacture of silicon capacitors with high capacitance density and high reliability.
Patent Information
- Application Number
- CN202511700249.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-19
- Publication Date
- 2026-02-13
AI Technical Summary
The etching process for existing silicon capacitors has high requirements, which can easily lead to fluctuations in capacitance parameters, difficulty in trench filling, fragile substrate structure, and stress during metal filling, resulting in wafer warping and sidewall cracking, thus reducing service life and reliability.
A multilayer stacked structure of alternating carbon nanotubes and alumina dielectric layers is formed on an insulating substrate using carbon nanotube patterning transfer and atomic layer deposition processes. Metal electrode mounting grooves are formed by photolithography and wet etching, and then filled with metal material.
It increases capacitance density, enhances the stability and reliability of capacitors, simplifies the manufacturing process, reduces manufacturing costs, and improves production efficiency, making it suitable for high-end applications.
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Figure CN121531727A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of silicon capacitor manufacturing technology, and in particular to a method for manufacturing a three-dimensional electrode structure for a silicon capacitor and a silicon capacitor. Background Technology
[0002] In the field of electronic information, silicon capacitors, as key passive electronic components, have been widely used in high-end fields such as optical communication and radio frequency due to their excellent electrical performance. With the rapid development of electronic devices towards miniaturization and high integration, higher requirements are being placed on the capacitance density per unit area of silicon capacitors. To meet this demand, the industry generally adopts a technical approach of constructing a three-dimensional structure inside the capacitor, thereby increasing the effective area of the capacitor and thus improving the capacitance density per unit area.
[0003] Currently, the mainstream fabrication method for the three-dimensional structure of silicon capacitors is based on a substrate. The core process flow is as follows: First, an inward etching process is performed on the surface of the substrate to form several regularly distributed trench regions on the substrate. Then, physical vapor deposition (PVD), chemical vapor deposition (CVD), and other processes are used to complete the uniform deposition of the dielectric layer in the trench regions and the filling of the trenches with metal materials, finally constructing a complete silicon capacitor structure.
[0004] However, the aforementioned fabrication process still faces numerous technical challenges in practical applications, hindering the performance improvement and large-scale production of silicon capacitors. Specific problems include: stringent etching requirements: the etching quality of the trench area directly affects subsequent capacitor performance, necessitating strict control over the trench shape accuracy, sidewall angle consistency, and sidewall surface flatness. Any minute deviation can lead to fluctuations in capacitor parameters, increasing the difficulty of process control; significant trench filling challenges: the process is significantly limited by the aspect ratio of the etched trenches. As the aspect ratio increases, the technical challenges in the metal filling process rise sharply. On the one hand, it is difficult to achieve uniform coverage of the metal seed layer on the inner wall of the trench (especially at the bottom of deep trenches), easily resulting in insufficient local thickness or gaps; on the other hand, cavities are easily formed at the bottom of the trench due to differences in metal deposition rates, leading to incomplete filling and severely affecting the conductivity and stability of the capacitor; insufficient product reliability: after the substrate is etched to form trenches, the overall structural strength is significantly reduced, making it more fragile. During the subsequent metal filling process, the difference in thermal expansion coefficients between the metal material and the substrate and dielectric layer will generate stress. This stress acts on the entire wafer, which can easily cause structural damage such as wafer warping and trench sidewall cracking. Ultimately, this leads to a shortened lifespan of the silicon capacitor and its reliability cannot meet the stringent requirements of high-end application scenarios. Summary of the Invention
[0005] Therefore, the technical problem to be solved by the present invention is to overcome the problems in the prior art, such as high etching process requirements, easy fluctuation of capacitance parameters; difficulty in trench filling, affecting conductivity and stability; fragile structure of substrate after etching, easy stress during metal filling, resulting in wafer warping, sidewall cracking, and reduced service life and reliability.
[0006] In a first aspect, to solve the above-mentioned technical problems, the present invention provides a method for manufacturing a three-dimensional structure electrode for a silicon capacitor, comprising: S1. Select an insulating substrate and perform patterned transfer of carbon nanotubes on the insulating substrate to obtain a first layer of carbon nanotube structure. S2. Deposit a first alumina dielectric layer on the first carbon nanotube structure; S3. A second carbon nanotube structure is fabricated on the surface of the first alumina dielectric layer. The position of the second carbon nanotube structure is staggered with that of the first carbon nanotube structure, so that the first carbon nanotube structure and the second carbon nanotube structure form an interdigitated structure. S4. Deposit a second alumina dielectric layer on the second carbon nanotube structure; generate an alternating stacked structure of multilayer carbon nanotube structure and multilayer alumina dielectric layer according to the target design value of silicon capacitor; S5. Remove the alumina dielectric layer on both sides of the multilayer carbon nanotube structure in the alternating stacked structure to obtain the metal electrode mounting groove. S6. Fill the metal electrode mounting groove with metal material to obtain the metal electrode of the silicon capacitor.
[0007] In one embodiment of the present invention, in step S1, selecting an insulating substrate and performing patterned transfer of carbon nanotubes on the insulating substrate to obtain a first layer of carbon nanotube structure is as follows: The insulating substrate is repeatedly immersed in a carbon nanotube dispersion, left to stand for a preset time, and then removed and dried to form a carbon nanotube film. A polydimethylsiloxane soft film template with a preset pattern is fabricated. The polydimethylsiloxane soft film template is then brought into contact with the carbon nanotube film. Carbon nanotubes in non-target areas are removed by patterned transfer to obtain the first layer of carbon nanotube structure.
[0008] In one embodiment of the present invention, a patterned transfer method is used to remove carbon nanotubes from non-target areas, wherein the patterned transfer method is a nanoimprint lithography process.
[0009] In one embodiment of the present invention, step S5, which involves removing the alumina dielectric layer on both sides of the multilayer carbon nanotube structure in the alternating stacked structure to obtain the metal electrode mounting groove, is as follows: The alternating stacked structure is used as a substrate; photoresist is coated on the surface of the alumina dielectric layer of the substrate; a first mask with a designed etching pattern is aligned with the substrate, and the photoresist is exposed; the exposed substrate is developed, and the photoresist in the exposed area is dissolved and removed using a developer, so that a photoresist pattern consistent with the mask pattern is formed on the surface of the alumina dielectric layer. The exposed substrate is cleaned sequentially to obtain a pretreated substrate; the pretreated substrate is completely immersed in a container with phosphoric acid as the etching solution to obtain an etched substrate; the etched substrate is transferred to a pure water tank to obtain a metal electrode mounting tank.
[0010] In one embodiment of the present invention, step S6, in which metal material is filled into the metal electrode mounting groove to obtain the metal electrode of the silicon capacitor, is as follows: Obtain the etched substrate in S5, coat the surface of the alumina dielectric layer in the etched substrate with photoresist, align the second mask with the designed etching pattern with the etched substrate, and expose the photoresist to harden the exposed area and make it a substance that hinders development; perform development treatment on the exposed substrate, use the developer to dissolve the photoresist in the unexposed light-shielding area, and form a photoresist pattern on the surface of the alumina dielectric layer that is opposite to the pattern of the second mask; The etched substrate is placed in a vacuum chamber, and the vacuum chamber is evacuated. The metal material is deposited and filled into the metal electrode mounting tank by vacuum evaporation to obtain the metal electrode of the silicon capacitor.
[0011] In one embodiment of the present invention, step S2, which involves depositing a first alumina dielectric layer on the first carbon nanotube structure, is as follows: An insulating substrate with the first layer of carbon nanotube structure is placed in a reaction chamber, and a first type of precursor gas is introduced; the first type of precursor gas adsorbs or reacts chemically with the surface of the first layer of carbon nanotube structure. Stop the flow of the first type of precursor gas and introduce an inert gas into the reaction chamber; use the inert gas to flush out any excess first type of precursor gas that has not been adsorbed in the reaction chamber; After the inert gas cleaning is completed, a second precursor gas is introduced into the reaction chamber; the second precursor gas adsorbed on the surface of the first carbon nanotube structure reacts chemically to generate the first alumina dielectric layer.
[0012] In one embodiment of the present invention, step S4, in which the alternating stacked structure of multilayer carbon nanotubes and multilayer alumina dielectric layers is generated according to the target design value of the silicon capacitor, includes: in the first step Fabrication of the first layer of alumina dielectric layer surface +1 layer carbon nanotube structure, in the first +1 layer of carbon nanotube structure deposited +1 layer of alumina dielectric layer, repeat this process until the target design value is reached; wherein .
[0013] In one embodiment of the present invention, the insulating substrate is made of a material that is not corroded by phosphoric acid.
[0014] Secondly, in order to solve the above-mentioned technical problems, the present invention provides a silicon capacitor, which is manufactured by the above-mentioned manufacturing method, characterized in that it comprises: an insulating substrate, a multilayer carbon nanotube structure, a multilayer alumina dielectric layer and a metal electrode. The multilayer carbon nanotube structure and the multilayer alumina dielectric layer are alternately stacked on the insulating substrate, and adjacent two layers of carbon nanotube structure form an interdigitated structure. The metal electrodes are disposed in the reserved grooves on both sides of the multilayer carbon nanotube structure, connected to the corresponding extended carbon nanotube layers, and not in contact with the non-corresponding extended carbon nanotube layers.
[0015] In one embodiment of the present invention, the stagger distance between two adjacent carbon nanotube structures is 496 μm.
[0016] Compared with the prior art, the above-described technical solution of the present invention has the following advantages: (1) The method for manufacturing a three-dimensional structure electrode for a silicon capacitor and the silicon capacitor described in this invention form a first layer of carbon nanotube structure by patterning and transferring carbon nanotubes on an insulating substrate. This step achieves precise arrangement of carbon nanotubes, laying the foundation for subsequent multilayer stacking. Alumina dielectric layer is uniformly deposited on the carbon nanotube structure using atomic layer deposition, which not only enhances insulation performance but also improves the stability and reliability of the capacitor. Its uniformity and high quality are key to achieving low leakage current. In constructing the multilayer structure, the second layer of carbon nanotube structure is staggered with the first layer, forming an interdigitated structure. This design significantly increases the effective area of the capacitor plates and improves capacitance density. The alternating stacking of the multilayer structure further disperses the electric field, increases the breakdown voltage, and enhances the capacitor's ability to operate at high voltages. Furthermore, excess alumina dielectric layer is removed by photolithography and wet etching processes to form a metal electrode mounting groove, which is then filled with metal material to form a metal electrode. This step ensures precise electrode mounting and improves the overall performance and reliability of the capacitor.
[0017] (2) The manufacturing process of this invention is simple and efficient, and the structure is flat, which not only facilitates uniform deposition of the dielectric layer, but also avoids the limitation of etching aspect ratio on the process. Compared with the traditional method of etching trenches and filling them, this invention not only improves production efficiency, but also reduces manufacturing costs. Attached Figure Description
[0018] To make the content of this invention easier to understand, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings.
[0019] Figure 1 This is a flowchart of a method for manufacturing a three-dimensional structure electrode for a silicon capacitor according to a preferred embodiment of the present invention; Figure 2 This is a schematic diagram of the first layer of carbon nanotube structure and the insulating substrate structure in a preferred embodiment of the present invention; Figure 3 This is a schematic diagram of the deposition of the first alumina dielectric layer in a preferred embodiment of the present invention; Figure 4 This is a schematic diagram of the deposition of a second layer of carbon nanotubes in a preferred embodiment of the present invention; Figure 5 This is a schematic diagram of the deposition of the second alumina dielectric layer in a preferred embodiment of the present invention; Figure 6 This is a schematic diagram of the alternating stacked structure in a preferred embodiment of the present invention; Figure 7 This is a schematic diagram of the structure of the metal electrode mounting groove obtained by removing excess alumina dielectric layer from the alternating stacked structure in a preferred embodiment of the present invention; Figure 8 This is a cross-sectional view of a silicon capacitor according to a preferred embodiment of the present invention; Figure 9 This is a top view of a silicon capacitor according to a preferred embodiment of the present invention.
[0020] Explanation of reference numerals in the accompanying drawings: 1. Insulating substrate; 2. First carbon nanotube structure; 3. First alumina dielectric layer; 4. Second carbon nanotube structure; 5. Second alumina dielectric layer; 6. Alternating stacked structure; 7. Metal electrode mounting groove; 8. Metal electrode. Detailed Implementation
[0021] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, so that those skilled in the art can better understand and implement the present invention. However, the embodiments described are not intended to limit the present invention.
[0022] Example 1: Reference Figures 1 to 9As shown, this embodiment of the invention provides a method for manufacturing a three-dimensional electrode structure for a silicon capacitor, including but not limited to the following steps: S1. Select an insulating substrate 1 and perform patterned transfer of carbon nanotubes on the insulating substrate 1 to obtain the first layer of carbon nanotube structure 2. S2. Deposit the first alumina dielectric layer 3 on the first carbon nanotube structure 2; S3. A second carbon nanotube structure 4 is fabricated on the surface of the first alumina dielectric layer 3. The position of the second carbon nanotube structure 4 is staggered with that of the first carbon nanotube structure 2, so that the first carbon nanotube structure 2 and the second carbon nanotube structure 4 form an interdigitated structure. S4. Deposit a second alumina dielectric layer 5 on the second carbon nanotube structure 4; Generate an alternating stacked structure 6 of multilayer carbon nanotube structure and multilayer alumina dielectric layer according to the target design value of silicon capacitor. S5. Remove the alumina dielectric layer on both sides of the multilayer carbon nanotube structure in the alternating stacked structure 6 to obtain the metal electrode mounting groove 7. S6. Fill the metal electrode mounting tank 7 with metal material to obtain the metal electrode 8 of the silicon capacitor.
[0023] The method for manufacturing a three-dimensional structure electrode for a silicon capacitor according to embodiments of the present invention has the advantages of simple manufacturing, uniform and flat structure, and high product reliability. A first layer of carbon nanotube structure is formed by patterning and transferring carbon nanotubes on an insulating substrate. This step ensures the precise alignment of the carbon nanotubes, providing a foundation for subsequent multilayer stacking. Next, an alumina dielectric layer is deposited on the carbon nanotube structure using atomic layer deposition (ALD), which not only enhances insulation performance but also improves the stability and reliability of the capacitor. The uniformity and high quality of the alumina dielectric layer are key to achieving low leakage current. When repeating the above steps to form a multilayer structure, the second layer of carbon nanotube structure is staggered with the first layer, forming an interdigitated structure. This structural design significantly increases the effective area of the capacitor plates, further improving the capacitance density. The alternating stacking of multilayer structures not only improves the capacitance density but also enhances the breakdown voltage by dispersing the electric field, thereby improving the capacitor's ability to operate at high voltages. Excess alumina dielectric layer is removed using photolithography and wet etching processes to form a metal electrode mounting groove, which is then filled with metal material to form the metal electrode. This step ensures precise electrode mounting, improving the overall performance and reliability of the capacitor. These steps work together to produce silicon capacitors with high capacitance density, low leakage current, high breakdown voltage, good thermal stability and environmental adaptability, as well as excellent high-frequency performance. Furthermore, this method is simple and efficient, producing a flat structure, which not only facilitates uniform dielectric layer deposition but also avoids the limitations imposed by etching aspect ratio. Compared to traditional trench etching and filling methods, carbon nanotube (CNT) fabrication efficiency is significantly improved, increasing production efficiency and reducing manufacturing costs, making this capacitor more competitive in large-scale production and commercial applications.
[0024] Specifically, carbon nanotubes (CNTs) are hollow tubular structures formed by the orderly arrangement of sp² hybridized carbon atoms. Their unique molecular structure endows them with excellent material properties: on the one hand, CNTs have extremely high current carrying capacity and can withstand high current densities, far exceeding traditional metal electrode materials, which can meet the high current conduction requirements of silicon capacitors in highly integrated scenarios; on the other hand, their axial thermal conductivity can quickly conduct the heat generated during electrode operation, avoiding local overheating that leads to capacitance performance degradation; at the same time, CNTs are chemically stable over a certain temperature range and are not prone to oxidation or structural decomposition, ensuring the long-term reliability of silicon capacitors in extreme environments. Based on the above characteristics, CNTs are preferred as one of the metal electrode materials in this invention. CNTs can be used to form electrode extension layers with specific structures through patterning processes (such as NIL nanoimprint lithography), which can not only form a good interface bond with the alumina dielectric layer, but also increase the effective electrode area through multilayer stacking and interdigitation layout, thereby improving the capacitance density per unit area of silicon capacitors. They are the core material for the fabrication of high-precision and high-stability electrodes for silicon capacitors.
[0025] Specifically, in step S1, the steps of selecting an insulating substrate 1 and performing patterned transfer of carbon nanotubes on the insulating substrate 1 to obtain the first layer of carbon nanotube structure 2 are as follows: S110. The material of the insulating substrate 1 is selected to be non-corrosive to phosphoric acid. The insulating substrate 1 is immersed in the carbon nanotube dispersion multiple times, and after standing for a preset time, it is taken out and dried to naturally form a carbon nanotube film. The thickness of the film can be adjusted by controlling the number of immersions, so that the surface of the film obtained is relatively smooth and can be transferred from the original substrate to other substrates.
[0026] S120. Fabricate a polydimethylsiloxane (PDMS) soft film template containing a preset pattern. Contact this template with a carbon nanotube film and remove carbon nanotubes from non-target areas using patterned transfer, thereby obtaining the first carbon nanotube structure 2. This structure can serve as an extension structure for the metal electrode 8, such as... Figure 2 As shown. In this embodiment, the patterning transfer method is preferably NIL nanoimprint lithography.
[0027] Specifically, refer to Figure 3 As shown, in step S2, using atomic layer deposition (ALD) technology, materials such as Al and O are selected as sources to deposit the first alumina dielectric layer 3 on the first carbon nanotube structure 2. The specific steps are as follows: S210. The insulating substrate 1 with the first carbon nanotube structure 2 is placed in the ALD reaction chamber, and then a first precursor gas is introduced into the chamber to make it uniformly adsorb or chemically react with the surface of the first carbon nanotube structure 2.
[0028] S220. Stop introducing the first precursor gas, and then introduce an inert gas into the chamber. By flushing with the inert gas, the excess first precursor gas and reaction byproducts that have not been adsorbed in the reaction chamber are completely removed, thereby preventing reactions from occurring in subsequent processes and avoiding an increase in impurities in the medium layer.
[0029] S230. After the inert gas cleaning is completed, a second precursor gas is introduced into the cavity. This gas reacts chemically with the first precursor gas adsorbed on the surface of the first carbon nanotube structure 2 to form a coating. Alternatively, it can continue to react with the products of the reaction between the first precursor gas and the first carbon nanotube structure 2 to form a coating.
[0030] S240: After stopping the introduction of the second precursor gas, introduce the inert gas again. Control the flow rate and ventilation time of the inert gas to be consistent with those in step S220 to ensure that unreacted second precursor gas and residual byproducts are completely removed from the cavity. At this point, the deposition process of the first alumina dielectric layer 3 is complete.
[0031] Specifically, refer to Figure 4 and Figure 9 As shown, in step S3, similar to step S1, a second carbon nanotube structure 4 is fabricated on the already formed first alumina dielectric layer 3. The spacing d1 between the first carbon nanotube structure 2 and the second carbon nanotube structure 4 is set to 22 μm, and the stagger distance d2 is set to 496 μm, thus forming an interdigitated structure. In this embodiment of the invention, setting the spacing d1 to 22 μm effectively balances the requirements of structural size and target capacitance.
[0032] Furthermore, in this embodiment of the invention, the spacing distance d1 is allowed to have a deviation of ±2μm, that is, it can be controlled within the range of 22μm±2μm in actual setting. In addition, it should be noted that the settings of the spacing distance and the staggered distance are not fixed and can be flexibly adjusted according to the specific requirements of the target capacitance and withstand voltage.
[0033] Specifically, in step S4, based on the target design values of the silicon capacitor (such as capacitance density, breakdown voltage, and size specifications), a composite structure composed of alternating and stacked multilayer carbon nanotube structures and multilayer alumina dielectric layers is finally generated using a method similar to steps S1 (carbon nanotube structure preparation step) and S2 (alumina dielectric layer preparation step). Specifically, in the... Fabrication of the first layer of alumina dielectric layer surface +1 layer of carbon nanotube structure, in the first +1 layer of carbon nanotube structure deposited +1 layer of alumina dielectric layer, repeat this process until the target design value is reached; where .
[0034] It should be noted that the specific number of carbon nanotube structures and alumina dielectric layers is not a fixed value, but can be flexibly set according to the performance requirements of the actual product. For example, if it is necessary to increase the capacitance density per unit area, the number of stacked layers can be increased to expand the effective electrode area; if it is necessary to reduce the overall thickness to adapt to miniaturization scenarios, the number of layers can be reduced and the pattern density of the single-layer carbon nanotube structure can be optimized. Through this adjustable stacking design, silicon capacitors can meet the differentiated needs of different application scenarios.
[0035] Specifically, in step S5, photolithography and wet etching processes are preferred to remove the alumina dielectric layer on both sides of the multilayer carbon nanotube structure in the alternating stacked structure 6, thereby obtaining the metal electrode mounting groove 7. The specific steps are as follows: S510, Photolithography defines the etching pattern. Alternating stacked structures 6 are used as the substrate; photoresist is coated onto the surface of the alumina dielectric layer of the substrate; the first mask with the designed etching pattern is aligned with the substrate, and the photoresist is exposed; the exposed substrate is developed, and the photoresist in the exposed areas is dissolved and removed using a developer, forming a photoresist pattern on the surface of the alumina dielectric layer that matches the mask pattern.
[0036] S520, Wet etching of the alumina dielectric layer. The exposed substrate is sequentially cleaned to obtain a pretreated substrate. Cleaning can be done with water. The pretreated substrate is completely immersed in a container with phosphoric acid as the etching solution to obtain the etched substrate; the etched substrate is then transferred to a pure water bath to obtain the metal electrode mounting tank 7, as shown. Figure 7 As shown.
[0037] For example, in the pretreatment stage, the substrate is sequentially subjected to gradient cleaning to efficiently remove oil, organic residues, and microparticle impurities from the substrate surface, providing a clean and uniform surface environment for the subsequent etching reaction. In the reaction stage, the pretreated substrate is completely immersed in the etching solution. This process uses phosphoric acid as the etching solution. To ensure uniform and controllable etching results, key parameters during the reaction process must be strictly controlled, including maintaining a stable etching solution concentration to avoid localized reaction rate differences, maintaining a constant reaction environment temperature to prevent temperature fluctuations from affecting the etching depth, and precisely controlling the etching duration to avoid over-etching or under-etching, thereby effectively avoiding uneven etching problems. In the termination stage, after the etching reaction reaches the preset requirements, the substrate is quickly removed from the etching solution and transferred to a water tank containing pure water. The etching reaction is quickly terminated by rinsing with pure water, simultaneously washing away residual etching solution and reaction products from the substrate surface to prevent damage to the substrate structure from subsequent secondary etching.
[0038] Specifically, in step S6, photolithography and vapor deposition processes are preferred to fill the metal electrode mounting tank 7 with metal material, thereby obtaining the metal electrode 8 of the silicon capacitor. The specific steps are as follows: S610. Define the etching pattern using photolithography. Obtain the etched substrate from step S5. Coat the surface of the alumina dielectric layer in the etched substrate with photoresist. Align the second mask with the designed etching pattern with the etched substrate and expose the photoresist to harden the exposed areas and make them a material that hinders development. Develop the exposed substrate, using a developer to dissolve the unexposed, light-shielding areas of the photoresist, forming a photoresist pattern on the surface of the alumina dielectric layer that is the opposite of the pattern on the second mask.
[0039] S620, Vacuum Evaporation Metal Electrode 8. The etched substrate is placed into a vacuum chamber, which is then evacuated. Using vacuum evaporation, metal material is deposited and filled into the metal electrode mounting tank 7 to obtain the metal electrode 8 of the silicon capacitor. Figure 8 As shown.
[0040] It should be noted that when filling the pre-reserved grooves on both sides of the alternating stacked structure 6 with metal electrodes 8 through the vapor deposition process (step S620 vacuum vapor deposition), the deposition range and morphology of the metal electrodes 8 must be controlled. Any physical contact between the metal electrodes 8 and the carbon nanotube (CNT) structures on the non-corresponding side is prohibited. Specifically, the metal electrodes 8 must not cover or touch CNT layers that are not electrically connected to them (e.g., the left metal electrode 8 can only connect to the left CNT structure and must not contact the right interdigitated CNT structure). Furthermore, due to excessive metal deposition or edge overflow, a conductive path must not be formed with adjacent CNT structures. The core purpose of this restriction is to avoid short-circuit faults caused by contact between the metal electrodes 8 and the opposite-side CNT structures. If contact occurs, it will directly lead to conduction between the positive and negative electrodes of the silicon capacitor, destroying the capacitor core structure composed of the CNT structure and the alumina dielectric layer, causing the capacitor to lose its charge storage function. Simultaneously, the large current generated by the short circuit may burn out the stack, ultimately causing the silicon capacitor to fail and failing to meet the stringent electrical performance requirements of components in fields such as optical communication and radio frequency.
[0041] The method described in this invention effectively solves many problems existing in the prior art. In the prior art, the etching process has high requirements, the trench filling process is difficult, and the substrate structure becomes extremely fragile after etching. During metal filling, stress is easily generated, leading to a series of problems such as wafer warping and sidewall cracking, all of which greatly reduce the product's lifespan and reliability. Compared with the prior art, the carbon nanotube (CNT) manufacturing method used in this method has significant advantages. Its manufacturing process is simple, and the structure is flat, making dielectric layer deposition easy and no longer limited by the etching aspect ratio. Simultaneously, the electrode and dielectric layer adopt a stacked structure, greatly improving product reliability. Furthermore, the CNT fabrication efficiency of this method is far higher than that of the traditional method of etching trenches and then filling them.
[0042] Example 2: This embodiment provides a silicon capacitor, which is manufactured using the manufacturing method described in Embodiment 1, and includes: an insulating substrate 1, a multilayer carbon nanotube structure, a multilayer alumina dielectric layer, and a metal electrode 8. Multilayer carbon nanotube structures and multilayer alumina dielectric layers are alternately stacked on insulating substrate 1, with adjacent carbon nanotube structures forming interdigitated structures. Metal electrodes 8 are disposed in reserved grooves on both sides of the multilayer carbon nanotube structure, connected to the corresponding extended carbon nanotube layers, and not in contact with non-corresponding extended carbon nanotube layers.
[0043] This embodiment provides a silicon capacitor that achieves high capacitance density and low leakage current through the alternating stacking of multilayer carbon nanotube structures and alumina dielectric layers. The multilayer structure significantly increases the number of capacitor plates, improving capacitance density, while the excellent insulation properties of the alumina dielectric layer effectively reduce leakage current. Furthermore, the multilayer structure disperses the electric field, increasing the breakdown voltage and enhancing the capacitor's ability to operate at high voltages. The interdigitated structure further optimizes the electric field distribution, increases the effective area, and improves performance and reliability. The use of mature processes such as atomic layer deposition and photolithography makes this design highly compatible with existing semiconductor manufacturing processes, facilitating mass production. The silicon capacitor described in this embodiment also exhibits good thermal stability and environmental adaptability, making it suitable for harsh environments such as high temperature and humidity. Its excellent high-frequency performance reduces signal loss and interference, making it suitable for radio frequency and high-speed digital circuits. This design offers strong customizability and scalability, meeting the diverse needs of different application scenarios.
[0044] Specifically, the stagger distance d2 between two adjacent carbon nanotube structures is 496 μm.
[0045] Specifically, refer to Figure 9 As shown, the preferred size of a single silicon capacitor is 0.7mm × 0.5mm, and the preferred size of the metal electrode 8 is 100um × 500um.
[0046] It should be noted that, in Figure 9 The black part represents the multilayer carbon nanotube structure, the light gray part represents the multilayer alumina dielectric layer, the white part represents the insulating substrate 1, and the dark gray part represents the metal electrode 8.
[0047] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.
Claims
1. A method for manufacturing a three-dimensional electrode structure for a silicon capacitor, characterized in that, include: S1. Select an insulating substrate and perform patterned transfer of carbon nanotubes on the insulating substrate to obtain a first layer of carbon nanotube structure. S2. Deposit a first alumina dielectric layer on the first carbon nanotube structure; S3. A second carbon nanotube structure is fabricated on the surface of the first alumina dielectric layer. The position of the second carbon nanotube structure is staggered with that of the first carbon nanotube structure, so that the first carbon nanotube structure and the second carbon nanotube structure form an interdigitated structure. S4. Deposit a second alumina dielectric layer on the second carbon nanotube structure; generate an alternating stacked structure of multilayer carbon nanotube structure and multilayer alumina dielectric layer according to the target design value of silicon capacitor; S5. Remove the alumina dielectric layer on both sides of the multilayer carbon nanotube structure in the alternating stacked structure to obtain the metal electrode mounting groove. S6. Fill the metal electrode mounting groove with metal material to obtain the metal electrode of the silicon capacitor.
2. The method for manufacturing a three-dimensional structure electrode for a silicon capacitor according to claim 1, characterized in that, In step S1, the step of selecting an insulating substrate and performing patterned transfer of carbon nanotubes on the insulating substrate to obtain the first layer of carbon nanotube structure is as follows: The insulating substrate is repeatedly immersed in a carbon nanotube dispersion, left to stand for a preset time, and then removed and dried to form a carbon nanotube film. A polydimethylsiloxane soft film template with a preset pattern is fabricated. The polydimethylsiloxane soft film template is then brought into contact with the carbon nanotube film. Carbon nanotubes in non-target areas are removed by patterned transfer to obtain the first layer of carbon nanotube structure.
3. The method for manufacturing a three-dimensional structure electrode for a silicon capacitor according to claim 2, characterized in that, Carbon nanotubes in non-target areas are removed by patterned transfer, and the patterned transfer method is nanoimprint lithography.
4. The method for manufacturing a three-dimensional structure electrode for a silicon capacitor according to claim 1, characterized in that, In step S5, the step of removing the alumina dielectric layer on both sides of the multilayer carbon nanotube structure in the alternating stacked structure to obtain the metal electrode mounting groove is as follows: The alternating stacked structure is used as a base; Photoresist is coated on the surface of the alumina dielectric layer of the substrate, a first mask with the designed etching pattern is aligned with the substrate, and the photoresist is exposed. The exposed substrate is developed, and the photoresist in the exposed area is dissolved and removed using a developer to form a photoresist pattern on the surface of the alumina dielectric layer that is consistent with the mask pattern. The exposed substrates are cleaned sequentially to obtain pretreated substrates; The pretreated substrate is completely immersed in a container with phosphoric acid as the etching solution to obtain an etched substrate; the etched substrate is then transferred to a pure water tank to obtain a metal electrode mounting tank.
5. The method for manufacturing a three-dimensional structure electrode for a silicon capacitor according to claim 1, characterized in that, In step S6, the step of filling the metal electrode mounting groove with metal material to obtain the metal electrode of the silicon capacitor is as follows: Obtain the etched substrate in S5, coat the surface of the alumina dielectric layer in the etched substrate with photoresist, align the second mask with the designed etching pattern with the etched substrate, and expose the photoresist to harden the exposed area and make it a substance that hinders development. The exposed substrate is developed, and the unexposed photoresist in the light-shielding area is dissolved by the developer to form a photoresist pattern on the surface of the alumina dielectric layer that is opposite to the pattern of the second mask. The etched substrate is placed into a vacuum chamber, and the vacuum chamber is evacuated. The metal electrode of the silicon capacitor is obtained by vacuum evaporation to deposit the metal material and fill the metal electrode mounting tank.
6. The method for manufacturing a three-dimensional structure electrode for a silicon capacitor according to claim 1, characterized in that, In step S2, the step of depositing the first alumina dielectric layer on the first carbon nanotube structure is as follows: An insulating substrate with the first layer of carbon nanotube structure is placed in a reaction chamber, and a first type of precursor gas is introduced; the first type of precursor gas adsorbs or reacts chemically with the surface of the first layer of carbon nanotube structure. Stop the flow of the first type of precursor gas and introduce an inert gas into the reaction chamber; use the inert gas to flush out any excess first type of precursor gas that has not been adsorbed in the reaction chamber; After the inert gas cleaning is completed, a second precursor gas is introduced into the reaction chamber; the second precursor gas adsorbed on the surface of the first carbon nanotube structure reacts chemically to generate the first alumina dielectric layer.
7. The method for manufacturing a three-dimensional structure electrode for a silicon capacitor according to claim 1, characterized in that, In step S4, the process of generating an alternating stacked structure of multilayer carbon nanotubes and multilayer alumina dielectric layers according to the target design value of the silicon capacitor includes: in the first step Fabrication of the first layer of alumina dielectric layer surface +1 layer carbon nanotube structure, in the first +1 layer of carbon nanotube structure deposited +1 layer of alumina dielectric layer, repeat this process until the target design value is reached; wherein .
8. The method for manufacturing a three-dimensional structure electrode for a silicon capacitor according to claim 1, characterized in that, The insulating substrate is made of a material that is not corroded by phosphoric acid.
9. A silicon capacitor, manufactured using the manufacturing method according to any one of claims 1 to 8, characterized in that, include: Insulating substrate, multilayer carbon nanotube structure, multilayer alumina dielectric layer and metal electrode; The multilayer carbon nanotube structure and the multilayer alumina dielectric layer are alternately stacked on the insulating substrate, and adjacent two layers of carbon nanotube structure form an interdigitated structure. The metal electrodes are disposed in the reserved grooves on both sides of the multilayer carbon nanotube structure, connected to the corresponding extended carbon nanotube layers, and not in contact with the non-corresponding extended carbon nanotube layers.
10. A silicon capacitor according to claim 9, characterized in that, The stagger distance between the two adjacent carbon nanotube structures is 496 μm.