Field plate manufacturing method and semiconductor device

Abstract

The invention provides a method for manufacturing a field plate of a semiconductor device, which comprises the following steps of: providing a semiconductor structure which comprises an intermediate dielectric layer, a stop layer formed on the intermediate dielectric layer and an etching dielectric layer formed on the stop layer; the etching dielectric layer and the stop layer are patterned to form a field plate opening, and the stop layer is laterally corroded at the bottom edge of the field plate opening, so that a lateral cavity is formed between the etching dielectric layer and the intermediate dielectric layer; forming a side wall layer covering the side wall and the bottom of the field plate opening and filling the lateral cavity by depositing a side wall material; and depositing a metal field plate material on the side wall layer to form a metal field plate. The method has the beneficial effects that holes in a transverse corrosion region of the stop layer are eliminated, and potential defects are eliminated; the method eliminates side wall cavities of the stop layer, strengthens electric field control of a cavity region, and enhances the reliability of the device.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor, and in particular to a field plate manufacturing method and a semiconductor device. BACKGROUND

[0002] The description in this section merely provides background information related to the present application disclosure and does not constitute the prior art.

[0003] As shown in Figure 1 , currently, gallium nitride HEMT is basically a planar device, which needs to use a field plate to modulate the electric field, reduce the electric field on the surface of the device, and improve the reliability of the device. The uniformity control of the field plate height is very important. If the uniformity of the field plate height is poor, the reliability of the device will be affected.

[0004] It should be noted that the above introduction to the technical background is only to facilitate the clear and complete description of the technical scheme of the present application, and to facilitate the understanding of those skilled in the art. The above technical scheme cannot be considered as known to those skilled in the art only because it is described in the background section of the present application. SUMMARY

[0005] In the prior art, FP etching is usually performed with no-etch-stop layer and with etch-stop layer.

[0006] Referring to Figures 2A to 2C , the forming method of the no-etch-stop layer includes forming a dielectric layer 10 on a semiconductor structure front layer structure 1, etching the dielectric layer 10 to form a field plate opening, and forming a metal field plate 6 on the field plate opening. This forming method simply relies on the control of etching rate, resulting in large fluctuation of field plate height.

[0007] Referring to Figures 3A to 3D , the forming method of the etch-stop layer includes forming an intermediate dielectric layer 2 on a semiconductor structure front layer structure 1, forming a stop layer 3 on the intermediate dielectric layer 2, forming an etching dielectric layer 4 on the stop layer 3, and patterning the etching dielectric layer 4 and the stop layer 3 to form a field plate opening, as shown in Figure 3A Figure 3B 3C , the stop layer 3 is laterally etched at the bottom edge of the field plate opening, causing a lateral cavity 7 to be formed between the etching dielectric layer 4 and the intermediate dielectric layer 2. Referring to Figure 3D ​​As shown, a metal field plate 6 is formed by depositing metal material. This forming process relies on a high selectivity ratio between the etching medium and the stop layer 3, resulting in minimal fluctuations in the field plate height. However, since the stop layer and the etching medium layer 4 are generally made of different materials, lateral corrosion of the stop layer may occur during subsequent processing, leading to potential defects and low reliability in the semiconductor device.

[0008] Based on the aforementioned deficiencies in the prior art, the field plate fabrication method and semiconductor device of this application have better performance.

[0009] To achieve the above objectives, this application provides the following technical solution: a method for fabricating a field plate for a semiconductor device, comprising the following steps: A semiconductor structure is provided, the semiconductor structure including an intermediate dielectric layer, a stop layer formed on the intermediate dielectric layer, and an etch dielectric layer formed on the stop layer; The etching medium layer and the stop layer are patterned to form a field plate opening, while the stop layer undergoes lateral etching at the bottom edge of the field plate opening, resulting in a lateral void between the etching medium layer and the intermediate medium layer. The sidewalls and bottom of the field plate openings are formed by depositing sidewall material, and the sidewall layer is filled with the lateral voids. Metal field plate material is deposited on the sidewall layer to form a metal field plate.

[0010] Preferably, the sidewall material is deposited using chemical vapor deposition or atomic layer deposition in the step of “forming a sidewall layer covering the opening of the field plate and filling the lateral voids by depositing sidewall material”.

[0011] Preferably, a portion of the sidewall layer fills the lateral void.

[0012] Preferably, the sidewall layer and the stop layer are made of the same material.

[0013] This application discloses a semiconductor device, which is manufactured by the method described in any one of the above embodiments.

[0014] This application discloses a semiconductor device, including... A semiconductor structure includes an intermediate dielectric layer, a stop layer formed on the intermediate dielectric layer, an etch dielectric layer formed on the stop layer, and a field plate opening penetrating the etch dielectric layer and the stop layer; the intermediate dielectric layer has a contact portion at the field plate opening that is not covered by the etch dielectric layer and the stop layer; a lateral void communicating with the field plate opening is formed between the etch dielectric layer and the intermediate dielectric layer. The sidewall layer includes a first sidewall portion formed on the sidewall of the opening in the field plate, a second sidewall portion formed on the contact portion, and a third sidewall portion extending from the second sidewall portion into the lateral cavity and filling the lateral cavity; A metal field plate, which is formed on the sidewall layer.

[0015] Preferably, the third sidewall portion fills the lateral cavity.

[0016] Preferably, the sidewall layer includes a fourth sidewall portion formed on the etching medium layer, the fourth sidewall portion being connected to the third sidewall portion; the metal field plate includes a first field plate portion formed on the fourth sidewall portion, a second field plate portion formed on the second sidewall portion, and a third field plate portion formed on the third sidewall portion.

[0017] Preferably, the sidewall layer and the stop layer are made of the same material.

[0018] The beneficial effects of this application, based on the above technical solutions, are as follows: 1. Eliminate voids in the lateral corrosion zone of the stop layer to remove potential defects; 2. Eliminate voids in the sidewalls of the stop layer, enhance electric field control in void areas, and improve device reliability.

[0019] Specific embodiments of this application are disclosed in detail with reference to the following description and accompanying drawings, illustrating how the principles of this application can be employed. It should be understood that the embodiments of this application are not limited in scope. Within the spirit and scope of the appended claims, the embodiments of this application include many changes, modifications, and equivalents.

[0020] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0021] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components. Attached Figure Description

[0022] The accompanying drawings described herein are for illustrative purposes only and are not intended to limit the scope of this application in any way. Furthermore, the shapes and scales of the components in the drawings are merely illustrative to aid in understanding this application and do not specifically limit the shapes and scales of the components. Those skilled in the art, guided by the teachings of this application, can select various possible shapes and scales to implement this application according to specific circumstances. In the drawings: Figure 1 A schematic diagram of the semiconductor device is shown.

[0023] Figures 2A to 2C This paper illustrates a first method for fabricating a field plate in a semiconductor device in the prior art.

[0024] Figures 3A to 3D This illustrates a second method for fabricating a field plate in a semiconductor device in the prior art.

[0025] Figures 4A to 4E A method for fabricating a field plate for a semiconductor device according to an embodiment of this application is illustrated.

[0026] The reference numerals in the above figures are as follows: 1. Front layer structure; 10. Dielectric layer; 2. Intermediate dielectric layer; 3. Stop layer; 4. Etching dielectric layer; 5. Sidewall layer; 51. First sidewall portion; 52. Second sidewall portion; 53. Third sidewall portion; 54. Fourth sidewall portion; 6. Metal field plate; 61. First field plate portion; 62. Second field plate portion; 63. Third field plate portion; 7. Lateral void. Detailed Implementation

[0027] To enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this application.

[0028] It should be noted that when an element is referred to as being "set on" another element, it can be directly on the other element or there may be an intervening element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or there may be an intervening element. The terms "vertical," "horizontal," "left," "right," and similar expressions used herein are for illustrative purposes only and do not represent the only embodiments.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0030] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0031] It should be noted that in the description of this application, the terms "first," "second," etc., are used only for descriptive purposes and to distinguish similar objects; there is no order between them, nor should they be construed as indicating or implying relative importance. Furthermore, in the description of this application, unless otherwise stated, "multiple" means two or more.

[0032] This application discloses a method for fabricating a field plate for a semiconductor device, including the following steps: Reference Figure 4A As shown, a semiconductor structure is provided, the semiconductor structure including an intermediate dielectric layer 2, a stop layer 3 formed on the intermediate dielectric layer 2, and an etch dielectric layer 4 formed on the stop layer 3; Reference Figure 4B and Figure 4C As shown, the etching medium layer 4 and the stop layer 3 are graphically represented to form a field plate opening. At the same time, the stop layer 3 undergoes lateral etching at the bottom edge of the field plate opening, resulting in a lateral void 7 between the etching medium layer 4 and the intermediate medium layer 2. Reference Figure 4D As shown, a sidewall layer 5 is formed by depositing sidewall material to cover the sidewalls and bottom of the field plate opening and to fill the lateral voids 7; Reference Figure 4E As shown, a metal field plate 6 material is deposited on the sidewall layer 5 to form the metal field plate 6.

[0033] Specifically, in the step "providing a semiconductor structure, the semiconductor structure including an intermediate dielectric layer 2, a stop layer 3 formed on the intermediate dielectric layer 2, and an etching dielectric layer 4 formed on the stop layer 3", to Figure 1 In the case of the bottommost metal field plate 6, the intermediate dielectric layer 2 can be an in-situ SiN layer. The intermediate dielectric layer 2 forms a barrier layer (previous structure 1). A stop layer 3 is deposited on the in-situ SiN layer, and an etch dielectric layer 4 is deposited above the stop layer 3. Similar to existing technologies, there is a high etch selectivity between the etch dielectric layer 4 and the stop layer 3. Generally, the etch selectivity between the etch dielectric layer 4 and the stop layer 3 is greater than 10.

[0034] Of course, when fabricating the other layers of the metal field plate 6, the stop layer 3 can also be adapted to be SiN (silicon nitride). The intermediate dielectric layer 2 and the etching dielectric layer 4 can also be adapted to be SiO2. Alternatively, the stop layer 3 can also be adapted to be SiO2. The intermediate dielectric layer 2 and the etching dielectric layer 4 can also be adapted to be SiN. Alternatively, the stop layer 3 can also be adapted to be metallic AlN. The intermediate dielectric layer 2 and the etching dielectric layer 4 can also be adapted to be SiN / SiO2. Alternatively, the stop layer 3 can also be adapted to be SiC / SiN. The etching dielectric layer 4 can also be adapted to be a low-k dielectric material.

[0035] In the step "graphicalizing the etch medium layer 4 and the stop layer 3 to form a field plate opening, while the stop layer 3 undergoes lateral etching at the bottom edge of the field plate opening, resulting in a lateral void 7 between the etch medium layer 4 and the intermediate dielectric layer 2", the etch medium layer 4 and the stop layer 3 are graphically patterned. Similar to existing technologies, due to the high etching ratio selection, the process automatically stops on the surface of the stop layer 3, thereby obtaining a highly uniform field plate height. In other words, the thickness of the intermediate dielectric layer 2 determines the field plate height of the metal field plate 6.

[0036] Similar to the technology, inevitably, there is a certain degree of over-etching of the stop layer 3. That is, not only is the stop layer 3 inside the field plate opening etched, but also the stop layer 3 near the field plate opening is etched to a certain extent, resulting in the formation of lateral voids 7 between the etched medium layer 4 and the intermediate medium layer 2.

[0037] In the step "forming a sidewall layer 5 covering the sidewalls and bottom of the field plate opening by depositing sidewall material and filling the lateral voids 7", sidewall material is deposited on the surface of the etched dielectric layer 4 and inside the field plate opening using a spacer process (such as chemical vapor deposition or atomic layer deposition). During deposition, the sidewall layer 5 covers the sidewalls and bottom of the field plate opening (the portion of the intermediate dielectric layer 2 exposed above the field plate opening), and simultaneously fills the lateral voids 7. Similar to existing technologies, the sidewall layer 5 is made of at least one of silicon nitride, silicon dioxide, a low-k dielectric material, and a high-k dielectric material. Preferably, the material of the sidewall layer 5 is the same as the material of the stop layer 3.

[0038] After depositing the sidewall material, the sidewall material is anisotropically etched to remove a portion of the horizontal portion covering the upper surface of the etching medium layer 4, retaining its vertical portion to form a monolithic sidewall layer 5. The sidewall layer 5 includes a first sidewall portion 51 formed on the sidewall of the field plate opening, a second sidewall portion 52 formed at the bottom of the field plate opening, a third sidewall portion 53 extending from the second sidewall portion 52 into the lateral cavity 7 and filling the lateral cavity 7, and a fourth sidewall portion 54 formed on the etching medium layer 4. The fourth sidewall portion 54 is connected to the first sidewall portion 51. The first sidewall portion 51 is connected to the second sidewall portion 52. The second sidewall portion 52 and the third sidewall portion 53 are connected.

[0039] In the step "depositing metal field plate 6 material on the sidewall layer 5 to form metal field plate 6", the metal field plate 6 is also a monolithic structure after deposition and etching. The metal field plate 6 includes a first field plate portion 61, a second field plate portion 62 connected to the first field plate portion 61, and a third field plate portion 63 connected to the second field plate portion 62. The first field plate portion 61 is also horizontal and is formed on the fourth sidewall portion 54 of the sidewall layer 5. The second field plate portion 62 is also inclined and is formed on the first sidewall portion 51 of the sidewall layer 5. The third field plate portion 63 is horizontal and is formed on the third sidewall of the sidewall layer 5.

[0040] Based on the above method, the lateral void 7 can be completely filled by the sidewall layer 5, thereby eliminating potential defects. At the same time, it enhances the electric field control of the void region, improves device reliability, and overcomes the electric field inhomogeneity caused by the non-uniform dielectric constant below the metal field plate 6 due to the presence of the lateral void 7 in the prior art.

[0041] Furthermore, this method can further etch the stop layer 3 cleanly, break the connection of the entire stop layer 3, and reduce leakage current, especially for cases where the stop layer 3 has a certain polarization charge.

[0042] Reference Figure 4E As shown in the embodiments, this application also discloses a semiconductor device, including: A semiconductor structure includes an intermediate dielectric layer 2, a stop layer 3 formed on the intermediate dielectric layer 2, an etch dielectric layer 4 formed on the stop layer 3, and a field plate opening penetrating the etch dielectric layer 4 and the stop layer 3; the intermediate dielectric layer 2 has a contact portion at the field plate opening that is not covered by the etch dielectric layer 4 and the stop layer 3; a lateral cavity 7 communicating with the field plate opening is formed between the etch dielectric layer 4 and the intermediate dielectric layer 2. The sidewall layer 5 includes a first sidewall portion 51 formed on the sidewall of the opening of the field plate, a second sidewall portion 52 formed on the contact portion, and a third sidewall portion 53 extending from the second sidewall portion 52 into the lateral cavity 7 and filling the lateral cavity 7. Metal field plate 6 is formed on the sidewall layer 5.

[0043] Preferably, the third sidewall portion 53 fills the lateral cavity 7. Correspondingly, the sidewall layer 5 includes a fourth sidewall portion 54 formed on the etching medium layer 4, the fourth sidewall portion 54 being connected to the third sidewall portion 53; the metal field plate 6 includes a first field plate portion 61 formed on the fourth sidewall portion 54, a second field plate portion 62 formed on the second sidewall portion 52, and a third field plate portion 63 formed on the third sidewall portion 53. The second field plate portion 62 and the third field plate portion 63 are generally located within the field plate opening.

[0044] It should be understood that the above description is for illustrative purposes and not for limitation. Many embodiments and applications beyond the provided examples will be apparent to those skilled in the art upon reading the above description. Therefore, the scope of this teaching should not be determined by reference to the above description, but rather by reference to the foregoing claims and the full scope of their equivalents. For purposes of completeness, all articles and references, including patent applications and publications, are incorporated herein by reference. The omission of any aspect of the subject matter disclosed herein in the foregoing claims is not intended as a waiver of that subject matter, nor should it be construed as an indication that the applicant has not considered that subject matter as part of the disclosed application subject matter.

Claims

1. A method for fabricating a field plate for a semiconductor device, characterized in that, Includes the following steps: A semiconductor structure is provided, the semiconductor structure including an intermediate dielectric layer, a stop layer formed on the intermediate dielectric layer, and an etch dielectric layer formed on the stop layer; The etching medium layer and the stop layer are patterned to form a field plate opening, while the stop layer undergoes lateral etching at the bottom edge of the field plate opening, resulting in a lateral void between the etching medium layer and the intermediate medium layer. The sidewalls and bottom of the field plate openings are formed by depositing sidewall material, and the sidewall layer is filled with the lateral voids. Metal field plate material is deposited on the sidewall layer to form a metal field plate.

2. The method for manufacturing a test plate according to claim 1, characterized in that, In the step "forming a sidewall layer that covers the opening of the field plate and the bottom by depositing sidewall material and filling the lateral voids", the sidewall material is deposited using chemical vapor deposition or atomic layer deposition processes.

3. The method for manufacturing a test plate according to claim 1, characterized in that, Part of the sidewall layer fills the lateral void.

4. The method for manufacturing a test plate according to claim 1, characterized in that, The sidewall material and the stop layer are made of the same material.

5. A semiconductor device, characterized in that, The device is manufactured by the method described in any one of claims 1 to 4.

6. A semiconductor device, characterized in that, include A semiconductor structure includes an intermediate dielectric layer, a stop layer formed on the intermediate dielectric layer, an etch dielectric layer formed on the stop layer, and a field plate opening penetrating the etch dielectric layer and the stop layer; the intermediate dielectric layer has a contact portion at the field plate opening that is not covered by the etch dielectric layer and the stop layer; a lateral void communicating with the field plate opening is formed between the etch dielectric layer and the intermediate dielectric layer. The sidewall layer includes a first sidewall portion formed on the sidewall of the opening in the field plate, a second sidewall portion formed on the contact portion, and a third sidewall portion extending from the second sidewall portion into the lateral cavity and filling the lateral cavity; A metal field plate, which is formed on the sidewall layer.

7. The semiconductor device according to claim 6, characterized in that, The third side wall portion fills the lateral cavity.

8. The semiconductor device according to claim 6, characterized in that, The sidewall layer includes a fourth sidewall portion formed on the etching medium layer, the fourth sidewall portion being connected to the third sidewall portion; the metal field plate includes a first field plate portion formed on the fourth sidewall portion, a second field plate portion formed on the second sidewall portion, and a third field plate portion formed on the third sidewall portion.

9. The semiconductor device according to claim 6, characterized in that, The sidewall layer and the stop layer are made of the same material.

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