Semiconductor device
By employing a first base region and a second base region configuration in a semiconductor device, the base region density is increased and an ohmic contact is formed, thus solving the current conduction problem caused by parasitic inductance, avoiding an increase in device size, and improving current conduction capability.
Patent Information
- Application Number
- CN202411091490.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-09
- Publication Date
- 2026-02-13
AI Technical Summary
In semiconductor devices, adding a base region to conduct away the current caused by parasitic inductance leads to an increase in device size and affects chip size.
By employing a configuration of a first base region and a second base region, the unit density of the base region is increased without increasing the device volume, and an internal PN diode is formed with the source pad through an ohmic contact to conduct current.
It effectively diverts current caused by parasitic inductance, preventing damage to semiconductor devices without increasing device size, and ensuring current conduction capability in critical areas.
Smart Images
Figure CN121531773A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present disclosure relates to a semiconductor device. BACKGROUND
[0002] In the field of semiconductor, P+ doped base regions can usually play the role of internal diodes, which can lead away the current caused by parasitic inductances, avoiding damage to the semiconductor device.
[0003] Because of the properties of the base regions, it is more desirable to have more base regions in some critical regions. However, this means that the size of the device may increase due to the increase in the number of base regions, thereby affecting the size of the wafer. SUMMARY
[0004] A technical aspect of the present disclosure is a semiconductor device.
[0005] According to an embodiment of the present disclosure, a semiconductor device includes a substrate, a gate structure, a well region, a first base region, and a second base region. The gate structure is on the substrate. The well region is in the substrate, wherein the well region at least partially overlaps the gate structure in a vertical direction. The first base region is in the substrate and is on a side of the well region, wherein the first base region does not overlap the gate structure in the vertical direction. The second base region is in the substrate and is on a side of the first base region away from the gate structure.
[0006] In an embodiment of the present disclosure, the semiconductor device further includes a source. The source is in the well region, wherein the source does not overlap the first base region in the vertical direction.
[0007] In an embodiment of the present disclosure, the semiconductor device further includes a source pad. The source pad is on the first base region and the second base region.
[0008] In an embodiment of the present disclosure, the source pad has a protrusion, the protrusion covering the second base region.
[0009] In an embodiment of the present disclosure, the source pad forms an ohmic contact with the first base region and the second base region.
[0010] In an embodiment of the present disclosure, the second base region is adjacent to a side of the first base region in a horizontal direction.
[0011] In an embodiment of the present disclosure, the gate structure includes a gate conductive layer, a gate dielectric layer, and an interlayer dielectric layer. The gate dielectric layer is between the gate conductive layer and the substrate. The interlayer dielectric layer covers the gate conductive layer and the gate dielectric layer.
[0012] In one embodiment of this disclosure, the sidewalls of the gate conductive layer and the sidewalls of the gate dielectric layer overlap in the vertical direction.
[0013] In one embodiment of this disclosure, the semiconductor device further includes a junction field-effect transistor region. The junction field-effect transistor region is located within the substrate and under the gate structure.
[0014] In one embodiment of this disclosure, the semiconductor device further includes a drift region. The drift region is located within a substrate, wherein the drift region is located beneath the gate structure, the well region, the first base region, and the second base region.
[0015] In the embodiments disclosed above, since the semiconductor device includes a first base region and a second base region, the unit density of the base region is increased without increasing the volume of the semiconductor device, thereby affecting the size of the wafer. Furthermore, through this configuration, current caused by parasitic inductance can be diverted in critical areas, preventing damage to the semiconductor device. Attached Figure Description
[0016] When accompanied by Figure One When reading this document, the best understanding of its contents can be obtained from the embodiments described below. Note that, according to standard industry practice, the various features are not drawn to scale. In fact, the dimensions of the various features can be increased or decreased arbitrarily for clarity of explanation.
[0017] Figure 1 A top view is shown for illustrating a semiconductor device according to an embodiment of this disclosure.
[0018] Figure 2 For illustration Figure 1 A cross-sectional view of the semiconductor device along line segment AA.
[0019] Figure 3 and Figure 4 For illustration Figure 1 A cross-sectional view of a semiconductor device during the manufacturing process. Detailed Implementation
[0020] The following description of embodiments provides numerous different implementations, or examples, for carrying out various features of the provided object. Specific examples of elements and arrangements are described below to simplify the subject matter. Of course, these examples are merely illustrative and are not intended to be limiting. Furthermore, element symbols and / or letters may be repeated in various examples. This repetition is for simplicity and clarity purposes and does not in itself specify the relationship between the various embodiments and / or configurations discussed.
[0021] Spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
[0022] As used herein, "about", "approximately", or "substantially" include the stated value and the average value within an acceptable range of deviation determined by one of ordinary skill in the art to be within the scope of what is claimed in view of the specific quantity being measured and the error associated with measuring that quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ± 30%, ± 20%, ± 10%, ± 5%. Further, as used herein, "about", "approximately", or "substantially" can select a more acceptable range of deviation or standard deviation for optical properties, etching properties, or other properties, and can not apply one standard deviation to all properties.
[0023] Figure 1 FIG. 1 is a top view of a semiconductor device 100 according to an embodiment of the present disclosure. Figure 2 FIG. 2 is a cross-sectional view of the semiconductor device 100 along line A-A of FIG. 1. Figure 1 FIG. 3 is a cross-sectional view of the semiconductor device 100 along line A-A of FIG. 1. Figure 1 FIG. 4 is a cross-sectional view of the semiconductor device 100 along line A-A of FIG. 1. Figure 2 Referring to FIGS. 1-4, the semiconductor device 100 includes a substrate 110, a gate structure 120, a well region 150, a first base region 130, and a second base region 140. The gate structure 120 is located on the substrate 110. In some embodiments, the substrate 110 can be silicon carbide and can be doped (e.g., N+ type doped), although the present disclosure is not limited thereto. The well region 150 is located within the substrate 110, where the well region 150 at least partially overlaps the gate structure 120 in a vertical direction V. For example, in the present embodiment, the well region 150 overlaps the gate structure 120 in the vertical direction V. In some embodiments, the well region 150 can be doped opposite to the electrical property of the substrate 110 (e.g., P- type doped), although the present disclosure is not limited thereto. The first base region 130 is located within the substrate 110 and located on a side of the well region 150, where the first base region 130 does not overlap the gate structure 120 in the vertical direction V. The second base region 140 is located within the substrate 110 and located on a side of the first base region 130 away from the gate structure 120. That is, the second base region 140 does not overlap the gate structure 120 in the vertical direction V. In some embodiments, the first base region 130 and the second base region 140 can be P+ type doped, although the present disclosure is not limited thereto.
[0024] Since the semiconductor device 100 includes a first base region 130 and a second base region 140, the unit density of the base region is increased without increasing the volume of the semiconductor device 100, thereby affecting the size of the chip. In addition, through the above configuration, the current caused by parasitic inductance can be conducted away in critical areas, avoiding damage to the semiconductor device 100.
[0025] Continue to refer to Figure 1 and Figure 2 The semiconductor device 100 further includes a source 160. The source 160 is located within the well region 150, wherein the source 160 does not overlap with the first base region 130 in the vertical direction V. Furthermore, the semiconductor device 100 also includes a source pad 170. The source pad 170 is located on the uppermost layer and covers... Figure 1 For clarity, the other layers, Figure 1 To illustrate Figure 1 The structure below the source pad 170. The source pad 170 is located on the first base region 130 and the second base region 140. That is, the source pad 170 is located on the substrate 110 and spans the gate structure 120. In some embodiments, the source pad 170 has an outwardly extending protrusion 172. The protrusion 172 of the source pad 170 is located on... Figure 1 The left and right sides surround the second base region 140, and the protrusion 172 covers the second base region 140. In this way, the second base region 140 is located on the side of the first base region 130 away from the gate structure 120, and the source pad 170 can be connected to the second base region 140 through the protrusion 172. Furthermore, the source pad 170 forms an ohmic contact with both the first base region 130 and the second base region 140. In some embodiments, the material of the source pad 170 may include titanium (Ti), cobalt (Co), nickel (Ni), copper (Cu), tungsten (W), molybdenum (Mo), or combinations thereof.
[0026] When a large current suddenly flows into the semiconductor device 100, the first base region 130 and the second base region 140, which form an ohmic contact with the source pad 170, utilize their internal PN diode properties to help conduct away the excessive current. Due to the increased density of the first base region 130 and the second base region 140, the instantaneous current that can be conducted away is also greater.
[0027] Furthermore, in this embodiment, the second base region 140 is located on the side (outer side) adjacent to the first base region 130 in the horizontal direction H. However, this disclosure is not limited to this. As long as the second base region 140 is positioned on the side of the first base region 130 away from the gate structure 120, its arrangement is unrestricted. This configuration avoids the phenomenon that the second base region 140 overlaps with the gate structure 120, making alignment difficult in the photolithography process and thus damaging the entire semiconductor device 100.
[0028] In some embodiments, the gate structure 120 includes a gate conductive layer 122, a gate dielectric layer 124, and an interlayer dielectric layer 126. The gate dielectric layer 124 is between the gate conductive layer 122 and the substrate 110. The interlayer dielectric layer 126 covers the gate conductive layer 122 and the gate dielectric layer 124. That is, the gate conductive layer 122 is on the gate dielectric layer 124, which is on the substrate 110. In addition, the sidewall of the gate conductive layer 122 overlaps the sidewall of the gate dielectric layer 124 in the vertical direction V. This is because the gate conductive layer 122 and the gate dielectric layer 124 are patterned together in the process, so the sidewall of the gate conductive layer 122 overlaps the sidewall of the gate dielectric layer 124 in the vertical direction V. In some embodiments, the material of the gate conductive layer 122 is metal or polysilicon or other suitable material. The material of the gate dielectric layer 124 is silicon dioxide or other suitable material. The material of the interlayer dielectric layer 126 includes phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), undoped silicate glass (USG), silicon oxycarbide (SiOxCy), spin-on glass (SOG), spin-on polymers, carbon-doped silicon material, combinations thereof, or similar materials. The interlayer dielectric layer 126 can be formed by a spin-on coating method, a chemical vapor deposition method, or similar methods.
[0029] In some embodiments, the semiconductor device 100 also includes a junction field effect transistor region 180. The junction field effect transistor region 180 is in the substrate 110 and under the gate structure 120. In some embodiments, the width of the junction field effect transistor region 180 is less than the width of the gate structure 120. In the present embodiment, the junction field effect transistor region 180, the well region 150, and the first base region 130 have substantially the same depth in the substrate 110. In the present embodiment, the area of the well region 150 exposed to the gate structure 120 is used as the channel region 152 when the semiconductor device 100 is in operation.
[0030] In some embodiments, the semiconductor device 100 further includes a drift region 190. The drift region 190 is located within the substrate 110, specifically beneath the gate structure 120, well region 150, first base region 130, second base region 140, and junction field-effect transistor region 180. In some embodiments, the doping of the drift region 190 may be the same electrical type as the substrate 110 (e.g., N-type doping), but this disclosure is not limited thereto. Furthermore, the semiconductor device 100 also includes a drain pad 192 located on the surface of the substrate 110 opposite to the drift region 190. In some embodiments, the drain pad 192 is made of a metal or other suitable material, but this disclosure is not limited thereto.
[0031] Figure 3 and Figure 4 For illustration Figure 1 A cross-sectional view of the semiconductor device 100 during the manufacturing process. (Refer to...) Figure 3 First, a well region 150, a source region 160, a first base region 130, and a second base region 140 (not shown) are formed in the substrate by doping. Since the doping properties of each region are different (e.g., the well region is a P-type region and the source region is an N+ type region), the desired doping sites are exposed using photolithography, followed by high-temperature diffusion doping, ion implantation, or any suitable method to implant the dopant. Afterwards, the gate structure 120 (see reference) is formed. Figure 1 The junction field-effect transistor region 180 is formed below the junction.
[0032] Reference Figure 4 Next, a gate structure 120 is formed. The formation of the gate structure 120 includes forming a dielectric layer on the substrate 110; forming a conductive layer on the dielectric layer; patterning the dielectric layer and the conductive layer to form a gate conductive layer 122 and a gate dielectric layer 124; and finally covering the gate conductive layer 122 and the gate dielectric layer 124 (and the entire substrate 110) with an interlayer dielectric layer 126. Then, an opening is cut out in the interlayer dielectric layer 126, and metal is filled into the opening to form a source pad 170.
[0033] Reference Figure 2 After the source pad 170 is formed and forms an ohmic contact with the first base region 130 and the second base region 140, the drain pad 192 is formed on the surface of the substrate 110 on the other side opposite to the drift region 190. In this way, the semiconductor device 100 is manufactured.
[0034] The foregoing summary of features of several embodiments enables a person skilled in the art to better understand the aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same objectives and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications here without departing from the spirit and scope of the present disclosure.
[0035] SYMBOL DESCRIPTION
[0036] 100: semiconductor device
[0037] 110: substrate
[0038] 120: gate structure
[0039] 122: gate conductive layer
[0040] 124: gate dielectric layer
[0041] 126: interlayer dielectric layer
[0042] 130: first base region
[0043] 140: second base region
[0044] 150: well region
[0045] 152: channel region
[0046] 160: source
[0047] 170: source pad
[0048] 172: bump
[0049] 180: junction field effect transistor region
[0050] 190: drift region
[0051] 192: drain pad
[0052] A-A: line segment
[0053] H: horizontal direction
[0054] V: vertical direction
Claims
1. A semiconductor device, characterized in that, Include: substrate; The gate structure is located on the substrate; A well region is located within the substrate, wherein the well region at least partially overlaps with the gate structure in the vertical direction; A first base region is located within the substrate and on one side of the well region, wherein the first base region does not overlap with the gate structure in the vertical direction; as well as The second base region is located within the substrate and on the side of the first base region away from the gate structure.
2. The semiconductor device according to claim 1, characterized in that, Also includes: The source electrode is located within the well region, wherein the source electrode does not overlap with the first base electrode region in the vertical direction.
3. The semiconductor device according to claim 1, characterized in that, Also includes: The source pad is located on the first base region and the second base region.
4. The semiconductor device according to claim 3, characterized in that, The source pad has a protrusion that covers the second base region.
5. The semiconductor device according to claim 3, characterized in that, The source pad forms an ohmic contact with the first base region and the second base region.
6. The semiconductor device according to claim 1, characterized in that, The second base region is located on the side adjacent to the first base region in the horizontal direction.
7. The semiconductor device according to claim 1, characterized in that, The gate structure includes: Gate conductive layer; A gate dielectric layer is located between the gate conductive layer and the substrate; and An interlayer dielectric layer covers the gate conductive layer and the gate dielectric layer.
8. The semiconductor device according to claim 7, characterized in that, The sidewalls of the gate conductive layer overlap with the sidewalls of the gate dielectric layer in the vertical direction.
9. The semiconductor device according to claim 1, characterized in that, Also includes: The junction field-effect transistor region is located within the substrate and under the gate structure.
10. The semiconductor device according to claim 1, characterized in that, Also includes: A drift region is located within the substrate, wherein the drift region is located below the gate structure, the well region, the first base region, and the second base region.