A silicon carbide-gallium nitride hetero-integrated high voltage power device structure

Abstract

The application relates to the technical field of gallium nitride transistors, and discloses a silicon carbide-gallium nitride hetero-integrated high-voltage power device structure, which comprises a silicon carbide device composed of a plurality of parallel MOS cells and a gallium nitride device composed of two GaN structures, wherein the gallium nitride device is located on the back surface of the silicon carbide device; a single MOS cell comprises a semiconductor epitaxial layer, an MOS source, an MOS gate and an MOS dielectric layer covering the surface of the MOS gate; wherein the semiconductor epitaxial layer comprises an N substrate layer and an N diffusion layer from top to bottom. The application combines the lateral high electron mobility characteristics of a GaN HEMT and the longitudinal voltage resistance advantage of a SiC MOSFET, realizes the cooperative work of two wide-bandgap semiconductors on a single substrate, effectively utilizes the excellent heat conduction and voltage resistance performance of the SiC substrate as a common carrier, and through the series voltage resistance design at the device level, the overall breakdown voltage is significantly improved.

Description

Technical Field

[0001] This invention relates to the field of gallium nitride transistor technology, and more particularly to a silicon carbide-gallium nitride heterogeneous integrated high-voltage power device structure. Background Technology

[0002] With the development of microelectronics technology, gallium nitride high electron mobility transistors (HEMTs), as representatives of power semiconductor devices, have enormous market potential in high-frequency applications. GaN, a wide-bandgap semiconductor material, possesses an ultra-high critical breakdown electric field, nearly 10 times higher than that of silicon (Si), and the heterojunction composed of AlGaN and GaN exhibits a strong two-dimensional electron gas. Therefore, under the same voltage withstand conditions, GaN power devices have an on-resistance nearly three orders of magnitude lower than Si devices, significantly reducing chip area and the weight of the drive circuit. Furthermore, gallium nitride (GaN) material has excellent thermal conductivity, making it highly valuable for applications in high-temperature power electronic devices. In the future, GaN-based power electronics are highly likely to become a replacement for Si-based power devices and play a crucial role in emerging industries such as smart grids, hybrid vehicles, aerospace, and high-speed rail.

[0003] However, existing GaN HEMTs are two-dimensional devices. As the breakdown voltage increases, the area also increases, and the defects also increase with the area, leading to a significant decrease in device reliability. Therefore, despite its many advantages, GaN HEMTs still cannot be well applied in high-voltage fields.

[0004] Compared to GaN HEMTs, SiC MOSFET devices primarily utilize vertical breakdown voltage, effectively avoiding the lateral breakdown voltage limitations of GaN HEMTs. Furthermore, silicon carbide boasts significantly superior thermal conductivity, high-frequency performance, and low resistance compared to silicon. Therefore, replacing the GaN HEMT substrate with silicon carbide and employing specialized structural design can lead to a major breakthrough in the breakdown voltage capabilities of power devices.

[0005] Existing patent CN115832040A discloses a silicon carbide-based gallium nitride device and its fabrication method. However, the breakdown voltage of existing silicon carbide-based GaN HEMT devices under high voltage is still limited by the lateral breakdown voltage capability of the two-dimensional electron gas, and there are issues with the increase in area and defects associated with improving the breakdown voltage of a single device. Summary of the Invention

[0006] This invention provides a silicon carbide-gallium nitride heterogeneous integrated high-voltage power device structure to solve existing technical problems, thereby addressing the inherent issues of increased area and decreased reliability of traditional GaN devices under high voltage.

[0007] To solve the above-mentioned technical problems, according to one aspect of the present invention, more specifically, a silicon carbide-gallium nitride heterogeneous integrated high-voltage power device structure, comprising a silicon carbide device composed of a plurality of parallel MOS cells, and a gallium nitride device composed of two GaN structures, wherein the gallium nitride device is located on the back side of the silicon carbide device.

[0008] Each MOS cell includes a semiconductor epitaxial layer, a MOS source, a MOS gate, and a MOS dielectric layer covering the surface of the MOS gate;

[0009] The semiconductor epitaxial layer includes an N substrate layer and an N diffusion layer from top to bottom; a P well layer is formed inside the N diffusion layer and between two adjacent MOS cells by ion implantation, and two non-contact N well layers are formed inside each P well layer by ion implantation.

[0010] A single GaN structure, from bottom to top, includes a buffer layer, a GaN channel layer, an AlGaN barrier layer, a cover dielectric layer, and a GaN gate;

[0011] In this configuration, two independent barrier dielectric layers are deposited between two adjacent GaN structures, and the two barrier dielectric layers are in direct contact with the buffer layer and GaN channel layer on the two GaN structures, respectively.

[0012] A GaN source electrode is deposited between two adjacent GaN structures; a GaN drain electrode is deposited on a single GaN structure on the side furthest from the GaN source electrode.

[0013] Furthermore, the P-well layer is in ohmic contact with the MOS source, and the two non-contacting N-well layers are both in ohmic contact with the MOS source.

[0014] Furthermore, the side of the GaN source is in ohmic contact with the GaN channel layer and the AlGaN barrier layer; the bottom of the GaN source is in ohmic contact with the N substrate layer.

[0015] Furthermore, the GaN gates on the two GaN structures are independent of each other, and the GaN gates are located near the GaN source.

[0016] Furthermore, the GaN source electrodes on two adjacent GaN structures are integrated into one unit.

[0017] Furthermore, the GaN source comprises two independent sources that are not in contact with each other, and the two independent sources are respectively in ohmic contact with the GaN channel layer and the AlGaN barrier layer on the two GaN structures.

[0018] Furthermore, a second P-well layer is formed inside the N-substrate layer and between the two GaN structures by ion implantation.

[0019] Furthermore, the covering dielectric layer includes a through dielectric layer, the other end of which extends through and between the two independent source electrodes and is in direct contact with the N substrate layer.

[0020] Furthermore, the GaN gate includes a T-shaped gate, with two adjacent T-shaped gates on the GaN structure being integral, and the cross-sectional profile of the T-shaped gate is in the shape of a "T".

[0021] The horizontal portion of the T-shaped gate "T" is located above the dielectric layer, and the vertical portion of the T-shaped gate "T" extends through and to the second surface of the P-well layer.

[0022] The present invention provides a silicon carbide-gallium nitride heterogeneous integrated high-voltage power device structure. Compared with the prior art, the advantages achieved by this method are as follows:

[0023] 1. This invention combines the high lateral electron mobility of GaN HEMT with the longitudinal breakdown voltage advantage of SiC MOSFET, achieving the synergistic operation of two wide bandgap semiconductors on a single substrate. This structure effectively utilizes the excellent thermal conductivity and breakdown voltage properties of the SiC substrate as a common carrier. At the same time, through device-level series breakdown voltage design, the overall breakdown voltage is significantly improved, overcoming the inherent limitations of traditional GaN devices that increase area and decrease reliability under high voltage. This provides a compact and efficient solution for high-voltage and high-frequency power applications.

[0024] 2. This invention achieves automatic stabilization of the GaN gate potential without the need for external clamping components through an integrated potential self-clamping structure. Specifically, by introducing an internal PN junction formed by the P-well layer and the N-substrate layer, combined with an integrated design that penetrates the dielectric layer and the T-shaped gate, the gate potential can float synchronously with the source potential. This ensures reliable cutoff of the GaN HEMT during device shutdown and avoids gate overvoltage damage. This not only enhances the safety and reliability of the device under high-voltage blocking but also simplifies the peripheral circuitry and packaging process.

[0025] 3. This invention significantly improves the chip's power density by placing GaN devices on the back side of the SiC MOSFET and achieving electrical interconnection and thermal management through a shared N-substrate layer and N-diffusion layer. This design, combining vertical stacking and lateral arraying, achieves higher current handling capability and a better thermal diffusion path within a limited area, helping to reduce on-resistance and improve overall energy efficiency.

[0026] 4. The present invention ultimately presents a standardized device with only three external electrodes: gate, drain, and source, fully compatible with the pin definitions of mainstream power MOSFETs. This allows this high-performance heterogeneous integrated device to directly replace existing silicon-based or single wide-bandgap devices without changing the drive circuit or system design, greatly reducing the barriers and costs of technology upgrades in high-voltage applications such as power conversion and motor drives, and accelerating the popularization and application of wide-bandgap semiconductor technology in high-end power fields. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the structure in Embodiment 1 of the present invention;

[0028] Figure 2 This is a schematic diagram of the structure in Embodiment 2 of the present invention;

[0029] Figure 3 This is a structural relationship diagram of Embodiment 1 of the present invention.

[0030] In the figure: 1. MOS cell; 2. GaN structure; 101. MOS source; 102. MOS gate; 103. MOS dielectric layer; 104. P-well layer one; 105. N-well layer; 106. N-diffusion layer; 107. N-substrate layer; 201. Buffer layer; 202. GaN channel layer; 203. GaN drain; 204. AlGaN barrier layer; 205. GaN gate; 206. GaN source; 207. Cover dielectric layer; 208. Barrier dielectric layer; 209. P-well layer two; 2051. T-shaped gate; 2061. Independent source; 2071. Through dielectric layer. Detailed Implementation

[0031] To make the technical solution of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0032] Example 1

[0033] like Figure 1 , Figure 3As shown, a silicon carbide-gallium nitride heterogeneous integrated high-voltage power device structure includes a silicon carbide device composed of several parallel MOS cells 1 and a gallium nitride device composed of two GaN structures 2, wherein the gallium nitride device is located on the back side of the silicon carbide device; a single MOS cell 1 includes a semiconductor epitaxial layer, a MOS source 101, a MOS gate 102, and a MOS dielectric layer 103 covering the surface of the MOS gate 102; wherein the semiconductor epitaxial layer includes an N substrate layer 107 and an N diffusion layer 106 from top to bottom; a P-well layer 104 is formed inside the N diffusion layer 106 and between two adjacent MOS cells 1 by ion implantation, and a single P-well layer 104... The interior of GaN structure 04 is formed by ion implantation to form two non-contact N-well layers 105. A single GaN structure 2 includes, from bottom to top, a buffer layer 201, a GaN channel layer 202, an AlGaN barrier layer 204, a cover dielectric layer 207, and a GaN gate 205. Two independent barrier dielectric layers 208 are deposited between two adjacent GaN structures 2, and the two barrier dielectric layers 208 are in direct contact with the buffer layer 201 and the GaN channel layer 202 on the two GaN structures 2, respectively. A GaN source 206 is also deposited between two adjacent GaN structures 2. A GaN drain 203 is deposited on the single GaN structure 2 on the side away from the GaN source 206.

[0034] The P-well layer 104 has an ohm contact with the MOS source 101, and both non-contacting N-well layers 105 have an ohm contact with the MOS source 101. The side of the GaN source 206 has an ohm contact with the GaN channel layer 202 and the AlGaN barrier layer 204; the bottom of the GaN source 206 has an ohm contact with the N-substrate layer 107. The GaN gates 205 on the two GaN structures 2 are independent of each other, and the GaN gates 205 are located close to the GaN source 206. The GaN sources 206 on two adjacent GaN structures 2 are integrated.

[0035] In this embodiment, the substrate of GaN structure 2 is replaced with silicon carbide N substrate layer 107 and N diffusion layer 107, and silicon carbide MOSFET device (MOSFET device composed of several MOS cells 1) is fabricated on silicon carbide N diffusion layer 107, which makes reasonable and full use of the device's lateral and vertical space.

[0036] The drain of the MOSFET device and the source of the GaN structure 2 are combined into electrode S1 (GaN source 206). The overall withstand voltage is increased by connecting the two voltage-resistant devices in series.

[0037] Furthermore, the GaN HEMT used is a depletion-mode device structure, and four electrodes will be brought out during device packaging: GaN drain 203, GaN gate 205, MOS gate 102, and MOS source 101.

[0038] During the packaging process, a clamping diode can be used to clamp the voltage between the G1 electrode (GaN gate 205) and the S1 electrode (GaN source 206), so that when the device is in the blocking state, the GaN HEMT can be turned off precisely without the G1 electrode (GaN gate 205) being damaged due to the huge voltage. At the same time, the pins of the packaged device become the normal G (MOS gate 102), D (GaN drain 203), and S (MOS source 101).

[0039] In this embodiment, the structure replaces the GaN HEMT substrate with a silicon carbide N-substrate layer 107 and N-diffusion layer 106, and integrates multiple MOS cells 1 on its surface to form a SiC MOSFET device, achieving heterogeneous integration of SiC's vertical breakdown voltage and GaN's high lateral electron mobility. Its core innovation lies in merging the MOSFET's drain function into the GaN source 206, forming a series breakdown voltage structure. Through an external clamping circuit between the GaN gate 205 and the GaN source 206, reliable turn-off of the GaN device is achieved in the blocking state, thereby significantly improving the overall breakdown voltage capability. Furthermore, only three electrodes—G (MOS gate 102), D (GaN drain 203), and S (MOS source 101)—are externally connected, simplifying packaging and application.

[0040] Example 2

[0041] like Figure 2 As shown, a silicon carbide-gallium nitride heterogeneous integrated high-voltage power device structure includes a silicon carbide device composed of several parallel MOS cells 1 and a gallium nitride device composed of two GaN structures 2, wherein the gallium nitride device is located on the back side of the silicon carbide device; a single MOS cell 1 includes a semiconductor epitaxial layer, a MOS source 101, a MOS gate 102, and a MOS dielectric layer 103 covering the surface of the MOS gate 102; wherein the semiconductor epitaxial layer includes an N substrate layer 107 and an N diffusion layer 106 from top to bottom; a P-well layer 104 is formed inside the N diffusion layer 106 and between two adjacent MOS cells 1 by ion implantation, and a single P-well layer 104... The interior of GaN structure 04 is formed by ion implantation to form two non-contact N-well layers 105. A single GaN structure 2 includes, from bottom to top, a buffer layer 201, a GaN channel layer 202, an AlGaN barrier layer 204, a cover dielectric layer 207, and a GaN gate 205. Two independent barrier dielectric layers 208 are deposited between two adjacent GaN structures 2, and the two barrier dielectric layers 208 are in direct contact with the buffer layer 201 and the GaN channel layer 202 on the two GaN structures 2, respectively. A GaN source 206 is also deposited between two adjacent GaN structures 2. A GaN drain 203 is deposited on the single GaN structure 2 on the side away from the GaN source 206.

[0042] P-well layer 104 is in ohmic contact with MOS source 101, and both non-contacting N-well layers 105 are in ohmic contact with MOS source 101. The side of GaN source 206 is in ohmic contact with GaN channel layer 202 and AlGaN barrier layer 204; the bottom of GaN source 206 is in ohmic contact with N-substrate layer 107. GaN source 206 includes two independent, non-contacting sources 2061, and each independent source 2061 is in ohmic contact with GaN channel layer 202 and AlGaN barrier layer 204 on the two GaN structures 2, respectively. A second P-well layer 209 is formed inside the N-substrate layer 107, located between the two GaN structures 2, through ion implantation. The covering dielectric layer 207 includes a through dielectric layer 2071, the other end of which extends through and between the two independent sources 2061, and is in direct contact with the N-substrate layer 107. The GaN gate 205 includes a T-shaped gate 2051. The T-shaped gates 2051 on two adjacent GaN structures 2 are integrated, and the cross-sectional profile of the T-shaped gate 2051 is in the shape of a "T". The lateral portion of the "T" shape of the T-shaped gate 2051 is located above the dielectric layer 2071, and the longitudinal portion of the "T" shape of the T-shaped gate 2051 extends through and extends to the surface of the P-well layer 209.

[0043] In this embodiment, a P-shaped impurity is implanted on the N substrate layer 107 to form a second P-well layer 209, thereby forming a pn junction with the N substrate layer 107 (the principle of this part is: after the pn junction is formed, the charge can only flow in one direction. If the potential of the independent source 2061 decreases, then the potential of the T-gate 2051 increases relatively). The implantation concentration and depth of the second P-well layer 209 can be determined by the designer. It is necessary to ensure that the potential of the S1 electrode (independent source 2061) is higher than that of the G1 electrode (T-gate 2015) so that when the device is blocked, the GaN HEMT can remain off, and not so high that the G1 electrode (T-gate 2015) and the S1 electrode (independent source 2061) break down.

[0044] This embodiment has three external electrodes as the electrodes of the entire structure, namely: Figure 2 The diagram shows three electrodes: G (MOS gate 102), D (GaN drain), and S (MOS source). The specific working principle is as follows:

[0045] When a voltage is applied to the G (MOS gate 102) terminal to turn on the device, the potential of the S1 terminal (independent source 2061) decreases, and the potential of the G1 terminal (T-gate 2051) is higher than the threshold voltage of the pn junction by one pn junction. The GaN HEMT device turns on, and the current flows from the D terminal (GaN drain) through the S1 terminal (independent source 2061) and finally to the S terminal (MOS source).

[0046] When the voltage at the gate (MOS gate 102) drops to 0, the MOSFET structure is partially turned off, and the potential at the source (independent source 2061) increases. When the potential difference between the source (independent source 2061) and the gate (T-shaped gate 2051) is higher than the pn junction blocking voltage, the potential at the gate (T-shaped gate 2051) begins to rise synchronously with that at the source (independent source 2061), and at the same time, the GaN HEMT structure begins to turn off under pressure.

[0047] In this embodiment, the substrate of GaN HEMT is replaced with silicon carbide N substrate layer 107 and N diffusion layer 107, and silicon carbide MOSFET device is fabricated on silicon carbide N diffusion layer 107, which makes reasonable and full use of the device's lateral and vertical space.

[0048] This embodiment further optimizes upon embodiment 1 by designing the GaN source 206 as two independent source 2061s, and implanting a second P-well layer 209 in the N-substrate layer 107. The dielectric layer 207 is improved to penetrate the dielectric layer 2071, and an integrated T-shaped gate 2051 extends to the surface of the second P-well layer 209. This combined structure achieves a potential self-clamping function: when the potential of the S1 electrode (independent source 2061) changes, the potential of the T-shaped gate 2051 is automatically adjusted through the PN junction formed by the second P-well layer 209 and the N-substrate layer 107. This ensures reliable turn-off of the GaN HEMT in the blocking state without the need for an external clamping circuit, while simultaneously optimizing the electric field distribution and further improving the high-voltage reliability and integration of the device.

[0049] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A silicon carbide-gallium nitride heterogeneous integrated high-voltage power device structure, characterized in that, It includes a silicon carbide device composed of several parallel MOS cells (1) and a gallium nitride device composed of two GaN structures (2), wherein the gallium nitride device is located on the back side of the silicon carbide device; Each MOS cell (1) includes a semiconductor epitaxial layer, a MOS source (101), a MOS gate (102), and a MOS dielectric layer (103) covering the surface of the MOS gate (102). The semiconductor epitaxial layer includes an N substrate layer (107) and an N diffusion layer (106) from top to bottom. A P well layer (104) is formed inside the N diffusion layer (106) and between two adjacent MOS cells (1) by ion implantation. Two non-contact N well layers (105) are formed inside each P well layer (104) by ion implantation. Each GaN structure (2) comprises, from bottom to top, a buffer layer (201), a GaN channel layer (202), an AlGaN barrier layer (204), a cover dielectric layer (207), and a GaN gate (205). Two independent barrier dielectric layers (208) are deposited between two adjacent GaN structures (2), and the two barrier dielectric layers (208) are in direct contact with the buffer layer (201) and the GaN channel layer (202) on the two GaN structures (2), respectively. A GaN source (206) is also deposited between two adjacent GaN structures (2); a GaN drain (203) is deposited on a single GaN structure (2) on the side away from the GaN source (206).

2. The silicon carbide-gallium nitride heterogeneous integrated high-voltage power device structure according to claim 1, characterized in that: The P-well layer (104) is in ohmic contact with the MOS source (101), and the two non-contacting N-well layers (105) are both in ohmic contact with the MOS source (101).

3. The silicon carbide-gallium nitride heterogeneous integrated high-voltage power device structure according to claim 1, characterized in that: The side of the GaN source (206) is in ohmic contact with the GaN channel layer (202) and the AlGaN barrier layer (204); the bottom of the GaN source (206) is in ohmic contact with the N substrate layer (107).

4. The silicon carbide-gallium nitride heterogeneous integrated high-voltage power device structure according to claim 3, characterized in that: The GaN gates (205) on the two GaN structures (2) are independent of each other, and the GaN gates (205) are located near the GaN source (206).

5. The silicon carbide-gallium nitride heterogeneous integrated high-voltage power device structure according to claim 4, characterized in that: The GaN source (206) on two adjacent GaN structures (2) are integrated into one unit.

6. The silicon carbide-gallium nitride heterogeneous integrated high-voltage power device structure according to claim 3, characterized in that: The GaN source (206) comprises two independent sources (2061) that do not contact each other, and the two independent sources (2061) are in ohmic contact with the GaN channel layer (202) and AlGaN barrier layer (204) on the two GaN structures (2), respectively.

7. The silicon carbide-gallium nitride heterogeneous integrated high-voltage power device structure according to claim 6, characterized in that: A second P-well layer (209) is formed inside the N substrate layer (107) and between the two GaN structures (2) by ion implantation.

8. The silicon carbide-gallium nitride heterogeneous integrated high-voltage power device structure according to claim 7, characterized in that: The covering dielectric layer (207) includes a through dielectric layer (2071), the other end of which extends through and between two independent source electrodes (2061) and is in direct contact with the N substrate layer (107).

9. The silicon carbide-gallium nitride heterogeneous integrated high-voltage power device structure according to claim 8, characterized in that: The GaN gate (205) includes a T-shaped gate (2051), and the T-shaped gates (2051) on two adjacent GaN structures (2) are integrated, and the cross-sectional profile of the T-shaped gate (2051) is in the shape of a "T". The lateral portion of the "T" shape of the T-shaped gate (2051) is located above the dielectric layer (2071), and the longitudinal portion of the "T" shape of the T-shaped gate (2051) extends through and to the surface of the second P-well layer (209).

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