Wafer level graphene-silicon three-terminal phototransistor and method of fabrication

Abstract

The application discloses a wafer-level graphene-silicon three-terminal phototransistor and a preparation method thereof. The emitter stage of the transistor is a silicon substrate covered with a silicon oxide layer, and a silicon window is etched in the silicon oxide layer. The silicon substrate is a doped silicon substrate. The base electrode comprises single-layer graphene in the silicon window region, which is opposite to the doping mode of the silicon substrate, and forms a shallow Schottky junction with the silicon substrate. The base electrode graphene extends from the silicon window to the position of the metal electrode corresponding to the silicon oxide surface. A tunnel layer is arranged between the metal electrode and the base electrode graphene. The collector electrode comprises collector single-layer graphene isolated from the base electrode graphene through the tunnel layer, and extends to the position of the metal electrode corresponding to the silicon oxide surface. The base electrode graphene, the tunnel layer and the collector graphene form a tunnel junction. The application utilizes the barrier difference between graphene-silicon and graphene-graphene-silicon Schottky junction to enhance the rectification characteristics, and can realize large-scale and low cost.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and particularly relates to a wafer-level graphene-silicon three-terminal phototransistor and a preparation method thereof. BACKGROUND

[0002] With the development of semiconductor technology, the size scaling of silicon-based transistors has approached the physical limit, and it is difficult to meet the demand of the next generation of integrated circuits for high performance, high density and low power consumption. Two-dimensional (2D) materials have been promoted from material-level research to product-level application due to their unique electrical and optical properties, becoming an important direction to replace traditional silicon-based materials. Among them, graphene occupies a key position in the field of low-dimensional semiconductors due to its high conductivity and ultra-wide operating bandwidth, and the maturity of roll-to-roll production and wafer-level batch preparation technology has met the basic requirements for commercialization.

[0003] The existing vertical transistor based on 2D material heterojunction has the following core scheme: adopting a vertically stacked 2D material heterojunction as a core structure, and using interlayer tunneling effect to realize current regulation; relying on a full 2D material system to construct source, drain and gate three terminals, or realizing carrier injection through combination of 2D material and metal electrode; the preparation process mainly depends on small-area laboratory preparation, relying on precise photolithography and transfer technology, and has not realized wafer-level compatible silicon-based CMOS large-scale production.

[0004] The existing vertical graphene heterojunction phototransistor forms a photoelectric response structure by stacking graphene and other 2D semiconductor materials (such as MoS2), but has the following limitations: poor material compatibility, high cost of large-scale preparation, switch ratio less than 10 4 , unstable rectification characteristics, and cannot be directly integrated into existing silicon-based chips.

[0005] In summary, a variety of structures have been developed in the field of low-dimensional transistors, including field effect tunneling low-dimensional transistors, vertical low-dimensional transistors, low-dimensional hot electron transistors, low-dimensional bipolar transistors, etc., but these technologies still face core challenges:

[0006] Large-scale preparation is difficult: the full 2D material three-terminal transistor is limited by the wafer-level uniform growth and transfer process of 2D materials, and it is difficult to realize low-cost and large-area mass production, and the batch consistency is poor;

[0007] The inherent zero-bandgap property of graphene makes it difficult to be directly used as a transistor or logic device in large-scale low-dimensional integrated circuits, although the performance can be regulated by layer control, fluorination, nano patterning, etc., but there are problems such as difficulty in material growth, performance balance (such as the contradiction between conductivity and bandgap regulation), etc.;

[0008] Performance indicators are insufficient: the switch ratio is generally less than 10 4The sub-threshold swing is greater than 300 mV / dec, the rectification characteristic linearity (R2) is less than 0.99, the amplification coefficient is less than 10, and the core requirements of a logic circuit cannot be met;

[0009] Incompatible with a silicon-based process: the existing structure design does not consider the compatibility of a silicon-based CMOS process, and it is difficult to integrate into an existing semiconductor manufacturing process, which hinders industrial application;

[0010] Poor reliability and stability: current decay and performance drift caused by interface charge accumulation exist under long-term work, tunnel layer breakdown easily occurs under high bias, and the wavelength adaptability of the light response is narrow;

[0011] Poor power consumption control: due to improper selection of the tunnel layer material or unreasonable design of the electrode, the device has high power consumption and weak regulation and control capability. SUMMARY

[0012] The present application aims to overcome the shortcomings of the prior art and provides a wafer-level graphene-silicon three-terminal phototransistor which is low in cost, high in performance, high in reliability and compatible with a silicon-based CMOS process.

[0013] The present application aims to overcome the shortcomings of the prior art and provides a wafer-level graphene-silicon three-terminal phototransistor which is low in cost, high in performance, high in reliability and compatible with a silicon-based CMOS process.

[0014] The emitter stage is a silicon substrate covered with a silicon oxide layer, the silicon oxide layer has a silicon window etched therein, and the silicon substrate is a doped silicon substrate.

[0015] The base includes single-layer graphene in the silicon window region, the doping mode of the single-layer graphene is opposite to that of the silicon substrate, a shallow Schottky junction is formed between the single-layer graphene and the silicon substrate, the base graphene extends from the silicon window to the position of the metal electrode corresponding to the base on the surface of the silicon oxide, and a tunnel layer is arranged between the metal electrode and the base graphene.

[0016] The collector includes collector single-layer graphene isolated from the base graphene by the tunnel layer, the collector single-layer graphene extends to the position of the metal electrode corresponding to the collector on the surface of the silicon oxide, and the base graphene, the tunnel layer and the collector graphene form a tunnel junction.

[0017] Further, the metal electrode includes metal electrodes corresponding to the emitter, the base and the collector, the metal electrode corresponding to the emitter is arranged on the silicon substrate, and the metal electrodes corresponding to the base and the collector are arranged at different positions on the silicon oxide layer.

[0018] Further, the tunnel layer is an Al2O3 thin film obtained by atomic layer deposition, or HfO2 or ZrO2 compatible with the interface of graphene.

[0019] Further, the doping type of the silicon substrate and the base graphene includes: a lightly doped n-type silicon substrate is matched with p-doped graphene to form a shallow Schottky junction, or a p-type silicon substrate is matched with n-doped graphene to form a Schottky junction.

[0020] Further, the metal electrode uses Cr / Au as the electrode of the emitter and the collector, and Cr / Ag as the base electrode, and the size includes: the Cr / Au electrode is 20 nanometers / 70 nanometers, and the Cr / Ag electrode uses 20 nanometers / 300 nanometers.

[0021] Further, the metal electrode further includes Ti / Au and Ni / Au instead of Cr / Ag and Cr / Au electrodes to ensure the ohmic contact and stability of the electrode and graphene / silicon.

[0022] According to another aspect of the specification, a preparation method of the transistor is also provided, which includes:

[0023] A lightly doped silicon wafer with a thermally grown SiO2 layer is used to prepare the electrodes of the emitter and the collector and the metal pad by photolithography and electron beam evaporation;

[0024] A photoresist is used for patterning, and an etching solution is used for selective etching of the SiO2 layer to form a silicon window;

[0025] A single-layer graphene is prepared by chemical vapor deposition, and a CVD single-layer graphene is transferred to the surface of the substrate containing the silicon window by a PMMA-assisted wet transfer technology; photolithography is performed again, and oxygen plasma etching is used to etch the excess graphene to form a Schottky junction;

[0026] A tunnel dielectric thin film is grown by atomic layer deposition to cover the silicon window area and the metal pad area;

[0027] A CVD single-layer graphene is wet-transferred to the surface of the tunnel dielectric thin film for the second time, and after photolithography, oxygen plasma etching is used to etch the excess graphene to form a graphene-tunnel dielectric-graphene tunnel junction;

[0028] The tunnel layer of the collector metal pad area is wet-etched to reduce the contact resistance;

[0029] The base electrode is deposited by electron beam evaporation to complete the preparation of the device.

[0030] Further, when the tunnel dielectric thin film is Al2O3, the Al2O3 layer of the collector metal pad area is wet-etched using an Al etching solution, and the ratio of the Al etching solution is H3PO4: HNO3: CH3COOH: H2O = 16: 1: 1: 2.

[0031] Further, the oxygen plasma etching of the excess graphene during the transfer of each layer of graphene includes two etching processes, the first etching process is to perform oxygen plasma treatment on the excess single-layer graphene for 90 seconds at an O2 flow rate of 300 sccm and a power of 50 W, and the second etching process is to perform treatment for 3 minutes at an O2 flow rate of 300 sccm and a power of 30 W.

[0032] Further, the SiO2 layer is formed by a thermal oxidation process of 100±5 nanometers on the surface of a silicon wafer.

[0033] Advantages of the present application:

[0034] The vertical stacked graphene-silicon three-terminal structure is adopted, the base graphene and the collector graphene are isolated by an Al2O3 tunnel layer to form a synergistic effect of a double Schottky junction and a tunnel junction.

[0035] Based on the growth quality difference of Al2O3 on the surface of graphene and metal, selective transmission of channel current is realized, and the rectification characteristic is enhanced by using the barrier difference of graphene-silicon and graphene-graphene-silicon Schottky junction; the device operating voltage is reduced (within ±5 V range), and the power consumption is lower than that of the existing vertical transistor by more than 30%;

[0036] Large scale and low cost: 4-inch wafer-level preparation is realized, relying on mature CVD graphene growth and wet transfer technology, the cost is lower than that of full 2D heterojunction devices; the on-off ratio, rectification characteristic and amplification coefficient are better than those of existing low-dimensional transistors, solving the logic performance defects caused by the zero band gap of traditional graphene devices;

[0037] Through two times of graphene wet transfer, patterning and ALD Al2O3 deposition, the device is fully compatible with the silicon-based CMOS process, without the need for additional development of special equipment, reducing the industrialization threshold;

[0038] No performance degradation after long-term pulse test, good stability of the tunnel layer under high bias, wide optical response band (covering visible light to infrared);

[0039] Multifunctional integration: the structure utilizes the photoelectric performance of the graphene-silicon Schottky junction, so that the device has photoelectric detection. The base region forward channel controls the signal amplification of the emitter-collector channel, and the excellent Schottky junction ensures its self-rectifying function, which can replace the combination structure of traditional "detector + amplifier", simplifying the circuit design. BRIEF DESCRIPTION OF DRAWINGS

[0040] Figure 1 A wafer-level graphene-silicon three-terminal phototransistor structure schematic diagram is provided for the embodiments of the present application.

[0041] Figure 2 A flowchart illustrating the overall transistor fabrication process provided in this embodiment of the invention;

[0042] Figure 3 A diagram illustrating the transistor's working mechanism provided in an embodiment of the present invention;

[0043] Figure 4 Photoelectric characteristics diagram of a graphene-silicon vertical phototransistor provided in an embodiment of the present invention;

[0044] Figure 5 Performance analysis of the graphene-silicon vertical phototransistor provided in the embodiments of the present invention;

[0045] Figure 6 Long-term stability test diagram provided for embodiments of the present invention;

[0046] Figure 7 A simplified preparation flowchart is provided for embodiments of the present invention. Detailed Implementation

[0047] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0048] like Figure 1 As shown, the present invention provides a wafer-level graphene-silicon three-terminal phototransistor, the device having a three-terminal vertical structure, the core of which includes:

[0049] Emitter: Lightly doped n-type Si substrate, with a 100±5 nm thermally oxidized SiO2 layer covering the surface;

[0050] Base: A monolayer of p-doped graphene located above the silicon window region formed by SiO2 etching, forming a shallow Schottky junction (Emit-Base junction) with n-type Si.

[0051] A p-type Si substrate can be used in conjunction with n-doped graphene to form an n-type graphene / p-type Si Schottky junction, which can also achieve rectification and tunneling control.

[0052] The existing p-doping process can be replaced by ion implantation, chemical doping, etc., as long as a stable Schottky junction between p-type graphene and n-type Si can be formed.

[0053] Collector: A single layer of graphene located above the base graphene, isolated from the base graphene by an Al2O3 tunnel layer, forming a graphene–Al2O3–graphene tunnel junction (Base-Collect junction).

[0054] Tunneling layer: A 7 nm thick Al2O3 film, grown by atomic layer deposition (ALD), located between the base graphene and the current collector graphene, and between the base graphene and the base metal electrode. Other high-k dielectric materials such as HfO2 and ZrO2 can be used to replace Al2O3, and the tunneling control function can still be achieved. The key lies in the interface compatibility between the dielectric layer and graphene.

[0055] Metal electrodes: emitter electrode (Cr / Au = 20 nm / 70 nm), base electrode (Cr / Au = 20 nm / 70 nm - Al₂O₃ = 7 nm - Cr / Ag = 20 nm / 300 nm), and collector electrode (Cr / Au = 20 nm / 70 nm). The Al₂O₃ layer in the collector region is removed by wet etching to reduce contact resistance. Ti / Au and Ni / Au materials can be used to replace Cr / Ag and Cr / Au electrodes; the key is to ensure ohmic contact and stability between the electrode and graphene / silicon.

[0056] The difference in growth quality of Al2O3 on graphene and metal surfaces is utilized: Al2O3 grown on metal surfaces is of higher quality, while Al2O3 grown on graphene surfaces forms a tunneling / resistive layer, enabling selective transmission of channel current.

[0057] The barrier difference between the graphene-silicon Schottky junction (barrier 0.74 eV) and the graphene-graphene-silicon Schottky junction (barrier 0.76 eV) enhances the self-rectification characteristics.

[0058] Vertical stacking design: The base and collector graphene are vertically stacked and isolated by an Al2O3 tunnel layer, which shortens the carrier transport path and improves the response speed.

[0059] Based on the transistors described above, such as Figure 2 As shown, the embodiment also provides a method for fabricating a wafer-level graphene-silicon three-terminal phototransistor, specifically including:

[0060] Step 1: Substrate preparation

[0061] like Figure 2 As shown in Figure a, a lightly doped n-type Si wafer was selected, and its surface underwent a 100±5 nm thermal oxidation treatment to form a silicon dioxide layer. AZ6130 was used as the photoresist, and Cr / Au (20 nm / 70 nm) was prepared by photolithography and electron beam evaporation. Collector and base electrodes were then fabricated. The emitter electrode was composed of a gallium-indium alloy.

[0062] Step 2: Silicon window etching

[0063] Patterning was performed using AZ6130 photoresist, and the SiO2 layer was selectively etched using an HF-based etching solution (HF:NH4F:H2O=30 mL:60 g:45 mL, HF concentration 48%) to form silicon windows, as shown below. Figure 2 b in the text.

[0064] Step 3: Base Graphene Transfer and Patterning

[0065] Monolayer graphene was prepared by chemical vapor deposition (CVD) and transferred to the surface of a substrate containing a silicon window using PMMA-assisted wet transfer technology (Figure 2c). Subsequently, AZ6130 was used as a photoresist for re-patterning. Excess graphene was etched using an Alpha Plasma AL18 system with oxygen plasma (O2 = 300 sccm, 50 W × 90 s + 30 W × 3 min). A second removal of excess graphene was then performed using the Alpha Plasma AL18 system under the following conditions: oxygen flow rate 300 mAg, power 30 W. This formed a p-doped graphene / n-type Si Schottky junction (Emit-Base junction) (Figure 2c). Figure 2 (d in the text)

[0066] Step 4: Deposition of Al2O3 tunnel layer

[0067] A 7 nm thick Al₂O₃ film was grown at 200 °C using a Lesker ALD150LX, covering the silicon window region (tunneling layer) and the metal pad region (resistive layer). (See attached image) Figure 2 (e in the text).

[0068] Step 5: Collector Graphene Transfer and Patterning

[0069] Second wet transfer CVD process to transfer monolayer graphene to the surface of Al2O3 film (with attached) Figure 2 (f) Then, AZ6130 is used as the photoresist for conventional photolithography. After photolithographic patterning, oxygen plasma is used to etch excess graphene, forming a graphene-Al2O3-graphene tunnel junction (Base-Collect junction) (see appendix). Figure 2 g in (the middle part).

[0070] The step of oxygen plasma etching the excess graphene includes: oxygen plasma treating the excess single-layer graphene for 90 seconds by an Alpha Plasma AL18 system at an O2 flow rate of 300 sccm and a power of 50 W to remove the excess single-layer graphene. Then, the oxygen plasma treatment is used again for 3 minutes, also by the Alpha Plasma AL18 system, but at an O2 flow rate of 300 sccm and a power of 30 W to further remove the excess single-layer graphene.

[0071] Step 6: Collector Region Al2O3 Etching

[0072] The Al2O3 layer of the collector metal pad region is wet-etched using an Al etching solution (H3PO4: HNO3: CH3COOH: H2O = 80 mL: 5 mL: 5 mL: 10 mL) to reduce the contact resistance (Fig. 6 in the accompanying drawings). Figure 2

[0073] Step 7: Metal Electrode Preparation

[0074] The base electrode of Cr / Ag (20 nm / 300 nm) is deposited by electron beam evaporation, and the device preparation is completed (Fig. 7 in the accompanying drawings). Figure 2 The subsequent application can be used in the fields of photodetectors, logic gate circuits, signal amplifiers, integrated optoelectronic chips, etc.

[0075] The graphene used in this embodiment is a 200x300 square millimeter copper-based single-layer chemical vapor deposition graphene purchased from the National Graphene Innovation Center in Ningbo, Zhejiang Province, China.

[0076] ​For wet transfer of graphene, it specifically includes: first spin-coat a polymethyl methacrylate (PMMA) layer on graphene / copper / graphene at a speed of 4000 revolutions per minute for 60 seconds. After coating the PMMA layer on the top graphene, the graphene under the copper layer on the other side of the graphene is subjected to 15 minutes of oxygen plasma treatment by a Plasma Washer PT-5 system, with an oxygen flow rate of 300 standard cubic centimeters per minute and a power of 60 watts. The copper etching liquid formula is 16 grams: 50 milliliters: 45 milliliters (copper sulfate pentahydrate: hydrochloric acid: water), and the ammonium persulfate stabilizing liquid formula is 10 grams: 100 milliliters (ammonium persulfate: water). Then the supported copper layer is etched using the etching liquid. After the copper is completely etched, the graphene / PMMA is transferred to fresh deionized water three times to remove residues. Then, the cleaned graphene / PMMA stack is transferred to the target sample, and the excess deionized water is naturally air-dried for more than 8 hours. Further annealing at 100 degrees Celsius for 30 minutes enhances the adhesion between the graphene and the substrate. The PMMA is removed by immersing the graphene / PMMA stack in fresh acetone for 1 hour, and this operation is repeated at least three times.

[0077] As Figure 3 shown is the mechanism analysis of the device of the embodiment of the application: the device adopts an emitter (Si substrate) grounded, and the carrier transmission is regulated by applying a bias voltage through the base and the collector, and the core mechanism is:

[0078] 1) Schottky junction rectification effect: the Schottky junction formed by the p-doped graphene / n-type Si has an internal electric field direction from the Si to the graphene, realizing self-rectification of the Emit-Base and Emit-Collect channels;

[0079] 2) Tunneling regulation: the base bias (V EB ) injects holes, and part of the holes enter the collector through the graphene-Al2O3-graphene tunneling junction, and part of the holes offset the internal electric field of the Schottky junction to regulate the Emit-Collect channel current;

[0080] 3) Photoelectric response: under laser irradiation, photo-generated carriers are generated in the Schottky junction region, and the internal electric field separates the electrons (injected into the emitter) and the holes (enter the collector through the tunneling junction), realizing photoelectric current amplification.

[0081] As Figure 4 , Figure 5 and Figure 6 shown are the test results of the embodiment of the application: the on / off ratio is as high as 15062.24;

[0082] Sub-threshold swing (SS): 218.7274 mV・dec⁻¹;

[0083] Self-rectification figure of merit (R 2 ): 0.9998;

[0084] Amplification factor: β' = 19.8 (common emitter), α' = 0.95 (common base);

[0085] Photoresponse wavelength range: 532 nm (visible light) to 1064 nm (infrared);

[0086] Long-term stability: No current decay after 3 cycles of 250 s pulse test, no obvious breakdown under high bias.

[0087] Specifically, wherein Figure 4 is the photoelectric characteristics of the graphene-silicon phototransistor. a is the I-V characteristics of the BE (base-emitter) junction, CE (collector-emitter) junction and BC (base-collector) junction in the dark state. b is the I EC -V EC output characteristic curve. V EB varies from -1 V to -5 V in steps of 1 V. V EC varies from -2 V to 6 V in steps of 0.1 V. c is the I EC -V EC output characteristic curve. V EB varies from -1 V to -5 V in steps of 1 V. V EC varies from -2 V to 6 V in steps of 0.1 V. d is the I EC -V EC input characteristic curve. V EB varies from -1 V to -5 V in steps of 1 V. V EC varies from -2 V to 6 V in steps of 0.1 V.

[0088] Figure 5 is the performance analysis of the graphene-silicon vertical phototransistor. a is the ratio of current (V EC = 5 V) to current (V EC = 0 V) and threshold voltage. b is the minimum dV EC / d (log 10 I EC). V EC c is a linear self-rectification parameter (R 2 ) according to the variation range of V EB ) and the variation range of V EC ) (from 2 V to 5 V). d is the amplification factor of the common base amplification circuit (a = b’ / (1+b’)) and the common emitter amplification circuit (b’ = I CE / I BC ) calculated based on the ratio of I EC and I BC ). And the variation range of V EB is -1 V to -3 V. These parameters are applicable in the case of the variation range of V EB is -1 V to -5 V, the laser wavelength is 532 nm and 1064 nm, and the laser power is 532 nm - 130 nanowatts (1), 281 nanowatts (2) and 490 nanowatts (3), 1064 nm - 140 nanowatts (1), 10.97 microwatts (2) and 23.6 microwatts (3).

[0089] Figure 6 is a long-term stability test. (a) I EC -V EB characteristic test under dark conditions. V EB -t (s) represents an electrical pulse of -3 V (1 s) / -1 V (9 s). (b) I EB -V EB characteristic test under dark conditions. V EB -t (s) represents an electrical pulse of -3 V (1 s) / -1 V (9 s). (c) I EC -V EC characteristic test under dark conditions. V EC -t (s) represents an electrical pulse of 5 V (1 s) / 10 V (10 s).

[0090] Figure 7 is the structure and characteristics of a two-dimensional graphene-silicon vertical phototransistor device. a-i. Process flow for fabricating the device. j. Optical image of a 4-inch wafer-level phototransistor. k-l. Optical images of the device. It covers the silicon window (k), the first patterned graphene (l), aluminum oxide deposition (m), and the second patterned graphene (n). The scale bar is 100 microns.

[0091] Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. It is intended that the specification and examples be considered as exemplary only, with the true scope and spirit of the application being indicated by the following claims.

[0092] It is to be understood that the above general description and the subsequent detailed description are merely exemplary and explanatory and are not restrictive of the application. The application is not restricted to the precise construction and combinations of parts and steps described above and shown in the accompanying drawings, as such variations and modifications are intended to be included within the scope of the application. The scope of the application is limited only by the claims that follow.

Claims

1. A wafer-level graphene-silicon three-terminal phototransistor, characterized in that, include: Emitter, base, collector, tunnel layer, and metal electrode; The emitter is a silicon substrate covered with a silicon oxide layer, in which silicon windows are etched, and the silicon substrate is a doped silicon substrate; The base includes: a single layer of graphene located in the silicon window region with the opposite doping mode to the silicon substrate, forming a shallow Schottky junction with the silicon substrate, the base graphene extending from the silicon window to the metal electrode position corresponding to the base on the silicon oxide surface, and a tunnel layer is provided between the metal electrode and the base graphene. The current collector includes: a single layer of current collector graphene isolated on the base graphene by a tunnel layer, extending to the metal electrode position corresponding to the current collector on the silicon oxide surface, wherein the base graphene, the tunnel layer and the current collector graphene form a tunnel junction.

2. The wafer-level graphene-silicon three-terminal phototransistor according to claim 1, characterized in that, The metal electrodes include metal electrodes corresponding to the emitter, base, and collector. The metal electrode corresponding to the emitter is disposed on the silicon substrate; the metal electrodes corresponding to the base and collector are disposed at different positions on the silicon oxide layer.

3. The wafer-level graphene-silicon three-terminal phototransistor according to claim 1, characterized in that, The tunnel layer is an Al2O3 film obtained by atomic layer deposition, or HfO2 or ZrO2 that is compatible with the graphene interface.

4. The wafer-level graphene-silicon three-terminal phototransistor according to claim 1, characterized in that, The doping types of the silicon substrate and the base graphene include: a lightly doped n-type silicon substrate combined with p-doped graphene to form a shallow Schottky junction, or a p-type silicon substrate combined with n-doped graphene to form a Schottky junction.

5. A wafer-level graphene-silicon three-terminal phototransistor according to claim 1, characterized in that, The metal electrodes use Cr / Au as the emitter and collector electrodes, and Cr / Ag as the base electrode. The dimensions include: Cr / Au electrodes are 20 nm / 70 nm, and Cr / Ag electrodes are 20 nm / 300 nm.

6. A wafer-level graphene-silicon three-terminal phototransistor according to claim 5, characterized in that, The metal electrode also includes Ti / Au and Ni / Au electrodes, which replace Cr / Ag and Cr / Au electrodes to ensure ohmic contact and stability between the electrode and graphene / silicon.

7. A method for fabricating a transistor according to any one of claims 1-6, characterized in that, include: Electrodes and metal pads for emitter and collector electrodes were fabricated using lightly doped silicon wafers with a surface-grown thermally oxidized SiO2 layer, via photolithography and electron beam evaporation. Photoresist is used for patterning, and an etching solution is used to selectively etch the SiO2 layer to form a silicon window; Monolayer graphene was prepared by chemical vapor deposition and transferred to a substrate containing silicon windows using PMMA-assisted wet transfer technology. The graphene was then patterned by photolithography and excess graphene was etched using oxygen plasma to form a Schottky junction. Tunnel dielectric films are grown by atomic layer deposition to cover the silicon window region and the metal pad region; The second wet transfer CVD process transfers monolayer graphene to the surface of the tunneling medium film. After photolithography patterning, excess graphene is etched by oxygen plasma to form a graphene-tunneling medium-graphene tunnel junction. Wet etching of the tunnel layer in the collector metal pad area reduces contact resistance; The device was fabricated by depositing the base electrode using electron beam evaporation.

8. The preparation method according to claim 7, characterized in that, When the tunnel dielectric film is made of Al2O3, the Al2O3 layer in the collector metal pad area is etched by wet etching with Al etching solution. The Al etching solution has a ratio of H3PO4: HNO3:CH3COOH: H2O = 16: 1:1:

2.

9. The preparation method according to claim 7, characterized in that, The oxygen plasma etching of excess graphene used during the transfer of each graphene layer includes two etching processes. The first etching process involves treating the excess monolayer graphene with oxygen plasma at an O2 flow rate of 300 sccm and a power of 50 W for 90 seconds. The second etching process involves treating the excess monolayer graphene with an O2 flow rate of 300 sccm and a power of 30 W for 3 minutes.

10. The preparation method according to claim 7, characterized in that, The SiO2 layer is formed by thermal oxidation of the silicon wafer surface at a depth of 100±5 nanometers.

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