Display device

Abstract

A display device according to an embodiment of the present disclosure may include: a substrate; an insulating layer disposed on the substrate, and disposed on the display area and the non-display area; an electrostatic discharge line in the non-display area and disposed on the insulating layer; the passivation layer is arranged on the electrostatic discharge wire; an organic insulating layer disposed on the passivation layer and having two or more holes in the non-display area; and two or more electrostatic discharge patterns in the non-display area, and each of the two or more electrostatic discharge patterns is disposed within the two or more holes. Each of the two or more electrostatic discharge patterns may be disposed on the passivation layer within the two or more holes and may be electrically connected to the electrostatic discharge wire through a contact hole of the passivation layer.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0107837, filed on August 12, 2024, which is incorporated herein by reference for all purposes, as if fully set forth herein. Technical Field

[0003] Embodiments of this disclosure relate to a display device. Background Technology

[0004] Display devices are used in various electronic devices such as televisions, mobile phones, laptops, and tablets. Display devices can include organic light-emitting displays (OLEDs) that emit their own light and liquid crystal displays (LCDs) that require a separate light source.

[0005] Recently, display devices with light-emitting diodes (LEDs) have attracted attention as the next generation of display devices. Because LEDs are made of inorganic materials rather than organic materials, LED-based display devices have faster turn-on speeds, superior luminous efficiency, and the ability to display high-brightness images compared to liquid crystal displays or organic light-emitting displays. Summary of the Invention

[0006] Embodiments of this disclosure may provide a display device having a wiring structure arranged in a matrix form, thereby effectively driving multiple light-emitting devices.

[0007] Embodiments of this disclosure may provide a display device capable of effectively driving multiple light-emitting devices by using multiple column lines connecting first electrodes of two or more light-emitting devices arranged along a column direction and multiple row lines connecting second electrodes of two or more light-emitting devices arranged along a row direction.

[0008] Embodiments of this disclosure may provide a display device having an electrostatic discharge structure that prevents damage to the circuit caused by static electricity.

[0009] Embodiments of this disclosure may provide a display device having a structure for improving luminous efficiency, the structure being able to reduce the amount of light lost within the display panel and increase the amount of light emitted outside the display panel, in addition to the amount of light emitted by the light-emitting device within the display panel.

[0010] Embodiments of this disclosure may provide a display device having a luminous efficiency improvement structure including a light scattering structure.

[0011] Embodiments of the disclosure can provide a display device having a light emission efficiency improvement structure including a light reflection structure.

[0012] Embodiments of the disclosure can provide a display device capable of driving with low power by improving light emission efficiency, and thereby achieving a desired brightness with less power.

[0013] Embodiments of the disclosure can provide a display device capable of reducing the number of driving components (e.g., drivers) connected to the outside of a display panel, thereby reducing the number of assembly processes in a manufacturing process, and thereby achieving process optimization.

[0014] The objects of embodiments of the disclosure are not limited to the objects described in the disclosure, and other objects not mentioned can be clearly understood by those skilled in the art from the following description.

[0015] A display device according to an embodiment of the disclosure can include a substrate, an insulating layer disposed on the substrate and disposed on a display area and a non-display area, an electrostatic discharge line located in the non-display area and disposed on the insulating layer, a passivation layer disposed on the electrostatic discharge line, an organic insulating layer disposed on the passivation layer and having two or more holes located in the non-display area, and two or more electrostatic discharge patterns located in the non-display area and each disposed within the two or more holes. Each of the two or more electrostatic discharge patterns can be disposed on the passivation layer within the two or more holes and can be electrically connected to the electrostatic discharge line through a contact hole of the passivation layer.

[0016] A display device according to an embodiment of the disclosure can include a substrate, a bank disposed in a display area, an outer bank disposed in a non-display area which is an outer area of the display area, a light emitting device disposed on the bank, and an electrostatic discharge pattern disposed on the outer bank.

[0017] According to an embodiment of the disclosure, a display device can be provided, which has a wiring structure arranged in a matrix form, thereby effectively driving a plurality of light emitting devices.

[0018] According to an embodiment of the disclosure, a display device can be provided, which is capable of effectively driving a plurality of light emitting devices by using a plurality of column lines connecting first electrodes of two or more light emitting devices arranged in a column direction and a plurality of row lines connecting second electrodes of two or more light emitting devices arranged in a row direction.

[0019] According to embodiments of the present disclosure, a display device having an electrostatic discharge structure capable of preventing damage to a circuit caused by static electricity can be provided.

[0020] According to embodiments of the present disclosure, a display device having a structure for improving light emission efficiency capable of reducing an amount of light lost within a display panel between an amount of light emitted by a light emitting device within the display panel and increasing an amount of light emitted outside the display panel can be provided.

[0021] According to embodiments of the present disclosure, a display device having a light emission efficiency improvement structure including a light scattering structure can be provided.

[0022] According to embodiments of the present disclosure, a display device having a light emission efficiency improvement structure including a light reflection structure can be provided.

[0023] According to embodiments of the present disclosure, a display device capable of being driven at low power by improving light emission efficiency and thereby achieving a desired brightness with less power can be provided.

[0024] According to embodiments of the present disclosure, a display device capable of reducing the number of driving components (e.g., drivers) connected to the outside of a display panel, thereby reducing the number of assembly processes in a manufacturing process, and thereby achieving process optimization can be provided.

[0025] Effects of embodiments of the present disclosure are not limited to what has been described above and other effects not mentioned above will become apparent to those skilled in the art from the description of the claims. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 A display device according to embodiments of the present disclosure is illustrated.

[0027] Figure 2 is a plan view of a display device according to embodiments of the present disclosure.

[0028] Figure 3 is a plan view of a display panel according to embodiments of the present disclosure.

[0029] Figure 4 is a plan view of a unit driving area of a display panel according to embodiments of the present disclosure.

[0030] Figure 5 A sub-pixel of a display panel according to embodiments of the present disclosure is illustrated.

[0031] Figure 6 is an equivalent circuit diagram of a unit driving area of a display panel according to embodiments of the present disclosure.

[0032] Figure 7 A driving timing diagram of n row lines and one column line included in a first sub-driving area of a display panel according to an embodiment of the disclosure is shown.

[0033] Figure 8 is a plan view of a display panel according to an embodiment of the disclosure.

[0034] Figure 9 A unit driving area of a display panel according to an embodiment of the disclosure is shown.

[0035] Figure 10 and Figure 11 is a plan view of a portion of a display panel according to an embodiment of the disclosure.

[0036] Figure 12 is a cross-sectional view of a display panel according to an embodiment of the disclosure.

[0037] Figure 13 is a detailed cross-sectional view of a display panel according to an embodiment of the disclosure taken along the A-B cutting line of Figure 8

[0038] Figure 14 is a magnified cross-sectional view of a first sub-pixel of a display panel according to an embodiment of the disclosure.

[0039] Figure 15 is a plan view of a display device according to an embodiment of the disclosure.

[0040] Figure 16 and Figure 17 is a plan view of a portion of a display device according to an embodiment of the disclosure.

[0041] Figure 18 is a plan view of a display area of a display device according to an embodiment of the disclosure.

[0042] Figure 19 is a cross-sectional view of a display area of a display device according to an embodiment of the disclosure.

[0043] Figure 20 and Figure 21 is a cross-sectional view of an electrostatic discharge area included in a non-display area of a display device according to an embodiment of the disclosure.

[0044] Figure 22 is a diagram for explaining electrostatic discharge according to an embodiment of the disclosure. DETAILED DESCRIPTION

[0045] ​The advantages and features of the present disclosure and implementation methods thereof will become apparent from the detailed description of the embodiments given below with reference to the accompanying drawings. However, the present disclosure is not limited to the embodiments disclosed below, but can be implemented in various different forms, and the embodiments are merely used to make the disclosure of the present disclosure complete and fully convey the scope of the present invention to those of ordinary skill in the art.

[0046] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present disclosure are exemplary, and thus the present disclosure is not limited to the matters shown. When assigning reference numerals to the components in each drawing, the same components can be assigned the same reference numerals even though they are illustrated in different drawings. Details of known technology or functions can be omitted when it is determined that such an omission makes the subject matter of the present disclosure unclear. As used herein, when a component "includes," "has," or "consists of" another component or "consists essentially of" another component, additional components can be added unless "only" is used. When a component is expressed in the singular form, it includes the plural case unless explicitly stated otherwise.

[0047] When explaining components, even if there is no separate explicit description of an error range, it is interpreted to include an error range.

[0048] In the case of describing positional relationships, for example, if the positional relationship between two parts is described as "on", "above", "below", "beside", or "adjacent to", unless the words "directly" or "tightly" are used, one or more other parts can be located between the two parts.

[0049] When describing temporal relationships, if temporal continuity is described as "after", "follows", "immediately after", or "before", it can also include a non-continuous case unless "immediately" or "directly" is used.

[0050] Although the terms first, second, etc. are used to describe various elements, the elements are not limited by these terms. The terms are used only to distinguish one element from another. Thus, the first element mentioned below can also be a second element within the technical scope of the present disclosure.

[0051] In describing the components of the present disclosure, terms such as first, second, A, B, (a), or (b) can be used. These terms are only intended to distinguish between components and are not limited to the nature, order, sequence, or number of components.

[0052] If a component is described as being "connected," "coupled," "linked," or "attached" to another component, it should be understood that the component can be directly connected, coupled, linked, or attached to the other component, but other components can be interposed therebetween without any specific explicit description.

[0053] When a component or layer is described as being "in contact with" or "overlapping" another component or layer, it should be understood that the component or layer can be directly in contact with or overlapping the other component or layer, but other components can be interposed between each component such that the components can be indirectly in contact or overlapping without any specific explicit description.

[0054] "at least one of" should be understood as including any combination of one or more of the associated components. For example, "at least one of a first component, a second component, and a third component" can be interpreted as including only a first component, only a second component, only a third component, as well as any combination of a first component, a second component, and a third component.

[0055] "first direction," "second direction," "third direction," "X-axis direction," "Y-axis direction," and "Z-axis direction" should not be interpreted only as geometric relationships, i.e., their relationship with each other is perpendicular, but can represent a wider directionality within a range in which the configuration of the present disclosure can functionally act.

[0056] Each feature of various embodiments of the present disclosure can be partially or wholly combined together, or combined with each other, and various technical connections and operations are possible, and each embodiment can be implemented independently of each other or can be implemented together in a related relationship.

[0057] Hereinafter, various embodiments of the present disclosure are described in detail with reference to the accompanying drawings.

[0058] Figure 1 A display device 100 according to an embodiment of the present disclosure is illustrated, and Figure 2 is a plan view of a display device 100 according to an embodiment of the present disclosure.

[0059] Referring to Figure 1 , a display device 100 according to an embodiment of the present disclosure can include a display panel 110, a cover member 118 disposed on the display panel 110, a flexible printed circuit 102 connected to the display panel 110, and a printed circuit board 104 connected to the flexible printed circuit 102.

[0060] The display device 100 according to an embodiment of the disclosure can further include a support substrate 106 disposed under the display panel 110 and supporting a lower portion of the display panel 110, a polarizing layer 114 disposed on the display panel 110, a first adhesive layer 112 disposed between the display panel 110 and the polarizing layer 114, and a second adhesive layer 116 disposed between the polarizing layer 114 and the cover member 118.

[0061] The display panel 110 can include a substrate 210. The substrate 210 can be a member on which various components such as a plurality of metal layers and a plurality of insulating material layers are formed. The substrate 210 can be made of an insulating material. For example, the substrate 210 can be made of glass or resin. In addition, the substrate 210 can be made of a flexible material. For example, the substrate 210 can be made of a flexible plastic material such as polyimide (PI). However, embodiments of the disclosure are not limited thereto.

[0062] The display panel 110 can display information and / or an image to a user. For example, the display panel 110 can include a display area DA and a non-display area NDA. For example, the substrate 210 can include the display area DA and the non-display area NDA. The display area DA and the non-display area NDA are not limited to the substrate 210, but can be described throughout the display device 100.

[0063] The display area DA can be an area in which an image is displayed. The display area DA can include a plurality of pixels P. Each of the plurality of pixels P can be composed of a plurality of sub-pixels. At least one light emitting device can be disposed in each of the plurality of sub-pixels. The light emitting device can be variously configured depending on a type of the display device 100. For example, if the display device 100 is an inorganic light emitting display device, the light emitting device can be an inorganic-based light emitting device such as a light emitting diode (LED), a micro LED, or a mini LED, but embodiments of the disclosure are not limited thereto.

[0064] The non-display area NDA can be an area in which an image is not displayed. In the non-display area NDA, various wirings and circuits for driving the plurality of pixels P of the display area DA can be disposed. For example, various driving circuits and various wirings can be disposed in the non-display area NDA, and a pad portion 211 to which an integrated circuit and a printed circuit are connected can be disposed, but embodiments of the disclosure are not limited thereto.

[0065] For example, the driving circuit can include a data driving circuit and / or a gate driving circuit, but embodiments of the present disclosure are not limited thereto. Lines or wires supplied with control signals for controlling the driving circuit can be arranged on the substrate 210. For example, the control signals can include various timing signals including a clock signal, an input data enable signal, and a synchronization signal, but embodiments of the present disclosure are not limited thereto. The control signals can be supplied to the substrate 210 from the outside of the substrate 210 through the pad portion 211. For example, a circuit member such as the flexible printed circuit 102 and the printed circuit board 104 can be connected to the pad portion 211.

[0066] According to embodiments of the present disclosure, the non-display area NDA can include a first non-display area NDA1, a bending area BA, and a second non-display area NDA2. For example, the first non-display area NDA1 can be an area surrounding at least a portion of the display area DA. The bending area BA can be an area extending from at least one of the plurality of sides of the first non-display area NDA1 and can be a bendable area. The second non-display area NDA2 can be an area extending from the bending area BA and can include the pad portion 211. For example, the bending area BA can be in a bent state, and the remaining area of the substrate 210 except for the bending area BA can be in a flat state. In this case, when the bending area BA is bent, the second non-display area NDA2 can be located at the back of the display area DA. However, embodiments of the present disclosure are not limited thereto.

[0067] According to the design of the display device 100, the substrate 210 or the display area DA of the display device 100 can be configured in various shapes. For example, the display area DA can be configured to have a four-cornered rectangle formed in a circular shape, but embodiments of the present disclosure are not limited thereto. For another example, the display area DA can be configured to have a rectangular shape having four corners formed in a right-angled shape, a circular shape, but embodiments of the present disclosure are not limited thereto.

[0068] According to embodiments of the present disclosure, the second non-display area NDA2 in which the pad portion 211 is arranged can have a width wider than that of the bending area BA. Further, the display area DA can have a width wider than that of the bending area BA. In the drawing, the width of the bending area BA is depicted as being narrower than that of the other area of the substrate 210, but the shape of the substrate 210 including the bending area BA is exemplary, and embodiments of the present disclosure are not limited thereto.

[0069] Reference Figure 1 and Figure 2The flexible printed circuit 102 and the printed circuit board 104 can be disposed at a lower portion of the display panel 110. The flexible printed circuit 102 and the printed circuit board 104 can be arranged at one edge of the display panel 100, but embodiments of the present disclosure are not limited thereto. One side of the flexible circuit board 102 can be connected with the display panel 110, and the other side can be connected with the printed circuit board 104, but embodiments of the present disclosure are not limited thereto. The flexible printed circuit 102 can be a flexible film, but embodiments of the present disclosure are not limited thereto.

[0070] The pad portion 211 disposed in the second non-display area NDA2 includes a plurality of pads, and can attach or bond driving components including one or more flexible printed circuits 102 and a printed circuit board 104. The plurality of pads included in the pad portion 211 are electrically connected to the one or more flexible printed circuits 102, and can transmit various signals (or power) from the printed circuit board 104 and the one or more flexible printed circuits 102 to driving circuits (e.g., drivers DRV) arranged in the display area DA. Figure 3

[0071] The flexible printed circuit 102 can be a film in which various components are arranged on a flexible base film. For example, first circuit components 230, such as gate driving integrated circuits and / or data driving integrated circuits, can be arranged on the one or more flexible printed circuits 102, but embodiments of the present disclosure are not limited thereto. The first circuit components 230 can be components that process data and driving signals for displaying an image. The first circuit components 230 can be disposed in, for example, a chip on glass (COG), a chip on film (COF), or a tape carrier package (TCP), according to a mounting method, but embodiments of the present disclosure are not limited thereto. The flexible printed circuit 102 can be attached or bonded to the plurality of pads by a conductive adhesive layer, but embodiments of the present disclosure are not limited thereto.

[0072] The printed circuit board 104 can be a component that is electrically connected to the flexible printed circuit 102 and supplies signals to the first circuit components 230. The printed circuit board 104 can be arranged on one side of the flexible printed circuit 102 and can be electrically connected to the flexible printed circuit 102. Various components for supplying various signals to the first circuit components 230 can be arranged on the printed circuit board 104. For example, various second circuit components 240, such as a timing controller, a power supply, a memory, or a processor, can be arranged on the printed circuit board 104. For example, the second circuit components 240 arranged on the printed circuit board 104 can include a timing controller and / or a power management integrated circuit (PMIC), but embodiments of the present disclosure are not limited thereto.

[0073] ​The printed circuit board 104 can include at least one hole, but embodiments of the present disclosure are not limited thereto. Internal components (e.g., a plurality of sensors) that detect ambient light or temperature can be disposed in an area corresponding to the at least one hole. For example, the internal components can include an ambient light sensor (ALS) or a temperature sensor, but embodiments of the present disclosure are not limited thereto. For example, the hole can be a transmission hole, but embodiments of the present disclosure are not limited thereto.

[0074] Referring to Figure 1 The polarization layer 114 can be disposed on the display panel 110 and can prevent or reduce light generated from an external light source from entering the display panel 110 and affecting the light emitting device.

[0075] The cover member 118 can be disposed on the polarization layer 114 and can be a member for protecting the display panel 110.

[0076] The second adhesive layer 116 can be disposed between the polarization layer 114 and the cover member 118. The second adhesive layer 116 can attach the cover member 118 to the display panel 110 or the polarization layer 114.

[0077] The first adhesive layer 112 can be disposed between the display panel 110 and the polarization layer 114. The first adhesive layer 112 can attach the polarization layer 114 to the display panel 110. The first adhesive layer 112 can be omitted.

[0078] Each of the first adhesive layer 112 and the second adhesive layer 116 can include an optical clear adhesive (OCA), an optical clear resin (OCR), or a pressure sensitive adhesive (PSA), but embodiments of the present disclosure are not limited thereto.

[0079] The support substrate 106 is disposed between the display panel 110 and the printed circuit board 104 to reinforce the rigidity of the display panel 110. The support substrate 106 can be a back plate, but embodiments of the present disclosure are not limited thereto.

[0080] Figure 3 is a plan view of the display panel 110 according to an embodiment of the present disclosure, and Figure 4 is a plan view of a unit driving area UDA of the display panel 110 according to an embodiment of the present disclosure.

[0081] Referring to Figure 3 The display area DA of the display panel 110 according to an embodiment of the present disclosure can include a plurality of unit driving areas UDA.

[0082] Referring to Figure 3According to an embodiment of the disclosure, the display panel 110 can include a driver DRV disposed in each of the plurality of unit driving areas UDAs. For example, the driver DRV can be a driving chip manufactured on a semiconductor substrate using a MOSFET (Metal Oxide Silicon Field Effect Transistor) manufacturing process, but embodiments of the disclosure are not limited thereto.

[0083] Referring to Figure 3 Each of the plurality of unit driving areas UDAs can be a driving area driven by one driver DRV. That is, the plurality of unit driving areas UDAs can be independent driving areas driven by different drivers DRV.

[0084] Referring to Figure 3 According to an embodiment of the disclosure, the display panel 110 can include a substrate 210 including a display area DA and a plurality of pixels P arranged in the display area DA in a matrix form.

[0085] The plurality of pixels P can be arranged in each of the plurality of unit driving areas UDAs. Each of the plurality of pixels P can include a plurality of sub-pixels SP. Each sub-pixel SP can include at least one light emitting device.

[0086] For example, the plurality of sub-pixels SP can include a first sub-pixel SPa, a second sub-pixel SPb, and a third sub-pixel SPc, but are not limited thereto. The first sub-pixel SPa can include a first light emitting device emitting first color light, the second sub-pixel SPb can include a second light emitting device emitting second color light, and the third sub-pixel SPc can include a third light emitting device emitting third color light. For example, the first color light, the second color light, and the third color light can be red light, green light, and blue light, respectively, but are not limited thereto.

[0087] Referring to Figure 4 According to an embodiment of the disclosure, the display panel 110 can include a plurality of light emitting devices ED. Each of the plurality of sub-pixels SP can include a light emitting device ED.

[0088] For example, the first sub-pixel SPa can include a first light emitting device EDa, the second sub-pixel SPb can include a second light emitting device EDb, and the third sub-pixel SPc can include a third light emitting device EDc.

[0089] Referring to Figure 4 According to an embodiment of the disclosure, the display panel 110 can include a plurality of row lines RL and a plurality of column lines CL.

[0090] Each of the plurality of row lines RL can be arranged to extend in a row direction. The plurality of row lines RL can be electrically connected to a first electrode of each of the plurality of light emitting devices ED.

[0091] Each of the plurality of column lines CL can be arranged to extend in a column direction. The plurality of column lines CL can be electrically connected to the second electrode of each of the plurality of light emitting devices ED.

[0092] For example, the first electrode of each of the plurality of light emitting devices ED can be an anode electrode, and the second electrode of each of the plurality of light emitting devices ED can be a cathode electrode. For another example, the first electrode of each of the plurality of light emitting devices ED can be a cathode electrode, and the second electrode of each of the plurality of light emitting devices ED can be an anode electrode.

[0093] Each of the plurality of row lines RL can be electrically connected to the second electrode of each of the plurality of light emitting devices ED. That is, the second electrode of each of the plurality of light emitting devices ED can be commonly connected to one row line RL.

[0094] Each of the plurality of column lines CL can be electrically connected to the first electrode of each of the plurality of light emitting devices ED. That is, the first electrode of each of the plurality of light emitting devices ED can be commonly connected to one column line CL.

[0095] Referring to Figure 4 , the line width of each of the plurality of row lines RL can be greater than the line width of each of the plurality of column lines CL.

[0096] Referring to Figure 4 The display panel 110 according to an embodiment of the disclosure can include a plurality of drivers DRV. The plurality of drivers DRV can drive the plurality of light emitting devices ED, the plurality of column lines CL, and the plurality of row lines RL.

[0097] The plurality of drivers DRV can be constructed in the display panel 110. The plurality of drivers DRV can be arranged in the display area DA and can be arranged on the substrate 210. The plurality of drivers DRV can be arranged to correspond to the plurality of unit driving areas UDA. That is, one driver DRV can be arranged in one unit driving area UDA.

[0098] Each of the plurality of drivers DRV can drive the plurality of row lines RL and the plurality of column lines CL arranged in a corresponding unit driving area UDA among the plurality of unit driving areas UDA, thereby emitting light from the plurality of light emitting devices ED arranged in the corresponding unit driving area UDA.

[0099] The plurality of drivers DRV are disposed in the display area DA and can be positioned closer to the substrate 210 than the plurality of light emitting devices ED.

[0100] For example, the plurality of row lines RL can be sequentially driven. For another example, the plurality of row lines RL can be simultaneously driven. For another example, two or more of the plurality of row lines RL can be simultaneously driven.

[0101] For example, during a particular display driving period, among the plurality of row lines RL arranged in the unit driving region UDA, at least one row line RL can be driven, and the remaining row lines RL can not be driven.

[0102] According to an embodiment of the present disclosure, a voltage applied to a row line RL can be referred to as a low potential voltage, and the low potential voltage can also be referred to as a row line voltage or a cathode voltage. The low potential voltage can have various voltage values depending on a driving type or a driving state. For example, the low potential voltage can include a first low potential voltage, a second low potential voltage, and a third low potential voltage.

[0103] Driving a row line RL can mean that a first low potential voltage is supplied to the row line RL. Not driving a row line RL can mean that a second low potential voltage higher than the first low potential voltage is supplied to the row line RL. Thus, the light emitting device ED overlapping the driven row line RL can emit light, and the light emitting device ED overlapping the non-driven row line RL can not emit light.

[0104] For example, any first row line RL of the plurality of row lines RL can be supplied with a first low potential voltage during a first period, and can be supplied with a second low potential voltage higher than the first low potential voltage during a second period different from the first period. Thus, the light emitting device ED overlapping the first row line RL can emit light during the first period, and can not emit light during the second period different from the first period. For example, the first period and the second period can be included in one display driving period. For another example, the first period and the second period can be included in different display driving periods.

[0105] A structure of one unit driving region UDA will be described in more detail. Figure 4 A structure of one unit driving region UDA will be described in more detail.

[0106] Referring to FIG. 1, one unit driving region UDA can be divided into a first sub driving region SDA1 and a second sub driving region SDA2. Figure 4 For example, one unit driving region UDA can be divided into a first sub driving region SDA1 and a second sub driving region SDA2. For another example, one unit driving region UDA can be divided into three or more sub driving regions. For another example, one unit driving region UDA can not be divided into two or more sub driving regions.

[0107] Referring to FIG. 1, one unit driving region UDA can be divided into a first sub driving region SDA1 and a second sub driving region SDA2. Figure 4, one unit driving area UDA can include one driver DRV and (2n x m) pixels P(1, 1), …, P(1, m), P(2, 1), …, P(2, m), …, P(2n, 1), …, P(2n, m) driven by the one driver DRV.

[0108] In embodiments of the present disclosure, n can be a serial number of a row, or a number of rows in each of the first sub-driving area SDA1 and the second sub-driving area SDA2, or a number of row lines RL in each of the first sub-driving area SDA1 and the second sub-driving area SDA2, or a number of pixel rows in each of the first sub-driving area SDA1 and the second sub-driving area SDA2. m can be a serial number of a column, or a number of columns in each of the first sub-driving area SDA1 and the second sub-driving area SDA2, or a number of column lines CL in each of the first sub-driving area SDA1 and the second sub-driving area SDA2, or a number of pixel columns in each of the first sub-driving area SDA1 and the second sub-driving area SDA2.

[0109] In embodiments of the present disclosure, n can be a natural number greater than or equal to 1, and m can be a natural number greater than or equal to 1.

[0110] Reference is made to Figure 4 , the (2n x m) pixels P(1, 1), …, P(1, m), P(2, 1), …, P(2, m), …, P(2n, 1), …, P(2n, m) can be arranged into 2n rows R(1), …, R(2n) and m columns C(1), …, C(m).

[0111] In the (2n x m) pixels P(1, 1), …, P(1, m), P(2, 1), …, P(2, m), …, P(2n, 1), …, P(2n, m), the (n x m) pixels P(1, 1), …, P(1, m), P(2, 1), …, P(2, m), …, P(n, 1), …, P(n, m) arranged in the first row R(1) to the n-th row R(n) can be arranged in the first sub-driving area SDA1.

[0112] In the (2n x m) pixels P(1, 1), …, P(1, m), P(2, 1), …, P(2, m), …, P(2n, 1), …, P(2n, m), the (n x m) pixels P(n+1, 1), …, P(n+1, m), P(n+2, 1), …, P(n+2, m), …, P(2n, 1), …, P(2n, m) arranged in the (n+1)-th row R(n+1) to the 2n-th row R(2n) can be arranged in the second sub-driving area SDA2.

[0113] refer to Figure 4 A unit driving region UDA can include 2n line lines RL(1), ..., RL(2n) to drive (2n×m) pixels P(1,1), ..., P(1,m), P(2,1), ..., P(2,m), ..., P(2n,1), ..., P(2n,m).

[0114] In the 2n row lines RL(1),…,RL(2n), the first to the nth row lines RL(1),…,RL(n) can be arranged in the first sub-driving region SDA1. In the 2n row lines RL(1),…,RL(2n), the (n+1)th to the 2nth row lines RL(n+1),…,RL(2n) can be arranged in the second sub-driving region SDA2.

[0115] Each of the 2n row lines RL(1),…,RL(2n) can overlap with m pixels. For example, the first row line RL(1) can overlap with m pixels P(1,1),…,P(1,m) arranged in the first row R(1). The nth row line RL(n) can overlap with m pixels P(n,1),…,P(n,m) arranged in the nth row R(n). The (n+1)th row line RL(n+1) can overlap with m pixels P(n+1,1),…,P(n+1,m) arranged in the (n+1)th row R(n+1). The 2nth row line RL(2n) can overlap with m pixels P(2n,1),…,P(2n,m) arranged in the 2nth row R(2n).

[0116] For example, the first row line RL(1) can be connected to k sub-pixels SPa, SPb, and SPc in each of the m pixels P(1,1),...,P(1,m) arranged in the first row R(1). More specifically, the first row line RL(1) can be connected to the second electrode of the k light-emitting devices EDa, EDb, and EDc in each of the m pixels P(1,1),...,P(1,m) arranged in the first row R(1).

[0117] For example, the nth row line RL(n) can be connected to k sub-pixels SPa, SPb, and SPc in each of the m pixels P(n,1),...,P(n,m) arranged in the nth row R(n). More specifically, the nth row line RL(n) can be connected to the first electrode of the k light-emitting devices EDa, EDb, and EDc in each of the m pixels P(n,1),...,P(n,m) arranged in the nth row R(n).

[0118] For example, the (n+1)th row line RL(n+1) can be connected to the k sub-pixels SPa, SPb, and SPc included in each of the m pixels P(n+1,1), …, P(n+1,m) arranged in the (n+1)th row R(n+1). More specifically, the (n+1)th row line RL(n+1) can be connected to the first electrodes of the k light emitting devices EDa, EDb, and EDc included in each of the m pixels P(n+1,1), …, P(n+1,m) arranged in the (n+1)th row R(n+1).

[0119] For example, the 2nth row line RL(2n) can be connected to the k sub-pixels SPa, SPb, and SPc included in each of the m pixels P(2n,1), …, P(2n,m) arranged in the 2nth row R(2n). More specifically, the 2nth row line RL(2n) can be connected to the first electrodes of the k light emitting devices EDa, EDb, and EDc included in each of the m pixels P(2n,1), …, P(2n,m) arranged in the 2nth row R(2n).

[0120] Referring to Figure 4 , one unit driving area UDA can include (m×k×2) column lines CL to drive (2n×m) pixels P(1,1), …, P(1,m), P(2,1), …, P(2,m), …, P(2n,1), …, P(2n,m). Here, k is the number of sub-pixels SP included in one pixel P. In Figure 4 , k is 3. That is, one pixel P can include three sub-pixels SPa, SPb, and SPc.

[0121] The first sub driving area SDA1 can include (m×k) column lines CL to drive (n×m) pixels P(1,1), …, P(1,m), …, P(n,1), …, P(n,m) arranged in the first sub driving area SDA1. Here, k is the number of sub-pixels SP included in one pixel P. In Figure 4 , since k is 3, the first sub driving area SDA1 can include 3m column lines CL.

[0122] In the first sub driving area SDA1, k column lines CLa, CLb, and CLb can be arranged in each of m columns C(1), …, C(m). In Figure 4 , since k is 3, in the first sub driving area SDA1, each of m columns C(1), …, C(m) can include three column lines CLa, CLb, and CLc.

[0123] In each of the m columns C(1), C(m), each of the k column lines CL can be commonly connected to the n pixels arranged in the respective column. In each of the m columns C(1), C(m), each of the k column lines CL can be commonly connected to the first electrodes of the n light emitting devices ED arranged in the respective column. In Figure 4 In the example of FIG. 10, since k is 3, in each of the m columns C(1), C(m), three column lines CLa, CLb, and CLc can be connected to the first electrodes of 3n light emitting devices ED included in the n pixels arranged in the respective column. For example, in each of the m columns C(1), C(m), the first column line CLa can be commonly connected to the first electrodes of the n first light emitting devices EDa arranged in the respective column. In each of the m columns C(1), C(m), the second column line CLb can be commonly connected to the first electrodes of the n second light emitting devices EDb arranged in the respective column. In each of the m columns C(1), C(m), the third column line CLc can be commonly connected to the first electrodes of the n third light emitting devices EDc arranged in the respective column.

[0124] The second sub-driving region SDA2 can include (m x k) column lines CL to drive the (n x m) pixels P(n+1, 1), P(n+1, m), P(2n, 1), P(2n, m) arranged in the second sub-driving region SDA2. In Figure 4 In the example of FIG. 10, since k is 3, the second sub-driving region SDA2 can include 3m column lines CL.

[0125] In the second sub-driving region SDA2, the k column lines CL can be arranged in each of the m columns C(1), C(m). In Figure 4 In the example of FIG. 10, since k is 3, in the second sub-driving region SDA2, each of the m columns C(1), C(m) can include three column lines CLa, CLb, and CLc.

[0126] In each of the m columns C(1), C(m), each of the k column lines CL can be commonly connected to the n pixels arranged in the respective column. In each of the m columns C(1), C(m), each of the k column lines CL can be commonly connected to the first electrodes of the n light emitting devices ED arranged in the respective column. In Figure 4In the example of FIG. 1, since k is 3, in each of the m columns C(1), …, C(m), three column lines CLa, CLb, and CLc can be connected to the first electrodes of 3n light emitting devices ED included in the n pixels arranged in the respective columns. For example, in each of the m columns C(1), …, C(m), the first column line CLa can be commonly connected to the first electrodes of n first light emitting devices EDa arranged in the respective columns. In each of the m columns C(1), …, C(m), the second column line CLb can be commonly connected to the first electrodes of n second light emitting devices EDb arranged in the respective columns. In each of the m columns C(1), …, C(m), the third column line CLc can be commonly connected to the first electrodes of n third light emitting devices EDc arranged in the respective columns.

[0127] Figure 5 A sub-pixel SP of the display panel 110 according to an embodiment of the disclosure is illustrated.

[0128] Referring to Figure 5 , a sub-pixel SP according to an embodiment of the disclosure can include a light emitting device ED including a first electrode Ecl and a second electrode Erl, a column driver C-DRV for driving a column line CL electrically connected to the first electrode Ecl of the light emitting device ED, and a row driver R-DRV for driving a row line RL electrically connected to the second electrode Erl of the light emitting device ED.

[0129] Referring to Figure 5 , the light emitting device ED can include the first electrode Ecl and the second electrode Erl. The first electrode Ecl can be electrically connected to the column line CL, and the second electrode Erl can be electrically connected to the row line RL. For example, the first electrode Ecl can be an anode electrode, and the second electrode Erl can be a cathode electrode. For another example, the first electrode Ecl can be a cathode electrode, and the second electrode Erl can be an anode electrode.

[0130] Referring to Figure 5 , the column driver C-DRV included in the unit driving area UDA can be connected to and can drive the plurality of column lines CL included in the unit driving area UDA. Each of the plurality of column lines CL can be commonly connected to the first electrode Ecl of each of the plurality of light emitting devices ED included in the plurality of sub-pixels SP arranged in the respective columns.

[0131] Referring to Figure 5The row driver R-DRV included in the unit driving area UDA can be connected to and can drive the plurality of row lines RL included in the unit driving area UDA. Each of the plurality of row lines RL can be commonly connected to the second electrode Erl of each of the plurality of light emitting devices ED included in the plurality of sub-pixels SP arranged in a corresponding row.

[0132] Referring to Figure 5 The column driver C-DRV can include a main node including a first node N1, a second node N2, a third node N3, and a fourth node N4. The column driver C-DRV can include a driving transistor DRT and a first emission control transistor EMT1.

[0133] The first node N1 can be a node to which a voltage Vg for controlling the turn-on and turn-off of the driving transistor DRT is applied. The second node N2 can be a node electrically connected to a high potential voltage node NVDD to which a high potential voltage VDD is applied. The third node N3 can be a node to which the driving transistor DRT and the first emission control transistor EMT1 are connected. The fourth node N4 can be a node to which the first emission control transistor EMT1 and the light emitting device ED are electrically connected, and can be a node to which the column line CL is electrically connected. Here, the source or drain of the first emission control transistor EMT1 and the first electrode Ecl of the light emitting device ED can be commonly connected to the column line CL.

[0134] The driving transistor DRT supplies a driving current to cause the light emitting device ED to emit light, is connected between the second node N2 and the third node N3, and can control the connection between the second node N2 and the third node N3 according to the voltage of the first node N1.

[0135] The gate of the driving transistor DRT is electrically connected to the first node N1, and a gate voltage Vg can be applied to the first node N1. The drain or source of the driving transistor DRT can be electrically connected to the second node N2. The source or drain of the driving transistor DRT can be electrically connected to the third node N3.

[0136] The first emission control transistor EMT1 can control the connection of a path through which a driving current flows, and can play a role in controlling the emission of light of the light emitting device ED.

[0137] If the driving transistor DRT and the first emission control transistor EMT1 are turned on between the high potential voltage VDD and the low potential voltage VSS, a driving current can be supplied to the light emitting device ED through the driving transistor DRT and the first emission control transistor EMT1. Accordingly, the light emitting device ED can emit light.

[0138] The first emission control transistor EMT1 is connected between the third node N3 and the fourth node N4, and can control a connection between the third node N3 and the fourth node N4 according to a first emission control signal EM1. The first emission control signal EM1 can be applied to a gate of the first emission control transistor EMT1. A drain or a source of the first emission control transistor EMT1 can be electrically connected to the third node N3. A source or a drain of the first emission control transistor EMT1 can be electrically connected to the fourth node N4.

[0139] The first emission control signal EM1 can be a pulse width modulation signal that varies at a predetermined time (e.g., every frame, or every sub-frame included in one frame), but embodiments of the present disclosure are not limited thereto.

[0140] The first emission control signal EM1 can be generated by the driver DRV, or can be supplied to the driver DRV from a driving-related circuit such as a timing controller. For example, if the first emission control signal EM1 is a pulse width modulation signal, the first emission control signal EM1 can have a pulse width corresponding to an image signal (e.g., a data voltage, a data signal). For example, if the pulse width of the first emission control signal EM1 is large, the luminance of the light emitting device ED can be high. If the pulse width of the first emission control signal EM1 is small, the luminance of the light emitting device ED can be low.

[0141] Referring to Figure 5 The row driver R-DRV can drive at least one row line RL by supplying a low potential voltage VSS to the at least one row line RL.

[0142] The row driver R-DRV can perform display-on driving or display-off driving with respect to one row line RL.

[0143] The row driver R-DRV can supply a low potential voltage for display-on driving to one row line RL in order to perform display-on driving with respect to the one row line RL. The row driver R-DRV can supply a low potential voltage for display-off driving to one row line RL in order to perform display-off driving with respect to the one row line RL.

[0144] The low potential voltage for display-on driving and the low potential voltage for display-off driving can be different. For example, the low potential voltage for display-on driving can be lower than the low potential voltage for display-off driving. In embodiments of the present disclosure, the "low potential voltage for display-on driving" is also referred to as a "first low potential voltage", and the "low potential voltage for display-off driving" is also referred to as a "second low potential voltage".

[0145] Referring to Figure 5The column driver C-DRV can further include at least one switching element and / or at least one transistor, except for the driving transistor DRT and the first emission control transistor EMT1. Each transistor included in the column driver C-DRV can be an n-type transistor or a p-type transistor.

[0146] The column driver C-DRV can further include at least one capacitor.

[0147] The column driver C-DRV can further include at least one circuit element. For example, the at least one circuit element can include a power output buffer.

[0148] Referring to Figure 5 The row driver R-DRV can include at least one switching element and / or at least one transistor. Each transistor included in the row driver R-DRV can be an n-type transistor or a p-type transistor.

[0149] The row driver R-DRV can further include at least one circuit element. For example, the at least one circuit element can include a power output buffer.

[0150] Referring to Figure 5 The column driver C-DRV and the row driver R-DRV can be internal circuits included in the driver DRV. For another example, the column driver C-DRV and the row driver R-DRV can not be included in the driver DRV and can be circuits formed on the substrate 210 of the display panel 110.

[0151] Figure 6 is an equivalent circuit diagram of a unit driving area UDA of the display panel 110 according to an embodiment of the disclosure. In the following description, reference is also made to Figure 4 and Figure 5 .

[0152] Referring to Figure 6 Each of the plurality of unit driving areas UDA can correspond to one of the plurality of drivers DRV. For example, one of the plurality of drivers DRV can be arranged in each of the plurality of unit driving areas UDA.

[0153] Referring to Figure 6 Each of the plurality of unit driving areas UDA can include two or more row lines RL(1) to RL(2n) among all the row lines RL arranged in the display panel 110 and two or more column lines CL among all the column lines CL arranged in the display panel 110.

[0154] Referring to Figure 6Each of the plurality of unit driving areas UDA can include a first sub driving area SDA1 and a second sub driving area SDA2. Some of the two or more row lines RL(1) to RL(2n) can be arranged in the first sub driving area SDA1, and the remaining row lines can be arranged in the second sub driving area SDA2. Some of the two or more column lines CL can be arranged in the first sub driving area SDA1, and the remaining column lines can be arranged in the second sub driving area SDA2.

[0155] Referring to Figure 6 Each of the plurality of unit driving areas UDA can include a plurality of pixels P(1,1), …, P(1,m), P(2,1), …, P(2,m), …, P(2n,1), …, P(2n,m) arranged in a matrix form.

[0156] Each of the plurality of pixels P(1,1), …, P(1,m), P(2,1), …, P(2,m), …, P(2n,1), …, P(2n,m) can include k sub-pixels SPa, SPb, and SPc. The k sub-pixels SPa, SPb, and SPc can include k light emitting devices EDa, EDb, and EDc.

[0157] Some of the plurality of pixels P(1,1), …, P(1,m), P(2,1), …, P(2,m), …, P(2n,1), …, P(2n,m) can be arranged in the first sub driving area SDA1, and the remaining pixels can be arranged in the second sub driving area SDA2.

[0158] where k is the number of sub-pixels included in one pixel. In Figure 6 In an example of k = 3, one pixel can include three sub-pixels SPa, SPb, and SPc. The structure of the unit driving area UDA will be exemplarily explained below with k = 3 as an example.

[0159] The unit driving area UDA can include (2n x m) pixels P(1,1), …, P(1,m), P(2,1), …, P(2,m), …, P(2n,1), …, P(2n,m). The (2n x m) pixels P(1,1), …, P(1,m), P(2,1), …, P(2,m), …, P(2n,1), …, P(2n,m) can be arranged in 2n rows and m columns.

[0160] According to Figure 6Each of the (2n x m) pixels P(1,1),..., P(1,m), P(2,1),..., P(2,m),..., P(2n,1),..., P(2n,m) can include three sub-pixels SPa, SPb, and SPc, according to an example.

[0161] According to Figure 6 The three sub-pixels can include a first sub-pixel SPa, a second sub-pixel SPb, and a third sub-pixel SPc, the first sub-pixel SPa includes a first light emitting device EDa, the second sub-pixel SPb includes a second light emitting device EDb, and the third sub-pixel SPc includes a third light emitting device EDc, according to an example.

[0162] Half of the (2n x m) pixels P(1,1),..., P(1,m), P(2,1),..., P(2,m),..., P(2n,1),..., P(2n,m), that is, (n x m) pixels P(1,1),..., P(1,m),..., P(n,1),..., P(n,m) can be arranged in the first sub-driving area SDA1.

[0163] The remaining half (n x m) pixels P(n+1,1),..., P(n+1,m),..., P(2n,1),..., P(2n,m) of the (2n x m) pixels P(1,1),..., P(1,m), P(2,1),..., P(2,m),..., P(2n,1),..., P(2n,m) can be arranged in the second sub-driving area SDA2.

[0164] According to Figure 6 The unit driving area UDA can include 2n row lines RL(1) to RL(2n) and (m x 3 x 2) column lines CL, according to an example.

[0165] Referring to Figure 6 The n row lines RL(1) to RL(n) (which is half of the 2n row lines RL(1) to RL(2n)) can be arranged in the first sub-driving area SDA1, and the n row lines RL(n+1) to RL(2n) (which is the remaining half of the 2n row lines RL(1) to RL(2n)) can be arranged in the second sub-driving area SDA2.

[0166] The n row lines RL(1) to RL(n) arranged in the first sub-driving area SDA1 can correspond to the (n x m) pixels P(1,1),..., P(1,m),..., P(n,1),..., P(n,m) arranged in the first sub-driving area SDA1 by rows (i.e., pixel rows).

[0167] For example, among the n row lines RL(1)-RL(n) arranged in the first sub-driving region SDA1, a first row line RL(1) arranged in a first row (i.e., a first pixel row) can correspond to m pixels P(1,1),..., P(1,m) included in the first pixel row. The first row line RL(1) can be electrically connected to all of the second electrodes Erl of each of the 3m light emitting devices ED included in the first pixel row.

[0168] For another example, among the n row lines RL(1)-RL(n) arranged in the first sub-driving region SDA1, a second row line RL(2) arranged in a second row (i.e., a second pixel row) can correspond to m pixels P(2,1),..., P(2,m) included in the second pixel row. The second row line RL(2) can be electrically connected to all of the second electrodes Erl of each of the 3m light emitting devices ED included in the second pixel row.

[0169] For another example, among the n row lines RL(1)-RL(n) arranged in the first sub-driving region SDA1, an n-th row line RL(n) arranged in an n-th row (i.e., an n-th pixel row) can correspond to m pixels P(n,1),..., P(n,m) included in the n-th pixel row. The n-th row line RL(n) can be electrically connected to all of the second electrodes Erl of each of the 3m light emitting devices ED included in the n-th pixel row.

[0170] The n rows RL(n+1) to RL(2n) arranged in the second sub-driving region SDA2 can correspond to (n x m) pixels P(n+1,1),..., P(n+1,m),..., P(2n,1),..., P(2n,m) arranged by row (i.e., pixel row) in the second sub-driving region SDA2.

[0171] For example, among the n row lines RL(n+1) to RL(2n) arranged in the second sub-driving region SDA2, an (n+1)-th row line RL(n+1) arranged in an (n+1)-th row (i.e., an (n+1)-th pixel row) can correspond to m pixels P(n+1,1),..., P(n+1,m) included in the (n+1)-th pixel row. The (n+1)-th row line RL(n+1) can be electrically connected to all of the second electrodes Erl of each of the 3m light emitting devices ED included in the (n+1)-th pixel row.

[0172] For example, in the n row lines RL(n+1) to RL(2n) arranged in the second sub-driving region SDA2, the (2n-1)th row line RL(2n-1) arranged in the (2n-1)th row (i.e., the (2n-1)th pixel row) can correspond to the m pixels P(2n-1,1), …, P(2n-1,m) included in the (2n-1)th pixel row. The (2n-1)th row line RL(2n-1) can be electrically connected to all the second electrodes Erl of each of the 3m light emitting devices ED included in the (2n-1)th pixel row.

[0173] For example, in the n row lines RL(n+1) to RL(2n) arranged in the second sub-driving region SDA2, the (2n-1)th row line RL(2n-1) arranged in the (2n-1)th row (i.e., the (2n-1)th pixel row) can correspond to the m pixels P(2n-1,1), …, P(2n-1,m) included in the (2n-1)th pixel row. The (2n-1)th row line RL(2n-1) can be electrically connected to all the second electrodes Erl of each of the 3m light emitting devices ED included in the (2n-1)th pixel row.

[0174] Referring to FIG. 1, the 3m column lines CL arranged in the first sub-driving region SDA1 can correspond to the (n×m) pixels P(1,1), …, P(1,m), …, P(n,1), …, P(n,m) placed in the first sub-driving region SDA1 by column (i.e., pixel column). Figure 6 Referring to FIG. 1, the 3m column lines CL arranged in the first sub-driving region SDA1 can correspond to the (n×m) pixels P(1,1), …, P(1,m), …, P(n,1), …, P(n,m) placed in the first sub-driving region SDA1 by column (i.e., pixel column).

[0175] Figure 6 For example, in the 3m column lines CL arranged in the first sub-driving region SDA1, the three first column lines CLa, CLb, and CLc arranged in the first column (i.e., the first pixel column) can correspond to the n pixels P(1,1), P(2,1), …, P(n,1) arranged in the first pixel column.

[0176] For example, in the 3m column lines CL arranged in the first sub-driving region SDA1, the three first column lines CLa, CLb, and CLc arranged in the first column (i.e., the first pixel column) can correspond to the n pixels P(1,1), P(2,1), …, P(n,1) arranged in the first pixel column.

[0177] In the first sub-driving region SDA1, the three first column lines CLa, CLb, and CLc arranged in the first pixel column can be connected to the three sub-pixels SPa, SPb, and SPc included in each of the n pixels P(1,1), P(2,1), …, P(n,1) arranged in the first pixel column.

[0178] ​In the first sub-driving region SDA1, the three mth column lines CLa, CLb, and CLc arranged in the mth column (i.e., the mth pixel column) can correspond to the n pixels P(1,m), P(2,m), …, P(n,m) arranged in the mth pixel column.

[0179] For example, among the 3m column lines CL arranged in the first sub-driving region SDA1, the three first column lines CLa, CLb, and CLc arranged in the first column (i.e., the first pixel column) can correspond to the n pixels P(1,1), P(2,1), …, P(n,1) arranged in the first pixel column.

[0180] In the first sub-driving region SDA1, the three mth column lines CLa, CLb, and CLc arranged in the mth pixel column can be connected to the three sub-pixels SPa, SPb, and SPc included in each of the n pixels P(1,m), P(2,m), …, P(n,m) arranged in the mth pixel column.

[0181] In the first sub-driving region SDA1, the three mth column lines CLa, CLb, and CLc arranged in the mth pixel column can be electrically connected to all the first electrodes Ecl of the three light emitting devices EDa, EDb, and EDc included in each of the n pixels P(1,m), P(2,m), …, P(n,m) arranged in the mth pixel column.

[0182] Reference Figure 6 Among the 3m column lines CL arranged in the second sub-driving region SDA2, the three first column lines CLa, CLb, and CLc arranged in the first column (i.e., the first pixel column) can correspond to the n pixels P(n+1,1), …, P(2n-1,1), P(2n,1) arranged in the first pixel column.

[0183] For example, among the 3m column lines CL arranged in the second sub-driving region SDA2, the three first column lines CLa, CLb, and CLc arranged in the first column (i.e., the first pixel column) can correspond to the n pixels P(n+1,1), …, P(2n-1,1), P(2n,1) arranged in the first pixel column.

[0184] In the second sub-driving region SDA2, the three first column lines CLa, CLb, and CLc arranged in the first pixel column can be connected to the three sub-pixels SPa, SPb, and SPc included in each of the n pixels P(n+1,1), …, P(2n-1,1), P(2n,1) arranged in the first pixel column.

[0185] In the second sub-driving region SDA2, the three first column lines CLa, CLb and CLc arranged in the first pixel column can be electrically connected to all the first electrodes Ecl of the three light-emitting devices EDa, EDb and EDc in each of the n pixels P(n+1,1),...,P(2n-1,1),P(2n,1) arranged in the first pixel column.

[0186] For example, in the 3m column lines CL arranged in the second sub-driving region SDA2, the three m-th column lines CLa, CLb and CLc arranged in the m-th column (i.e. the m-th pixel column) can correspond to the n pixels P(n+1,m),...,P(2n-1,m) and P(2n,m) arranged in the m-th pixel column.

[0187] In the second sub-driving region SDA2, the three m-th column lines CLa, CLb, and CLc arranged in the m-th pixel column can be connected to the three sub-pixels SPa, SPb, and SPc in each of the n pixels P(n+1,m),…,P(2n-1,m),P(2n,m) arranged in the m-th pixel column.

[0188] In the second sub-driving region SDA2, the three m-th column lines CLa, CLb and CLc arranged in the m-th pixel column can be electrically connected to all the first electrodes Ecl of the three light-emitting devices EDa, EDb and EDc included in each of the n pixels P(n+1,m),...,P(2n-1,m),P(2n,m) arranged in the m-th pixel column.

[0189] refer to Figure 6 Two or more row lines RL(1) to RL(2n) arranged in the cell drive area UDA can be electrically connected to the row driver R-DRV in the driver DRV included in the cell drive area UDA. Two or more column lines CL arranged in the cell drive area UDA can be electrically connected to the column driver C-DRV in the driver DRV included in the cell drive area UDA.

[0190] refer to Figure 6 The driver DRV can be arranged between the first sub-drive area SDA1 and the second sub-drive area SDA2.

[0191] Figure 7 A timing diagram showing the drive of n row lines RL(1) to RL(n) and one column line CL in a first sub-driving region SDA1 of a display panel 110 according to an embodiment of the present disclosure is shown. However, reference is also made to the following description. Figure 6 .

[0192] The row driver R-DRV of the driver DRV can drive the n rows of lines RL(1) to RL(n) arranged in the first sub-driving region SDA1.

[0193] The driving of each of the n rows of lines RL(1) to RL(n) arranged in the first sub-driving region SDA1 can include display-on driving of the light emitting devices ED arranged in each of the n rows of lines RL(1) to RL(n) and display-off driving of the light emitting devices ED arranged in each of the n rows of lines RL(1) to RL(n).

[0194] Hereinafter, the driving sequence of each of the n rows of lines RL(1) to RL(n) arranged in the first sub-driving region SDA1 will be exemplified.

[0195] For example, the display-on driving of each of the plurality of rows of lines RL can be sequentially performed. For another example, the display-on driving of each of the plurality of rows of lines RL can be simultaneously performed. For yet another example, the display-on driving of each of two or more of the plurality of rows of lines RL can be simultaneously performed. Hereinafter, for convenience of explanation, a case in which the display-on driving of each of the plurality of rows of lines RL is sequentially performed will be described as an example. However, the present disclosure is not limited thereto.

[0196] The row driver R-DRV of the driver DRV can sequentially drive the n rows of lines RL(1) to RL(n) arranged in the first sub-driving region SDA1. That is, the display-on driving periods D_ON(1) to D_ON(n) of the n rows of lines RL(1) to RL(n) arranged in the first sub-driving region SDA1 can be sequential.

[0197] In the n rows of lines RL(1) to RL(n) arranged in the first sub-driving region SDA1, for any one row of line RL, the display-on driving period D_ON(1) of the corresponding row of line RL can exist at least once during the display driving period D. During the display driving period D, all of the remaining time other than the display-on driving period D_ON(1) of the corresponding row of line RL can be a display-off driving period.

[0198] Reference Figure 7 During any one display driving period D, in the n rows of lines RL(1) to RL(n) arranged in the unit driving region UDA, display-on driving can be performed for at least one row of line RL and display-off driving can be performed for the remaining rows of line RL.

[0199] For example, during any one display driving period D, among n row lines RL(1) to RL(n) arranged in the unit driving area UDA, display-on driving can be performed for the first row line RL(1), and display-off driving can be performed for the second to nth row lines RL(2) to RL(n).

[0200] For another example, during any one display driving period D, among n row lines RL(1) to RL(n) arranged in the unit driving area UDA, display-on driving can be performed for the second row line RL(2), and display-on driving can not be performed for the first row line RL(1) and the third to nth row lines RL(3) to RL(n).

[0201] For another example, during any one display driving period D, among n row lines RL(1) to RL(n) arranged in the unit driving area UDA, display-on driving can be performed for the third row line RL(3), and display-off driving instead of display-on driving can be performed for the first row line RL(1), the second row line RL(2), and the fourth to nth row lines RL(4) to RL(n).

[0202] For another example, during any one display driving period D, among n row lines RL(1) to RL(n) arranged in the unit driving area UDA, display-on driving can be performed for the (n-1)th row line RL(n-1), and display-off driving instead of display-on driving can be performed for the first to (n-2)th row lines RL(1) to RL(n-2) and the nth row line RL(n).

[0203] For another example, during any one display driving period D, among n row lines RL(1) to RL(n) arranged in the unit driving area UDA, display-on driving can be performed for the nth row line RL(n), and display-off driving instead of display-on driving can be performed for the first to (n-1)th row lines RL(1) to RL(n-1).

[0204] Reference Figure 7 If display-on driving is performed for any row line RL among n row lines RL(1) to RL(n) arranged in the unit driving area UDA, it can mean that a first low-potential voltage VSS1 of a predetermined level is supplied to the corresponding row line RL. When display-on driving is performed for any row line RL, the light emitting device ED arranged corresponding to the respective row line RL can emit light.

[0205] When display-off driving is performed without display-on driving for any of the n row lines RL(1) to RL(n) arranged in the unit drive region UDA, it can mean that a second low potential voltage VSS2 of a predetermined level is supplied to the corresponding row line RL. The light emitting device ED arranged corresponding to the respective row line RL can not emit light when display-off driving is performed for the specific row line RL.

[0206] The first low potential voltage VSS1 can be a low potential voltage VSS for display-on driving, and the second low potential voltage VSS2 can be a low potential voltage VSS for display-off driving. The second low potential voltage VSS2 can be a voltage higher than the first low potential voltage VSS1.

[0207] Reference Figure 7 Any of the n row lines RL(1) to RL(n) arranged in the unit drive region UDA can be supplied with the first low potential voltage VSS1 during a first period, and can be supplied with a second low potential voltage VSS2 higher than the first low potential voltage VSS1 during a second period different from the first period. For example, the first period and the second period can be included in one display driving period D. For another example, the first period and the second period can be included in different display driving periods D.

[0208] For example, among the n row lines RL(1) to RL(n) arranged in the unit drive region UDA, the first row line RL(1) can be supplied with the first low potential voltage VSS1 during a first display-on driving period D_ON(1), and can be supplied with the second low potential voltage VSS2 higher than the first low potential voltage VSS1 during a second display-on driving period D_ON(2) to an n-th display-on driving period D_ON(n) different from the first display-on driving period D_ON(1).

[0209] For example, during the first display-on driving period D_ON(1), the first row line RL(1) can be supplied with the first low potential voltage VSS1, and the second to n-th row lines RL(2) to RL(n) can be supplied with the second low potential voltage VSS2. During the second display-on driving period D_ON(2), the second row line RL(2) can be supplied with the first low potential voltage VSS1, and the first row line RL(1) and the third to n-th row lines RL(3) to RL(n) can be supplied with the second low potential voltage VSS2.

[0210] For example, during a first display-on driving period D_ON(1), a plurality of light emitting devices ED overlapping with a first row line RL(1) and arranged in a first row can emit light, and a plurality of light emitting devices ED overlapping with second to nth row lines RL(2) to RL(n) and arranged in second to nth rows can not emit light. During a second display-on driving period D_ON(2), a plurality of light emitting devices ED overlapping with a second row line RL(2) and arranged in a second row can emit light, and a plurality of light emitting devices ED overlapping with a first row line RL(1) and third to nth row lines RL(3) to RL(n) and arranged in a first row and third to nth rows can not emit light.

[0211] For example, the first display-on driving period D_ON(1) and the second to nth display-on driving periods D_ON(2) to D_ON(n) can be included in one display driving period D. For another example, the first display-on driving period D_ON(1) and the second to nth display-on driving periods D_ON(2) to D_ON(n) can be included in different display driving periods D.

[0212] Referring to Figure 7 In the cell driving region UDA, the (m×k) column lines CL can intersect the n row lines RL(1) to RL(n). Figure 7 The column line CL shown in FIG. 1 can be one of the (m×k) column lines CL.

[0213] During the display driving period D, each of the (m×k) column lines CL intersecting the n row lines RL(1) to RL(n) can be supplied with a display voltage VEM required for a corresponding light emitting device ED to emit light in synchronization with a display-on driving period D_ON(1) to D_ON(n) of each of the n row lines RL(1) to RL(n). Here, the display voltage VEM can also be referred to as a light emission driving voltage or a reflection driving voltage.

[0214] During the display driving period D, a reset voltage VRST can be applied to each of the (m×k) column lines CL intersecting the n row lines RL(1) to RL(n) during all remaining time except for the display-on driving periods D_ON(1) to D_ON(n) of each of the n row lines RL(1) to RL(n).

[0215] The display voltage VEM can be a constant voltage or a voltage varying according to an image signal. The reset voltage VRST can be a voltage lower than the display voltage VEM, and can be a constant voltage or a variable voltage.

[0216] During the display driving period D, during a display-on driving period D_ON(1) to D_ON(n) of each of the n row lines RL(1) to RL(n), a voltage difference VEM-VSS1 between a display voltage VEM applied to the corresponding column line CL and a first low potential voltage VSS1 applied to the corresponding row line RL can be a display-on voltage ΔVon.

[0217] The light emitting device ED can be connected between the corresponding column line CL and the corresponding row line RL. The display voltage VEM and the first low potential voltage VSS1 can be applied to each of the first electrode Ecl and the second electrode Erl of the light emitting device ED.

[0218] The display-on voltage ΔVon is a voltage difference between the first electrode Ecl and the second electrode Erl of the light emitting device ED, and can be a voltage capable of causing the light emitting device ED to emit light. For example, the display-on voltage ΔVon can be equal to or higher than a threshold voltage, which is a unique characteristic value of the light emitting device ED.

[0219] During the display driving period D, during all remaining time except for the display-on driving period D_ON(1) to D_ON(n) of each of the n row lines RL(1) to RL(n), a voltage difference VRST-VSS2 between a reset voltage VRST applied to the corresponding column line CL and a second low potential voltage VSS2 applied to the corresponding row line RL can be a display-off voltage ΔVoff.

[0220] The light emitting device ED can be connected between the corresponding column line CL and the corresponding row line RL. The reset voltage VRST and the second low potential voltage VSS2 can be applied to each of the first electrode Ecl and the second electrode Erl of the light emitting device ED.

[0221] The display-off voltage ΔVoff is a voltage difference between the first electrode Ecl and the second electrode Erl of the corresponding light emitting device ED, and can be a voltage that does not allow the corresponding light emitting device ED to emit light. For example, the display-off voltage ΔVoff can be less than a threshold voltage, which is a unique characteristic of the corresponding light emitting device ED. That is, the display-on voltage ΔVon can be greater than or equal to the display-off voltage ΔVoff.

[0222] In order for the plurality of drivers DRV included in the display device 100 according to an embodiment of the disclosure to perform a driving operation, power required for the driving operation needs to be supplied to the plurality of drivers DRV. Accordingly, hereinafter, a power supply structure for supplying the power required for the driving operation to the plurality of drivers DRV will be described with reference to FIGS. 6 to 8. Figure 8

[0223] Figure 8 ​is a plan view of a display panel 110 according to an embodiment of the disclosure.

[0224] Referring to Figure 8 , a substrate 210 of a display panel 110 according to an embodiment of the disclosure can include a display area DA and a non-display area NDA, and the non-display area NDA can include a first non-display area NDA1, a bending area BA, and a second non-display area NDA2.

[0225] Referring to Figure 8 , a plurality of drivers DRV can be disposed in the display area DA. Each of the plurality of drivers DRV can be a circuit for driving light emitting devices of a plurality of sub-pixels included in a corresponding unit driving area (UDA) of the display panel 110. Figure 4 and 6 Each of the plurality of drivers DRV can include a row driver R-DRV for driving a plurality of row lines and a column driver C-DRV for driving a plurality of column lines, so as to drive a plurality of light emitting devices ED included in a corresponding unit driving area (UDA) of the display panel 110. Figure 4 and 6

[0226] Referring to Figure 8 , a pad portion 211 including a plurality of pads PD can be disposed in the second non-display area NDA2.

[0227] Referring to Figure 8 , a plurality of signal lines SL and a plurality of link lines LL for signal transmission between the plurality of drivers DRV disposed in the display area DA and the pad portion 211 can be disposed on the substrate 210. The plurality of signal lines SL can be electrically connected between the plurality of link lines LL and the plurality of drivers DRV. The plurality of link lines LL can electrically connect the plurality of pads PD and the plurality of signal lines SL.

[0228] Referring to Figure 8 , the plurality of link lines LL can be disposed in the non-display area NDA, and all or a part of each of the plurality of signal lines SL can be disposed in the display area DA.

[0229] Each of the plurality of drivers DRV can receive various signals to perform a driving operation through the plurality of link lines LL and the plurality of signal lines SL. Here, the various signals can include various power voltages and various signals required for a driving operation of each of the plurality of drivers DRV.

[0230] ​When the bending area BA is bent, a portion of the plurality of link lines LL can also be bent. Stress can concentrate on the portion of the link line LL that is bent, and thus a crack can occur in the link line LL. Accordingly, the plurality of link lines LL can be formed of a conductive material having excellent ductility to reduce a crack when the bending area BA is bent. For example, the plurality of link lines LL can be formed of a conductive material having excellent ductility, such as gold (Au), silver (Ag), aluminum (Al), but embodiments of the present disclosure are not limited thereto. In addition, the plurality of link lines LL can be composed of one of various conductive materials used in the display area DA. For example, the plurality of link lines LL can be composed of an alloy of silver (Ag) and magnesium (Mg), molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or an alloy thereof, but embodiments of the present disclosure are not limited thereto. The plurality of link lines LL can be composed of a multi-layer structure including various conductive materials. For example, the plurality of link lines LL can be composed of a three-layer structure of titanium (Ti) / aluminum (Al) / titanium (Ti), but embodiments of the present disclosure are not limited thereto.

[0231] The plurality of link lines LL can be formed in various shapes to reduce stress. At least a portion of the plurality of link lines LL disposed on the bending area BA can extend in the same direction as the extension direction of the bending area BA, or can extend in a direction different from the extension direction of the bending area BA to reduce stress. For example, if the bending area BA extends in one direction from the first non-display area NDA1 toward the second non-display area NDA2, at least a portion of the link lines LL disposed on the bending area BA can extend in a direction inclined from the one direction. For another example, at least a portion of the plurality of link lines LL can be configured in various shapes of patterns. For example, at least a portion of the plurality of link lines LL disposed on the bending area BA can be in a shape in which a conductive pattern is repeatedly arranged in at least one of a diamond shape, a lozenge shape, a trapezoidal wave shape, a triangular wave shape, a sawtooth wave shape, a sine wave shape, a circle, and an omega shape, but embodiments of the present disclosure are not limited thereto. Accordingly, to minimize stress concentrated on the plurality of link lines LL and a crack generated thereby, the shape of the plurality of link lines LL can be formed in various shapes including the above-described shapes, but embodiments of the present disclosure are not limited thereto.

[0232] Figure 9 A unit driving area UDA of the display panel 110 according to an embodiment of the present disclosure is illustrated. In the following description, reference is also made to Figure 3 and Figure 4 and the same content described with reference to Figure 3 and Figure 4 may be omitted.

[0233] Reference is made to Figure 9According to an example of the display panel 110 according to an embodiment of the disclosure, the plurality of pixels P can include (2n x m) pixels P(1,1), …, P(1,m), P(2,1), …, P(2,m), …, P(2n,1), …, P(2n,m) arranged in the unit driving area UDA. The plurality of row lines RL can include 2n row lines RL(1) to RL(2n) arranged in the unit driving area UDA.

[0234] According to an example of the display panel 110 according to an embodiment of the disclosure, the plurality of pixels P can include (2n x m) pixels P(1,1), …, P(1,m), P(2,1), …, P(2,m), …, P(2n,1), …, P(2n,m) arranged in the unit driving area UDA. The plurality of row lines RL can include 2n row lines RL(1) to RL(2n) arranged in the unit driving area UDA. Figure 9 According to an example of the display panel 110 according to an embodiment of the disclosure, the plurality of pixels P can include (2n x m) pixels P(1,1), …, P(1,m), P(2,1), …, P(2,m), …, P(2n,1), …, P(2n,m) arranged in the unit driving area UDA. The plurality of row lines RL can include 2n row lines RL(1) to RL(2n) arranged in the unit driving area UDA.

[0235] Figure 9 According to an example of the display panel 110 according to an embodiment of the disclosure, the plurality of pixels P can include (2n x m) pixels P(1,1), …, P(1,m), P(2,1), …, P(2,m), …, P(2n,1), …, P(2n,m) arranged in the unit driving area UDA. The plurality of row lines RL can include 2n row lines RL(1) to RL(2n) arranged in the unit driving area UDA.

[0236] According to an example of the display panel 110 according to an embodiment of the disclosure, the plurality of pixels P can include (2n x m) pixels P(1,1), …, P(1,m), P(2,1), …, P(2,m), …, P(2n,1), …, P(2n,m) arranged in the unit driving area UDA. The plurality of row lines RL can include 2n row lines RL(1) to RL(2n) arranged in the unit driving area UDA. Figure 9 According to an example of the display panel 110 according to an embodiment of the disclosure, the plurality of pixels P can include (2n x m) pixels P(1,1), …, P(1,m), P(2,1), …, P(2,m), …, P(2n,1), …, P(2n,m) arranged in the unit driving area UDA. The plurality of row lines RL can include 2n row lines RL(1) to RL(2n) arranged in the unit driving area UDA.

[0237] Figure 9 According to an example of the display panel 110 according to an embodiment of the disclosure, the plurality of pixels P can include (2n x m) pixels P(1,1), …, P(1,m), P(2,1), …, P(2,m), …, P(2n,1), …, P(2n,m) arranged in the unit driving area UDA. The plurality of row lines RL can include 2n row lines RL(1) to RL(2n) arranged in the unit driving area UDA.

[0238] The first sub-pixel SPa can include a first main sub-pixel SPa_M and a first redundant sub-pixel SPa_R. The first main sub-pixel SPa_M can include a first main light emitting device EDa_M, and the first redundant sub-pixel SPa_R can include a first redundant light emitting device EDa_R.

[0239] The first sub-pixel SPa can include a first light emitting device EDa that emits a first color light, and the first light emitting device EDa can include a first main light emitting device EDa_M and a first redundant light emitting device EDa_R.

[0240] The second sub-pixel SPb can include a second main sub-pixel SPb_M and a second redundant sub-pixel SPb_R. The second main sub-pixel SPb_M can include a second main light emitting device EDb_M, and the second redundant sub-pixel SPb_R can include a second redundant light emitting device EDb_R.

[0241] ​​The second sub-pixel SPb can include a second light emitting device EDb emitting a second color light, and the second light emitting device EDb can include a second main light emitting device EDb_M and a second redundant light emitting device EDb_R.

[0242] The third sub-pixel SPc can include a third main sub-pixel SPc_M and a third redundant sub-pixel SPc_R. The third main sub-pixel SPc_M can include a third main light emitting device EDc_M, and the third redundant sub-pixel SPc_R can include a third redundant light emitting device EDc_R.

[0243] The third sub-pixel SPc can include a third light emitting device EDc emitting a third color light, and the third light emitting device EDc can include a third main light emitting device EDc_M and a third redundant light emitting device EDc_R.

[0244] Referring to Figure 9 , the plurality of column lines CL can include a plurality of main column lines CLa_M, CLb_M, and CLc_M and a plurality of redundant column lines CLa_R, CLb_R, and CLc_R.

[0245] In each of the plurality of columns (i.e., the plurality of pixel columns) included in each of the first sub-driving area SDA1 and the second sub-driving area SDA2, k main column lines CLa_M, CLb_M, and CLc_M and k redundant column lines CLa_R, CLb_R, and CLc_R can be arranged.

[0246] In each column (i.e., each pixel column), the k main column lines CLa_M, CLb_M, and CLc_M can be connected to the first electrodes Ecl of the k main light emitting devices EDa_M, EDb_M, and EDc_M.

[0247] In each column (i.e., each pixel column), the k redundant column lines CLa_R, CLb_R, and CLc_R can be connected to the first electrodes Ecl of the k redundant light emitting devices EDa_R, EDb_R, and EDc_R.

[0248] Hereinafter, in order to examine the planar structure of the display panel 110 according to the embodiment of the disclosure in more detail, the planar structure of a portion 1100 of the plan view of Figure 9 will be described in more detail as an example.

[0249] Figure 12 and Figure 13 are plan views of the portion 1100 of the display panel 110 according to the embodiment of the disclosure.

[0250] Figure 10 and Figure 11 are Figure 9is an enlarged plan view of a portion 1100 of the plan view, and is an enlarged plan view of two rows and two columns of regions 1100.

[0251] Figure 10 is a plan view of the plan view without showing the two rows of lines RL(1) and RL(2) arranged in the two rows and two columns of regions 1100, and Figure 11 is a plan view of the plan view with the addition of the two rows of lines RL(1) and RL(2) arranged in the two rows and two columns of regions 1100. Figure 10 is a plan view of the plan view.

[0252] Referring to Figure 10 and Figure 11 , in the two rows and two columns of regions 1100, four pixels P(1,1), P(1,2), P(2,1), P(2,2) can be arranged in two rows and two columns. That is, in the two rows and two columns of regions 1100, two pixels P(1,1) and P(1,2) can be arranged in a first row (e.g., a first pixel row), and two pixels P(2,1) and P(2,2) can be arranged in a second row (e.g., a second pixel row). In addition, two pixels P(1,1) and P(2,1) can be arranged in a first column (e.g., a first pixel column), and two pixels P(1,2) and P(2,2) can be arranged in a second column (e.g., a second pixel column).

[0253] Referring to Figure 10 and Figure 11 , in the two rows and two columns of regions 1100, each of the four pixels P(1,1), P(1,2), P(2,1), and P(2,2) arranged in two rows and two columns can include k sub-pixels. Here, k is the number of sub-pixels included in one pixel.

[0254] In Figure 10 and Figure 11 , a case where k is 3 is exemplified. Thus, in the two rows and two columns of regions 1100, each of the four pixels P(1,1), P(1,2), P(2,1), and P(2,2) arranged in two rows and two columns can include three sub-pixels SPa, SPb, and SPc. In the following description, the case where k is 3 can be explained.

[0255] The three sub-pixels can include a first sub-pixel SPa including a first light emitting device EDa emitting a first color light, a second sub-pixel SPb including a second light emitting device EDb emitting a second color light, and a third sub-pixel SPc including a third light emitting device EDc emitting a third color light.

[0256] If the display panel 110 according to an embodiment of the present application has a redundant structure, the sub-pixel redundant structure is as follows.

[0257] The first sub-pixel SPa can include a first main sub-pixel SPa_M including a first main light emitting device EDa_M and a first redundant sub-pixel SPa_R including a first redundant light emitting device EDa_R, the second sub-pixel SPb can include a second main sub-pixel SPb_M including a second main light emitting device EDb_M and a second redundant sub-pixel SPb_R including a second redundant light emitting device EDb_R, and the third sub-pixel SPc can include a third main sub-pixel SPc_M including a third main light emitting device EDC_M and a third redundant sub-pixel SPc_R including a third redundant light emitting device EDC_R.

[0258] If the display panel 110 according to an embodiment of the disclosure has a redundant structure, the light emitting device redundant structure is as follows.

[0259] The first light emitting device EDa can include a first main light emitting device EDa_M emitting a first color light and a first redundant light emitting device EDa_R emitting the first color light, the second light emitting device EDb can include a second main light emitting device EDb_M emitting a second color light and a second redundant light emitting device EDb_R emitting the second color light, and the third light emitting device EDC can include a third main light emitting device EDC_M emitting a third color light and a third redundant light emitting device EDC_R emitting the third color light.

[0260] Reference Figure 10 and Figure 11 In the two-row two-column region 1100, a first row line RL(1) and a second row line RL(2) can be arranged. The first row line RL(1) can be arranged in a first row (i.e., a first pixel row), and the second row line RL(2) can be arranged in a second row (i.e., a second pixel row).

[0261] The first row line RL(1) can correspond to two pixels P(1,1) and P(1,2) arranged in the first row (or the first pixel row), and can correspond to three sub-pixels SPa, SPb, and SPc included in each of the two pixels P(1,1) and P(1,2) arranged in the first row (or the first pixel row).

[0262] In terms of a sub-pixel redundant structure, the first row line RL(1) can be connected to a first main sub-pixel SPa_M, a first redundant sub-pixel SPa_R, a second main sub-pixel SPb_M, a second redundant sub-pixel SPb_R, a third main sub-pixel SPc_M, and a third redundant sub-pixel SPc_R arranged in the first row (or the first pixel row).

[0263] At least a portion of the first row line RL(1) can overlap the first main sub-pixel SPa_M, the first redundant sub-pixel SPa_R, the second main sub-pixel SPb_M, the second redundant sub-pixel SPb_R, the third main sub-pixel SPc_M, and the third redundant sub-pixel SPc_R arranged in the first row (or the first pixel row).

[0264] From the perspective of the light emitting device redundancy structure, the first row line RL(1) can be connected to the second electrode Erl of each of the first main light emitting device EDa_M, the first redundant light emitting device EDa_R, the second main light emitting device EDb_M, the second redundant light emitting device EDb_R, the third main light emitting device EDc_M, and the third redundant light emitting device EDc_R arranged in the first row (or the first pixel row).

[0265] At least a portion of the first row line RL(1) can overlap the first main light emitting device EDa_M, the first redundant light emitting device EDa_R, the second main light emitting device EDb_M, the second redundant light emitting device EDb_R, the third main light emitting device EDc_M, and the third redundant light emitting device EDc_R arranged in the first row (or the first pixel row).

[0266] The second row line RL(2) can correspond to two pixels P(2,1) and P(2,2) arranged in the second row (or the second pixel row), and can correspond to three sub-pixels SPa, SPb, and SPc included in each of the two pixels P(2,1) and P(2,2) arranged in the second row (or the second pixel row).

[0267] From the perspective of the sub-pixel redundancy structure, the second row line RL(2) can be connected to the first main sub-pixel SPa_M, the first redundant sub-pixel SPa_R, the second main sub-pixel SPb_M, the second redundant sub-pixel SPb_R, the third main sub-pixel SPc_M, and the third redundant sub-pixel SPc_R arranged in the second row (or the second pixel row).

[0268] At least a portion of the second row line RL(2) can overlap the first main sub-pixel SPa_M, the first redundant sub-pixel SPa_R, the second main sub-pixel SPb_M, the second redundant sub-pixel SPb_R, the third main sub-pixel SPc_M, and the third redundant sub-pixel SPc_R arranged in the second row (or the second pixel row).

[0269] As for the light emitting device redundancy structure, the second row line RL(2) can be connected to the second electrode Erl of each of the first main light emitting device EDa_M, the first redundant light emitting device EDa_R, the second main light emitting device EDb_M, the second redundant light emitting device EDb_R, the third main light emitting device EDc_M, and the third redundant light emitting device EDc_R arranged in the second row (or the second pixel row).

[0270] At least a portion of the second row line RL(2) can overlap the first main light emitting device EDa_M, the first redundant light emitting device EDa_R, the second main light emitting device EDb_M, the second redundant light emitting device EDb_R, the third main light emitting device EDc_M, and the third redundant light emitting device EDc_R arranged in the second row (or the second pixel row).

[0271] Referring to Figure 10 and Figure 11 , a plurality of column lines CL can be arranged in the two-row two-column region 1100. The plurality of column lines CL arranged in the two-row two-column region 1100 can include a plurality of first column lines CL connected to the two pixels P(1,1) and P(2,1) arranged in the first column (or the first pixel column) and a plurality of second column lines CL connected to the two pixels P(1,2) and P(2,2) arranged in the second column (or the second pixel column).

[0272] Referring to Figure 10 and Figure 11 , from the perspective of the sub-pixel redundancy structure, the plurality of first column lines CL arranged in the first column (or the first pixel column) can include a first main column line CLa_M commonly connected to a first main pixel SPa_M included in each of the two pixels P(1,1) and P(2,1) arranged in the first column (or the first pixel column) and a first redundant column line CLa_R commonly connected to a first redundant sub-pixel SPa_R included in each of the two pixels P(1,1) and P(2,1) arranged in the first column (or the first pixel column).

[0273] The first main sub-pixel SPa_M included in each of the two pixels P(1,1) and P(2,1) arranged in the first column (or the first pixel column) can include a first main light emitting device EDa_M, and the first redundant sub-pixel SPa_R included in each of the two pixels P(1,1) and P(2,1) arranged in the first column (or the first pixel column) can include a first redundant light emitting device EDa_R.

[0274] The first main column line CLa_M arranged in the first column (or the first pixel column) can be commonly connected to the first electrodes Ecl of the two first main light emitting devices EDa_M arranged in the first column (or the first pixel column).

[0275] The first redundant column line CLa_R arranged in the first column (or the first pixel column) can be commonly connected to the first electrodes Ecl of the two first redundant light emitting devices EDa_R arranged in the first column (or the first pixel column).

[0276] Further, the plurality of first column lines CL arranged in the first column (or the first pixel column) can further include a second main column line CLb_M commonly connected to a second main sub-pixel SPb_M included in each of two pixels P(1,1) and P(2,1) arranged in the first column (or the first pixel column), and a second redundant column line CLb_R commonly connected to a second redundant sub-pixel SPb_R included in each of the two pixels P(1,1) and P(2,1) arranged in the first column (or the first pixel column).

[0277] The second main sub-pixel SPb_M included in each of the two pixels P(1,1) and P(2,1) arranged in the first column (or the first pixel column) can include a second main light emitting device EDb_M, and the second redundant sub-pixel SPb_R included in each of the two pixels P(1,1) and P(2,1) arranged in the first column (or the first pixel column) can include a second redundant light emitting device EDb_R.

[0278] The second main column line CLb_M arranged in the first column (or the first pixel column) can be commonly connected to the first electrodes Ecl of the two second main light emitting devices EDb_M arranged in the first column (or the first pixel column).

[0279] The second redundant column line CLb_R arranged in the first column (or the first pixel column) can be commonly connected to the first electrodes Ecl of the two second redundant light emitting devices EDb_R arranged in the first column (or the first pixel column).

[0280] Further, the plurality of first column lines CL arranged in the first column (or the first pixel column) can further include a third main column line CLc_M commonly connected to a third main sub-pixel SPc_M included in each of two pixels P(1,1) and P(2,1) arranged in the first column (or the first pixel column), and a third redundant column line CLc_R commonly connected to a third redundant sub-pixel SPc_R included in each of the two pixels P(1,1) and P(2,1) arranged in the first column (or the first pixel column).

[0281] The third main sub-pixel SPc_M included in each of the two pixels P(1,1) and P(2,1) arranged in the first column (or first pixel column) can include a third main light emitting device EDc_M, and the third redundant sub-pixel SPc_R included in each of the two pixels P(1,1) and P(2,1) arranged in the first column (or first pixel column) can include a third redundant light emitting device EDc_R.

[0282] The third main column line CLc_M arranged in the first column (or first pixel column) can be commonly connected to the first electrodes Ecl of the two third main light emitting devices EDc_M arranged in the first column (or first pixel column).

[0283] The third redundant column line CLc_R arranged in the first column (or first pixel column) can be commonly connected to the first electrodes Ecl of the two third redundant light emitting devices EDc_R arranged in the first column (or first pixel column).

[0284] Referring to Figure 10 and Figure 11 From the perspective of a sub-pixel redundancy structure, the plurality of second column lines CL arranged in the second column (or second pixel column) can include a first main column line CLa_M commonly connected to the first main sub-pixels SPa_M included in each of the two pixels P(1,2) and P(2,2) arranged in the second column (or second pixel column), and a first redundant column line CLa_R commonly connected to the first redundant sub-pixels SPa_R included in each of the two pixels P(1,2) and P(2,2) arranged in the second column (or second pixel column).

[0285] The first main sub-pixel SPa_M included in each of the two pixels P(1,2) and P(2,2) arranged in the second column (or second pixel column) can include a first main light emitting device EDa_M, and the first redundant sub-pixel SPa_R included in each of the two pixels P(1,2) and P(2,2) arranged in the second column (or second pixel column) can include a first redundant light emitting device EDa_R.

[0286] The first main column line CLa_M arranged in the second column (or second pixel column) can be commonly connected to the first electrodes Ecl of the two first main light emitting devices EDa_M arranged in the second column (or second pixel column).

[0287] The first redundant column line CLa_R arranged in the second column (or the second pixel column) can be commonly connected to the first electrodes Ecl of the two first redundant light emitting devices EDa_R arranged in the second column (or the second pixel column).

[0288] Further, the plurality of second column lines CL arranged in the second column (the second pixel column) can further include a second main column line CLb_M commonly connected to a second main sub-pixel SPb_M included in each of two pixels P(1,2) and P(2,2) arranged in the second column (or the second pixel column), and a second redundant column line CLb_R commonly connected to a second redundant sub-pixel SPb_R included in each of the two pixels P(1,2) and P(2,2) arranged in the second column (or the second pixel column).

[0289] The second main sub-pixel SPb_M included in each of the two pixels P(1,2) and P(2,2) arranged in the second column (or the second pixel column) can include a second main light emitting device EDb_M, and the second redundant sub-pixel SPb_R included in each of the two pixels P(1,2) and P(2,2) arranged in the second column (or the second pixel column) can include a second redundant light emitting device EDb_R.

[0290] The second main column line CLb_M arranged in the second column (or the second pixel column) can be commonly connected to the first electrodes Ecl of the two second main light emitting devices EDb_M arranged in the second column (or the second pixel column).

[0291] The second redundant column line CLb_R arranged in the second column (or the second pixel column) can be commonly connected to the first electrodes Ecl of the two second redundant light emitting devices EDb_R arranged in the second column (or the second pixel column).

[0292] Further, the plurality of second column lines CL arranged in the second column (or the second pixel column) can further include a third main column line CLc_M commonly connected to a third main sub-pixel SPc_M included in each of two pixels P(1,2) and P(2,2) arranged in the second column (or the second pixel column), and a third redundant column line CLc_R commonly connected to a third redundant sub-pixel SPc_R included in each of the two pixels P(1,2) and P(2,2) arranged in the second column (or the second pixel column).

[0293] The third main sub-pixel SPc_M included in each of the two pixels P(1,2) and P(2,2) arranged in the second column (or second pixel column) can include a third main light emitting device EDc_M, and the third redundant sub-pixel SPc_R included in each of the two pixels P(1,2) and P(2,2) arranged in the second column (or second pixel column) can include a third redundant light emitting device EDc_R.

[0294] The third main column line CLc_M arranged in the second column (or second pixel column) can be commonly connected to the first electrodes Ecl of the two third main light emitting devices EDc_M arranged in the second column (or second pixel column).

[0295] The third redundant column line CLc_R arranged in the second column (or second pixel column) can be commonly connected to the first electrodes Ecl of the two third redundant light emitting devices EDc_R arranged in the second column (or second pixel column).

[0296] Referring to Figure 10 and Figure 11 In each of the first column (or first pixel column) and the second column (or second pixel column), each of the plurality of column lines CL can include at least one column connection electrode having a shape protruding above the bank BNK. For example, the at least one column connection electrode can be an electrode electrically connected with or a portion protruding from each of the plurality of column lines CL.

[0297] Referring to Figure 10 and Figure 11 Each of the first main column line CLa_M, the second main column line CLb_M, and the third main column line CLc_M can include a main column connection electrode CCE_M protruding above and extending above the bank BNK.

[0298] The first main light emitting device EDa_M, the second main light emitting device EDb_M, and the third main light emitting device EDc_M can be arranged on the main column connection electrode CCE_M arranged to extend above the bank BNK.

[0299] Referring to Figure 10 and Figure 11 In each of the first column (or first pixel column) and the second column (or second pixel column), each of the first redundant column line CLa_R, the second redundant column line CLb_R, and the third redundant column line CLc_R can include a redundant column connection electrode CCE_R protruding toward and extending above the bank BNK.

[0300] On the redundant column connection electrode CCE_R arranged to extend over the bank BNK, the first redundant light emitting device EDa_R, the second redundant light emitting device EDb_R, and the third redundant light emitting device EDc_R can be arranged.

[0301] The main column connection electrode CCE_M and the redundant column connection electrode CCE_R arranged in the first column (or first pixel column) can be disposed between the first main column line CLa_M and the first redundant column line CLa_R.

[0302] The main column connection electrode CCE_M and the redundant column connection electrode CCE_R arranged in the second column (or second pixel column) can be disposed between the second main column line CLb_M and the second redundant column line CLb_R.

[0303] The main column connection electrode CCE_M and the redundant column connection electrode CCE_R arranged in the third column (or third pixel column) can be disposed between the third main column line CLc_M and the third redundant column line CLc_R.

[0304] The display panel 110 according to an embodiment of the disclosure can further include at least one row connection electrode for electrically connecting each of the plurality of row lines RL to the driver DRV.

[0305] Referring to Figure 10 and Figure 11 The display panel 110 according to an embodiment of the disclosure can further include at least one first row connection electrode RCE(1) connected to a first row line RL(1) arranged in a first row (or first pixel row), and at least one second row connection electrode RCE(2) connected to a second row line RL(2) arranged in a second row (or second pixel row).

[0306] The first row line RL(1) can be vertically overlapped with the at least one first row connection electrode RCE(1), and the second row line RL(2) can be vertically overlapped with the at least one second row connection electrode RCE(2).

[0307] The first row line RL(1) can be electrically connected to a row driver R-DRV of the corresponding driver DRV through the at least one first row connection electrode RCE(1). The second row line RL(2) can be electrically connected to a row driver R-DRV of the corresponding driver DRV through the at least one second row connection electrode RCE(2).

[0308] According to embodiments of this disclosure, embankment BNKs can be arranged in each of a plurality of sub-pixels SP. The plurality of embankment BNKs can be structures on which a plurality of light-emitting devices ED are mounted. During panel manufacturing, in the transfer process for transferring the plurality of light-emitting devices ED to the display device 100, the plurality of embankment BNKs can guide the position of the plurality of light-emitting devices ED. That is, during panel manufacturing, the plurality of light-emitting devices ED can be transferred onto the plurality of embankment BNKs during the transfer process of the plurality of light-emitting devices ED. The plurality of embankment BNKs can be organic insulating layers, embankment patterns, or structures, but embodiments of this disclosure are not limited thereto.

[0309] The embankment BNK of each of the multiple sub-pixels SP can be arranged to be spaced apart from each other. The embankment BNK of each of the multiple sub-pixels SP can be configured to be separated from each other. Therefore, it is easy to identify the embankment BNK of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, where different types of light-emitting devices ED are transferred.

[0310] The dam portion BNK of the first primary sub-pixel SPa_M and the dam portion BNK of the first redundant sub-pixel SPa_R can be connected to each other, or they can be spaced apart or separated from each other. For example, considering the design requirements of the transfer process, the dam portion BNK of the first primary sub-pixel SPa_M and the dam portion BNK of the first redundant sub-pixel SPa_R can be connected to each other, or they can be spaced apart or separated from each other, wherein light-emitting devices EDa_M and EDb_M of the same type (e.g., emitting the same color of light) are arranged in the dam portion BNK of the first primary sub-pixel SPa_M and the dam portion BNK of the first redundant sub-pixel SPa_R. In addition, the dam portion BNK of the second primary sub-pixel SPb_M and the dam portion BNK of the second redundant sub-pixel SPb_R can be connected to each other, or they can be spaced apart or separated from each other. The dam portion BNK of the third primary sub-pixel SPc_M and the dam portion BNK of the third redundant sub-pixel SPc_R can be connected to each other, or they can be spaced apart or separated from each other.

[0311] The embankment BNK of the first principal sub-pixel SPa_M and the first redundant sub-pixel SPa_R, the embankment BNK of the second principal sub-pixel SPb_M and the second redundant sub-pixel SPb_R, and the embankment BNK of the third principal sub-pixel SPc_M and the third redundant sub-pixel SPc_R can be formed in various ways, and the embodiments of this disclosure are not limited thereto.

[0312] For example, multiple dammed BNKs can be formed of organic insulating materials. Multiple dammed BNKs can be formed of single-layer or multi-layer organic insulating materials. For example, multiple dammed BNKs can be composed of photoresist, polyimide (PI), or acrylic materials, but the embodiments of this disclosure are not limited thereto.

[0313] The plurality of row lines RL can be formed of a transparent conductive material, but embodiments of the present disclosure are not limited thereto. The plurality of row lines RL can be composed of a transparent conductive material so that light emitted from the light emitting devices ED can be directed upward through the row lines RL. For example, the plurality of row lines RL can be composed of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), or the like, but embodiments of the present disclosure are not limited thereto.

[0314] The plurality of column lines CL can be made of a conductive material. For example, the plurality of column lines CL can be formed of a conductive material such as titanium (Ti), aluminum (Al), copper (Cu), molybdenum (Mo), nickel (Ni), chromium (Cr), indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), or the like, but embodiments of the present disclosure are not limited thereto. For another example, the plurality of column lines CL can have a multi-layer structure of a conductive material. For example, the plurality of column lines CL can be made of a multi-layer structure of titanium (Ti) / aluminum (Al) / titanium (Ti) / indium tin oxide (ITO), but embodiments of the present disclosure are not limited thereto.

[0315] For example, if the light emitting devices ED are devices manufactured through a semiconductor process, such as micro-LEDs, the plurality of light emitting devices ED can be formed on a wafer, and the light emitting devices ED can be transferred to the substrate 210 of the display panel 110 to manufacture the display panel 110. In the process of transferring the plurality of light emitting devices ED having a microscopic size from the wafer to the substrate 210, various defects can occur. For example, a non-transfer defect in which the light emitting devices ED are not transferred to some of the sub-pixels SP can occur, and a misalignment defect in which the light emitting devices ED are transferred beyond their correct positions due to alignment errors of other sub-pixels SP can occur. In addition, the transfer process can proceed normally, but the transferred light emitting devices ED themselves can have defects. Accordingly, considering defects (including non-transfer defects) that occur during the transfer process of the light emitting devices ED, a main light emitting device and a redundant light emitting device that are the same type of light emitting device (e.g., light emitting devices that emit the same color light) can be transferred to one sub-pixel SP. The same type of main light emitting device and redundant light emitting device can be subjected to a light emission test, and only one of the main light emitting device and the redundant light emitting device that is finally determined to be normal can be utilized.

[0316] For example, the first main light emitting device EDa_M and the first redundant light emitting device EDa_R can be transferred together to one first sub-pixel SPa, and the first main light emitting device EDa_M and the first redundant light emitting device EDa_R can be subjected to a defect inspection. If, as a result of the inspection, both the first main light emitting device EDa_M and the first redundant light emitting device EDa_R are determined to be normal, only the first main light emitting device EDa_M can be used, and the first redundant light emitting device EDa_R can not be used. If, as a result of the inspection, only the first redundant light emitting device EDa_R of the first main light emitting device EDa_M and the first redundant light emitting device EDa_R is normal, the first main light emitting device EDa_M is not used, and only the first redundant light emitting device EDa_R can be used. Thus, even if the same first main light emitting device EDa_M and first redundant light emitting device EDa_R are transferred to one first sub-pixel SPa, only one of the first main light emitting device EDa_M and the first redundant light emitting device EDa_R can be finally used.

[0317] Thus, among the main light emitting device and the redundant light emitting device arranged in one sub-pixel SP, the redundant light emitting device can be a backup light emitting device transferred to prepare for a failure of the main light emitting device. In the case where the main light emitting device fails, the redundant light emitting device can be used as a replacement. Thus, by transferring the main light emitting device and the redundant light emitting device together to one sub-pixel SP, degradation of display quality due to a defect of one of the main light emitting device and the redundant light emitting device can be minimized.

[0318] In an embodiment of the disclosure, the first main sub-pixel SPa_M and the first redundant sub-pixel SPa_R can also be referred to as a 1-1 sub-pixel and a 1-2 sub-pixel, respectively, the second main sub-pixel SPb_M and the second redundant sub-pixel SPb_R can also be referred to as a 2-1 sub-pixel and a 2-2 sub-pixel, respectively, and the third main sub-pixel SPc_M and the third redundant sub-pixel SPc_R can also be referred to as a 3-1 sub-pixel and a 3-2 sub-pixel, respectively.

[0319] In an embodiment of the disclosure, the first main light emitting device EDa_M and the first redundant light emitting device EDa_R can also be referred to as a 1-1 light emitting device and a 1-2 light emitting device, the second main light emitting device EDb_M and the second redundant light emitting device EDb_R can also be referred to as a 2-1 light emitting device and a 2-2 light emitting device, and the third main light emitting device EDc_M and the third redundant light emitting device EDc_R can also be referred to as a 3-1 light emitting device and a 3-2 light emitting device.

[0320] Reference Figure 10 and Figure 11The display panel 110 according to the embodiment of the disclosure can further include a plurality of communication lines NL. The plurality of communication lines NL can be arranged not to overlap with the metal layer in the vertical direction. For example, the plurality of communication lines NL can be arranged between the first row line RL(1) and the second row line RL(2).

[0321] For example, the plurality of communication lines NL can be a wire for short-range communication such as NFC (Near Field Communication) and Bluetooth. The plurality of communication lines NL can serve as a signal transmission line and / or an antenna, but embodiments of the disclosure are not limited thereto.

[0322] Referring to FIG. 1A, Figure 13 The first row line RL(1) can be arranged above the plurality of light emitting devices arranged in the first row (or the first pixel row), and can be arranged in a bar shape overlapping all of the plurality of light emitting devices arranged in the first row (or the first pixel row).

[0323] The second row line RL(2) can be arranged above the plurality of light emitting devices arranged in the second row (or the second pixel row), and can be arranged in a bar shape overlapping all of the plurality of light emitting devices arranged in the second row (or the second pixel row).

[0324] Figure 12 is a cross-sectional view of the display panel 110 according to the embodiment of the disclosure. However, Figure 12 is a cross-sectional view of a portion of the unit driving area UDA in which one driver DRV is arranged.

[0325] Referring to FIG. 1A, Figure 12 The display panel 110 according to the embodiment of the disclosure can include a substrate 210, a driver DRV on the substrate 210, a layer stack 1410 on the driver DRV, a plurality of light emitting devices ED disposed on the layer stack 1410, an optical layer 1420 disposed on the layer stack 1410 and between the plurality of light emitting devices ED, an outer coating layer 1430 disposed on the plurality of light emitting devices ED and the optical layer 1420, an adhesive layer 1440 disposed on the outer coating layer 1430, and a cover member 118 disposed on the adhesive layer 1440.

[0326] Referring to FIG. 1A, Figure 12 The plurality of column lines CL can be arranged on the layer stack 1410. Each of the plurality of column lines CL can be arranged between the layer stack 1410 and the light emitting device ED. The plurality of row lines RL can be arranged on the plurality of light emitting devices ED and the optical layer 1420.

[0327] The display panel 110 according to an embodiment of the present disclosure may include a substrate 210, the substrate 210 including a display area DA, a plurality of light-emitting devices ED disposed in the display area DA, a plurality of column lines CL electrically connected to a first electrode Ecl of each of the plurality of light-emitting devices ED, a plurality of row lines RL electrically connected to a second electrode Erl of each of the plurality of light-emitting devices ED, and a plurality of drivers DRV configured to drive the plurality of light-emitting devices ED, the plurality of column lines CL and the plurality of row lines RL.

[0328] Multiple driver DRVs can be arranged in the display area DA and can be positioned closer to the substrate 210 than multiple light-emitting devices EDs.

[0329] The layer stack 1410 may include multiple insulating layers. The multiple insulating layers may include multiple organic layers. At least one of the multiple organic layers may be disposed on one side of the driver DRV. For example, two or more organic layers may be disposed on one side of the driver DRV.

[0330] The layer stack 1410 may further include at least one metal layer connecting the driver DRV and column line CL, and at least one metal layer connecting the driver DRV and row line RL.

[0331] Figure 13 It is according to the embodiments of this disclosure along Figure 8 A detailed cross-sectional view of the display panel 110 taken by the AB cutting line, and Figure 14 This is an enlarged cross-sectional view of the sub-pixels SP of the display panel 110 according to an embodiment of the present disclosure. However, Figure 13 It is a cross-sectional view of the display area DA, the first non-display area NDA1, the curved area BA, and the second non-display area NDA2.

[0332] At the same time, for ease of explanation, Figure 8 The AB cut line is shown as not overlapping with the signal line SL and the link line LL, but Figure 8 The AB cut line is intended to indicate the same position as the adjacent signal line SL and link line LL.

[0333] refer to Figure 13 The buffer layer 1511 may be included on the substrate 210. The buffer layer 1511 may include a first buffer layer 1511a and a second buffer layer 1511b. The first buffer layer 1511a and the second buffer layer 1511b may be disposed in the display area DA, the first non-display area NDA1 and the second non-display area NDA2, and may not be disposed in the entirety or part of the curved area BA. However, this disclosure is not limited thereto.

[0334] The first buffer layer 1511a and the second buffer layer 1511b can reduce penetration of moisture or impurities through the substrate 210. The first buffer layer 1511a and the second buffer layer 1511b can be made of an inorganic insulating material. For example, the first buffer layer 1511a and the second buffer layer 1511b can be composed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but embodiments of the present disclosure are not limited thereto.

[0335] For example, a portion of the first buffer layer 1511a and the second buffer layer 1511b on the bending area BA can be removed. The upper surface of the substrate 210 located on the bending area BA can be exposed by removing the area (e.g., an opening) of the first buffer layer 1511a and the second buffer layer 1511b.

[0336] By removing the first buffer layer 1511a and the second buffer layer 1511b from the bending area BA, the occurrence of cracks in the first buffer layer 1511a and the second buffer layer 1511b that can occur during bending can be minimized.

[0337] A plurality of alignment members MK can be disposed between the first buffer layer 1511a and the second buffer layer 1511b. The plurality of alignment members MK can be configured to identify the position of the driver DRV during the manufacturing process of the display panel 110. For example, the plurality of alignment members MK can be configured to align the position of the driver DRV transferred onto the adhesive layer 1512. In another example, the plurality of alignment members MK can be omitted.

[0338] The adhesive layer 1512 can be disposed on the second buffer layer 1511b. The adhesive layer 1512 can be disposed in the display area DA, the first non-display area NDA1, the bending area BA, and the second non-display area NDA2. For another example, at least a portion of the adhesive layer 1512 can be removed in the non-display area NDA including the bending area BA. For example, the adhesive layer 1512 can be made of any one of an adhesive polymer, an epoxy resin, a UV-cured resin, a polyimide series, an acrylate series, a urethane series, and a polydimethylsiloxane (PDMS), but embodiments of the present disclosure are not limited thereto.

[0339] The driver DRV can be disposed on the adhesive layer 1512 in the display area DA. If the driver DRV is implemented as a driver chip (e.g., a driver integrated circuit), the driver can be mounted on the adhesive layer 1512 through a transfer process, but embodiments of the present disclosure are not limited thereto.

[0340] The display panel 110 can further include a side protection layer 1513 disposed on a side surface of the plurality of drivers DRV, and an upper protection layer 1514 disposed on the plurality of drivers DRV and the side protection layer 1513. For example, the side protection layer 1513 can include at least one of a first protection layer 1513a and a second protection layer 1513b disposed on a side surface of the plurality of drivers DRV, and in some cases, can further include at least one additional protection layer. The first protection layer 1513a and the second protection layer 1513b can be disposed on the adhesive layer 1512. The first protection layer 1513a and the second protection layer 1513b can be arranged to surround a side surface of the driver DRV, but embodiments of the present disclosure are not limited thereto. For example, the second protection layer 1513b can be arranged to cover at least a portion of an upper surface of the driver DRV. For example, at least one of the first protection layer 1513a and the second protection layer 1513b arranged on the bending area BA can be omitted. For example, the first protection layer 1513a can be completely arranged on the display area DA and the non-display area NDA, and the second protection layer 1513b can be partially arranged on the display area DA, the first non-display area NDA1, and the second non-display area NDA2. For example, at least a portion of the second protection layer 1513b can be removed in all or a portion of the bending area BA. However, embodiments of the present disclosure are not limited thereto.

[0341] For example, the side protection layer 1513 including at least one of the first protection layer 1513a and the second protection layer 1513b can be composed of an organic insulating material (i.e., an organic layer), but embodiments of the present disclosure are not limited thereto. For example, the first protection layer 1513a and the second protection layer 1513b can be composed of a photoresist, polyimide (PI), or an acrylic-based material, but embodiments of the present disclosure are not limited thereto. For example, the first protection layer 1513a and the second protection layer 1513b can be a cover layer or an insulating layer, but embodiments of the present disclosure are not limited thereto.

[0342] According to embodiments of the present disclosure, in the display area DA, a plurality of line connection patterns LCP can be arranged on the second protection layer 1513b. The plurality of line connection patterns LCP can be a wiring for electrically connecting the driver DRV to other components. For example, the driver DRV can be electrically connected to the plurality of column lines CL, the plurality of row lines RL, and the plurality of row connection electrodes RCE through the plurality of line connection patterns LCP.

[0343] For example, the plurality of line connection patterns LCP can include a first line connection pattern LCP1, a second line connection pattern LP2, a third line connection pattern LCP3, and a fourth line connection pattern LCP4, but embodiments of the present disclosure are not limited thereto. For example, the first line connection pattern LCP1, the second line connection pattern LP2, the third line connection pattern LCP3, and the fourth line connection pattern LCP4 can be arranged in different metal layers.

[0344] For example, the plurality of first line connection patterns LCP1 can be arranged on the second protection layer 1513b. The plurality of first line connection patterns LCP1 can be electrically connected to the driver DRV. The plurality of first line connection patterns LCP1 can transmit a voltage output from the driver DRV to the column line CL or the row line RL.

[0345] The display panel 110 can further include a side protection layer 1513 including at least one of the first protection layer 1513a and the second protection layer 1513b, and an upper protection layer 1514 arranged on the plurality of drivers DRV. For example, the upper protection layer 1514 can include a third protection layer 1514, and in some cases, can further include at least one additional protection layer. The third protection layer 1514 can be disposed on the second protection layer 1513b and the plurality of first line connection patterns LCP1. The third protection layer 1514 can be completely disposed in the display area DA and the non-display area NDA. In the bending area BA, the third protection layer 1514 can cover or encapsulate the side surface of the second protection layer 1513b and the upper surface of the first protection layer 1513a.

[0346] For example, the third protection layer 1514 can be composed of an organic insulating material. For example, the third protection layer 1514 can be composed of a photoresist, a polyimide (PI), or an acrylic-based material, but embodiments of the present disclosure are not limited thereto. For example, the first protection layer 1513a, the second protection layer 1513b, and the third protection layer 1514 can be composed of the same insulating material, or at least one of the first protection layer 1513a, the second protection layer 1513b, and the third protection layer 1514 can be composed of an insulating material different from the remaining portion. However, embodiments of the present disclosure are not limited thereto.

[0347] The plurality of second line connection patterns LCP2 can be disposed on the third protective layer 1514. The plurality of second line connection patterns LCP2 can be electrically connected or directly connected to the driver DRV. For example, some of the second line connection patterns LCP2 can be directly or indirectly connected to the driver DRV through a contact hole of the third protective layer 1514. Other portions of the second line connection patterns LCP2 can be electrically connected to the first line connection patterns LCP1 through a contact hole of the third protective layer 1514. However, embodiments of the present disclosure are not limited thereto. The voltage output from the driver DRV can be transmitted to the column line CL or the row line RL through the plurality of second line connection patterns LCP2 and other connection patterns.

[0348] The first insulating layer 1515a can be disposed on the plurality of second line connection patterns LCP2. The first insulating layer 1515a can be disposed entirely over the display area DA and the non-display area NDA, but embodiments of the present disclosure are not limited thereto. The first insulating layer 1515a can be composed of an organic insulating material, but embodiments of the present disclosure are not limited thereto. For example, the first insulating layer 1515a can be composed of a photoresist, polyimide (PI), or an acrylic-based material, but embodiments of the present disclosure are not limited thereto.

[0349] The plurality of third line connection patterns LCP3 can be disposed on the first insulating layer 1515a. The plurality of third line connection patterns LCP3 can be electrically connected to the plurality of second line connection patterns LCP2. For example, the third line connection patterns LCP3 can be electrically connected to the second line connection patterns LCP2 through a contact hole of the first insulating layer 1515a.

[0350] The second insulating layer 1515b can be disposed on the plurality of third line connection patterns LCP3. The second insulating layer 1515b can be disposed in the display area DA, the first non-display area NDA1, and the second non-display area NDA2, and can not be disposed in the entirety or a portion of the bend area BA, but embodiments of the present disclosure are not limited thereto. For example, the second insulating layer 1515b can be removed from all or a portion of the bend area BA. The second insulating layer 1515b can be composed of an organic insulating material, but embodiments of the present disclosure are not limited thereto. For example, the second insulating layer 1515b can be composed of a photoresist, polyimide (PI), or an acrylic-based material, but embodiments of the present disclosure are not limited thereto.

[0351] The plurality of fourth line connection patterns LCP4 can be disposed on the second insulating layer 1515b. The plurality of fourth line connection patterns LCP4 can be electrically connected to the plurality of third line connection patterns LCCP3. For example, the fourth line connection patterns LCP4 can be electrically connected to the third line connection patterns LCP3 through a contact hole of the second insulating layer 1515b.

[0352] Reference Figure 13According to embodiments of the present disclosure, in the non-display area NDA, a plurality of pad connection patterns PCP can be disposed on the second protection layer 1513b. The plurality of pad connection patterns PCP can be wiring for transmitting a signal transmitted from the flexible printed circuit 102 to the pad portion 211 to the driver DRV of the display area DA. For example, the plurality of pad connection patterns PCP can be electrically connected to the plurality of pads PD and can receive a signal from the flexible printed circuit 102 through the plurality of pads PD. The flexible printed circuit 102 can be connected to the printed circuit board 104 (see Figure 1 and Figure 2 ).

[0353] For example, the plurality of pad connection patterns PCP can extend from the pad portion 211 toward the display area DA and transmit a signal to the wiring of the display area DA. In this case, the plurality of pad connection patterns PCP can function as the link wiring LL (see Figure 10 ). The plurality of pad connection patterns PCP can include a first pad connection pattern PCP1, a second pad connection pattern PCP2, a third pad connection pattern PCP3, and a fourth pad connection pattern PCP4.

[0354] The plurality of first pad connection patterns PCP1 can be disposed on the second protection layer 1513b. Each of the plurality of first pad connection patterns PCP1 can be disposed to span the second non-display area NDA2, the bend area BA, and the first non-display area NDA1. Each of the plurality of first pad connection patterns PCP1 can include a first portion disposed in the bend area BA, a second portion extending from the first portion to the first non-display area NDA1, and a third portion extending from the first portion to the second non-display area NDA2. Each of the plurality of first pad connection patterns PCP1 can extend from the first non-display area NDA1 to a portion of the display area DA. The plurality of first pad connection patterns PCP1 can transmit a signal transmitted from the flexible printed circuit 102 to the pad portion 211 to the driver DRV of the display area DA.

[0355] Each of the plurality of first pad connection patterns PCP1 can be electrically connected to the pad PD of the pad portion 211 by a connection pattern disposed in the second non-display area NDA2. Here, the connection pattern electrically connecting each of the plurality of first pad connection patterns PCP1 to the pad PD can include at least one of the second pad connection pattern PCP2, the third pad connection pattern PCP3, and the fourth pad connection pattern PCP4 disposed in the second non-display area NDA2.

[0356] Each of the plurality of first pad connection patterns PCP1 can be electrically connected to the driver DRV through a connection pattern arranged in the display area DA. Here, the connection pattern electrically connecting each of the plurality of first pad connection patterns PCP1 to the driver DRV can include at least one of a second pad connection pattern PCP2, a third pad connection pattern PCP3, and a fourth pad connection pattern PCP4 arranged in the display area DA.

[0357] The plurality of second pad connection patterns PCP2 can be arranged on the third protective layer 1514. The plurality of second pad connection patterns PCP2 can be arranged in the second non-display area NDA2. The second pad connection pattern PCP2 can be electrically connected to the first pad connection pattern PCP1 through a contact hole of the third protective layer 1514. Accordingly, a signal supplied from the flexible printed circuit 102 can be transmitted to the first pad connection pattern PCP1 through the second pad connection pattern PCP2.

[0358] The third pad connection pattern PCP3 can be arranged on the first insulating layer 1515a. The third pad connection pattern PCP3 can be arranged in the second non-display area NDA2. The third pad connection pattern PCP3 can be electrically connected to the second pad connection pattern PCP2 through a contact hole of the first insulating layer 1515a. Accordingly, a signal supplied from the flexible printed circuit 102 can be transmitted to the second pad connection pattern PCP2 through the third pad connection pattern PCP3, and the signal transmitted to the second pad connection pattern PCP2 can be transmitted again to the first pad connection pattern PCP1.

[0359] The fourth pad connection pattern PCP4 can be arranged on the second insulating layer 1515b. The fourth pad connection pattern PCP4 can be arranged in the second non-display area NDA2. The fourth pad connection pattern PCP4 can be electrically connected to the third pad connection pattern PCP3 through a contact hole of the second insulating layer 1515b. The pad PD of the pad portion 211 can be electrically connected to the fourth pad connection pattern PCP4 through a contact hole of the third insulating layer 1515c.

[0360] A signal supplied by the flexible printed circuit 102 is input to the pad PD of the pad portion 211, and the signal input to the pad PD is transmitted to the third pad connection pattern PCP3 through the fourth pad connection pattern PCP4, and the signal transmitted to the third pad connection pattern PCP3 can be transmitted again to the first pad connection pattern PCP1 through the second pad connection pattern PCP2. The signal transmitted to the first pad connection pattern PCP1 can be transmitted to the driver DRV through a connection pattern arranged in the display area DA.

[0361] REFERENCE Figure 13The plurality of line connection patterns LCP and the plurality of pad connection patterns PCP can be arranged in various metal layers. The plurality of line connection patterns LCP and the plurality of pad connection patterns PCP can be formed of a conductive material having excellent ductility or any one of various conductive materials used in the display area DA.

[0362] For example, a metal pattern such as the first pad connection pattern PCP1 disposed at least partially in the bending area BA can consist of a conductive material having excellent ductility (e.g., gold (Au), silver (Ag), or aluminum (Al)), but embodiments of the present disclosure are not limited thereto. For another example, the plurality of line connection patterns LCP and the plurality of pad connection patterns PCP can consist of molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and an alloy of silver (Ag) and magnesium (Mg), or an alloy thereof, but embodiments of the present disclosure are not limited thereto.

[0363] The third insulating layer 1515c can be disposed on the plurality of line connection patterns LCP and the plurality of pad connection patterns PCP. The third insulating layer 1515c is disposed in the display area DA, the first non-display area NDA1, and the second non-display area NDA2, and can be disposed in all or part of the bending area BA, but embodiments of the present disclosure are not limited thereto. In the bending area BA, part of the third insulating layer 1515c can be removed. The third insulating layer 1515c can consist of an organic insulating material, but embodiments of the present disclosure are not limited thereto. For example, the third insulating layer 1515c can consist of a photoresist, polyimide (PI), or an acrylic-based material, but embodiments of the present disclosure are not limited thereto.

[0364] The plurality of banks BNK can be disposed on the third insulating layer 1515c in the display area DA. The plurality of banks BNK can be arranged to overlap at least part of each of the plurality of sub-pixels SPa, SPb, and SPc. For example, the first sub-pixel SPa can include a first light emitting device EDa that emits light of a first color, the second sub-pixel SPb can include a second light emitting device EDb that emits light of a second color, and the third sub-pixel SPc can include a third light emitting device EDc that emits light of a third color.

[0365] For example, one light emitting device ED can be disposed on the top of each of the plurality of banks BNK. For another example, two or more light emitting devices ED can be disposed on the top of each of the plurality of banks BNK. The two or more light emitting devices ED disposed on the top of each of the plurality of banks BNK can be the same type of light emitting device. For example, the same type of light emitting device can be a light emitting device that emits the same color of light. For example, the two or more light emitting devices ED disposed on the top of each of the plurality of banks BNK can include a main light emitting device and a redundant light emitting device.

[0366] In the display area DA, a plurality of row connection electrodes RCE can be disposed on the third insulating layer 1515c. The plurality of row connection electrodes RCE can transmit a low potential voltage VSS output from the driver DRV to the row line RL.

[0367] In the display area DA, a plurality of column lines CL can be disposed on the third insulating layer 1515c. The plurality of column lines CL can be disposed in an area between the plurality of banks BNK. For example, the plurality of column lines CL can be disposed adjacent to one of the plurality of banks BNK.

[0368] Each of the plurality of column lines CL can include a wiring portion and a column connection electrode CCE protruding from the wiring portion. The wiring portion and the column connection electrode CCE included in each of the plurality of column lines CL can be integrally formed or can be different metals that are electrically connected.

[0369] For example, each of the plurality of column lines CL can include a column connection electrode CCE that is a portion protruding above adjacent banks BNK of the plurality of banks BNK. The column connection electrode CCE of each of the plurality of column lines CL can be disposed to extend along the side surface and the upper surface of the bank BNK. The column connection electrode CCE can be an electrode that is electrically connected to each of the plurality of column lines CL or can be a portion protruding from each of the plurality of column lines CL.

[0370] Reference Figure 14 The column connection electrode CCE of the column line CL can consist of one conductive layer or a plurality of conductive layers. For example, the column connection electrode CCE that is electrically connected to or protrudes from the column line CL can include a first conductive layer 1601, a second conductive layer 1602, a third conductive layer 1603, and a fourth conductive layer 1604, but embodiments of the present application are not limited thereto.

[0371] The first conductive layer 1601 can be disposed on the bank BNK. The second conductive layer 1602 can be disposed on the first conductive layer 1601. The third conductive layer 1603 can be disposed on the second conductive layer 1602, and the fourth conductive layer 1604 can be disposed on the third conductive layer 1603. For example, each of the first conductive layer 1601, the second conductive layer 1602, the third conductive layer 1603, and the fourth conductive layer 1604 can be composed of titanium (Ti), molybdenum (Mo), aluminum (Al), or titanium (Ti) and indium tin oxide (ITO), but embodiments of the present disclosure are not limited thereto.

[0372] According to embodiments of the present disclosure, among the plurality of conductive layers constituting the column connection electrode CCE, some conductive layers having good reflection efficiency can be configured as an alignment member for aligning the light emitting device ED and / or a reflector. For example, among the plurality of conductive layers constituting the column connection electrode CCE, the second conductive layer 1602 can include a reflective material. For example, the second conductive layer 1602 can include aluminum (Al), but embodiments of the present disclosure are not limited thereto. Thus, the second conductive layer 1602 can be configured as a reflector. In addition, due to the high reflection efficiency of the second conductive layer 1602, it can be easily identified in the manufacturing process, and thus the position or transfer position of the light emitting device ED can be aligned based on the second conductive layer 1602.

[0373] For example, in order to configure the second conductive layer 1602 as a reflector, the third conductive layer 1603 and the fourth conductive layer 1604 disposed on the second conductive layer 1602 can be partially removed or etched. For example, a portion of the third conductive layer 1603 and the fourth conductive layer 1604 disposed on the bank BNK can be removed or etched to expose an upper surface of the second conductive layer 1602. That is, an opening of the third conductive layer 1603 and the fourth conductive layer 1604 can overlap a portion of the upper surface of the second conductive layer 1602. For example, in the third conductive layer 1603 and the fourth conductive layer 1604, a center portion and an edge portion in which the solder pattern SDP is arranged can be left, and the remaining portion other than the portion (e.g., the center portion, the edge portion) can be removed. For example, an edge portion of each of the third conductive layer 1603 made of titanium (Ti) and the fourth conductive layer 1604 made of indium tin oxide (ITO) can not be etched. Thus, it is possible to prevent other conductive layers of the column connection electrode CCE of the column line CL from being corroded by a TMAH (tetramethylammonium hydroxide) solution used in a mask process of the column connection electrode CCE.

[0374] According to an embodiment of the disclosure, the first conductive layer 1601 and the third conductive layer 1603 can include titanium (Ti) or molybdenum (Mo). The second conductive layer 1602 can include aluminum (Al). The fourth conductive layer 1604 can include a transparent conductive oxide layer such as indium tin oxide (ITO) or indium zinc oxide (IZO) that has good adhesion to the solder pattern SDP and is resistant to corrosion and acid. However, embodiments of the disclosure are not limited thereto.

[0375] The first conductive layer 1601, the second conductive layer 1602, the third conductive layer 1603, and the fourth conductive layer 1604 can be sequentially deposited and then patterned by performing a photolithography process and an etching process, but embodiments of the disclosure are not limited thereto.

[0376] According to an embodiment of the disclosure, two or more of the column connection electrode CCE, the column line CL, the row connection electrode RCE, and the pad PD can be disposed on the same layer. The column connection electrode CCE, the column line CL, the row connection electrode RCE, and the pad PD can be composed of a single layer or multiple layers of conductive material, but embodiments of the disclosure are not limited thereto. For example, two or more of the column connection electrode CCE, the column line CL, the row connection electrode RCE, and the pad PD can be composed of multiple layers of indium tin oxide (ITO) / titanium (Ti) / aluminum (Al) / titanium (Ti), but embodiments of the disclosure are not limited thereto.

[0377] According to an embodiment of the disclosure, the solder pattern SDP can be disposed on the column connection electrode CCE in each of the plurality of sub-pixels. The solder pattern SDP can bond the light emitting device ED to the column connection electrode CCE. The column connection electrode CCE and the light emitting device ED can be electrically connected by using eutectic bonding of the solder pattern SDP, but embodiments of the disclosure are not limited thereto. For example, if the solder pattern SDP is composed of indium (In) and the first electrode Ecl of the light emitting device ED is composed of gold (Au), the solder pattern SDP and the first electrode Ecl of the light emitting device ED can be bonded by applying heat and pressure in a transfer process of the light emitting device ED. Through eutectic bonding, the light emitting device ED can be bonded to the solder pattern SDP and the column connection electrode CCE without a separate adhesive. For example, the solder pattern SDP can be composed of indium (In), tin (Sn), or an alloy thereof, but embodiments of the disclosure are not limited thereto. For example, the solder pattern SDP can be a bonding pad, but embodiments of the disclosure are not limited thereto.

[0378] According to an embodiment of the disclosure, the passivation layer 1516 can be disposed on the plurality of column lines CL, the plurality of column connection electrodes CCE, the plurality of row connection electrodes RCE, and the third insulating layer 1515c.

[0379] For example, the passivation layer 1516 can be provided on the display area DA, the first non-display area NDA1, and the second non-display area NDA2. In all or a part of the bending area BA, at least a portion of the passivation layer 1516 covering the plurality of pads PD can be removed. A portion of the passivation layer 1516 covering the plurality of pads PD in the second non-display area NDA2 can be removed. Further, as shown in FIG. 15B, the passivation layer 1516 can be removed from an area where the solder pattern SDP is disposed. Figure 14

[0380] Since the passivation layer 1516 is disposed to cover the remaining area except for the bending area BA, the plurality of pads PD, and the area where the solder pattern SDP is disposed, penetration of moisture or impurities into the light emitting device ED can be reduced. For example, the passivation layer 1516 can be composed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but embodiments of the present disclosure are not limited thereto. For example, the passivation layer 1516 can be a protective layer or an insulating layer, but embodiments of the present disclosure are not limited thereto. For example, as shown in FIG. 15B, the passivation layer 1516 can include a hole through which the solder pattern SDP is exposed. That is, the hole of the passivation layer 1516 can overlap the solder pattern SDP. Figure 14

[0381] Referring to FIG. 16, Figure 14 the light emitting device ED can be disposed on the solder pattern SDP in each of the plurality of sub-pixels SP. The light emitting device ED can be formed on a silicon wafer by a method such as metal organic chemical vapor deposition (MOCVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PDCVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPD), or sputtering, but embodiments of the present disclosure are not limited thereto.

[0382] Referring to FIG. 17, Figure 14 the light emitting device ED can include a first electrode Ecl, a first semiconductor layer 1611, an active layer 1612, a second semiconductor layer 1613, a second electrode Erl, and an encapsulation film 1614, but embodiments of the present disclosure are not limited thereto. For example, the encapsulation film 1614 can not be included in the light emitting device ED.

[0383] The first semiconductor layer 1611 can be disposed on the solder pattern SDP. The second semiconductor layer 1613 can be disposed on the first semiconductor layer 1611.

[0384] ​​For example, one of the first semiconductor layer 1611 and the second semiconductor layer 1613 can be implemented as a compound semiconductor of Group III-V, Group II-VI, and can be doped with an impurity (or a dopant). For example, one of the first semiconductor layer 1611 and the second semiconductor layer 1613 can be a semiconductor layer doped with an n-type impurity, and the other can be a semiconductor layer doped with a p-type impurity, but embodiments of the present disclosure are not limited thereto. For example, at least one of the first semiconductor layer 1611 and the second semiconductor layer 1613 can be a layer doped with an n-type or p-type impurity in a material such as gallium nitride (GaN), gallium phosphide (GaP), gallium arsenide phosphide (GaAsP), aluminum gallium indium phosphide (AlGaInP), indium aluminum phosphide (InAlP), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), aluminum indium gallium nitride (AlInGaN), aluminum gallium arsenide (AlGaAs), or gallium arsenide (GaAs), but embodiments of the present disclosure are not limited thereto. For example, the n-type impurity can be silicon (Si), germanium (Ge), selenium (Se), carbon (C), tellurium (Te), or tin (Sn), but embodiments of the present disclosure are not limited thereto. For example, the p-type impurity can be magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba), or beryllium (Be), but embodiments of the present disclosure are not limited thereto.

[0385] For example, the first semiconductor layer 1611 and the second semiconductor layer 1613 can be a nitride semiconductor including an n-type impurity and a nitride semiconductor including a p-type impurity, respectively, but embodiments of the present disclosure are not limited thereto. For example, the first semiconductor layer 1611 can be a nitride semiconductor including a p-type impurity, and the second semiconductor layer 1613 can be a nitride semiconductor including an n-type impurity, but embodiments of the present disclosure are not limited thereto.

[0386] The active layer 1612 can be disposed between the first semiconductor layer 1611 and the second semiconductor layer 1613. The active layer 1612 can receive holes and electrons from the first semiconductor layer 1611 and the second semiconductor layer 1613 to emit light. For example, the active layer 1612 can be configured as one of a single well structure, a multi-well structure, a single quantum well structure, a multi-quantum well (MQW) structure, a quantum dot structure, and a quantum wire structure, but embodiments of the present disclosure are not limited thereto. For example, the active layer 1612 can be configured as indium gallium nitride (InGaN) or gallium nitride (GaN), but embodiments of the present disclosure are not limited thereto.

[0387] For another example, the active layer 1612 can include a multi-quantum well (MQW) structure having a well layer and a barrier layer, the barrier layer having a higher bandgap than the well layer. For example, the active layer 1612 can be formed of InGaN as the well layer and an AlGaN layer as the barrier layer, but embodiments of the present disclosure are not limited thereto.

[0388] The first electrode Ecl of the light emitting device ED can be disposed between the first semiconductor layer 1611 and the solder pattern SDP. For example, the first electrode Ecl of the light emitting device ED can electrically connect the first semiconductor layer 1611 and the column connection electrode CCE. The column line voltage (for example, anode voltage) output from the driver DRV can be applied to the first semiconductor layer 1611 through the column line CL, the column connection electrode CCE, and the first electrode Ecl. For example, the first electrode Ecl of the light emitting device ED can be composed of a conductive material capable of eutectic bonding with the solder pattern SDP, but embodiments of the present disclosure are not limited thereto. For example, the first electrode Ecl of the light emitting device ED can be composed of gold (Au), tin (Sn), tungsten (W), silicon (Si), silver (Ag), titanium (Ti), iridium (Ir), chromium (Cr), indium (In), zinc (Zn), lead (Pb), nickel (Ni), platinum (Pt), and copper (Cu), or an alloy thereof, but embodiments of the present disclosure are not limited thereto.

[0389] The second electrode Erl of the light emitting device ED can be disposed on the second semiconductor layer 1613. For example, the second electrode Erl of the light emitting device ED can electrically connect the second semiconductor layer 1613 and the row line RL. The row line voltage (for example, referred to as a low potential voltage VSS as a cathode voltage) output from the driver DRV can be applied to the second semiconductor layer 1613 through the row connection electrode RCE, the row line RL, and the second electrode Erl. The second electrode Erl of the light emitting device ED can be made of a transparent conductive material so that light emitted from the light emitting device ED can be guided to the upper portion of the light emitting device ED, but embodiments of the present disclosure are not limited thereto. For example, the second electrode Erl can be made of a material such as indium tin oxide (ITO), indium zinc oxide (IZO), or indium gallium zinc oxide (IGZO), but embodiments of the present disclosure are not limited thereto.

[0390] The encapsulation film 1614 can be disposed on at least a portion of the first semiconductor layer 1611, the active layer 1612, the second semiconductor layer 1613, the first electrode Ecl, and the second electrode Erl. For example, the encapsulation film 1614 can surround at least a portion of the first semiconductor layer 1611, the active layer 1612, the second semiconductor layer 1613, the first electrode Ecl, and the second electrode Erl.

[0391] For example, the encapsulation film 1614 can protect the first semiconductor layer 1611, the active layer 1612, and the second semiconductor layer 1613. For example, the encapsulation film 1614 can be disposed on the side surface of the first semiconductor layer 1611, the side surface of the active layer 1612, and the side surface of the second semiconductor layer 1613.

[0392] For example, the encapsulation film 1614 can be disposed on at least a portion of the first electrode Ecl and the second electrode Erl of the light emitting device ED. For example, the encapsulation film 1614 can be disposed on an edge portion (or one side) of the first electrode Ecl of the light emitting device ED and an edge portion (or one side) of the second electrode Erl of the light emitting device ED. At least a portion of the first electrode Ecl can be exposed from the encapsulation film 1614 so that the first electrode Ecl can be connected to the solder pattern SDP. For example, at least a portion of the second electrode Erl can be exposed from the encapsulation film 1614 so that the second electrode Erl can be connected to the row line RL. For example, the encapsulation film 1614 can be made of an insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx), but embodiments of the present disclosure are not limited thereto.

[0393] For another example, the encapsulation film 1614 can have a structure in which a reflective material is dispersed in a resin layer, but embodiments of the present disclosure are not limited thereto. For example, the encapsulation film 1614 can be manufactured as a reflector of various structures, but embodiments of the present disclosure are not limited thereto. Light emitted from the active layer 1612 can be upwardly reflected by the encapsulation film 1614, thereby improving light extraction efficiency. For example, the encapsulation film 1614 can be a reflective layer, but embodiments of the present disclosure are not limited thereto.

[0394] According to embodiments of the present disclosure, the light emitting device ED is described as having a vertical structure, but embodiments of the present disclosure are not limited thereto. For example, the light emitting device ED can have a lateral structure or a flip chip structure.

[0395] Figure 14 The structure of the light emitting device ED shown in FIG. 15A can be substantially equally applied to all of the first light emitting device EDa, the second light emitting device EDb, and the third light emitting device EDc. According to embodiments of the present disclosure, the first optical layer 1517a can be disposed to surround the plurality of light emitting devices ED in the display area DA. For example, the first optical layer 1517a can be disposed to cover the plurality of light emitting devices ED in the area of the plurality of sub-pixels SP and the bank BNK. For example, the first optical layer 1517a can cover the bank BNK, a portion of the passivation layer 1516, and an area between the plurality of light emitting devices ED. The first optical layer 1517a can be disposed or cover between the plurality of light emitting devices ED included in one pixel and between the plurality of banks BNK. For example, the first optical layer 1517a can be disposed to extend in the first direction (X) and be spaced apart from each other in the second direction (Y). For example, the first optical layer 1517a can be disposed to surround a side surface of the light emitting device ED and the bank BNK between the passivation layer 1516 and the row line RL, but embodiments of the present disclosure are not limited thereto. For example, the first optical layer 1517a can be a diffusion layer or a sidewall diffusion layer, but embodiments of the present disclosure are not limited thereto.

[0396] The first optical layer 1517a can include an organic insulating material having fine particles dispersed therein, but embodiments of the present disclosure are not limited thereto. For example, the first optical layer 1517a can be composed of silicone having fine metal particles (e.g., titanium dioxide (TiO2) particles) dispersed therein, but embodiments of the present disclosure are not limited thereto. Light from the plurality of light emitting devices ED can be scattered by the fine particles dispersed in the first optical layer 1517a and emitted to the outside of the display device 100. Accordingly, the first optical layer 1517a can improve the extraction efficiency of light emitted from the plurality of light emitting devices ED.

[0397] For example, the first optical layer 1517a can be disposed on each of the plurality of pixels, or can be disposed together on some pixels disposed in the same row, but embodiments of the present disclosure are not limited thereto. For example, the first optical layer 1517a can be disposed on each of the plurality of pixels, or the plurality of pixels can share one first optical layer 1517a. For another example, each of the plurality of sub-pixels can respectively include the first optical layer 1517a, but embodiments of the present disclosure are not limited thereto.

[0398] According to embodiments of the present disclosure, in the display area DA, the second optical layer 1517b can be disposed on the passivation layer 1516. For example, the second optical layer 1517b can be disposed to surround the first optical layer 1517a. For example, the second optical layer 1517b can be in contact with the side surface of the first optical layer 1517a. For example, the second optical layer 1517b can be disposed in an area between the plurality of pixels. However, embodiments of the present disclosure are not limited thereto. For example, the second optical layer 1517b can be a diffusion layer, a diffusion layer window, or a window diffusion layer, but embodiments of the present disclosure are not limited thereto.

[0399] The second optical layer 1517b can be composed of an organic insulating material, but embodiments of the present disclosure are not limited thereto. The second optical layer 1517b can be composed of the same material as the first optical layer 1517a, but embodiments of the present disclosure are not limited thereto. For example, the first optical layer 1517a can include fine particles, and the second optical layer 1517b can not include fine particles. For example, the second optical layer 1517b can be composed of silicone, but embodiments of the present disclosure are not limited thereto.

[0400] For example, the thickness of the first optical layer 1517a can be less than the thickness of the second optical layer 1517b, but embodiments of the present disclosure are not limited thereto. Accordingly, when viewed from a plan view, the area in which the first optical layer 1517a is disposed can include a recessed portion recessed inward from the upper surface of the second optical layer 1517b.

[0401] According to an embodiment of the disclosure, the row line RL can be disposed on the first optical layer 1517a and the second optical layer 1517b. For example, the row line RL can be electrically connected to the plurality of row connection electrodes RCE through the contact hole of the second optical layer 1517b. For example, the row line RL can be disposed on the plurality of light emitting devices ED. For example, the row line RL can include a transparent conductive oxide, for example, indium tin oxide (ITO) or indium zinc oxide (IZO), but embodiments of the disclosure are not limited thereto. For example, the row line RL can be disposed in contact with the second electrode Erl of the light emitting device ED. For example, the row line RL can overlap the first optical layer 1517a. For example, the row line RL can cover the plane on the outer side of the first optical layer 1517a.

[0402] The row line RL can continuously extend in the first direction (X) of the substrate 210. Accordingly, the row line RL can be commonly connected to the plurality of pixels arranged in the first direction (X) of the substrate 210. For example, the row line RL can be commonly connected to the plurality of pixels.

[0403] According to an embodiment of the disclosure, the row line RL can continuously extend on the first optical layer 1517a, the second optical layer 1517b, and the light emitting device ED. The area in which the first optical layer 1517a is disposed can include a recessed portion recessed inward from the upper surface of the second optical layer 1517b. Accordingly, the first portion of the row line RL disposed on the first optical layer 1517a can be disposed along the recessed portion, and thus can be disposed at a lower position than the second portion of the row line RL disposed on the second optical layer 1517b.

[0404] The third optical layer 1517c can be disposed on the row line RL. The third optical layer 1517c can be disposed to overlap the plurality of light emitting devices ED and the first optical layer 1517a. Since the third optical layer 1517c is disposed on the row line RL and the plurality of light emitting devices ED, mura that can occur in some of the plurality of light emitting devices ED can be improved. For example, when the plurality of light emitting devices ED are transferred onto the substrate 210 of the display panel 110, an area in which the interval between the plurality of light emitting devices ED is not uniform due to process deviation can occur. If the interval between the plurality of light emitting devices ED is not uniform, the emission area of each of the plurality of light emitting devices ED can be disposed non-uniformly, and thus a user can see mura. Accordingly, since the third optical layer 1517c is disposed to uniformly scatter light on the plurality of light emitting devices ED, light emitted from some of the light emitting devices ED can be less visible as mura. Accordingly, since the light emitted from the plurality of light emitting devices ED is uniformly scattered by the third optical layer 1517c and extracted to the outside of the display device 100, the brightness uniformity of the display device 100 can be improved.

[0405] The third optical layer 1517c can be composed of an organic insulating material in which fine particles are dispersed, but embodiments of the present disclosure are not limited thereto. For example, the third optical layer 1517c can be composed of silicone in which fine metal particles such as titanium dioxide (TiO2) particles are dispersed, but embodiments of the present disclosure are not limited thereto. For example, the third optical layer 1517c can be composed of the same material as the first optical layer 1517a, but embodiments of the present disclosure are not limited thereto. For example, the third optical layer 1517c can be a diffusion layer or an upper diffusion layer, but embodiments of the present disclosure are not limited thereto.

[0406] According to embodiments of the present disclosure, light from the plurality of light emitting devices ED can be scattered by the fine particles in the third optical layer 1517c and emitted to the outside of the display device 100. The third optical layer 1517c can uniformly mix light emitted from the plurality of light emitting devices ED, thereby further improving the brightness uniformity of the display device 100. In addition, the light extraction efficiency of the display device 100 can be improved by light scattered from the plurality of fine particles, thereby enabling the display device 100 to be driven at low power.

[0407] The black matrix BM can be disposed on the row line RL, the first optical layer 1517a, the second optical layer 1517b, and the third optical layer 1517c in the display area DA. For example, the black matrix BM can fill the contact hole of the second optical layer 1517b. The black matrix BM can be configured to cover the display area DA, thereby it can reduce color mixing of light and external light reflection of the plurality of sub-pixels. For example, the black matrix BM can also be disposed in the contact hole of the row line RL and the row connection electrode RCE connection, thereby it can prevent light leakage between adjacent plurality of sub-pixels.

[0408] For example, the black matrix BM can be composed of an opaque material, but embodiments of the present disclosure are not limited thereto. For example, the black matrix BM can be an organic insulating material to which black pigment or black dye is added, but embodiments of the present disclosure are not limited thereto.

[0409] The cover layer 1518 can be disposed on the black matrix BM in the display area DA. The cover layer 1518 can protect the configuration below the cover layer 1518. For example, the cover layer 1518 can be composed of an organic insulating material, but embodiments of the present disclosure are not limited thereto. For example, the cover layer 1518 can be composed of photoresist, polyimide (PI), or an acrylic-based material, but embodiments of the present disclosure are not limited thereto. For example, the cover layer 1518 can be a cover layer or an insulating layer, but embodiments of the present disclosure are not limited thereto.

[0410] The polarization layer 114 can be disposed on the cover layer 1518 via the first adhesive layer 112. The cover member 118 can be disposed on the polarization layer 114 via the second adhesive layer 116. For example, the first adhesive layer 112 and the second adhesive layer 116 can include an optical clear adhesive (OCA), an optical clear resin (OCR), or a pressure sensitive adhesive (PSA), but embodiments of the present disclosure are not limited thereto.

[0411] According to an embodiment of the present disclosure, a plurality of pads PD can be disposed on the third insulating layer 1515c in the second non-display area NDA2. For example, at least a portion of the plurality of pads PD can be exposed from the passivation layer 1516. For example, the plurality of pads PD can be electrically connected to the fourth pad connection pattern PCP4 through a contact hole of the third insulating layer 1515c.

[0412] An adhesive layer ACF can be disposed on the plurality of pads PD. The adhesive layer ACF can be an adhesive layer in which conductive balls are dispersed in an insulating material, but embodiments of the present disclosure are not limited thereto. When heat or pressure is applied to the adhesive layer ACF, the conductive balls can be electrically connected in a portion to which heat or pressure is applied, thereby having a conductive characteristic. The adhesive layer ACF can be disposed between the plurality of pads PD and the flexible printed circuit 102, so that the flexible printed circuit 102 can be attached or bonded to the plurality of pads PD. For example, the adhesive layer ACF can be an anisotropic conductive film ACF, but embodiments of the present disclosure are not limited thereto.

[0413] The flexible printed circuit 102 can be disposed on the adhesive layer ACF. The flexible printed circuit 102 can be electrically connected to the plurality of pads PD through the adhesive layer ACF. Accordingly, a signal supplied from the flexible printed circuit 102 can be transmitted to the driver DRV of the display area DA through the plurality of pads PD, the fourth pad connection pattern PCP4, the third pad connection pattern PCP3, the second pad connection pattern PCP2, and the first pad connection pattern PCP1.

[0414] Referring to Figure 13 , the display panel 110 according to an embodiment of the present disclosure can include a substrate 210, a layer stack 1410 disposed on a plurality of drivers DRV disposed on the substrate 210, a plurality of light emitting devices EDa, EDb, and EDc disposed between the layer stack 1410, an optical layer 1517a disposed between the plurality of light emitting devices EDa, EDb, and EDc and the layer stack 1410, an adhesive layer 116 disposed on the plurality of light emitting devices EDa, EDb, and EDc and the optical layer 1517a, and a cover member 118 disposed on the adhesive layer 116.

[0415] Referring to Figure 13 , a plurality of column lines CL can be disposed between the layer stack 1410 and the plurality of light emitting devices EDa, EDb, and EDc.

[0416] Referring to Figure 13A plurality of row lines RL can be disposed on the plurality of light emitting devices EDa, EDb, and EDc and the optical layer 1517a. The plurality of row lines RL can be disposed on the plurality of light emitting devices EDa, EDb, and EDc, the optical layer 1517a, and the adhesive layer 116.

[0417] Referring to Figure 13 The layer stack 1410 can include a plurality of protection layers 1513a, 1513b, and 1514 disposed on sides and an upper surface of each of the plurality of drivers DRV, a plurality of insulation layers 1515a, 1515b, and 1515c disposed on the plurality of protection layers 1513a, 1513b, and 1514, and a bank BN disposed on the plurality of insulation layers.

[0418] The plurality of protection layers 1513a, 1513b, and 1514 can further include a side protection layer 1513 disposed on each side of the plurality of drivers DRV and an upper protection layer 1514 disposed on an upper surface of each of the plurality of drivers DRV.

[0419] The side protection layer 1513 can include a first protection layer 1513a disposed on the substrate 210 and a second protection layer 1513b disposed on the first protection layer 1513a.

[0420] The upper protection layer 1514 can include a second protection layer 1513b disposed on the plurality of drivers DRV and a third protection layer 1514.

[0421] The plurality of insulation layers 1515a, 1515b, and 1515c can include a first insulation layer 1515a disposed on the upper protection layer 1514 and a second insulation layer 1515b disposed on the first insulation layer 1515a. The plurality of insulation layers 1515a, 1515b, and 1515c can further include a third insulation layer 1515c disposed on the second insulation layer 1515b.

[0422] Each of the plurality of light emitting devices EDa, EDb, and EDc can be disposed on the bank BN and in an opening of the optical layer 1517a.

[0423] At least a portion of each of the plurality of column lines CL can extend onto the bank BN on the plurality of insulation layers 1515a, 1515b, and 1515c. Each of the plurality of row lines RL can be disposed on the optical layer 1517a and the plurality of light emitting devices EDa, EDb, and EDc.

[0424] The first electrode Ecl of each of the plurality of light emitting devices EDa, EDb, and EDc can be electrically connected to at least a portion of the column lines CL extending onto the BNK among the plurality of column lines CL. The second electrode Erl of each of the plurality of light emitting devices EDa, EDb, and EDc can be electrically connected to one of the plurality of row lines RL.

[0425] Reference Figure 13 The display panel 110 according to the embodiment of the disclosure can include a plurality of line connection patterns LCP connecting each of the plurality of lines including the plurality of row lines RL and the plurality of column lines CL to the plurality of drivers DRV.

[0426] The plurality of line connection patterns LCP can include a first line connection pattern LCP1 disposed on the side protection layer 1513, a second line connection pattern LCP2 disposed on the upper protection layer 1514 and electrically connected to the first line connection pattern LCP1 through a hole in the upper protection layer 1514, a third line connection pattern LCP3 disposed on the first insulating layer 1515a and electrically connected to the second line connection pattern LCP2 through a hole in the first insulating layer 1515a, and a fourth line connection pattern LCP4 disposed on the second insulating layer 1515b and electrically connected to the third line connection pattern LCP3 through a hole in the second insulating layer 1515b.

[0427] The first line connection pattern LCP1 can be electrically connected to one of the plurality of drivers DRV. The fourth line connection pattern LCP4 can be electrically connected to at least one second electrode Erl of the plurality of light emitting devices EDa, EDb, and EDc, or can be electrically connected to at least one first electrode Ecl of the plurality of light emitting devices EDa, EDb, and EDc.

[0428] The side protection layer 1513 disposed on each side of the plurality of drivers DRV can include two or more organic layers.

[0429] The first protection layer 1513a and the second protection layer 1513b as the side protection layer 1513, the third protection layer 1514 as the upper protection layer 1514, and the first insulating layer 1515a, the second insulating layer 1515b, and the third insulating layer 1515c can each consist of an organic layer.

[0430] The structure and operation related to the display function of the display device 100 according to the embodiment of the disclosure have been described above.

[0431] The display device 100 according to the embodiment of the disclosure can not only provide a display function, but also provide a touch sensing function.

[0432] The display device 100 according to embodiments of the present disclosure may include multiple row lines RL used as touch sensors to perform touch sensing, multiple drivers DRV for driving and sensing the multiple row lines RL, and a touch control circuit 1700 for controlling the multiple drivers DRV.

[0433] Multiple drivers (DRVs) can supply a touch drive signal TDS with a variable voltage level to at least one of multiple row lines (RLs). The touch drive signal TDS is a voltage level fluctuating signal, also referred to as an AC signal or a pulse signal. For example, the touch drive signal TDS can have a signal waveform such as a square wave, sine wave, or triangle wave. For example, the frequency of the touch drive signal TDS can be constant. Alternatively, the frequency of the touch drive signal TDS can be variable. If the frequency of the touch drive signal TDS varies according to the touch drive period T or time, it can prevent touch sensitivity degradation caused by noise generated during touch drive.

[0434] Multiple driver DRVs can sense or detect the electrical state (e.g., capacitance change) of at least one of multiple row lines RL to generate sensing data and output the generated sensing data. Here, the sensing data may include digital sensing values.

[0435] Multiple driver DRVs may include at least one analog-to-digital converter (ADC) to sense the electrical state of at least one of multiple row lines RL, thereby obtaining a digital sensed value.

[0436] For example, the electrical state of at least one of the multiple row lines RL may include the capacitance Cf between the touching object (e.g., a finger or pen) and each row line RL. As another example, the electrical state of at least one of the multiple row lines RL may include the capacitance between two row lines RL.

[0437] The touch control circuit 1700 can supply a touch drive signal TDS or a signal as the basis for the touch drive signal TDS to each of the multiple drivers DRV, and determine the occurrence or location of a touch based on sensing data provided from each of the multiple drivers RV. For example, the touch control circuit 1700 may include a timing controller or a microcontroller unit. The touch control circuit 1700 may also include a power management integrated circuit (PMIC), etc.

[0438] The display device 100 according to embodiments of the present disclosure can perform touch sensing based on self-capacitance and / or touch sensing based on mutual capacitance.

[0439] One of the multiple line lines RL can be supplied with a first low potential voltage VSS1 during a first time period, and can be supplied with a second low potential voltage VSS2 during a second time period different from the first time period.

[0440] The first and second time periods can be included in a single display driving period or in different display driving periods.

[0441] The first low potential voltage VSS1 and the second low potential voltage VSS2 are of the type of low potential voltage VSS, and can be the line voltage applied to the line RL. Alternatively, the first low potential voltage VSS1 and the second low potential voltage VSS2 can be the voltage (e.g., cathode voltage or anode voltage) applied to the second electrode Erl of the light-emitting device ED connected to the line RL.

[0442] In the first low potential voltage VSS1 and the second low potential voltage VSS2, the first low potential voltage VSS1 can be a low potential voltage used to drive the display to turn on, and the second low potential voltage VSS2 can be a low potential voltage used to drive the display to turn off.

[0443] The first low potential voltage VSS1 can be lower than the second low potential voltage VSS2. That is, the second low potential voltage VSS2 can be higher than the first low potential voltage VSS1. Therefore, during the first time period PT1, the voltage difference between the first electrode Ecl and the second electrode Erl of the light-emitting device ED can be higher than the threshold voltage of the light-emitting device ED. Therefore, the light-emitting device ED can be in a state where it can emit light. Next, during the second time period PT2, the voltage difference between the first electrode Ecl and the second electrode Erl of the light-emitting device ED can be lower than the threshold voltage of the light-emitting device ED. Therefore, the light-emitting device ED can be in a state where it cannot emit light.

[0444] At the same time, one of the multiple line lines RL can be supplied with a touch drive signal, which is a signal whose voltage level oscillates during a third time period different from the first and second time periods.

[0445] The third time period can be a time period included in the touch-driven time period.

[0446] The touch drive signal TDS can be a signal with a predetermined frequency and fluctuating voltage level. The touch drive signal TDS can be a signal that oscillates between a predetermined high voltage and a low voltage. For example, the high voltage can be a second low potential voltage VSS2, and the low voltage can be a third low potential voltage VSS3. The amplitude of the touch drive signal TDS can be the voltage difference between the high and low voltages. For example, the third low potential voltage VSS3 can be a voltage lower than the second low potential voltage VSS2, and can be the same as or different from the first low potential voltage VSS1. For example, the third low potential voltage VSS3 can be a voltage higher than the first low potential voltage VSS1 and lower than the second low potential voltage VSS2.

[0447] According to the driving type and the driving timing, each of the plurality of row lines RL can be driven in a predetermined method.

[0448] For example, the display-on driving of each of the plurality of row lines RL can be sequentially performed. For another example, the display-on driving of each of the plurality of row lines RL can be simultaneously performed. For another example, the display-on driving of each of two or more of the plurality of row lines RL can be simultaneously performed.

[0449] For example, during a certain display driving period, among the plurality of row lines RL arranged in the unit driving area UDA, the display-on driving can be performed for at least one row line RL, and the display-off driving can be performed for the remaining row lines RL without the display-on driving.

[0450] The display-on driving performed for a certain row line RL can mean that a first low potential voltage VSS1 of a predetermined level is supplied to the corresponding row line RL.

[0451] When the display-on driving of a certain row line RL is performed, the light emitting device ED arranged corresponding to the respective row line RL can emit light.

[0452] The display-off driving performed for a certain row line RL without the display-on driving can mean that a second low potential voltage VSS2 of a predetermined level is supplied to the corresponding row line RL. Here, the second low potential voltage VSS2 can be a voltage higher than the first low potential voltage VSS1.

[0453] When the display-off driving is performed for a certain row line RL, the light emitting device ED arranged corresponding to the row line RL can not emit light.

[0454] For example, a first row line RL of the plurality of row lines RL can be supplied with the first low potential voltage VSS1 during a first period, and can be supplied with the second low potential voltage VSS2 higher than the first low potential voltage VSS1 during a second period different from the first period. For example, the first period and the second period can be included in one display driving period. For another example, the first period and the second period can be included in different display driving periods.

[0455] A structure for improving the light emitting efficiency of the display panel 110 of the display device 100 according to an embodiment of the disclosure will be described below. Reference can also be made to Figures 1 to 14 .

[0456] Figure 15 is a plan view of the display device 100 according to an embodiment of the disclosure.

[0457] Reference is made to Figure 15According to embodiments of the disclosure, the display device 100 can include a display area DA on which an image can be displayed and a non-display area NDA outside the area. The display device 100 according to embodiments of the disclosure can be disposed on a substrate 210 and can further include a ground GND positioned at the non-display area NDA.

[0458] The ground GND can be a body that discharges static electricity generated in the display panel 110 or flowing into the display panel 110. Static electricity can be generated during a panel manufacturing process, and in some cases, can be generated during a user's use of the display device 100 after the panel is manufactured.

[0459] The ground GND can have a plate shape or a ring shape as in Figure 15 However, embodiments of the disclosure are not limited thereto.

[0460] The static electricity discharge structure of the display device 100 according to embodiments of the disclosure will be described in greater detail below.

[0461] Figure 16 and Figure 17 are plan views of a portion 2000 of the display device 100 according to embodiments of the disclosure. Figure 16 and Figure 17 are two plan views of the portion 2000 of Figure 15

[0462] Referring to Figure 16 and Figure 17 , the non-display area NDA can include a dummy area DMY and a static electricity discharge area EDA. The dummy area DMY can be an area that is cut and removed when a panel manufacturing process is completed. The static electricity discharge area EDA can be an area in which a static electricity discharge structure is formed.

[0463] For example, referring to Figure 16 , the static electricity discharge area EDA can coincide with the dummy area DMY. In this case, the static electricity discharge structure disposed in the static electricity discharge area EDA can be removed during the panel manufacturing process, and can not exist in the manufactured display device 100.

[0464] For another example, referring to Figure 17 , the static electricity discharge area EDA can be disposed adjacent to the display area DA within the non-display area NDA, and the dummy area DMY can be disposed on the outer periphery of the static electricity discharge area EDA. In this case, the static electricity discharge structure disposed in the static electricity discharge area EDA can exist in the manufactured display device 100 after the panel manufacturing process is completed.

[0465] Referring to Figure 17 ​The electrostatic discharge structure according to an embodiment of the disclosure can be disposed in the non-display area NDA and can be disposed along a boundary of the display area DA.

[0466] Figure 18 is a plan view of the display area DA in the portion 2000 of the display device 100 according to an embodiment of the disclosure.

[0467] Figure 18 is a plan view of the display area DA in the portion 2000 of Figure 15 is a plan view of the display area DA in the portion 2000 of and is a plan view of the area 2000 in which two row lines RL1 and RL2 and four column lines CL1 to CL4 intersect in one unit driving area UDA among a plurality of unit driving areas UDA included in the display area DA of the display panel 110.

[0468] Referring to Figure 18 The display panel 110 according to an embodiment of the disclosure can further include a substrate 210, a plurality of light emitting devices ED1 to ED8 disposed on the substrate 210 and located in the display area DA, a plurality of bank portions BNK1 to BNK4 disposed on the substrate 210 and located in the display area DA, a plurality of row lines RL1 and RL2 disposed on the substrate 210, and a plurality of column lines CL1 to CL4 disposed on the substrate 210.

[0469] Referring to Figure 18 The plurality of column lines CL1 to CL4 can include a first column line CL1 and a second column line CL2 spaced apart from each other.

[0470] The plurality of light emitting devices ED1 to ED8 can include a first light emitting device ED1 and a second light emitting device ED2 disposed between the first column line CL1 and the second column line CL2. The second light emitting device ED2 can be disposed adjacent to the first light emitting device ED1.

[0471] A first electrode of the first light emitting device ED1 can be electrically connected to the first column line CL1. A first electrode of the second light emitting device ED2 can be electrically connected to the second column line CL2.

[0472] The plurality of bank portions BNK1 to BNK4 can include a first bank portion BNK1 on which the first light emitting device ED1 and the second light emitting device ED2 are mounted together. That is, the first light emitting device ED1 and the second light emitting device ED2 can be disposed together on the first bank portion BNK1. The plurality of bank portions BNK1 to BNK4 can be disposed on the third insulating layer 1515c of Figure 13

[0473] Referring to Figure 18 ​The plurality of light emitting devices ED1-ED8 can further include a fifth light emitting device ED5 and a sixth light emitting device ED6 disposed between the third column line CL3 and the fourth column line CL4.

[0474] The first light emitting device ED1 and the third light emitting device ED3 can be commonly electrically connected to the first column line CL1. The second light emitting device ED2 and the fourth light emitting device ED4 can be electrically connected to the second column line CL2.

[0475] The plurality of banks BNK1-BNK4 can further include a second bank BNK2 on which the third light emitting device ED3 and the fourth light emitting device ED4 are mounted together. That is, the third light emitting device ED3 and the fourth light emitting device ED4 can be disposed together on the second bank BNK2.

[0476] Referring to Figure 18 The plurality of column lines CL1-CL4 can further include a third column line CL3 and a fourth column line CL4 spaced apart from each other.

[0477] The plurality of light emitting devices ED1-ED8 can further include a fifth light emitting device ED5 and a sixth light emitting device ED6 disposed between the third column line CL3 and the fourth column line CL4.

[0478] The fifth light emitting device ED5 can be electrically connected to the third column line CL3. The sixth light emitting device ED6 can be electrically connected to the fourth column line CL4.

[0479] The plurality of banks BNK1-BNK4 can include a third bank BNK3 on which the fifth light emitting device ED5 and the sixth light emitting device ED6 are mounted together.

[0480] Referring to Figure 18 The plurality of light emitting devices ED1-ED8 can further include a seventh light emitting device ED7 and an eighth light emitting device ED8 disposed between the third column line CL3 and the fourth column line CL4.

[0481] The fifth light emitting device ED5 and the seventh light emitting device ED7 can be commonly electrically connected with the third column line CL3. The sixth light emitting device ED6 and the eighth light emitting device ED8 can be commonly electrically connected with the fourth column line CL4.

[0482] The plurality of banks BNK1-BNK4 can further include a fourth bank BNK4 on which the seventh light emitting device ED7 and the eighth light emitting device ED8 are mounted together.

[0483] Referring to Figure 18The display panel 110 according to an embodiment of the disclosure can further include a first column connection electrode CCE1 for electrically connecting the first column line CL1 and the first light emitting device ED1, a second column connection electrode CCE2 for electrically connecting the second column line CL2 and the second light emitting device ED2, a third column connection electrode CCE3 for electrically connecting the first column line CL1 and the third light emitting device ED3, and a fourth column connection electrode CCE4 for electrically connecting the second column line CL2 and the fourth light emitting device ED4.

[0484] Referring to Figure 18 Each of the first column connection electrode CCE1 and the third column connection electrode CCE3 can be in a form protruding from the first column line CL1. For example, each of the first column connection electrode CCE1 and the third column connection electrode CCE3 can be electrically connected to the first column line CL1. For another example, each of the first column connection electrode CCE1 and the third column connection electrode CCE3 can be a portion (e.g., a first protrusion) protruding and extending from a portion of the first column line CL1. Each of the first column connection electrode CCE1 and the third column connection electrode CCE3 can be integrally formed with the first column line CL1.

[0485] Referring to Figure 18 Each of the second column connection electrode CCE2 and the fourth column connection electrode CCE4 can be in a form protruding from the second column line CL2. For example, each of the second column connection electrode CCE2 and the fourth column connection electrode CCE4 can be electrically connected to the second column line CL2. For another example, each of the second column connection electrode CCE2 and the fourth column connection electrode CCE4 can be a portion (e.g., a second protrusion) protruding and extending from a portion of the second column line CL2. Each of the second column connection electrode CCE2 and the fourth column connection electrode CCE4 can be integrally formed with the second column line CL2.

[0486] Referring to Figure 18 The display panel 110 according to an embodiment of the disclosure can further include a fifth column connection electrode CCE5 for electrically connecting the third column line CL3 and the fifth light emitting device ED5, a sixth column connection electrode CCE6 for electrically connecting the fourth column line CL4 and the sixth light emitting device ED6, a seventh column connection electrode CCE7 for electrically connecting the third column line CL3 and the seventh light emitting device ED7, and an eighth column connection electrode CCE8 for electrically connecting the fourth column line CL4 and the eighth light emitting device ED8.

[0487] Referring to Figure 18Each of the fifth column connection electrode CCE5 and the seventh column connection electrode CCE7 can be in a form protruding from the third column line CL3. For example, each of the fifth column connection electrode CCE5 and the seventh column connection electrode CCE7 can be electrically connected to the third column line CL3. For another example, each of the fifth column connection electrode CCE5 and the seventh column connection electrode CCE7 can be a portion (e.g., a third protrusion) protruding from and extending from a portion of the third column line CL3. Each of the fifth column connection electrode CCE5 and the seventh column connection electrode CCE7 can be integrally formed with the third column line CL3.

[0488] Referring to Figure 18 Each of the sixth column connection electrode CCE6 and the eighth column connection electrode CCE8 can be in a form protruding from the fourth column line CL4. For example, each of the sixth column connection electrode CCE6 and the eighth column connection electrode CCE8 can be electrically connected to the fourth column line CL4. For another example, each of the sixth column connection electrode CCE6 and the eighth column connection electrode CCE8 can be a portion (e.g., a fourth protrusion) protruding from and extending from a portion of the fourth column line CL4. Each of the sixth column connection electrode CCE6 and the eighth column connection electrode CCE8 can be integrally formed with the fourth column line CL4.

[0489] Referring to Figure 18 The first column line CL1 can protrude toward the second column line CL2 and extend onto the first bank BNK1. The second column line CL2 can protrude toward the first column line CL1 and extend onto the first bank BNK1.

[0490] Referring to Figure 18 The first column line CL1 can extend along a first side slope of the first bank BNK1 to a first portion of an upper surface of the first bank BNK1. The second column line CL2 can extend along a second side slope of the first bank BNK1 to a second portion of the upper surface of the first bank BNK1.

[0491] Referring to Figure 18 The first column connection electrode CCE1 can electrically connect the first column line CL1 and a first electrode (e.g., an anode electrode) of the first light emitting device ED1. The second column connection electrode CCE2 can electrically connect the second column line CL2 and a first electrode (e.g., an anode electrode) of the second light emitting device ED2.

[0492] For example, the first column connection electrode CCE1 can be a portion (e.g., a first protrusion) protruding from the first column line CL1 toward the second column line CL2. The second column connection electrode CCE2 can be a portion (e.g., a second protrusion) protruding from the second column line CL2 toward the first column line CL1.

[0493] Referring to Figure 18The first column connection electrode CCE1 and the second column connection electrode CCE2 can be positioned together on the first bank BNK1. The first light emitting device ED1 can be disposed on the first column connection electrode CCE1, and the second light emitting device ED2 can be disposed on the second column connection electrode CCE2.

[0494] Referring to Figure 18 The plurality of row lines RL1 and RL2 can include a first row line RL1 and a second row line RL2. The first row line RL1 can be disposed on the first light emitting device ED1, the second light emitting device ED2, the fifth light emitting device ED5, and the sixth light emitting device ED6. The second row line RL2 can be disposed on the third light emitting device ED3, the fourth light emitting device ED4, the seventh light emitting device ED7, and the eighth light emitting device ED8.

[0495] The first row line RL1 can be commonly electrically connected with the second electrode of each of the first light emitting device ED1, the second light emitting device ED2, the fifth light emitting device ED5, and the sixth light emitting device ED6. The second row line RL2 can be commonly electrically connected with the second electrode of each of the third light emitting device ED3, the fourth light emitting device ED4, the seventh light emitting device ED7, and the eighth light emitting device ED8.

[0496] The first column line CL1 can be commonly electrically connected with the first light emitting device ED1 and the third light emitting device ED3. The second column line CL2 can be commonly electrically connected with the second light emitting device ED2 and the fourth light emitting device ED4. The third column line CL3 can be commonly electrically connected with the fifth light emitting device ED5 and the seventh light emitting device ED7. The fourth column line CL4 can be commonly connected to the sixth light emitting device ED6 and the eighth light emitting device ED8.

[0497] Referring to Figure 18 Each of the first light emitting device ED1 to the eighth light emitting device ED8 can include a first electrode and a second electrode.

[0498] The first electrode of each of the first light emitting device ED1 and the third light emitting device ED3 can be commonly electrically connected with the first column line CL.

[0499] The first electrode of each of the second light emitting device ED2 and the fourth light emitting device ED4 can be commonly electrically connected with the second column line CL2.

[0500] The first electrode of each of the fifth light emitting device ED5 and the seventh light emitting device ED7 can be commonly electrically connected with the third column line CL3.

[0501] The first electrode of each of the sixth light emitting device ED6 and the eighth light emitting device ED8 can be commonly electrically connected with the fourth column line CL4.

[0502] The second electrode of each of the first light emitting device ED1, the second light emitting device ED2, the fifth light emitting device ED5, and the sixth light emitting device ED6 can be commonly electrically connected with the first row line RL1. The second electrode of each of the third light emitting device ED3, the fourth light emitting device ED4, the seventh light emitting device ED7, and the eighth light emitting device ED8 can be commonly electrically connected with the second row line RL2.

[0503] Referring to Figure 18 The plurality of drivers DRV can include a first driver DRV configured to drive all or part of the first to fourth column lines CL1 to CL4 and to drive the first and second row lines RL1 and RL2.

[0504] The first driver DRV can be configured to drive all or part of the first and second column lines CL1 and CL2 and to drive the first row line RL1.

[0505] Referring to Figure 18 Each of the first and second light emitting devices ED1 and ED2 can include a first electrode and a second electrode. The first electrode of the first light emitting device ED1 can be electrically connected to the first column line CL1, and the first electrode of the second light emitting device ED2 can be electrically connected to the second column line CL2. The second electrode of the first light emitting device ED1 and the second electrode of the second light emitting device ED2 can be commonly electrically connected to the first row line RL1.

[0506] Meanwhile, for example, the first to eighth light emitting devices ED1 to ED8 can all be light emitting devices capable of emitting light.

[0507] For another example, among the first to eighth light emitting devices ED1 to ED8, the first, third, fifth, and seventh light emitting devices ED1, ED3, ED5, and ED7 can be main light emitting devices, and the second, fourth, sixth, and eighth light emitting devices ED2, ED4, ED6, and ED8 can be redundant light emitting devices. Here, the redundant light emitting devices can be light emitting devices used in the case where there is a defect in the main light emitting devices or the main light emitting devices are not transferred.

[0508] In this case, the first and third column lines CL1 and CL3 can be main column lines, and the second and fourth column lines CL2 and CL4 can be redundant column lines.

[0509] For another example, among the first to eighth light emitting devices ED1 to ED8, the second, fourth, sixth, and eighth light emitting devices ED2, ED4, ED6, and ED8 can be main light emitting devices, and the first, third, fifth, and seventh light emitting devices ED1, ED3, ED5, and ED7 can be redundant light emitting devices.

[0510] In this case, the second column line CL2 and the fourth column line CL4 can be main column lines, and the first column line CL1 and the third column line CL3 can be redundant column lines.

[0511] For example, only one of the main light emitting device and the redundant light emitting device can be driven. In this case, at any point in time, a signal can be applied to only one of the first column line CL1 and the second column line CL2. Accordingly, at any point in time, only one of the first light emitting device ED1 and the second light emitting device ED2 can emit light.

[0512] For another example, both the main light emitting device and the redundant light emitting device can be driven to emit light. In this case, at any point in time, a signal can be applied to both the first column line CL1 and the second column line CL2. Accordingly, at any point in time, both the first light emitting device ED1 and the second light emitting device ED2 can emit light.

[0513] Reference Figure 18 During emission of light by at least one of the first light emitting device ED1 and the second light emitting device ED2, the first low potential voltage VSS1 can be applied to the first row line RL1. For example, during emission of light by the first light emitting device ED1, the first low potential voltage VSS1 can be applied to the first row line RL1.

[0514] Reference Figure 7 and Figure 18 When a second low potential voltage VSS2 higher than the first low potential voltage VSS1 is applied to the first row line RL1, both the first light emitting device ED1 and the second light emitting device ED2 can not emit light.

[0515] Reference Figure 7 and Figure 18 During a first period, the first low potential voltage VSS1 can be applied to the first row line RL1. During a second period different from the first period, a second low potential voltage VSS2 higher than the first low potential voltage VSS1 can be applied to the first row line RL1. During a third period different from the first period and the second period, a signal TDS having a variable voltage level can be applied to the first row line RL1.

[0516] For example, the third period can be a period for touch sensing. During the third period, the signal TDS applied to the first row line RL1 can be a signal having a variable voltage level, and a low level voltage of the signal TDS can be higher than the first low potential voltage VSS1. Accordingly, during the third period, unwanted light emission of the light emitting devices ED1, ED2, ED5, and ED6 overlapping the first row line RL1 can be prevented.

[0517] Figure 19 is a cross-sectional view of a display area DA in a portion 2000 of the display device 100 according to an embodiment of the disclosure. Figure 19 is a cross-sectional view along Figure 18 a C-D cut line of

[0518] Referring to Figure 19 The display panel 110 according to an embodiment of the disclosure can further include a substrate 210, a layer stack 1410 on the substrate 210, a first bank BNK1 on the layer stack 1410, a first optical layer 1517a disposed on the layer stack 1410 and surrounding each of the first light emitting device ED1 and the second light emitting device ED2, and a cover layer 1518 disposed on the first optical layer 1517a.

[0519] The first light emitting device ED1 and the second light emitting device ED2 can be disposed together on the first bank BNK1. The first row line RL1 can be disposed on the first light emitting device ED1, the second light emitting device ED2, and the first optical layer 1517a. The first column line CL1 can protrude toward the first column line CL1, and the second column line CL2 can protrude toward the first column line CL1.

[0520] The first column line CL1 can extend along a first side slope of the first bank BNK1 to a first portion of an upper surface of the first bank BNK1 on the layer stack 1410. The second column line CL2 can extend along a second side slope of the first bank BNK1 to a second portion of the upper surface of the first bank BNK1 on the layer stack 1410.

[0521] Referring to Figure 19 The display panel 110 according to an embodiment of the disclosure can further include a second optical layer 1517b surrounding the first optical layer 1517a and a third optical layer 1517c disposed on the first row line RL1.

[0522] Referring to Figure 19 The display panel 110 according to an embodiment of the disclosure can further include a black matrix BM disposed on the third optical layer 1517c.

[0523] For example, the black matrix BM can overlap at least a portion of the first bank BNK1. The black matrix BM can overlap at least a portion of each of the first column line CL1 and the second column line CL2. The black matrix BM can contact the first row line RL1 at a boundary region of the first optical layer 1517a and the second optical layer 1517b.

[0524] The first driver DRV can be configured to drive the first column line and the first row line RL1, and can be disposed between the substrate 210 and the insulating layers 1515a, 1515b, and 1515c. The first driver DRV can be disposed in the display area DA.

[0525] The layer stack 1410 can include a side protection layer 1513 disposed on a side of the first driver DRV, an upper protection layer 1514 disposed on the first driver DRV and the side protection layer 1513, and a plurality of insulating layers 1515a, 1515b, and 1515c disposed on the upper protection layer 1514.

[0526] The side protection layer 1513 can include at least one organic layer. The plurality of insulating layers can include a first insulating layer 1515a on the upper protection layer 1514 and a second insulating layer 1515b on the first insulating layer 1515a. The side protection layer 1513 can include at least one thick organic layer to prevent the first driver DRV from falling.

[0527] The layer stack 1410 can further include a line connection pattern LCP connecting at least one of the first row line RL1, the first column line CL1, and the second column line CL2 to the first driver DRV.

[0528] The line connection pattern LCP can include a first line connection pattern LCP1 disposed on the side protection layer 1513, a second line connection pattern LCP2 disposed on the upper protection layer 1514 and electrically connected to the first line connection pattern LCP1 through a hole in the upper protection layer 1514, a third line connection pattern LCP3 disposed on the first insulating layer 1515a and electrically connected to the second line connection pattern LCP2 through a hole in the first insulating layer 1515a, and a fourth line connection pattern LCP4 disposed on the second insulating layer 1515b and electrically connected to the third line connection pattern LCP3 through a hole in the second insulating layer 1515b.

[0529] The first line connection pattern LCP1 can be electrically connected to the first driver DRV. The fourth line connection pattern LCP4 can be electrically connected to one of the first electrode and the second electrode of the first light emitting device ED1, or can be electrically connected to one of the first electrode and the second electrode of the second light emitting device ED2.

[0530] The layer stack 1410 can further include a passivation layer 1516 disposed on the first column line CL1 and the second column line CL2, the first column connection electrode CCE1 and the second column connection electrode CCE2, and the third insulating layer 1515c.

[0531] At least a portion of the passivation layer 1516 can be removed. For example, the passivation layer 1516 can be removed in regions where the first solder pattern SDP1 and the second solder pattern SDP2 are disposed. The first solder pattern SDP1 and the second solder pattern SDP2 can be disposed in the first opening and the second opening of the passivation layer 1516, respectively.

[0532] Referring to Figure 19 The first bank BNK1 can include a first mounting portion MP on which the first light emitting device ED1 is mounted and a second mounting portion RP on which the second light emitting device ED2 is mounted. The first mounting portion MP and the second mounting portion RP can be connected.

[0533] Referring to Figure 19 The layer stack 1410 can further include a buffer layer 1511 disposed on the substrate 210 and an adhesive layer 1512 disposed on the buffer layer 1511. The side protection layer 1513 can be disposed on the adhesive layer 1512.

[0534] The display panel 110 according to an embodiment of the disclosure can further include a first solder pattern SDP1 electrically connecting the first column connection electrode CCE1 and a first electrode of the first light emitting device ED1, and a second solder pattern SDP2 electrically connecting the second column connection electrode CCE2 and a first electrode of the second light emitting device ED2.

[0535] For example, each of the first solder pattern SDP1 and the second solder pattern SDP2 can include indium (In), tin (Sn), or an indium-tin alloy.

[0536] For example, the first column connection electrode CCE1 and the first light emitting device ED1 can be electrically connected by using eutectic bonding of the first solder pattern SDP1, and the second column connection electrode CCE2 and the second light emitting device ED2 can be electrically connected by using eutectic bonding of the second solder pattern SDP2. However, embodiments of the disclosure are not limited thereto. For example, each of the first solder pattern SDP1 and the second solder pattern SDP2 can be composed of indium (In), tin (Sn), or an alloy thereof, but embodiments of the disclosure are not limited thereto. For example, each of the first solder pattern SDP1 and the second solder pattern SDP2 can be a bonding pad, but embodiments of the disclosure are not limited thereto.

[0537] As described above, the first column connection electrode CCE1 can be electrically connected to a first electrode of the first light emitting device ED1. The first column connection electrode CCE1 can be a portion of the first column line CL1 protruding toward the second column line CL2 and extending along one side of the first bank BNK1 to an upper surface of the first bank BNK1.

[0538] The second column connection electrode CCE2 can be electrically connected to the first electrode of the second light emitting device ED2. The second column connection electrode CCE2 can be a portion of the second column line CL2 protruding toward the first column line CL1 and extending to the upper surface of the first bank BNK1 along the other side of the first bank BNK1.

[0539] The first optical layer 1517a can be disposed to surround the first light emitting device ED1 and the second light emitting device ED2 disposed on the first bank BNK1.

[0540] The first optical layer 1517a can also be disposed to surround the first bank BNK1.

[0541] As described above, one of the first column line CL1 and the second column line CL2 can be a main column line, and the other can be a redundant column line. In this case, a signal can be applied only to one of the first column line CL1 and the second column line CL2 as the main column line.

[0542] As described above, the first driver DRV is configured to drive the first row line RL1, the first column line CL1, and the second column line CL2, and can be disposed between the substrate 210 and the insulating layer 1515c. The first driver DRV can be disposed in a display area DA in which an image is displayed.

[0543] Reference Figure 19 The first bank BNK1 is located in the display area DA, and can be disposed on the third insulating layer 1515c.

[0544] The first column line CL1 can be disposed on the third insulating layer 1515c, and can include a protrusion extending to the upper side of the first bank BNK1 along one side of the first bank BNK1. The protrusion of the first column line CL1 can be referred to as a first column connection electrode CCE1.

[0545] The first light emitting device ED1 can be located in the display area DA, and can be disposed on the first column connection electrode CCE1.

[0546] The first optical layer 1517a can be disposed to surround the first light emitting device ED1. The second optical layer 1517b can be disposed on the side of the first optical layer 1517a.

[0547] The first row line RL1 can be disposed on the first light emitting device ED1 and the first optical layer 1517a.

[0548] The first electrode of the first light emitting device ED1 can be electrically connected to the first column line CL1. For example, the first electrode of the first light emitting device ED1 can be electrically connected to the first column line CL1 through the first solder pattern SDP1.

[0549] The second electrode of the first light emitting device ED1 can be electrically connected to the first row line RL1.

[0550] The second column line CL2 can be disposed on the third insulating layer 1515c and can include a protrusion extending to an upper portion of the first bank BNK1 along another side of the first bank BNK1. The protrusion of the second column line CL1 can be referred to as a second column connection electrode CCE2.

[0551] The second light emitting device ED2 can be located in the display area DA and can be disposed on the second column connection electrode CCE2.

[0552] The first optical layer 1517a can be disposed to surround the first light emitting device ED1 and the second light emitting device ED2. The second optical layer 1517b can be disposed on sides of the first optical layer 1517a. For example, the second optical layer 1517b can be disposed on two of four sides of the first optical layer 1517a.

[0553] The first row line RL1 can be disposed on the first light emitting device ED1, the second light emitting device ED2, and the first optical layer 1517a.

[0554] The first electrode of the second light emitting device ED2 can be electrically connected to the second column line CL2. For example, the first electrode of the second light emitting device ED2 can be electrically connected to the second column line CL2 through the second solder pattern SDP2.

[0555] The second electrode of the second light emitting device ED2 can be electrically connected to the first row line RL1 in common with the second electrode of the first light emitting device ED1.

[0556] The first row line RL1 can be disposed on the first light emitting device ED1 and the second light emitting device ED2 and can overlap the first light emitting device ED1 and the second light emitting device ED2.

[0557] The third optical layer 1517c can be disposed on the first row line RL1.

[0558] The black matrix BM can be disposed on the first row line RL1. The black matrix BM can have openings overlapping the first light emitting device ED1 and the second light emitting device ED2, respectively. At least a portion of the black matrix BM can overlap the first bank BNK1. At least a portion of the black matrix BM can overlap a boundary of the first optical layer 1517a and the second optical layer 1517b. At the boundary of the first optical layer 1517a and the second optical layer 1517b, an upper surface of the first row line RL1 and a back surface of the black matrix BM can be in contact.

[0559] REFERENCE Figure 19The first optical layer 1517a and the third optical layer 1517c can include metal particles (e.g., fine metal particles) that cause light scattering. The metal particles included in the first optical layer 1517a and the third optical layer 1517c can not be included in the second optical layer 1517b.

[0560] The display device 100 according to an embodiment of the disclosure can include a light scattering structure in which the first optical layer 1517a includes metal particles (e.g., fine metal particles). Through the light scattering structure, light emitted from at least one of the first light emitting device ED1 and the second light emitting device ED2 can be scattered by the first optical layer 1517a and emitted to the outside of the display panel 110 toward a light emission direction for image display. That is, the amount of light lost within the display panel 110 can be reduced by using the light scattering structure including the first optical layer 1517a, thereby increasing the amount of light emitted to the outside of the display panel 110. Accordingly, light emission efficiency (also referred to as light extraction efficiency) can be improved.

[0561] The display device 100 according to an embodiment of the disclosure can further include a light scattering structure in which the third optical layer 1517c includes metal particles (e.g., fine metal particles). Through the light scattering structure, light emitted from at least one of the first light emitting device ED1 and the second light emitting device ED2 can be scattered by the third optical layer 1517c and emitted to the outside of the display panel 110 toward a light emission direction for image display. That is, the amount of light lost within the display panel 110 can be reduced by the light scattering structure including the third optical layer 1517c, thereby increasing the amount of light emitted to the outside of the display panel 110. Accordingly, light emission efficiency (i.e., light extraction efficiency) can be further improved.

[0562] Referring to Figure 19 The display device 100 according to an embodiment of the disclosure can include a light reflection structure in which the first column connection electrode CCE1 and the second column connection electrode CCE2 include a reflective material. According to the light reflection structure, light emitted downward from at least one of the first light emitting device ED1 and the second light emitting device ED2 can be reflected by one of the first column connection electrode CCE1 and the second column connection electrode CCE2 and emitted to the outside of the display panel 110 toward a light emission direction for image display.

[0563] Since light reflection occurs by at least one of the first column connection electrode CCE1 and the second column connection electrode CCE2 through the light reflection structure, the amount of light lost within the display panel 110 can be reduced, thereby increasing the amount of light emitted to the outside of the display panel 110. Accordingly, light emission efficiency (i.e., light extraction efficiency) can be further improved.

[0564] As described above, the display device 100 according to an embodiment of the disclosure can further improve the light emission efficiency or light extraction efficiency by reducing the amount of light lost within the display panel 110 and by increasing the amount of light emitted outside the display panel 110 through the light emission efficiency improvement structure including the light scattering structure and the light reflection structure. In addition, by the light emission efficiency improvement described above, it is possible to reduce the power consumption of the display device 100 by expressing a desired brightness with less power.

[0565] Referring to Figure 19 The passivation layer 1516 can be disposed on the third insulating layer 1515c, extend along the side surface of the first bank BNK1, and can have an opening at the upper portion of the first bank BNK1. On the first bank BNK1, the passivation layer 1516 can be disposed on the first column line CL1 and the first column connection electrode CCE1.

[0566] The opening of the passivation layer 1516 can overlap at least a portion of the first column connection electrode CCE1. The first electrode of the first light emitting device ED1 can be electrically connected to the first column connection electrode CCE1 through the opening of the passivation layer 1516.

[0567] Figure 20 And Figure 21 is a cross-sectional view of an electrostatic discharge region EDA included in the non-display region NDA of the portion 2000 of the display device 100 according to an embodiment of the disclosure.

[0568] Referring to Figure 20 and Figure 21 The display device 100 according to an embodiment of the disclosure can include a substrate 210, a layer stack 1410, an electrostatic discharge line EDL, and two or more electrostatic discharge patterns EDP.

[0569] Referring to Figure 20 and Figure 21 The layer stack 1410 can include a buffer layer 1511 on the substrate 210, an adhesive layer 1512 on the buffer layer 1511, a side surface protection layer 1513 on the adhesive layer 1512, an upper protection layer 1514 on the side surface protection layer 1513, and an insulating layer on the upper protection layer 1514.

[0570] The insulating layer on the upper protection layer 1514 can be composed of one layer or two or more layers. For example, as shown in Figure 20 and Figure 21 The insulating layer on the upper protection layer 1514 can include a first insulating layer 1515a, a second insulating layer 1515b, and a third insulating layer 1515c. For ease of explanation, in the following description, a case in which the insulating layer includes the first to third insulating layers 1515a, 1515b, and 1515c will be described as an example.

[0571] Referring to Figure 20 and Figure 21 The layer stack 1410 can further include a passivation layer 1516 on the third insulating layer 1515c.

[0572] Referring to Figure 20 and Figure 21 An electrostatic discharge line EDL can be disposed between the third insulating layer 1515c and the passivation layer 1516. Two or more electrostatic discharge patterns EDP can be disposed on the passivation layer 1516.

[0573] For example, each of the two or more electrostatic discharge patterns EDP can have a lightning rod shape capable of collecting static electricity.

[0574] The first to third insulating layers 1515a, 1515b, and 1515c can be disposed on the substrate 210 and can be disposed across the display area DA and the non-display area NDA.

[0575] The electrostatic discharge line EDL can be located in the non-display area NDA and can be disposed on the third insulating layer 1515c.

[0576] The passivation layer 1516 can be disposed on the electrostatic discharge line EDL.

[0577] Referring to Figure 20 and Figure 21 The display device 100 according to an embodiment of the disclosure can further include an organic insulating layer 2500 disposed on the passivation layer 1516.

[0578] Referring to Figure 20 and Figure 21 The organic insulating layer 2500 can have two or more holes H located in the non-display area NDA.

[0579] Referring to Figure 20 and Figure 21 The two or more electrostatic discharge patterns EDP can be located in the non-display area NDA and can be respectively disposed within the two or more holes H of the organic insulating layer 2500.

[0580] Referring to Figure 20 and Figure 21 Each of the two or more electrostatic discharge patterns EDP can be disposed on the passivation layer 1516 within the two or more holes H and can be electrically connected to the electrostatic discharge line EDL through a contact hole CTH of the passivation layer 1516.

[0581] The electrostatic discharge line EDL can be electrically connected to a ground GND located in the non-display area NDA. That is, the two or more electrostatic discharge patterns EDP can be electrically connected to the ground GND through the electrostatic discharge line EDL.

[0582] For example, the electrostatic discharge line EDL and the ground GND can be directly connected without another conductor.

[0583] For another example, the electrostatic discharge line EDL and the ground GND can be connected via another conductor. To this end, as shown in FIGS. 1A and 1B, the display device 100 according to an embodiment of the disclosure can further include an electrostatic discharge path pattern EDLP electrically connecting the electrostatic discharge line EDL and the ground GND. Figure 20 and Figure 21 For another example, the electrostatic discharge line EDL and the ground GND can be connected via another conductor. To this end, as shown in FIGS. 1A and 1B, the display device 100 according to an embodiment of the disclosure can further include an electrostatic discharge path pattern EDLP electrically connecting the electrostatic discharge line EDL and the ground GND.

[0584] For example, the electrostatic discharge path pattern EDLP can include at least one of a first electrostatic discharge path pattern EDLP1, a second electrostatic discharge path pattern EDLP2, a third electrostatic discharge path pattern EDLP3, and a fourth electrostatic discharge path pattern EDLP4, but embodiments of the disclosure are not limited thereto. For example, the first electrostatic discharge path pattern EDLP1, the second electrostatic discharge path pattern EDLP2, the third electrostatic discharge path pattern EDLP3, and the fourth electrostatic discharge path pattern EDLP4 can be disposed within different metal layers.

[0585] For example, the first electrostatic discharge path pattern EDLP1 can be disposed on the side protection layer 1513. The upper protection layer 1514 can be disposed on the first electrostatic discharge path pattern EDLP1.

[0586] The second electrostatic discharge path pattern EDLP2 can be disposed on the upper protection layer 1514 and can be electrically connected to the first electrostatic discharge path pattern EDLP1 through a hole in the upper protection layer 1514. The first insulating layer 1515a can be disposed on the second electrostatic discharge path pattern EDLP2.

[0587] The third electrostatic discharge path pattern EDLP3 can be disposed on the first insulating layer 1515a and can be electrically connected to the second electrostatic discharge path pattern EDLP2 through a hole in the first insulating layer 1515a. The second insulating layer 1515b can be disposed on the third electrostatic discharge path pattern EDLP3.

[0588] The fourth electrostatic discharge path pattern EDLP4 can be disposed on the second insulating layer 1515b and the second insulating layer 1515b can be electrically connected to the third electrostatic discharge path pattern EDLP3 through a hole. The third insulating layer 1515c can be disposed on the fourth electrostatic discharge path pattern EDLP4.

[0589] The electrostatic discharge line EDL can be electrically connected to the ground GND through at least one of the first electrostatic discharge path pattern EDLP1, the second electrostatic discharge path pattern EDLP2, the third electrostatic discharge path pattern EDLP3, and the fourth electrostatic discharge path pattern EDLP4.

[0590] Referring to Figure 20 and Figure 21 , two or more electrostatic discharge patterns EDP can be disposed in the non-display area NDA and can be arranged along a boundary of the display area DA.

[0591] As described above with reference to Figure 16 and Figure 17 , the electrostatic discharge area EDA can be an area located in the non-display area NDA but present along a boundary of the display area DA. Two or more electrostatic discharge patterns EDP can be located in the electrostatic discharge area EDA.

[0592] Referring to Figure 20 and Figure 21 , the display device 100 according to an embodiment of the disclosure can further include an outer bank BNK_O located in the non-display area NDA and disposed on the third insulating layer 1515c.

[0593] The electrostatic discharge line EDL can be disposed on the third insulating layer 1515c, can extend along a side surface of the outer bank BNK_O, and can be disposed on an upper surface of the outer bank BNK_O.

[0594] The electrostatic discharge line EDL can be disposed in the non-display area NDA and can be electrically connected to the ground GND disposed in the non-display area NDA.

[0595] Two or more electrostatic discharge patterns EDP can be disposed in the non-display area NDA and can be arranged along a boundary of the display area DA.

[0596] Two or more electrostatic discharge patterns EDP can be located on the outer bank BNK_O and can be electrically connected to the electrostatic discharge line EDL on the outer bank BNK_O.

[0597] The passivation layer 1516 can be disposed between the two or more electrostatic discharge patterns EDP and the electrostatic discharge line ELD. Accordingly, each of the two or more electrostatic discharge patterns EDP can be electrically connected to the electrostatic discharge line EDL through a contact CHT of the passivation layer 1516.

[0598] Referring to Figure 20 and Figure 21The display device 100 according to an embodiment of the disclosure can further include a plurality of metal patterns MP disposed on the organic insulating layer 2500 and including the same material as the electrostatic discharge pattern EDP.

[0599] The plurality of metal patterns MP can be in an electrically floating state and can not be connected to the two or more electrostatic discharge patterns EDP.

[0600] Referring together Figure 20-21 and Figure 19 The electrostatic discharge line EDL can include the same material as the first column connection electrode CCE1.

[0601] Referring together Figure 20-21 and Figure 19 In one embodiment, the electrostatic discharge pattern EDP can include the same material as the first solder pattern SDP1. For another example, the electrostatic discharge pattern EDP can include the same material as the first row line RL1.

[0602] Referring together Figure 20-21 and Figure 19 The organic insulating layer 2500 can include the same material as the second optical layer 1517b. For example, the organic insulating layer 2500 can be the second optical layer 1517b.

[0603] The first optical layer 1517a can include metal particles that cause light scattering. The metal particles included in the first optical layer 1517a can not be included in the second optical layer 1517b and the organic insulating layer 2500.

[0604] Referring Figure 20 The organic insulating layer 1517c can have two holes H on the first bank BNK1. The electrostatic discharge pattern EDP can be disposed within each of the two holes H. One of the plurality of metal patterns MP can be disposed on the organic insulating layer 1517c between the two holes H. That is, one of the plurality of metal patterns MP can be disposed on the organic insulating layer 1517c between the two electrostatic discharge patterns EDP.

[0605] Referring Figure 21 The organic insulating layer 1517c can have three or more holes H on the first bank BNK1. The electrostatic discharge pattern EDP can be disposed within each of the three or more holes H. At least one of the plurality of metal patterns MP can be disposed on the organic insulating layer 1517c between two adjacent holes H. That is, at least one of the plurality of metal patterns MP can be disposed on the organic insulating layer 1517c between two adjacent electrostatic discharge patterns EDP.

[0606] If the number of holes H formed in the organic insulating layer 1517c increases, the gap between two adjacent holes H narrows, so that the organic insulating layer 1517c between the two holes H can be a column pattern PRT having an upward protruding shape. That is, the organic insulating layer 1517c between two adjacent electrostatic discharge patterns EDP can be a column pattern PRT having an upward protruding shape.

[0607] Referring to Figure 20-21 and Figure 19 , the display device 100 according to an embodiment of the disclosure can include a substrate 210, a first bank BNK1 disposed in a display area DA, an outer bank BNK_O disposed in a non-display area NDA which is an area outside the display area DA, a first light emitting device ED1 disposed on the first bank BNK1, and an electrostatic discharge pattern EDP disposed on the outer bank BNK_O.

[0608] Referring to Figure 20-21 and Figure 19 , the display device 100 according to an embodiment of the disclosure can further include a first column connection electrode CCE1 disposed between the first bank BNK1 and the first light emitting device ED1, an electrostatic discharge line EDL disposed between the outer bank BNK_O and the electrostatic discharge pattern EDP, and a passivation layer 1516 disposed on the first column connection electrode CCE1 and the electrostatic discharge line EDL.

[0609] Referring to Figure 20-21 and Figure 19 , the first electrode of the first light emitting device ED1 can be electrically connected to the first column connection electrode CCE1 through a contact hole of the passivation layer 1516. The electrostatic discharge pattern EDP can be electrically connected to the electrostatic discharge line EDL through another contact hole CTH of the passivation layer 1516.

[0610] Referring to Figure 20-21 and Figure 19 , the display device 100 according to an embodiment of the disclosure can further include a first optical layer 1517a surrounding the first light emitting device ED1 and a second optical layer 1517b disposed on one side of the first optical layer 1517a.

[0611] Referring to Figure 20 and Figure 21 , the first optical layer 1517a or the second optical layer 1517b can be disposed to extend from the display area DA to the non-display area NDA. In the non-display area NDA, the first optical layer 1517a or the second optical layer 1517b can have a hole H, and the electrostatic discharge pattern EDP can be disposed within the hole H of the first optical layer 1517a or the second optical layer 1517b.

[0612] Figure 22 is a diagram for explaining electrostatic discharge according to an embodiment of the disclosure. However, Figure 22 shows the same electrostatic discharge structure as Figure 21 . Thus, the description of the electrostatic discharge structure will be omitted.

[0613] Referring to Figure 22 , the electrostatic discharge structure according to an embodiment of the disclosure can include an electrostatic discharge pattern EDP, an electrostatic discharge line EDL, and a ground GND.

[0614] Referring to Figure 22 , each of the two or more electrostatic discharge patterns EDP can have a lightning rod shape in which electrostatic is easily collected, so that the electrostatic 2700 generated in or introduced into the display panel 110 can be easily collected in at least one electrostatic discharge pattern EDP.

[0615] The electrostatic 2700 flowing into the at least one electrostatic discharge pattern EDP can be discharged to the ground GND through the electrostatic discharge line EDL connected to the electrostatic discharge pattern EDP.

[0616] According to the electrostatic discharge structure according to an embodiment of the disclosure, it is possible to prevent the electrostatic 2700 generated in or introduced into the display panel 110 from flowing into the internal circuit configuration of the display panel 110 and / or the external circuit configuration of the display panel 110.

[0617] Thus, it is possible to prevent the internal circuit configuration of the display panel 110 and / or the external circuit configuration of the display panel 110 from being electrically damaged by the electrostatic 2700.

[0618] For example, the internal circuit configuration of the display panel 110 can include a plurality of drivers DRV, various electrodes or wires (e.g., row lines, column lines, signal lines), or a pad portion 211 disposed on the display panel 110, etc. The external circuit configuration of the display panel 110 can include a flexible printed circuit 102, a printed circuit board 104, or various circuit components mounted on the printed circuit board 104.

[0619] The display device 100 according to an embodiment of the disclosure can be included in various devices or electronic devices. For example, various electronic devices can include a wearable device such as a smart watch, a mobile device, a laptop computer, and a monitor or a television (TV).

[0620] Although the embodiments of the present disclosure are described in detail with reference to the accompanying drawings, the present disclosure is not necessarily limited to the embodiments and various modifications can be made without departing from the technical spirit of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are not intended to limit the technical spirit of the present disclosure, but to explain, and the scope of the technical spirit of the present disclosure is not limited by the embodiments. Accordingly, the above-described embodiments should be understood as illustrative rather than in all respects restrictive.

Claims

1. A display device, comprising: substrate; An insulating layer is disposed on the substrate and on both the display area and the non-display area; An electrostatic discharge line, wherein the electrostatic discharge line is located in the non-display area and is disposed on the insulating layer; A passivation layer is disposed on the electrostatic discharge line; An organic insulating layer is disposed on the passivation layer and has two or more holes located in the non-display area; as well as Two or more electrostatic discharge patterns, wherein the two or more electrostatic discharge patterns are located in the non-display area and each is disposed within the two or more holes; Each of the two or more electrostatic discharge patterns is disposed on the passivation layer within the two or more holes, and is electrically connected to the electrostatic discharge line through the contact holes of the passivation layer.

2. The display device according to claim 1, further comprising an outer retaining portion, the outer retaining portion being located in the non-display area and disposed on the insulating layer, in, The electrostatic discharge line is disposed on the insulating layer and extends along one side of the outer embankment to be disposed on the upper surface of the outer embankment.

3. The display device according to claim 2, wherein, The two or more electrostatic discharge patterns are located on the outer embankment.

4. The display device according to claim 1 further includes a plurality of metal patterns disposed on the organic insulating layer and comprising the same material as the electrostatic discharge pattern.

5. The display device according to claim 4, wherein, The plurality of metal patterns are in an electrically floating state and are not connected to the two or more electrostatic discharge patterns.

6. The display device according to claim 1, further comprising a grounding point disposed on the substrate and located in the non-display area. in, The grounding power is connected to the electrostatic discharge line.

7. The display device according to claim 1, wherein, The two or more electrostatic discharge patterns are disposed in the non-display area and arranged along the boundary of the display area.

8. The display device according to claim 1, further comprising: A first embankment is located in the display area and disposed on the insulating layer; The first column of lines is disposed on the insulating layer and includes a first column of connecting electrodes, the first column of connecting electrodes being protrusions extending along one side of the first embankment to the upper part of the first embankment; A first light-emitting device is disposed in the display area and on the first column connection electrode; A first optical layer surrounds the first light-emitting device; A second optical layer is disposed on one side of the first optical layer; as well as The first row of lines is disposed on the first light-emitting device and the first optical layer. Wherein, the first electrode of the first light-emitting device is electrically connected to the first column line; and The second electrode of the first light-emitting device is electrically connected to the first row line.

9. The display device according to claim 8, wherein, The electrostatic discharge line is made of the same material as the first column of connecting electrodes.

10. The display device according to claim 8, further comprising a first solder pattern disposed between the first column of connecting electrodes and the first electrode of the first light-emitting device. in, The electrostatic discharge pattern includes the same material as the first solder pattern or the first row line.

11. The display device according to claim 8, wherein, The organic insulating layer comprises the same material as the first optical layer or the second optical layer.

12. The display device according to claim 11, wherein, The first optical layer comprises metal particles.

13. The display device according to claim 8, wherein, The passivation layer is disposed on the insulating layer, extends along one side of the first embankment, and has an opening on the upper part of the first embankment; Wherein, on the first embankment, the passivation layer is disposed on the first column of connecting electrodes, and the opening overlaps with at least a portion of the first column of connecting electrodes; and The first electrode of the first light-emitting device is electrically connected to the first column connection electrode through the opening.

14. The display device according to claim 8, further comprising: The second column of lines is disposed on the insulating layer and includes a second column of connecting electrodes, the second column of connecting electrodes being protrusions extending along the other side of the first embankment to the upper part of the first embankment; as well as A second light-emitting device is located in the display area and is disposed on the second column of connecting electrodes; Wherein, the first electrode of the second light-emitting device is electrically connected to the second column line; and The second electrode of the second light-emitting device and the second electrode of the first light-emitting device are electrically connected to the first row line.

15. The display device according to claim 14, further comprising: The second dike is disposed on the insulating layer; A third light-emitting device and a fourth light-emitting device are located in the display area and are disposed on the second embankment; as well as The second row of lines is arranged on the third and fourth light-emitting devices; The first electrode of the third light-emitting device is electrically connected to the first column line together with the first electrode of the first light-emitting device; The first electrode of the fourth light-emitting device and the first electrode of the second light-emitting device are electrically connected to the second column line; and The second electrode of the third light-emitting device and the second electrode of the fourth light-emitting device are electrically connected to the second row line.

16. The display device of claim 8, further comprising a driver configured to drive the first column line and the first row line, and disposed between the substrate and the insulating layer.

17. The display device according to claim 16, wherein, The driver is located in the display area.

18. The display device according to claim 16, further comprising a side protective layer disposed on one side of the driver.

19. The display device according to claim 18, wherein, The side protective layer includes at least one organic layer.

20. The display device according to claim 8, wherein, During the emission of light by the first light-emitting device, a first low potential voltage is applied to the first row line, and During the period when a second low potential voltage higher than the first low potential voltage is applied to the first row line, the first light-emitting device does not emit light.

21. The display device according to claim 8, wherein, During the first time period, a first low potential voltage is applied to the first row line. During a second time period, different from the first time period, a second low potential voltage higher than the first low potential voltage is applied to the first line; and During a third time period, which is different from the first and second time periods, a signal with a variable voltage level is applied to the first row line.

22. The display device according to claim 21, wherein, The low-level voltage of the signal, which has a variable voltage level, is higher than the first low-potential voltage.

23. A display device, comprising: substrate; The embankment is located in the display area; An outer embankment is located in a non-display area, which is the area outside the display area. A light-emitting device is disposed on the embankment; as well as An electrostatic discharge pattern is disposed on the outer embankment.

24. The display device according to claim 23, further comprising: A connecting electrode is disposed between the embankment and the light-emitting device; An electrostatic discharge line is disposed between the outer embankment and the electrostatic discharge pattern. A passivation layer is disposed on the connecting electrode and the electrostatic discharge line; The first electrode of the light-emitting device is electrically connected to the connecting electrode through the contact hole of the passivation layer; and The electrostatic discharge pattern is electrically connected to the electrostatic discharge line through another contact hole in the passivation layer.

25. The display device according to claim 23, further comprising: A first optical layer surrounds the light-emitting device; as well as A second optical layer is disposed on one side of the first optical layer; Wherein, the first optical layer or the second optical layer is configured to extend from the display area to the non-display area; The first optical layer or the second optical layer includes a hole located in the non-display area; and The electrostatic discharge pattern is disposed within the hole.

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