Display panel

Abstract

The display panel includes pixels. The signal line is electrically connected to the pixel. The signal pad is connected to the signal line. The signal pad includes a first conductive layer electrically connected to a portion of the signal line. The second conductive layer is disposed on the first conductive layer. The insulating layer is disposed between the first conductive layer and the second conductive layer. An opening is defined in the second conductive layer. The opening exposes a portion of a top surface of the insulating layer.

Description

Technical Field

[0001] This disclosure relates to display panels, electronic devices, and methods for manufacturing electronic devices, and more particularly, to display panels, electronic devices, and methods for manufacturing electronic devices including pad areas. Background Technology

[0002] Various electronic devices include at least one display area that is activated in response to an electrical signal. The electronic device can detect input applied from the outside through the display area and also display various images in the display area to provide information to the user.

[0003] Electronic devices include a display panel and a circuit board. The display panel can be connected to the motherboard via the circuit board. A driver chip can be mounted on the display panel. Summary of the Invention

[0004] This disclosure provides a display panel with enhanced bonding reliability and an electronic device including the display panel.

[0005] This disclosure also provides a method for manufacturing electronic devices with increased processability.

[0006] According to an embodiment of the present invention, a display panel includes pixels. Signal lines are electrically connected to the pixels. Signal pads are connected to the signal lines. Each signal pad includes a first conductive layer on a portion electrically connected to the signal line. A second conductive layer is disposed on the first conductive layer. An insulating layer is disposed between the first and second conductive layers. An opening is defined in the second conductive layer. The opening exposes a portion of the top surface of the insulating layer.

[0007] In some embodiments, the insulating layer may include an elastomer.

[0008] In an implementation, the modulus of the insulating layer can be in the range of about 2 GPa to about 10 GPa.

[0009] In one embodiment, on a plane, the insulating layer may be disposed inside the first conductive layer and inside the second conductive layer.

[0010] In this embodiment, the first conductive layer and the second conductive layer may overlap each other on a plane. An insulating layer is not disposed on a portion of the first conductive layer, and the insulating layer exposes a portion of the first conductive layer.

[0011] In one embodiment, the side surface of the insulating layer may be covered by a second conductive layer.

[0012] In one embodiment, the bottom surface of the insulating layer may be covered by a first conductive layer.

[0013] In one embodiment, the portion of the signal line may be disposed below the first conductive layer, and the display panel may further include a pad insulating layer disposed between the portion of the signal line and the first conductive layer in the thickness direction of the signal pad.

[0014] In an embodiment, the display panel may further include a base layer disposed below this portion of the signal line.

[0015] In one embodiment, a contact hole is defined in the pad insulating layer. The contact hole exposes this portion of the signal line. A first conductive layer can be electrically connected to this portion of the signal line through the contact hole.

[0016] In one implementation, the contact holes and the insulating layer can be arranged to be spaced apart from each other on a plane.

[0017] In an implementation, the opening may include multiple openings.

[0018] In an implementation, each of the first conductive layer and the second conductive layer may have a titanium / aluminum / titanium three-layer structure.

[0019] According to an embodiment of the present invention, an electronic device includes a display module, which includes a display panel and an input sensor disposed on the display panel. The display panel has: a display area including pixels; and a pad area including signal pads connected to the pixels via signal lines. An electronic component includes bump electrodes disposed in the pad area. An adhesive layer is disposed between the display panel and the electronic component. The signal pads include a first conductive layer with a portion electrically connected to the signal lines. A second conductive layer is disposed on the first conductive layer. An insulating layer is disposed between the first and second conductive layers. An opening is defined in the second conductive layer. The opening exposes a portion of the top surface of the insulating layer. The second conductive layer is in direct contact with and electrically connected to the bump electrodes.

[0020] In one embodiment, on a plane, an insulating layer may be disposed inside a first conductive layer and a second conductive layer, and the side surface of the insulating layer may be covered by the second conductive layer.

[0021] In an embodiment, the insulating layer may include an elastomer, and each of the first conductive layer and the second conductive layer may have a titanium / aluminum / titanium three-layer structure.

[0022] In an implementation, the opening may include multiple openings.

[0023] According to an embodiment of the present invention, a method for manufacturing an electronic device includes preparing a preliminary display panel including preliminary signal pads, the preliminary signal pads including a first conductive layer, an insulating layer disposed on the first conductive layer, and a preliminary second conductive layer disposed on the insulating layer. The display panel is formed by patterning the preliminary second conductive layer to expose a portion of the top surface of the insulating layer to form the second conductive layer. The display panel and an electronic component including bump electrodes are bonded to each other via an adhesive layer. Bonding the electronic component includes bonding the second conductive layer and the bump electrodes to be in direct contact and electrically connected to each other.

[0024] In one embodiment, on a plane, an insulating layer may be disposed inside a first conductive layer and a second conductive layer, and the side surface of the insulating layer may be covered by the second conductive layer.

[0025] In an embodiment, the insulating layer may include an elastomer, and each of the first conductive layer and the second conductive layer may have a titanium / aluminum / titanium three-layer structure. Attached Figure Description

[0026] The accompanying drawings are included to provide a further understanding of the inventive concept, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the inventive concept and, together with the description, serve to explain the principles of the inventive concept. In the drawings: Figure 1 This is an assembled perspective view of a display device according to an embodiment of the present invention; Figure 2A and Figure 2B Each is an exploded perspective view of a display device according to an embodiment of the concept of the present invention; Figure 3 This is a cross-sectional view of a display module according to an embodiment of the present invention; Figure 4 This is a plan view of a display panel according to an embodiment of the present invention. Figure 5 This is a cross-sectional view showing a display panel of pixels according to an embodiment of the concept of the present invention; Figure 6 This is an enlarged exploded perspective view of the pad area of ​​a display device according to an embodiment of the present invention; Figure 7 This is an enlarged plan view of the pad area according to an embodiment of the present invention; Figures 8A to 8C Each is a cross-sectional view of a portion of a pad region according to an embodiment of the present invention; Figure 9 This is a cross-sectional view showing the joining structure of a display device according to an embodiment of the present invention; Figure 10This is a flowchart of a method for manufacturing a display device according to an embodiment of the present invention; and Figures 11 to 16 Each is a cross-sectional view illustrating one step of a method for manufacturing a display device according to an embodiment of the present invention. Detailed Implementation

[0027] In this disclosure, it will be understood that when an element (or region, layer, portion, etc.) is referred to as being “on,” “connected to,” or “linked to” another element, it may be directly disposed on, directly connected to, or directly linked to the other element, or a third element may be disposed between the elements. When an element is referred to as being “directly” on, directly connected to, or directly linked to another element, there may be no intermediate elements.

[0028] The same reference numerals or symbols always denote the same elements. Furthermore, in the drawings, the thickness, ratios, and dimensions of elements may be exaggerated in order to effectively describe the technical content. The term "and / or" includes one or more combinations that can be defined by the relevant elements.

[0029] It will be understood that although the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the teachings of the invention, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise.

[0030] Furthermore, terms such as "below," "under," "above," and "over" are used to explain the relationships between the elements shown in the accompanying drawings. These terms are relative concepts and are interpreted based on the directions shown in the drawings.

[0031] It will be further understood that, when used herein, terms such as “comprising” or “having” specify the presence of the stated features, figures, steps, operations, elements, parts or combinations thereof, but do not exclude the presence or addition of one or more other features, figures, steps, operations, elements, parts or combinations thereof.

[0032] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and will not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0033] In the following description, embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0034] This invention relates to a display panel including signal pads having an insulating layer directly disposed between a first conductive layer and a second conductive layer. The second conductive layer includes an opening exposing a portion of the top surface of the insulating layer. The insulating layer can be disposed as a body on a signal pad without being patterned. Therefore, the insulating layer can have material freedom in which it can be made of various different materials. Furthermore, the contact area between the insulating layer and the first conductive layer can have increased bonding strength.

[0035] The insulating layer may include an elastomer that provides restoring force to signal pads to increase bonding reliability. The second conductive layer may be patterned to provide high degrees of freedom for micropatterning and increase bonding reliability with bump electrodes.

[0036] Figure 1 This is an assembled perspective view of a display device DD according to an embodiment of the present invention. Figure 2A and Figure 2B Each is an exploded perspective view of a display device DD according to an embodiment of the concept of the present invention. As an example, Figure 2B It shows in Figure 2A The curved region BA shown is a display device DD in a curved state. In this disclosure, the display device DD may be referred to as an electronic device.

[0037] refer to Figure 1 A mobile phone terminal is shown as an example of a display device DD. The display device DD according to embodiments of the present invention can be applied to large electronic devices such as televisions or monitors, and also to medium and small electronic devices such as tablet computers, vehicle navigation units, game consoles, or smartwatches. However, embodiments of the present invention are not limited thereto, and the electronic devices to which the display device DD can be applied can be a variety of different small, medium, or large electronic devices.

[0038] In one embodiment, the display device DD may have a rectangular shape on a plane, having a long side extending in a first direction DR1 and a short side extending in a second direction DR2 intersecting the first direction DR1. However, the embodiments of the present invention are not limited to this, and the display device DD may have various shapes on a plane, such as circles and polygons.

[0039] In the following text, the direction that intersects substantially perpendicularly with the plane defined by the first direction DR1 and the second direction DR2 is defined as the third direction DR3. The state used in this text as "when viewed in a plane" can refer to the state when viewed in the third direction DR3.

[0040] Display devices (DDs) can be rigid or flexible. The term "flexible" refers to the property of being able to bend, and can include structures ranging from fully foldable to those capable of bending at a level of a few nanometers. For example, flexible display devices (DDs) can include curved display devices, rollable display devices, and foldable display devices.

[0041] The display device DD can display images IM via the display surface DD-IS. Software application icons and clock, temperature, and calendar windows are displayed. Figure 1 An example of an image IM is shown. The display surface DD-IS may be parallel to the plane defined by the first direction DR1 and the second direction DR2.

[0042] The display surface DD-IS may include a display area DD-DA for displaying the image IM and a non-display area DD-NDA adjacent to the display area DD-DA (e.g., in the first direction DR1 and / or the second direction DR2). The non-display area DD-NDA may be an area where the image IM is not displayed. However, embodiments of the present invention are not limited to this, and the non-display area DD-NDA may be adjacent to one side of the display area DD-DA or may be omitted.

[0043] refer to Figure 2A and Figure 2B The display device DD may include a window WM, a display module DM, and a housing component BC.

[0044] The window WM can be positioned above the display module DM and transmits the image provided by the display module DM to the outside. In an embodiment, the window WM may include a base layer and a functional layer disposed on the base layer. In an embodiment, the functional layer may include a protective layer, an anti-fingerprint layer, etc. The base layer of the window WM may be made of glass, sapphire, plastic, etc. The base layer of the window WM may include an optically transparent insulating material. For example, the base layer of the window WM may include a glass or plastic film, or include a glass substrate and a plastic film bonded together by an adhesive.

[0045] The window WM may include a transmissive region TA and a non-transmissive region NTA. In an embodiment, the transmissive region TA may be combined with... Figure 1 The display areas DD-DA shown overlap and have a shape corresponding to the display areas DD-DA. The non-transmissive area NTA can be... Figure 1The non-display area DD-NDA shown overlaps and has a shape corresponding to the non-display area DD-NDA. The non-transmissive area NTA can be a region with relatively low light transmittance compared to the transmissive area TA. The non-transmissive area NTA can be defined in a portion of the base layer of the window WM by a border pattern, and the area without a border pattern can be defined as the transmissive area TA. However, embodiments of the present invention are not limited to this, and in some embodiments the non-transmissive area NTA can be omitted.

[0046] In an implementation, an anti-reflective layer may be disposed (e.g., on a third-party DR3) between the window WM and the display module DM. The anti-reflective layer reduces the reflectivity of external light incident from outside the display device DD. The anti-reflective layer may include color filters. The color filters may be arranged in a manner that takes into account the emission colors of the pixels included in the display panel DP, as described later. Furthermore, the anti-reflective layer may also include a black matrix adjacent to the color filters.

[0047] According to an embodiment of the present invention, the display module DM may include a display panel DP and an input sensor ISU.

[0048] In embodiments, the display panel DP can be one of a liquid crystal display panel, an electrophoretic display panel, a microelectromechanical system (MEMS) display panel, an electrowetting display panel, an organic light-emitting display panel, an inorganic light-emitting display panel, and a quantum dot light-emitting display panel. However, the embodiments of the present invention are not limited to these. In the following description, for ease of explanation, the display panel DP is described as an organic light-emitting display panel.

[0049] In this implementation, the input sensor ISU may include any one of a capacitive sensor, an optical sensor, an ultrasonic sensor, and an electromagnetic induction sensor. The input sensor ISU may be formed on the display panel DP by a continuous process, or it may be manufactured separately and then attached to the top of the display panel DP by an adhesive layer, and the input sensor ISU is not limited to any one of these implementations.

[0050] The display device DD may further include a driver chip DC disposed on the display panel DP. The display device DD may also include a circuit board PB disposed on the display panel DP. In this embodiment, the circuit board PB may be a flexible circuit board. However, the embodiments of the present invention are not limited to this. For example, the circuit board PB may be rigid. The circuit board PB may electrically connect the display panel DP and the main circuit board to each other.

[0051] The driver chip DC may include driving elements for driving the pixels of the display panel DP, such as data driving circuitry. Figure 2AThe diagram illustrates a structure in which the driver chip DC is mounted on the display panel DP. However, embodiments of the present invention are not limited to this. For example, the driver chip DC can be mounted on a circuit board PB. In this embodiment, the driver chip DC directly mounted on the display panel DP and the circuit board PB can be collectively referred to as electronic components.

[0052] In one embodiment, the display panel DP may include a curved region BA and a first non-curved region NBA1 and a second non-curved region NBA2, the first non-curved region NBA1 and the second non-curved region NBA2 being arranged to be spaced apart from each other in a first direction DR1 and the curved region BA being between them.

[0053] The curved region BA can be defined as the area where the display panel DP bends along a virtual bending axis BX extending in the second direction DR2. The first non-curved region NBA1 can be defined as the area overlapping the transmissive region TA, and the second non-curved region NBA2 can be defined as the area connecting the circuit board PB. When the curved region BA bends about the bending axis BX, the circuit board PB and the driver chip DC can bend in a direction toward the rear surface of the display panel DP and are positioned below the rear surface of the display panel DP. In an embodiment, additional components may be provided to compensate for the height difference between the rear surface of the display panel DP and the circuit board PB caused by the curved region BA.

[0054] According to an embodiment, the width of the first non-curved region NBA1 in the second direction DR2 can be greater than the width of each of the curved region BA and the second non-curved region NBA2 in the second direction DR2. However, the embodiments of the present invention are not limited to this. For example, the width of the curved region BA in the second direction DR2 can be configured such that the width gradually decreases from the first non-curved region NBA1 to the second non-curved region NBA2, and is not limited to any one embodiment.

[0055] like Figure 2B As shown, when a portion of the display panel DP is bent, the circuit board PB electrically connected to the display panel DP can be disposed on the rear surface of the display panel DP.

[0056] The housing component BC can accommodate the display module DM and connect it to the window WM. The circuit board PB can be positioned at one end of the display panel DP and electrically connected to the reference... Figure 3 The circuit element layer DP-CL is described. In an embodiment, the display device DD may also include a motherboard, and electronic modules, camera modules, power modules, etc., mounted on the motherboard.

[0057] Although the mobile phone terminal described above is an example of a display device DD, the display device DD can be various other electronic devices comprising two or more coupled electronic components. The display panel DP and the driver chip DC mounted on the display panel DP may correspond to different electronic components, and only these components can constitute the display device DD. Similarly, the display panel DP and the circuit board PB connected to the display panel DP may correspond to different electronic components, and only these components can constitute the display device DD. Optionally, only the display panel DP, the motherboard, and the electronic modules mounted on the motherboard can constitute the display device DD. Hereinafter, the display device DD according to embodiments of the present invention will be described primarily based on the coupling structure of the display panel DP and the driver chip DC mounted on the display panel DP.

[0058] Figure 3 This is a cross-sectional view of a display module DM according to an embodiment of the present invention.

[0059] refer to Figure 3 In this embodiment, the display panel DP may include a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED, and an upper insulating layer TFL. The input sensor ISU may be disposed on the upper insulating layer TFL (e.g., directly thereon).

[0060] The display panel DP can include a display area DP-DA and a non-display area DP-NDA. The display area DP-DA of the display panel DP can correspond to... Figure 1 The display area shown is DD-DA or Figure 2A The transmission area TA shown, and the non-display area DP-NDA, can correspond to... Figure 1 The non-display area DD-NDA shown is... Figure 2A The non-transmissive region NTA is shown in the figure.

[0061] In the implementation, the base layer BL can be a flexible substrate and includes plastic substrates, glass substrates, metal substrates, organic / inorganic composite material substrates, etc.

[0062] The circuit element layer DP-CL may include at least one intermediate insulating layer and circuit elements. The intermediate insulating layer may include at least one intermediate inorganic layer and at least one intermediate organic layer. In embodiments, the circuit elements may include signal lines, pixel driving circuits, etc. The insulating layer, semiconductor layer, and conductive layer are formed by processes such as coating or deposition. Subsequently, the insulating layer, semiconductor layer, and conductive layer may be selectively patterned by photolithography and etching processes. Semiconductor patterns, conductive patterns, signal lines, etc., are formed by these processes. Patterns disposed on the same layer are formed by the same process. In the following, when patterns are formed by the same process, it means that the patterns include the same materials and have the same stacking structure.

[0063] The display element layer of a DP-OLED can include multiple light-emitting elements. The display element layer of a DP-OLED can also include an organic layer such as a pixel-defining film.

[0064] The upper insulating layer TFL can seal the display element layer DP-OLED. The upper insulating layer TFL can be disposed on the display element layer DP-OLED (e.g., directly disposed thereon). The upper insulating layer TFL can overlap with the display area DP-DA and the non-display area DP-NDA. The upper insulating layer TFL can overlap with at least a portion of the non-display area DP-NDA. As an example, the upper insulating layer TFL can include a thin-film encapsulation layer. The thin-film encapsulation layer can include a stacked structure of inorganic / organic / inorganic layers. The upper insulating layer TFL can protect the display element layer DP-OLED from moisture, oxygen, and foreign matter such as dust particles. However, embodiments of the inventive concept are not limited to this, and in addition to the thin-film encapsulation layer, the upper insulating layer TFL can also include additional insulating layers. For example, it can also include an optical insulating layer for controlling the refractive index.

[0065] In an embodiment of the present invention, an encapsulation substrate may be disposed instead of an upper insulating layer TFL. In this embodiment, the encapsulation substrate may (e.g., on a third-direction DR3) be opposite the base layer BL, and the circuit element layer DP-CL and the display element layer DP-OLED may (e.g., on a third-direction DR3) be disposed between the encapsulation substrate and the base layer BL.

[0066] In one embodiment, the input sensor ISU can be directly mounted on the display panel DP. In this disclosure, when "component A is directly mounted on component B," it means that no separate layer is provided between components A and B. In this embodiment, the input sensor ISU can be manufactured together with the display panel DP through a continuous process. However, the embodiments of the inventive concept are not limited to this; the input sensor ISU can be a separate panel and attached to the display panel DP via an adhesive layer. Alternatively, as an example, the input sensor ISU can be omitted.

[0067] Figure 4 This is a plan view of a display panel DP according to an embodiment of the present invention.

[0068] refer to Figure 4 In an implementation, the display panel DP may include multiple pixels PX, gate drive circuit GDC, multiple signal lines SGL and multiple signal pads DP-PD.

[0069] Pixels PX can be disposed within the display area DP-DA. Each pixel PX includes a light-emitting element and a pixel driving circuit connected thereto. In an embodiment, the light-emitting element may be an organic light-emitting element. The gate driving circuit GDC sequentially outputs gate signals to a plurality of gate lines GL, which will be described later. In an embodiment, the transistors of the gate driving circuit GDC can be formed using the same process as the transistors of the pixel PX (e.g., a low-temperature polycrystalline silicon (LTPS) process or a low-temperature polycrystalline oxide (LTPO) process). The display panel DP may also include another driving circuit that provides emission control signals to the pixels PX.

[0070] In an implementation, the signal line SGL may include a gate line GL, a data line DL, a power line PL, and a control signal line CSL. Each of the gate lines GL may be connected to a corresponding pixel PX of pixel PX (e.g., electrically connected to a corresponding pixel PX), and each of the data lines DL may be connected to a corresponding pixel PX of pixel PX (e.g., electrically connected to a corresponding pixel PX). The power line PL may be connected to pixel PX (e.g., electrically connected to pixel PX). The control signal line CSL may provide control signals to the gate drive circuit GDC.

[0071] Signal lines SGL may overlap with the display area DP-DA and the non-display area DP-NDA. In an embodiment, each of the signal lines SGL may include a line portion LP. In an embodiment, each of the signal lines SGL may also include a pad portion. The line portion LP may overlap with the display area DP-DA and the non-display area DP-NDA. The pad portion is connected to one end of the line portion LP.

[0072] In an implementation, the plurality of signal pads DP-PD may include a first pad PD1, a second pad PD2, and a third pad PD3. The area where the first pad PD1 and the second pad PD2 are set can be defined as the first pad area PA1, and the area where the third pad PD3 is set can be defined as the second pad area PA2.

[0073] The first pad region PA1 may be an area overlapping with the driver chip DC, and the second pad region PA2 may be an area overlapping with the circuit board PB. In an embodiment, the first pad region PA1 may include a first region B1 in which the first pad PD1 is disposed and a second region B2 in which the second pad PD2 is disposed. The first pad region PA1 and the second pad region PA2 may be disposed within the non-display area DP-NDA. The first pad region PA1 and the second pad region PA2 may be spaced apart from each other in the first direction DR1. Figure 4 The diagram illustrates, as an example, a first region B1, a second region B2, and a second pad region PA2 in which a single pad row is provided. However, embodiments of the present invention are not limited to this, and multiple pad rows may be provided in the first region B1, the second region B2, and the second pad region PA2.

[0074] Each of the first pads PD1 can be connected to a corresponding data line DL. In this embodiment, the first pads PD1 and the second pads PD2 can be electrically connected to each other. The second pad PD2 can be connected to the third pad PD3 via a connection signal line SCLn.

[0075] Figure 5 This is a cross-sectional view of a display panel DP of pixels PX according to an embodiment of the present invention.

[0076] refer to Figure 5 In one embodiment, the display area DP-DA may include an emitting area PXA and a non-emitting area NPXA. Each pixel may include a light-emitting element OLED and pixel driving circuitry connected to the light-emitting element OLED. In another embodiment, a pixel PX may include a transistor TR and a light-emitting element OLED.

[0077] As an example, Figure 5 A transistor TR is shown. However, embodiments of the present invention are not necessarily limited to this. A pixel PX according to an embodiment may include seven transistors and at least one capacitor, and these seven transistors and capacitors may be electrically connected to each other. However, the number of each of the transistors and capacitors constituting the pixel PX may vary and is not necessarily limited to any one embodiment.

[0078] In an embodiment, the display panel DP may include multiple insulating layers, semiconductor patterns, conductive patterns, signal lines, etc. The insulating layers, semiconductor layers, and conductive layers can be formed by processes such as coating or deposition. Subsequently, the insulating layers, semiconductor layers, and conductive layers can be selectively patterned by photolithography. The semiconductor patterns, conductive patterns, and signal lines included in the circuit element layer DP-CL and the display element layer DP-OLED can be formed by these processes.

[0079] In embodiments, the base layer BL may include a synthetic resin film. The base layer BL may have a multilayer structure. For example, in embodiments, the base layer BL may have a three-layer structure consisting of a synthetic resin layer, an inorganic layer, and a synthetic resin layer. In embodiments, the synthetic resin layer may be a polyimide-based resin layer; however, its material is not limited to this. Furthermore, the base layer BL may include a glass substrate, a metal substrate, an organic / inorganic composite substrate, etc.

[0080] In an embodiment, the circuit element layer DP-CL may include a barrier layer BRL, a buffer layer BFL, first insulating layers 10 to sixth insulating layers 60, a transistor TR, a connection signal line SCLd, an upper electrode UE, a first connection electrode CNE1, and a second connection electrode CNE2. At least one inorganic layer is disposed on the top surface of the base layer BL.

[0081] At least one inorganic layer is disposed on the top surface of the base layer BL. The inorganic layer can be configured as a multilayer structure. The barrier layer BRL can be disposed on the base layer BL (e.g., directly disposed on the third-direction DR3). The buffer layer BFL can be disposed on the barrier layer BRL (e.g., directly disposed on the third-direction DR3). The barrier layer BRL and the buffer layer BFL can each be an inorganic layer.

[0082] A semiconductor pattern is disposed on the buffer layer BFL. The semiconductor pattern may include polycrystalline silicon. However, embodiments of the present invention are not limited thereto, and the semiconductor pattern may include amorphous silicon or metal oxide.

[0083] Figure 5 Only a portion of the semiconductor pattern is shown, and the semiconductor pattern can be further disposed in another region of the pixel PX on the plane. The semiconductor pattern can be arranged on multiple pixels according to specific rules. Depending on whether the semiconductor pattern is doped, it has different electrical properties. The semiconductor pattern may include a first region and a second region. The first region may be doped with N-type or P-type dopant. A P-type transistor includes a doped region doped with P-type dopant.

[0084] The first region may have a higher conductivity than the second region and is essentially used as an electrode or signal line. The second region may be a region with a low doping concentration or no doping and may essentially correspond to the active (e.g., channel) region of a transistor. For example, one part of a semiconductor pattern may be the active region of a transistor, another part may be the source or drain of a transistor, and yet another part may be a connection electrode or connection signal line.

[0085] like Figure 5 As shown, the source S, active region A, and drain D of transistor TR can be provided by a semiconductor pattern.

[0086] Figure 5 A portion of a connection signal line SCLd provided by a semiconductor pattern is shown. In an embodiment, the connection signal line SCLd may be electrically connected to the drain of one of the transistors in the pixel PX.

[0087] A first insulating layer 10 is disposed on a buffer layer BFL (e.g., directly disposed thereon on a third-direction DR3). The first insulating layer 10 may cover a semiconductor pattern. The first insulating layer 10 may overlap with multiple pixels. A gate G may be disposed on the first insulating layer 10 (e.g., directly disposed thereon on a third-direction DR3). The gate G may be part of a metal pattern. The gate G may (e.g., on a third-direction DR3) overlap with an active region A. The gate G may be used as a mask in a process of doping the semiconductor pattern.

[0088] A second insulating layer 20 covering the gate G can be disposed on the first insulating layer 10 (e.g., directly disposed on the third-direction DR3). The second insulating layer 20 can overlap with multiple pixels. An upper electrode UE can be disposed on the second insulating layer 20 (e.g., directly disposed on the third-direction DR3). The upper electrode UE can overlap (e.g., on the third-direction DR3) with the gate G of the transistor TR. The upper electrode UE can be part of a metal pattern. A portion of the gate G and the upper electrode UE overlapping that portion can define a capacitor.

[0089] The third insulating layer 30 covering the upper electrode UE can be disposed on the second insulating layer 20 (e.g., directly disposed on the third-direction DR3). In an embodiment, the first connection electrode CNE1 disposed on the third insulating layer 30 can be connected to the connection signal line SCLd through the contact hole CNT-1 passing through the first insulating layer 10 to the third insulating layer 30.

[0090] The fourth insulating layer 40 covering the first connecting electrode CNE1 can be disposed on the third insulating layer 30 (e.g., directly disposed on the third directional DR3). The first insulating layer 10 to the fourth insulating layer 40 can each be an inorganic layer and / or an organic layer, and have a single-layer or multi-layer structure.

[0091] The first connecting electrode CNE1 may be disposed on the fourth insulating layer 40 (e.g., directly disposed on the third-direction DR3) and covered by the fifth insulating layer 50. Alternatively, the embodiment may include both a first connecting electrode disposed on the third insulating layer 30 and covered by the fourth insulating layer 40, and a first connecting electrode disposed on the fourth insulating layer 40 and covered by the fifth insulating layer 50.

[0092] The fifth insulating layer 50 may be disposed on the fourth insulating layer 40 (e.g., directly disposed on the third-direction DR3). The fifth insulating layer 50 may be an organic layer. The second connecting electrode CNE2 may be disposed on the fifth insulating layer 50 (e.g., directly disposed on the third-direction DR3). In an embodiment, the second connecting electrode CNE2 may be connected to the first connecting electrode CNE1 through a contact hole CNT-2 passing through the fourth insulating layer 40 and the fifth insulating layer 50.

[0093] A sixth insulating layer 60 covering the second connecting electrode CNE2 can be disposed on the fifth insulating layer 50 (e.g., directly disposed on the third directional DR3). The sixth insulating layer 60 can be an organic layer. The first electrode AE ​​can be disposed on the sixth insulating layer 60 (e.g., directly disposed on the third directional DR3). The first electrode AE ​​can be connected to the second connecting electrode CNE2 through a contact hole CNT-3 passing through the sixth insulating layer 60.

[0094] The circuit element layer DP-CL may include multiple connection electrodes connected to transistors, and some of these connection electrodes may be disposed on different layers. In one embodiment, the first connection electrode CNE1 may extend to connect to the transistor TR. However, embodiments of the present invention are not limited to this, and the positions of the multiple connection electrodes may vary.

[0095] The display element layer DP-OLED may include a pixel-defining film PDL and a light-emitting element OLED. A pixel aperture portion OPN may be defined within the pixel-defining film PDL. The pixel aperture portion OPN of the pixel-defining film PDL may expose at least a portion of the first electrode AE. In an embodiment, the emitting region PXA may be defined to correspond to the portion of the first electrode AE ​​exposed by the pixel aperture portion OPN.

[0096] A hole control layer (HCL) can be commonly disposed in the emitter region (PXA) and the non-emitter region (NPXA). In an embodiment, the hole control layer (HCL) may include a hole transport layer and / or a hole injection layer. An emitter layer (EML) can be disposed on the hole control layer (HCL). The emitter layer (EML) can be disposed in the region corresponding to the pixel aperture portion (OPN). For example, the emitter layer (EML) can be disposed individually in each pixel. However, embodiments of the inventive concept are not limited to this, and the emitter layer (EML) can be commonly disposed in multiple pixels by using an aperture mask.

[0097] An electronic control layer (ECL) can be disposed on an emitter layer (EML). The ECL may include an electron transport layer and / or an electron injection layer. A hole control layer (HCL) and the ECL can be co-located in multiple pixels using an aperture mask. A second electrode (CE) can be disposed on the ECL. The second electrode (CE) may have a monolithic shape and be co-located in multiple pixels. An upper insulating layer (TFL) can be disposed on the second electrode (CE). The upper insulating layer (TFL) may include multiple thin films.

[0098] Figure 6 This is an enlarged exploded perspective view of the pad areas PA1 and PA2 of a display device DD according to an embodiment of the present invention. As an example, Figure 6 The driver chip DC and circuit board PB are shown as separate from the display panel DP. Figure 6 The first pad PD1, the second pad PD2, the connecting signal line SCLn, and the third pad PD3 are respectively connected to... Figure 4 The first pad PD1, the second pad PD2, the connection signal line SCLn, and the third pad PD3 are the same / similar, and therefore will not be described again or will be briefly described.

[0099] refer to Figure 4 and Figure 6 In one embodiment, the driver chip DC can be bonded to the first pad region PA1 via the first adhesive layer CF1. The circuit board PB can be bonded to the second pad region PA2 via the second adhesive layer CF2. In another embodiment, the first adhesive layer CF1 and the second adhesive layer CF2 may each comprise a synthetic resin with adhesive properties. The first adhesive layer CF1 and the second adhesive layer CF2 may each be a non-conductive film. For example, each of the first adhesive layer CF1 and the second adhesive layer CF2 may not include conductive balls, but only comprise a synthetic resin with adhesive properties.

[0100] In one embodiment, the driver chip DC may include a driver integrated circuit D-IC and chip bump electrodes DC-BP mounted in the driver chip DC. The driver integrated circuit D-IC may include a top surface DC-US and a bottom surface DC-DS opposite to each other on a third-direction DR3, and the bottom surface DC-DS may be a surface facing the first pad PD1 and the second pad PD2. The chip bump electrodes DC-BP may be disposed on the bottom surface DC-DS of the driver integrated circuit D-IC.

[0101] In one embodiment, the chip bump electrode DC-BP may include a first bump BP1 electrically connected to a first pad PD1 and a second bump BP2 electrically connected to a second pad PD2. The first bump BP1 may be disposed along a second direction DR2, and the second bump BP2 may be spaced apart from the first bump BP1 on a first direction DR1 and disposed along the second direction DR2.

[0102] In this implementation, the driver chip DC can receive a first signal from the outside via the second pad PD2 and the second bump BP2. The driver chip DC can provide a second signal generated based on the first signal to the first pad PD1 via the first bump BP1. For example, the driver chip DC may include a data driving circuit. The first signal may be an image signal, which is a digital signal applied from the outside, and the second signal may be a data signal, which is an analog signal. In this implementation, the driver chip DC can generate an analog voltage corresponding to the grayscale value of the image signal. The data signal can be... Figure 4 The data line DL shown is provided to pixel PX.

[0103] In one embodiment, each of the first bump BP1 and the second bump BP2 may have a shape that protrudes from the bottom surface DC-DS of the driver integrated circuit D-IC and is exposed to the outside. In another embodiment, when the first adhesive layer CF1 is cured, the first pad PD1 and the first bump BP1 may be fixed in a state of contact with each other, and the second pad PD2 and the second bump BP2 may be fixed in a state of contact with each other.

[0104] In this embodiment, the circuit board PB may include a base layer P-BS and board bump electrodes PB-BP mounted in the circuit board PB. The circuit board PB may include a top surface PB-US and a bottom surface PB-DS, and the bottom surface PB-DS may be the surface facing the third pad PD3. The board bump electrodes PB-BP may be disposed on the bottom surface PB-DS of the base layer P-BS. The board bump electrodes PB-BP may be electrically connected to the third pad PD3. The board bump electrodes PB-BP may be arranged along the second direction DR2. The circuit board PB may provide image signals, drive voltages, and other control signals to the driver chip DC.

[0105] In one embodiment, the board bump electrode PB-BP may have a shape that protrudes from the bottom surface PB-DS of the base layer P-BS and is exposed to the outside. In another embodiment, when the second adhesive layer CF2 is cured, the third pad PD3 and the board bump electrode PB-BP may be fixed in a state of contact with each other.

[0106] The electronic component may include a substrate and bump electrodes disposed beneath the substrate. In an embodiment where the electronic component corresponds to a driver chip DC, the substrate may correspond to the driver integrated circuit D-IC of the driver chip DC, and the bump electrodes may correspond to the chip bump electrodes DC-BP. Optionally, in an embodiment where the electronic component corresponds to a circuit board PB, the substrate may correspond to the base layer P-BS of the circuit board PB, and the bump electrodes may correspond to the board bump electrodes PB-BP.

[0107] Figure 7 This is an enlarged plan view of the pad regions PA1 and PA2 according to an embodiment of the present invention. Figures 8A to 8C Each of these is a cross-sectional view of a portion of each of the pad regions PA1 and PA2 according to an embodiment of the present invention. Figure 9 This illustrates a display device DD according to an embodiment of the concept of the present invention (see [reference]). Figure 6 A cross-sectional view of the joint structure. Figure 8A It corresponds to Figure 7 A cross-sectional view of the pad areas PA1 and PA2 along line A-A'. Figure 8B It corresponds to Figure 7 A cross-sectional view of the pad areas PA1 and PA2 along line B-B'. Figure 8C It corresponds to Figure 7 A cross-sectional view of the pad areas PA1 and PA2 along line C-C'. Figure 9 It corresponds to Figure 7 The display device DD with line C-C' in it (see Figure 6 ) sectional view.

[0108] Figures 7 to 9 The signal pads DP-PD shown can be a reference. Figure 4 and Figure 6 One of the first pads PD1 to the third pad PD3 described. Figure 7 An example of a signal line, DL, is shown, comprising an end portion DL-E and a line portion DL-S with different widths. However, embodiments of the present invention are not limited to this. Here, the width may refer to the length or width of the end portion DL-E or the line portion DL-S in a second direction DR2, which may be perpendicular to the direction in which the data line DL extends longitudinally. In embodiments, the signal line may be a different type of signal line other than the data line DL, and may have a uniform width regardless of the end portion DL-E and the line portion DL-S. The end portion DL-E may correspond to a reference... Figure 4 The described pad portion. The terminal portion DL-E can be referred to as part of the data line DL or signal line.

[0109] In the following text, for ease of explanation, pad areas PA1 and PA2 will be described primarily based on the first pad area PA1 where the data line DL is set. However, the connection signal line SCLn is set in the second pad area PA2 (see...). Figure 4 Instead of the data line DL, the same content regarding the first pad area PA1 can be applied to the second pad area PA2.

[0110] refer to Figure 7 The signal pad DP-PD includes a first conductive layer CL1, a second conductive layer CL2, and an insulating layer PLM disposed inside the first conductive layer CL1 and the second conductive layer CL2.

[0111] The end portion DL-E of the data line DL can have a shape that extends longitudinally in a first direction DR1 on a plane. For example, in the end portion DL-E, the length or width in the first direction DR1 can be greater than the length or width in the second direction DR2. The end portion DL-E can overlap with the first conductive layer CL1 on a plane.

[0112] The first conductive layer CL1 can be configured (e.g., on the third-direction DR3) to overlap with the end portion DL-E of the data line DL. Figure 7 The diagram shows (e.g., in a plan view) an end portion DL-E disposed inside the first conductive layer CL1. However, embodiments of the present invention are not necessarily limited to this. In one embodiment, the first conductive layer CL1 can be connected to the end portion DL-E of the data line DL via at least one contact hole OP-C. Therefore, the first conductive layer CL1 can be electrically connected to a signal line, such as the data line DL. In other words, the signal pad DP-PD can be connected to the signal line. The contact hole OP-C can be defined in the pad insulating layer IL-P (see...). Figure 8A As an example, Figure 7 Two contact holes OP-C are shown. However, the number of contact holes OP-C can vary and is not limited to this.

[0113] Contact holes OP-C may overlap with end portions DL-E in a plane. Contact holes OP-C may be spaced apart from each other in the first direction DR1. Contact holes OP-C may be spaced apart from insulating layer PLM in a plane. Contact holes OP-C may be spaced apart from openings OP-CL2 of the second conductive layer CL2 in a plane. For example, in one embodiment, contact holes OP-C may be spaced apart from openings OP-CL2 of the second conductive layer CL2 in the first direction DR1. A portion of the first conductive layer CL1 may overlap with contact holes OP-C in a plane.

[0114] The second conductive layer CL2 can be configured to overlap with the first conductive layer CL1. Figure 7The diagram shows (e.g., in a plan view) a first conductive layer CL1 disposed inside the second conductive layer CL2. For example, the first conductive layer CL1 may be disposed inside the second conductive layer CL2 in the plan view. However, embodiments of the present invention are not necessarily limited thereto.

[0115] An opening OP-CL2 that exposes a portion of the top surface of the insulating layer PLM can be defined within the second conductive layer CL2. In an embodiment, multiple openings OP-CL2 can be provided. Figure 7 Five openings OP-CL2 are shown defined within a second conductive layer CL2 and arranged in a first direction DR1. However, embodiments of the present invention are not limited to this, and the number of openings OP-CL2 can vary. Figure 7 In the diagram, the planar shape of each of the openings OP-CL2 is shown as a rectangle. However, embodiments of the inventive concept are not limited to this. For example, the planar shape of each of the openings OP-CL2 may be a polygon other than a rectangle, or it may be a circle or an ellipse. Optionally, the individual planar shapes of the plurality of openings OP-CL2 may be the same as or different from each other.

[0116] The insulating layer PLM can be configured (e.g., in a plan view) to overlap with the first conductive layer CL1 and the second conductive layer CL2. The insulating layer PLM can be disposed planarly inside the first conductive layer CL1. For example, the insulating layer PLM can be disposed planarly inside the first conductive layer CL1 and the second conductive layer CL2. In one embodiment, the insulating layer PLM can be disposed planarly inside the second conductive layer CL2. The opening OP-CL2 defined in the second conductive layer CL2 can be configured to overlap with the insulating layer PLM planarly. The insulating layer PLM can be configured to be spaced apart planarly from the contact hole OP-C.

[0117] refer to Figures 8A to 8C The end portion DL-E can be disposed on the first insulating layer 10 (e.g., directly disposed on the third-party DR3). The end portion DL-E can be disposed with... Figure 5 The same layer as the gate G shown. In an embodiment, the end portion DL-E can be formed using the same process as the gate G. The end portion DL-E may include the same material as the gate G.

[0118] However, the location of the end portion DL-E is not limited to this. For example, in one embodiment, the end portion DL-E can be... Figure 5 The upper electrode UE shown is disposed on the same layer, comprises the same material, and has the same stacked structure. Optionally, some of the multiple signal lines can be connected to the gate G (see [link to relevant documentation]). Figure 5 It is formed using the same process, and other signal lines can be connected to the upper electrode UE (see...). Figure 5 Formed using the same process.

[0119] In one embodiment, the data line DL can be disposed on a single layer and have a monolithic shape. However, the embodiments of the present invention are not limited to this. For example, in one embodiment, a data line DL may include multiple portions disposed on different layers. For example, the line portion DL-S may include two or more portions.

[0120] The first conductive layer CL1 can be disposed on the fourth insulating layer 40 (e.g., directly disposed on the third insulating layer DR3). The first conductive layer CL1 can be connected to the end portion DL-E through a contact hole OP-C passing through the second insulating layer 20, the third insulating layer 30, and the fourth insulating layer 40. For example, the first conductive layer CL1 can be connected to the end portion DL-E through the contact hole OP-C. In an embodiment, the second insulating layer 20, the third insulating layer 30, and the fourth insulating layer 40 can be connected to... Figure 5 The second insulating layer 20, third insulating layer 30, and fourth insulating layer 40 of the display area DP-DA shown are formed using the same process. In this disclosure, the insulating layer disposed between the end portion DL-E and the first conductive layer CL1 (e.g., on the thickness direction of the signal pad DP-PD, such as the third direction DR3) can be defined as a pad insulating layer IL-P. In this embodiment, the second insulating layer 20, third insulating layer 30, and fourth insulating layer 40 can be defined as the pad insulating layer IL-P. However, the number of layers included in the pad insulating layer IL-P is not necessarily limited to this and can vary. For example, the stacking structure of the pad insulating layer IL-P can be based on the circuit element layer DP-CL (see...). Figure 5 The stacking structure can be modified. In an embodiment, the contact hole OP-C may be defined by an number of insulating layers greater than the number of the second insulating layer 20, the third insulating layer 30, and the fourth insulating layer 40, or it may be defined by a number of insulating layers less than the number of the second insulating layer 20, the third insulating layer 30, and the fourth insulating layer 40. The first conductive layer CL1 and the end portion DL-E can be distinguished from each other by the pad insulating layer IL-P (e.g., the second insulating layer 20, the third insulating layer 30, and the fourth insulating layer 40) disposed therebetween.

[0121] The second conductive layer CL2 may be disposed on the first conductive layer CL1 (e.g., on the third-direction DR3). In an embodiment, the region of the second conductive layer CL2 (e.g., on the third-direction DR3) that does not overlap with the insulating layer PLM may be in direct contact with the first conductive layer CL1. The region of the second conductive layer CL2 (e.g., on the third-direction DR3) that overlaps with the insulating layer PLM may be in direct contact with the insulating layer PLM. In other words, the insulating layer PLM may not be disposed on the portion of the first conductive layer CL1 that is in direct contact with the second conductive layer CL2, and the insulating layer PLM may expose that portion of the first conductive layer CL1.

[0122] In this implementation, the first conductive layer CL1 can be connected to a reference layer. Figure 5 The first connecting electrode CNE1 described is formed using the same process, and the second conductive layer CL2 can be formed using the same process as the reference. Figure 5 The second connection electrode CNE2 described is formed using the same process. The first conductive layer CL1 may include the same material as the first connection electrode CNE1 (see [link]). Figure 5 The second conductive layer CL2 may be made of the same material as the second connection electrode CNE2 (see [link to documentation]). Figure 5 The same material. As an example, Figures 8A to 8C Each embodiment shown depicts a first conductive layer CL1 disposed on (e.g., directly disposed thereon) a fourth insulating layer 40. However, embodiments of this disclosure are not necessarily limited to this. For example, in one embodiment, the first conductive layer CL1 may be disposed on (e.g., directly disposed thereon) a third insulating layer 30, and in that embodiment, the fourth insulating layer 40 may not be disposed in the pad regions PA1 and PA2. However, embodiments of the inventive concept are not necessarily limited to this, and combinations of connection electrodes formed by the same process as the first conductive layer CL1 and the second conductive layer CL2 can be based on the circuit element layer DP-CL (see...). Figure 5 The stacked structure can be chosen differently, as long as it can provide a first conductive layer CL1 and a second conductive layer CL2 on different layers.

[0123] In one embodiment, the second conductive layer CL2 has a larger surface area than the first conductive layer CL1 on a plane, and the edge of the second conductive layer CL2 is disposed outside the edge of the first conductive layer CL1 and covers the edge of the first conductive layer CL1. However, the embodiments of the present invention are not limited to this. For example, in one embodiment, the second conductive layer CL2 may have a substantially the same surface area as the first conductive layer CL1, and the edge of the second conductive layer CL2 may be substantially aligned with the edge of the first conductive layer CL1.

[0124] A portion of the second conductive layer CL2 may include a portion overlapping the insulating layer PLM in a plane. The insulating layer PLM may be disposed between the first conductive layer CL1 and the second conductive layer CL2 in cross-section. The insulating layer PLM may be disposed on the first conductive layer CL1 (e.g., directly disposed on the third-direction DR3), and the side surface of the insulating layer PLM may be covered by the second conductive layer CL2. For example, in one embodiment, the entire side surface of the insulating layer PLM may be covered by the second conductive layer CL2. In another embodiment, the second conductive layer CL2 may expose a portion of the top surface of the insulating layer PLM through an opening OP-CL2. The insulating layer PLM may be disposed in a plane inside the first conductive layer CL1 and the second conductive layer CL2.

[0125] In an embodiment, each of the first conductive layer CL1 and the second conductive layer CL2 may have a multilayer structure. For example, in an embodiment, each of the first conductive layer CL1 and the second conductive layer CL2 may have a three-layer structure (e.g., on a third-direction DR3) with a first layer, a second layer, and a third layer stacked sequentially. In an embodiment, the second layer may have a higher conductivity than each of the first and third layers. For example, in an embodiment, the first and third layers may be titanium (Ti), and the second layer may be aluminum (Al).

[0126] An insulating layer PLM may be disposed between a first conductive layer CL1 and a second conductive layer CL2. The bottom surface of the insulating layer PLM may be covered by the first conductive layer CL1, and the side surfaces of the insulating layer PLM may be covered by the second conductive layer CL2. For example, in one embodiment, the entire bottom surface of the insulating layer PLM may be covered by the first conductive layer CL1. A portion of the top surface of the insulating layer PLM may be exposed by an opening OP-CL2 defined in the second conductive layer CL2, and another portion of the top surface may be covered by the second conductive layer CL2.

[0127] In the implementation, the insulating layer PLM can be connected to the fifth insulating layer 50 (see...). Figure 5 The same process is used to form the first conductive layer CL1 and the second conductive layer CL2. However, embodiments of the present invention are not limited to this, and combinations of connection electrodes formed by the same process as the first conductive layer CL1 and the second conductive layer CL2 can be formed according to the circuit element layer DP-CL (see...). Figure 5 The stacking structure can be selected differently. Therefore, the insulating layer formed by the same process as the insulating layer PLM can also be selected differently.

[0128] In one embodiment, the insulating layer PLM may have a trapezoidal shape in cross-section. However, the embodiments of the present invention are not limited to this. For example, in some embodiments, the insulating layer PLM may have a rectangular shape or an inverted trapezoidal shape in cross-section.

[0129] The insulating layer PLM may include a polymer. In some embodiments, the insulating layer PLM may include a thermosetting polymer. However, embodiments of the present invention are not limited thereto, and the insulating layer PLM may include a thermoplastic polymer. The insulating layer PLM may be formed of a negative photoresist material. A negative photoresist material may refer to a material in which the non-exposed portion is dissolved in the developer. However, embodiments of the present invention are not limited thereto, and in some embodiments, the insulating layer PLM may be formed of a positive photoresist material. A positive photoresist material may refer to a material in which the exposed portion is dissolved in the developer. The insulating layer PLM of embodiments of the present invention may be configured as a single body without patterning on a signal pad DP-PD, and therefore has material freedom to apply various polymer materials to the insulating layer PLM. Furthermore, since the insulating layer PLM of embodiments of the present invention is configured as a single unit without patterning on a signal pad DP-PD, the contact area between the insulating layer PLM and the first conductive layer CL1 may be sufficiently strong to prevent the insulating layer PLM from being lost from the first conductive layer CL1. However, in comparative embodiments that involve micropatterning and providing an insulating layer, which differ from the embodiments conceived in this invention, micropatterning may be impossible or difficult to perform depending on the material, and even if micropatterning is performed, the contact area with the first conductive layer may be insufficient, resulting in low adhesion, and thus the insulating layer may be lost during the process.

[0130] In an embodiment, the insulating layer PLM may include an elastomer. An elastomer can refer to a polymer having the property of being stretched or compressed when an external force is applied and returning to its original shape when the external force is removed. In the signal pad DP-PD according to an embodiment of the present invention, the insulating layer PLM including the elastomer can be disposed between the first conductive layer CL1 and the second conductive layer CL2, thereby applying a restoring force to the signal pad DP-PD after bonding. Therefore, bonding reliability can be ensured. In an embodiment, the modulus of the insulating layer PLM can be in the range of about 2 GPa to about 10 GPa. When the insulating layer PLM has a modulus within the aforementioned range, the bonding retention of the signal pad DP-PD can be increased.

[0131] refer to Figure 8B and Figure 8C The second conductive layer CL2, disposed on the top surface of the insulating layer PLM, can be the farthest portion of the signal pad DP-PD protruding on the third-direction DR3. For example... Figure 9As shown, the portion of the second conductive layer CL2 in the signal pad DP-PD that protrudes furthest on the third-direction DR3 can directly contact and be electrically connected to the bump electrode BP of the electronic component. Since the signal pad DP-PD according to the embodiment of the present invention includes a patterned second conductive layer CL2, the degree of freedom for micropatterning can be high, and the resistance stability of the bump electrode BP of the electronic component can also be ensured.

[0132] refer to Figure 9 The second conductive layer CL2 can directly contact the bump electrode BP of the electronic component for electrical connection. For example, in one embodiment, the portion of the second conductive layer CL2 disposed on the top surface of the insulating layer PLM (e.g., directly disposed on the third-direction DR3) can be the furthest portion of the signal pad DP-PD protruding on the third-direction DR3. When the signal pad DP-PD of the display panel DP is bonded to the electronic component, the second conductive layer CL2 can directly contact the bump electrode BP.

[0133] For convenience, Figure 9 Only the bump electrode BP of the electronic component is shown, and the bump electrode BP can correspond to Figure 6 The chip bump electrode DC-BP and board bump electrode PB-BP are shown in the image. Furthermore, the adhesive layer CF that bonds the signal pads DP-PD and bump electrodes BP together can correspond to... Figure 6 The first adhesive layer CF1 and the second adhesive layer CF2 are described, and the same content regarding the first adhesive layer CF1 and the second adhesive layer CF2 can be applied to the adhesive layer CF.

[0134] Because the insulating layer PLM, including an elastomer, is disposed between the first conductive layer CL1 and the second conductive layer CL2, the signal pads DP-PD according to embodiments of the present invention exhibit excellent bonding retention with electronic components. For example, restoring force can be applied to the signal pads DP-PD through the elasticity of the insulating layer PLM, thereby increasing the display panel DP (see...). Figure 6 The reliability of the bonding between the signal pads and electronic components. However, in a comparative embodiment where the signal pads are simply made of metal, unlike the signal pads DP-PD of the embodiment conceived according to the present invention, the signal pads cannot have resilience and therefore have low bonding retention.

[0135] Furthermore, a second conductive layer CL2, including metal, can be disposed on the insulating layer PLM, thereby allowing for free patterning of the second conductive layer CL2. In an embodiment, the planar shape of the second conductive layer CL2 disposed on the top surface of the insulating layer PLM and the contact area with the bump electrode BP can be freely patterned using a metal mask patterning process. For example, the protruding portion of the signal pad DP-PD on the third-direction DR3 can be freely patterned. Therefore, when bonding to electronic components, a stable resistance with the bump electrode BP can be ensured through micro-patterning of the second conductive layer CL2, thereby increasing bonding reliability. However, in a comparative embodiment where the protruding portion of the signal pad is patterned with a polymer material, different from the embodiment of the signal pad DP-PD according to the present invention, there may be difficulties in micro-patterning, adhesion defects of the patterned polymer material, etc.

[0136] Furthermore, since the insulating layer PLM, including the elastomer, is disposed as a main body between the first conductive layer CL1 and the second conductive layer CL2 without being patterned to apply restoring force to the signal pad DP-PD, even polymer materials that are difficult to micro-pattern in the process can be applied to the insulating layer PLM. For example, the signal pad DP-PD according to the embodiment of the present invention can provide material freedom to apply various polymer materials to the insulating layer PLM.

[0137] Furthermore, in the display device DD (see embodiment of the present invention) Figure 6 In this design, the adhesive layer CF may not include conductive balls, thus preventing short-circuit defects caused by conductive balls even when signal pads DP-PD are densely arranged, and / or preventing conductivity defects when conductive balls are not positioned between the signal pads DP-PD and the bump electrodes BP. Therefore, high-resolution panels can be achieved.

[0138] Figure 10 This is an embodiment of the present invention for manufacturing a display device DD (see [reference]). Figure 6 The flowchart of the method. Figures 11 to 16 Each is an embodiment of a display device DD (see each other) illustrating a manufacturing method for a display device according to an embodiment of the present invention. Figure 6 A cross-sectional view of one step of the method.

[0139] Figures 11 to 16 Each is shown as an example of an embodiment of the present invention for manufacturing a display device DD (see [reference]). Figure 6 A step related to the method, corresponding to Figure 7 A sectional view of the section along line C-C'. (See above reference.) Figures 6 to 9 The same content described can be applied to Figures 10 to 16 .

[0140] refer to Figure 10 According to an embodiment of the present invention, a display device DD is used for manufacturing (see...) Figure 6 The method includes preparing a preliminary display panel in frame S100, forming a display panel in frame S200, and joining the display panel and electronic components together in frame S300.

[0141] Figure 11 and Figure 12 Each is a cross-sectional view showing one step in preparing the initial display panel in frame S100.

[0142] refer to Figure 11 The insulating layer PLM can be formed as a single entity on the first conductive layer CL1 without patterning. In an embodiment, the unpatterned insulating layer PLM with a monolithic shape can be formed on the first conductive layer CL1 (e.g., directly on the third-direction DR3). For the planar shape and arrangement of the insulating layer PLM, refer to... Figure 7 In one embodiment, the insulating layer PLM can be formed by coating, exposing, and curing a photocurable organic material onto the first conductive layer CL1. However, the embodiments of the present invention are not limited to this, and in some embodiments, thermosetting organic materials can be used. Furthermore, negative photoresist materials can be used as the material for forming the insulating layer PLM, or positive photoresist materials can be used. The insulating layer PLM can be formed on a first conductive layer CL1 with a large surface area without micropatterning, and therefore various materials can be applied to the insulating layer PLM. For example, even materials that are difficult to micropattern can be used as the material for forming the insulating layer PLM.

[0143] refer to Figure 12 In one embodiment, the preliminary display panel P-DP may include a preliminary signal pad DP-PPD. In another embodiment, the preliminary signal pad DP-PPD may include a first conductive layer CL1, an insulating layer PLM disposed on the first conductive layer CL1, and a preliminary second conductive layer P-CL2 disposed on the insulating layer PLM. The preliminary second conductive layer P-CL2 may be completely deposited on the insulating layer PLM. For example, the preliminary second conductive layer P-CL2 may cover the entire upper surface of the insulating layer PLM. The first conductive layer CL1 and the preliminary second conductive layer P-CL2 may each be formed as a three-layer structure. For example, in one embodiment, the first conductive layer CL1 and the preliminary second conductive layer P-CL2 may each be formed as a titanium / aluminum / titanium structure.

[0144] Figures 13 to 15Each of these is a cross-sectional view illustrating a step in forming a display panel within frame S200. In one embodiment, forming the display panel within frame S200 may include patterning a preliminary second conductive layer P-CL2 such that a portion of the top surface of the insulating layer PLM is exposed to form the second conductive layer CL2.

[0145] refer to Figure 13 In one embodiment, a photoresist material PR can be patterned on the initial second conductive layer P-CL2 to pattern the initial second conductive layer P-CL2. (See reference...) Figure 14 Based on the patterning of the photoresist material PR, a preliminary second conductive layer P-CL2 can be patterned to form the second conductive layer CL2. In one embodiment, the preliminary second conductive layer P-CL2 can be patterned using a dry etching process with a metal mask. (See reference...) Figure 15 The photoresist material PR on the second conductive layer CL2 can be removed by peeling, and a display panel DP including signal pads DP-PD can be formed.

[0146] Figure 16 This is a cross-sectional view showing one step in the bonding of the display panel and electronic components within frame S300. The display panel DP and electronic components can be bonded together via the adhesive layer CF.

[0147] refer to Figure 16 In this embodiment, the display panel DP may include a signal pad DP-PD, and the signal pad DP-PD may include a first conductive layer CL1, an insulating layer PLM disposed on the first conductive layer CL1, and a second conductive layer CL2 patterned on the insulating layer PLM. The second conductive layer CL2 patterned on the insulating layer PLM may be the farthest portion of the signal pad DP-PD protruding on the third direction DR3. The second conductive layer CL2 patterned on the insulating layer PLM may directly contact and be electrically connected to the bump electrode BP after bonding.

[0148] In the method for manufacturing an electronic device according to an embodiment of the present invention, the insulating layer comprising a polymer can be left unpatterned, thereby ensuring freedom of material application to the insulating layer and excellent adhesion to the conductive layer disposed beneath the insulating layer. Furthermore, a conductive layer comprising a metal disposed on the insulating layer can be patterned, thereby facilitating micropatterning of the portion in contact with the bump electrode and ensuring freedom of micropattern shape. Therefore, the bonding manufacturability of the electronic device can be increased.

[0149] As described above, the display panel and the electronic device including the display panel according to embodiments of the present invention may include an insulating layer between the conductive layer contained in the signal pads, thereby increasing the bonding retention between the display panel and the electronic components. Furthermore, a micropatterned conductive layer may be disposed on the insulating layer of the signal pads, thereby ensuring stable resistance between the signal pads and the bump electrodes. Therefore, the bonding reliability of the electronic device can be increased.

[0150] In the method for manufacturing an electronic device according to an embodiment of the present invention, the insulating layer comprising a polymer may not be patterned, thereby ensuring freedom of material application to the insulating layer and excellent adhesion to the conductive layer disposed beneath the insulating layer. Furthermore, a conductive layer comprising a metal disposed on the insulating layer may be patterned, thereby facilitating micro-patterning of the portion in contact with the bump electrode and ensuring freedom of micro-pattern shape.

[0151] Although embodiments of the inventive concept have been described, it should be understood that the inventive concept is not limited to these embodiments, and various changes and modifications can be made by those skilled in the art within the spirit and scope of the inventive concept. Therefore, the technical scope of the embodiments of the inventive concept is not limited to the embodiments described in the detailed description of the specification.

Claims

1. A display panel, comprising: Pixel; The signal line is electrically connected to the pixel; as well as The signal pads are connected to the signal lines. The signal pads include: The first conductive layer is electrically connected to the portion of the signal line; A second conductive layer is disposed on the first conductive layer; and An insulating layer is disposed between the first conductive layer and the second conductive layer. An opening is defined in the second conductive layer, the opening exposing a portion of the top surface of the insulating layer.

2. The display panel according to claim 1, wherein, The insulating layer includes an elastomer.

3. The display panel according to claim 1, wherein, The modulus of the insulating layer is in the range of 2 GPa to 10 GPa.

4. The display panel according to claim 1, wherein, On a plane, the insulating layer is disposed inside the first conductive layer and inside the second conductive layer.

5. The display panel according to claim 1, wherein: On a plane, the first conductive layer and the second conductive layer overlap each other, and The second conductive layer is disposed directly on a portion of the first conductive layer, wherein the insulating layer is not disposed on the portion of the first conductive layer, and the insulating layer exposes the portion of the first conductive layer.

6. The display panel according to claim 1, wherein, The side surface of the insulating layer is covered by the second conductive layer.

7. The display panel according to claim 1, wherein, The bottom surface of the insulating layer is covered by the first conductive layer.

8. The display panel according to claim 1, wherein: The portion of the signal line is disposed below the first conductive layer, and The display panel further includes a pad insulating layer disposed in the thickness direction of the signal pad between the portion of the signal line and the first conductive layer.

9. The display panel according to claim 8, further comprising a base layer disposed beneath the portion of the signal line.

10. The display panel according to claim 8, wherein, A contact hole is defined in the pad insulation layer, the contact hole exposing the portion of the signal line, and The first conductive layer is electrically connected to the portion of the signal line through the contact hole.

11. The display panel according to claim 10, wherein, The contact holes and the insulating layer are arranged to be spaced apart from each other on a plane.

12. The display panel according to claim 1, wherein, The opening includes multiple openings.

13. The display panel according to claim 1, wherein, Each of the first conductive layer and the second conductive layer has a titanium / aluminum / titanium three-layer structure.

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