Display device and electronic device including the same

Abstract

The invention relates to a display device and an electronic device including the same. The display device includes: a common electrode; a light emitting element between the pixel electrode and the common electrode; a reflective layer covering a side surface of the light emitting element; an element insulating layer provided between the reflective layer and the light emitting element; a first passivation layer disposed between the pixel circuit layer and the common electrode; a second passivation layer disposed on the common electrode; and a reflection wall defining a reflection opening of a closed curve shape around the light emitting element in a plan view, and filling a groove passing through the second passivation layer and the common electrode in a direction facing the pixel circuit layer.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0107697, filed on August 12, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to display devices and electronic devices including display devices. Background Technology

[0004] Recently, with the increasing interest in information display, research and development of display devices have been ongoing.

[0005] It should be understood that this background section is intended to provide useful context for understanding the technology. However, this background section may also include ideas, concepts, or knowledge that were not known or understood by one of ordinary skill in the art prior to the relevant valid application date of the subject matter disclosed herein. Summary of the Invention

[0006] The purpose of this disclosure is to provide a display device capable of preventing light mixing between adjacent sub-pixels.

[0007] According to embodiments of the present disclosure, a display device may include: a pixel electrode disposed on a pixel circuit layer; a common electrode facing the pixel electrode; a light-emitting element disposed between the pixel electrode and the common electrode, and including a first semiconductor layer connected to the pixel electrode, a second semiconductor layer connected to the common electrode, and an active layer disposed between the first semiconductor layer and the second semiconductor layer; a reflective layer covering a side surface of the light-emitting element; an element insulating layer disposed between the reflective layer and the light-emitting element; a first passivation layer disposed between the pixel circuit layer and the common electrode; a second passivation layer disposed on the common electrode; and a reflective wall defining a reflective opening in a closed curve shape around the light-emitting element in a plan view, and the reflective wall filling a groove passing through the second passivation layer and the common electrode in the direction facing the pixel circuit layer.

[0008] In this implementation, the reflector can directly contact the common electrode.

[0009] In one implementation, the groove may also extend through a first passivation layer adjacent to the common electrode.

[0010] In one implementation, the groove can expose the upper surface of the pixel circuit layer.

[0011] In an embodiment, the display device may further include: a light extraction portion disposed on a second passivation layer, surrounded by a reflective opening in a plan view, and protruding in a direction opposite to the direction facing the pixel circuit layer.

[0012] In some implementations, the reflective wall may be spaced apart from the pixel electrode.

[0013] In one embodiment, the reflective layer may cover the side surface of the pixel electrode, and the element insulating layer may be disposed between the pixel electrode and the reflective layer.

[0014] In some embodiments, the display device may further include an auxiliary electrode disposed between the pixel electrode and the first semiconductor layer.

[0015] In one implementation, the reflector wall may be spaced apart from the auxiliary electrode.

[0016] In an embodiment, the reflective wall may include a material with a light transmittance of about 5% or less, a light reflectance of about 60% or more, and a resistance of about 10Ω or less.

[0017] In some implementations, the reflective wall may include copper.

[0018] In one embodiment, the light-emitting element may have an inverted conical shape in which the width gradually increases in a direction away from the pixel circuit layer in a cross-sectional view.

[0019] According to an embodiment, the display device may include: a pixel electrode disposed on a pixel circuit layer; a common electrode facing the pixel electrode; a light-emitting element disposed between the pixel electrode and the common electrode, and including a first semiconductor layer connected to the pixel electrode, a second semiconductor layer connected to the common electrode, and an active layer disposed between the first semiconductor layer and the second semiconductor layer; a first passivation layer disposed between the pixel circuit layer and the common electrode; a second passivation layer disposed on the common electrode; and a reflective wall defining a reflective opening in a closed curve shape around the light-emitting element in a plan view, and the reflective wall may fill a groove passing through the second passivation layer, the common electrode, and the first passivation layer in a direction facing the pixel circuit layer.

[0020] In this embodiment, the first passivation layer can directly contact the side surface of the light-emitting element.

[0021] In one implementation, the groove can expose the upper surface of the pixel circuit layer.

[0022] In this implementation, the reflector can directly contact the common electrode.

[0023] In an embodiment, the display device may further include: a light extraction portion disposed on a second passivation layer, surrounded by a reflective opening in a plan view, and protruding in a direction opposite to the direction facing the pixel circuit layer.

[0024] In some implementations, the reflective wall may be spaced apart from the pixel electrode.

[0025] In some embodiments, the display device may further include an auxiliary electrode disposed between the pixel electrode and the first semiconductor layer.

[0026] In one implementation, the reflector wall may be spaced apart from the auxiliary electrode.

[0027] According to embodiments of this disclosure, an electronic device may include: a processor that provides input image data; and a display device that displays an image based on the input image data. The display device may include: a pixel electrode disposed on a pixel circuit layer; a common electrode facing the pixel electrode; a light-emitting element disposed between the pixel electrode and the common electrode, and including a first semiconductor layer connected to the pixel electrode, a second semiconductor layer connected to the common electrode, and an active layer disposed between the first and second semiconductor layers; a reflective layer covering a side surface of the light-emitting element; an element insulating layer disposed between the reflective layer and the light-emitting element; a first passivation layer disposed between the pixel circuit layer and the common electrode; a second passivation layer disposed on the common electrode; and a reflective wall that defines a reflective opening in a closed curve shape around the light-emitting element in a plan view, and the reflective wall fills a groove passing through the second passivation layer and the common electrode in the direction facing the pixel circuit layer.

[0028] The reflector can directly contact the common electrode.

[0029] The groove can also pass through the first passivation layer adjacent to the common electrode.

[0030] The grooves can expose the upper surface of the pixel circuit layer.

[0031] The electronic device may also include: a light extraction portion disposed on the second passivation layer, surrounded by a reflective opening in the plan view, and protruding in a direction opposite to the direction facing the pixel circuit layer.

[0032] The reflective wall can be spaced apart from the pixel electrode.

[0033] Electronic devices can be at least one of the following: organic light-emitting display devices; inorganic light-emitting display devices; quantum dot light-emitting display devices; displays for portable electronic devices such as mobile phones, smartphones, tablet PCs, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs); and displays for televisions, notebooks, monitors, advertising panels, Internet of Things (IoT) devices, portable communication devices, smartphones, computer equipment, portable multimedia devices, portable medical devices, cameras, wearable devices, and home appliances.

[0034] The display device according to the embodiment may include a reflective wall. In a plan view, the reflective wall may define a reflective opening in a closed curve shape around the light-emitting element and may fill a groove passing through the second passivation layer and the common electrode.

[0035] Totally internally reflected light at the interface between the common electrode and the layer in contact with the common electrode can be reflected by the reflective wall. Similarly, totally internally reflected light at the interface between the second passivation layer and the layer in contact with the second passivation layer can be reflected by the reflective wall. Therefore, light mixing from the light-emitting element can be prevented. Attached Figure Description

[0036] The above and other features of this disclosure will become more apparent from the accompanying drawings, which describe embodiments of the present disclosure in a further detailed manner. Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present disclosure; Figure 2 It is shown that it includes Figure 1 A block diagram of one of the subpixels in a display device; Figure 3 This shows the configuration. Figure 1 A schematic plan view of the display panel of the display device; Figure 4 This is a schematic plan view illustrating pixels according to an embodiment of the present disclosure; Figure 5 It shows along Figure 4 The line I1-I1' intercepted Figure 4 A schematic cross-sectional view of the first embodiment of the pixels; Figure 6 It shows along Figure 4 The line I1-I1' intercepted Figure 4 A schematic cross-sectional view of the second embodiment of the pixels; Figure 7 It shows along Figure 4 The line I1-I1' intercepted Figure 4 A schematic cross-sectional view of the third embodiment of the pixels; Figure 8 It shows along Figure 4 The line I1-I1' intercepted Figure 4 A schematic cross-sectional view of the fourth embodiment of the pixels; Figure 9 It shows along Figure 4 The line I1-I1' intercepted Figure 4 A schematic cross-sectional view of the fifth embodiment of the pixels; Figure 10 It shows along Figure 4 The line I1-I1' intercepted Figure 4A schematic cross-sectional view of the sixth embodiment of the pixels; Figures 11 to 15 This is a schematic plan view showing a reflective partition wall (or reflective wall) according to an embodiment of the present disclosure; Figure 16 This is a block diagram illustrating a display system according to an embodiment; and Figure 17 and Figure 18 It is shown Figure 16 A schematic 3D diagram illustrating an application example of the display system. Detailed Implementation

[0037] In the following, embodiments according to this disclosure are described in detail with reference to the accompanying drawings. It should be noted that in the following description, only the parts necessary for understanding operation according to this disclosure are described, and descriptions of other parts may be omitted so as not to obscure the subject matter of this disclosure. This disclosure may be implemented in other forms and is not limited to the embodiments described herein. However, the embodiments described herein are provided in sufficient detail to readily implement the technical spirit of this disclosure to those skilled in the art to which this disclosure pertains. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to also include the plural forms.

[0038] In the specification and claims, for the purposes of their meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" can be understood to mean "A, B, or A and B". The terms "and" and "or" can be used in the sense of conjunction or disjunction and can be understood as equivalent to "and / or".

[0039] In the specification and claims, the phrase "at least one of..." is intended, for the purposes of its meaning and interpretation, to include the meaning of "at least one selected from the group consisting of...". For example, "at least one of A and B" can be understood to mean "A, B, or A and B".

[0040] Throughout this specification, the phrase "connected" to another part includes not only cases where the part is "directly connected," but also cases where the part is "indirectly connected" via another element disposed therebetween. The terminology used herein is for describing embodiments and is not intended to limit this disclosure. Throughout this specification, the phrase "comprising..." means, unless otherwise stated, that part may also include, but is not excluded from, another component.

[0041] Here, terms such as "first" and "second" may be used to describe various components, but these components are not limited by these terms. These terms are used to distinguish one component from another. Therefore, without departing from the scope disclosed herein, "first component" may refer to "second component".

[0042] For descriptive purposes, spatial relative terms such as “below” and “above” may be used to describe the relationship between one element or feature and another element(s) as shown in the accompanying drawings. In addition to the directions depicted in the drawings, spatial relative terms are intended to also include other directions in use, operation, and / or manufacture. For example, when the device shown in the drawings is flipped upside down, an element depicted as positioned “below” other elements or features is positioned in an direction “above” other elements or features. Therefore, in embodiments, the term “below” can include both up and down directions. The device may face other directions (e.g., rotated 90 degrees or at other angles), and therefore the spatial relative terms used herein are interpreted accordingly.

[0043] The term “overlap” or “overlap with” means that the first object may be above or below the second object, or on one side of the second object, and vice versa. Additionally, the term “overlap” may include layering, stacking, facing or oriented, extending across, covering or partially covering, or any other suitable term that will be understood and appreciated by one of ordinary skill in the art.

[0044] The terms "facing" and "oriented" mean that the first element can be directly or indirectly opposite the second element. In the case where the third element is between the first and second elements, although the first and second elements are still facing each other, they can be understood as being indirectly opposite each other.

[0045] When an element is described as “not overlapping” or “not “overlapping” with another element, this may include the elements being spaced apart from each other, offset from each other, or positioned next to each other, or may include any other suitable terms as will be understood and appreciated by one of ordinary skill in the art.

[0046] The terms “comprising,” “including,” “containing,” and / or “containing,” “having,” “possessing,” and / or “having,” and variations thereof, when used in this specification, expressly indicate the presence of the stated features, integrals, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0047] Various embodiments are described with reference to the accompanying drawings, which schematically illustrate various implementations. Therefore, the desired shape may vary depending on, for example, tolerances and / or manufacturing techniques. Consequently, the embodiments disclosed herein should not be construed as limited to the specific shapes shown, but should be interpreted as including shape changes, for example, due to manufacturing processes. As described above, the shapes shown in the drawings may not represent the actual shape of an area of ​​the device, and the embodiments are not limited thereto.

[0048] Given the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), the terms “about” or “approximately” as used herein include the stated value and mean within an acceptable deviation of the particular value as determined by one of ordinary skill in the art. For example, “about” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0049] Unless otherwise specified or implied herein, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms, such as those defined in common dictionaries, shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formalized sense unless expressly so specified herein.

[0050] The embodiments can be described and illustrated in the accompanying drawings based on functional blocks, units and / or modules.

[0051] Those skilled in the art will understand that these blocks, units, and / or modules can be physically implemented by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wiring connections, etc., formed using semiconductor-based manufacturing techniques or other manufacturing techniques.

[0052] Where blocks, units, and / or modules are implemented by microprocessors or other similar hardware, they can be programmed and controlled by software (e.g., microcode) to perform the various functions discussed herein, and can optionally be driven by firmware and / or software.

[0053] It is also anticipated that each block, unit, and / or module can be implemented by dedicated hardware, or can be implemented as a combination of dedicated hardware performing certain functions and processors (e.g., one or more programmed microprocessors and associated circuitry) performing other functions.

[0054] Without departing from the scope of this disclosure, each block, unit, and / or module of an implementation may be physically divided into two or more interactive and discrete blocks, units, and / or modules.

[0055] Furthermore, without departing from the scope of this disclosure, the blocks, units, and / or modules of the embodiments may be physically combined into more complex blocks, units, and / or modules.

[0056] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0057] refer to Figure 1 The display device DD may include a display panel DP, a gate driver 120, a data driver 130, a voltage generator 140, and a controller 150.

[0058] The display panel DP may include sub-pixels SP. Sub-pixels SP can be connected to gate driver 120 via first gate line GL1 to m-th gate line GLm. Sub-pixels SP can be connected to data driver 130 via first data line DL1 to n-th data line DLn.

[0059] Subpixels (SPs) can generate light of two or more colors. For example, each subpixel SP can generate light such as red, green, blue, cyan, magenta, or yellow.

[0060] Two or more subpixels within a subpixel SP can be configured into a pixel PXL. For example, pixel PXL can include, for instance, ... Figure 1 The three sub-pixels are shown. As described above, pixel PXL can emit light of various colors and brightnesses based on the combination of light emitted from the sub-pixels SP included in pixel PXL.

[0061] Gate driver 120 can be connected to sub-pixels SP arranged (or configured) in the row direction via first gate lines GL1 to m-th gate lines GLm. Gate driver 120 can output gate signals to first gate lines GL1 to m-th gate lines GLm in response to gate control signal GCS. In embodiments, within the spirit and scope of this disclosure, gate control signal GCS may include a start signal indicating the start of each frame, a horizontal synchronization signal, etc.

[0062] The gate driver 120 may be disposed on one side or one side of the display panel DP. However, the implementation is not limited to this. For example, the gate driver 120 may be divided into two or more drivers that are physically and / or logically separated, and such drivers may be disposed on one side or one side of the display panel DP and on the opposite side of the display panel DP. As described above, according to the implementation, the gate driver 120 may be disposed around the display panel DP in various shapes.

[0063] The data driver 130 can be connected to sub-pixels SP arranged in the column direction via first data lines DL1 to nth data lines DLn. The data driver 130 can receive image data DATA and data control signals DCS from the controller 150. The data driver 130 can operate in response to the data control signals DCS. In embodiments, within the spirit and scope of this disclosure, the data control signals DCS may include source enable signals, source shift clocks, source output enable signals, etc.

[0064] The data driver 130 can receive voltage from the voltage generator 140. The data driver 130 can use the received voltage to apply a data signal having a grayscale voltage corresponding to the image data DATA to the first data lines DL1 through the nth data line DLn. When a gate signal is applied to each of the first gate lines GL1 through the mth gate line GLm, the data signal corresponding to the image data DATA can be applied to the first data lines DL1 through the nth data line DLn. Therefore, the sub-pixel SP can generate light corresponding to the data signal, and the display panel DP can display an image.

[0065] In one embodiment, the gate driver 120 and the data driver 130 may include complementary metal-oxide-semiconductor (CMOS) circuit elements.

[0066] Voltage generator 140 can operate in response to a voltage control signal VCS from controller 150. Voltage generator 140 can be configured to generate a voltage and provide the generated voltage to components of display device DD (such as gate driver 120, data driver 130, and controller 150). Voltage generator 140 can generate a voltage by receiving an input voltage from outside display device DD and adjusting the received voltage.

[0067] Voltage generator 140 can generate a first power supply voltage and a second power supply voltage. The generated first and second power supply voltages can be provided to the sub-pixel SP via power line PL. In other embodiments, at least one of the first and second power supply voltages can be provided externally to the display device DD.

[0068] Voltage generator 140 can provide various voltages and / or signals. For example, voltage generator 140 can provide one or more initialization voltages applied to sub-pixel SP. For example, during sensing operations for sensing the electrical characteristics of the transistors and / or light-emitting elements of sub-pixel SP, an optional reference voltage can be applied to first data lines DL1 to nth data lines DLn, and voltage generator 140 can generate the reference voltage and send it to data driver 130. For example, during display operations for displaying an image on display panel DP, a common pixel control signal can be applied to sub-pixel SP, and voltage generator 140 can generate the pixel control signal. In an embodiment, voltage generator 140 can provide pixel control signals to sub-pixel SP via pixel control line PXCL. Figure 1 In this embodiment, the pixel control line PXCL is connected between the voltage generator 140 and the display panel DP, but the implementation is not limited to this. For example, the pixel control line PXCL can be connected between the gate driver 120 and the display panel DP. In this case, the pixel control signal can be sent from the voltage generator 140 to the pixel control line PXCL through the gate driver 120.

[0069] The controller 150 can control the overall operation of the display device DD. The controller 150 can receive input image data IMG and a corresponding control signal CTRL from an external source. In response to the control signal CTRL, the controller 150 can provide a gate control signal GCS, a data control signal DCS, and a voltage control signal VCS.

[0070] The controller 150 can convert the input image data IMG to fit the display device DD or display panel DP, and output image data DATA. In one embodiment, the controller 150 can output image data DATA by aligning the input image data IMG to fit sub-pixels SP in rows.

[0071] Two or more of the components—data driver 130, voltage generator 140, and controller 150—can be mounted on a single integrated circuit. For example... Figure 1 As shown, the data driver 130, voltage generator 140, and controller 150 may be included in a driver integrated circuit (DIC). In this case, the data driver 130, voltage generator 140, and controller 150 may be functionally separate components within a single driver integrated circuit (DIC). In other embodiments, at least one of the data driver 130, voltage generator 140, and controller 150 may be provided as a component distinct from the driver integrated circuit (DIC).

[0072] Figure 2It is shown that it includes Figure 1 A block diagram of one subpixel among subpixels in a display device. Figure 2 In Figure 1 Among the sub-pixels SP, sub-pixels SPij are shown as an example, arranged in the i-th row (i is an integer greater than or equal to 1 and less than or equal to m) and the j-th column (j is an integer greater than or equal to 1 and less than or equal to n).

[0073] refer to Figure 2 Subpixel SPij may include subpixel circuit SPC and light-emitting element LD.

[0074] The light-emitting element (LD) can be connected between the first power supply voltage node VDDN and the second power supply voltage node VSSN. The first power supply voltage node VDDN can be connected to... Figure 1 One of the power lines PL receives the first power supply voltage. The second power supply voltage node VSSN can be connected to... Figure 1 The first power supply line (PL) is another power supply line and can receive a second power supply voltage. The first power supply voltage can have a voltage level higher than the second power supply voltage.

[0075] The light-emitting element (LD) can be connected between the pixel electrode AE ​​and the common electrode CE. The pixel electrode AE ​​can be connected to the first power supply voltage node VDDN via a sub-pixel circuit SPC. For example, the pixel electrode AE ​​can be connected to the first power supply voltage node VDDN via one or more transistors included in the sub-pixel circuit SPC. The common electrode CE can be connected to the second power supply voltage node VSSN. The light-emitting element LD can be configured to emit light according to the current flowing from the pixel electrode AE ​​to the common electrode CE.

[0076] In this implementation, the pixel electrode AE ​​can be referred to as one of the anode electrode and the cathode electrode, and the common electrode CE can be referred to as the other of the anode electrode and the cathode electrode. For example, the pixel electrode AE ​​can be referred to as the anode electrode, and the common electrode CE can be referred to as the cathode electrode.

[0077] Sub-pixel circuits (SPCs) can be connected to Figure 1 The i-th gate line GLi among the first gate line GL1 to the m-th gate line GLm and Figure 1 The first data line DL1 to the nth data line DLn, specifically the j-th data line DLj. In response to the gate signal received via the i-th gate line GL1, the sub-pixel circuit SPC can control the light-emitting element LD to emit light based on the data signal received via the j-th data line DLj. In this embodiment, the sub-pixel circuit SPC can also be connected to... Figure 1The pixel control line PXCL. In this case, the sub-pixel circuit SPC can further control the light-emitting element LD in response to the pixel control signal received through the pixel control line PXCL.

[0078] For this operation, the sub-pixel circuit SPC may include circuit elements (e.g., transistors and one or more capacitors).

[0079] The transistors of the sub-pixel circuit SPC may include P-type transistors and / or N-type transistors. In some embodiments, the transistors of the sub-pixel circuit SPC may include metal-oxide-semiconductor field-effect transistors (MOSFETs). In some embodiments, within the spirit and scope of this disclosure, the transistors of the sub-pixel circuit SPC may include amorphous silicon semiconductors, monocrystalline silicon semiconductors, polycrystalline silicon semiconductors, oxide semiconductors, etc.

[0080] Figure 3 This shows the configuration. Figure 1 A schematic plan view of the display panel of the display device.

[0081] refer to Figure 3 The display panel DP can include a display area DA and a non-display area NDA. The display panel DP can display images through the display area DA. The non-display area NDA can be positioned around the display area DA.

[0082] The display panel DP may include sub-pixels SP in the display area DA. The sub-pixels SP may be arranged along a first direction DR1 and a second direction DR2 intersecting the first direction DR1. For example, the sub-pixels SP may be arranged in a matrix along the first direction DR1 and the second direction DR2. As another example, the sub-pixels SP may be arranged in a zigzag pattern along the first direction DR1 and the second direction DR2. The arrangement of the sub-pixels SP may vary depending on the implementation. The first direction DR1 may be a column direction, and the second direction DR2 may be a row direction.

[0083] Two or more subpixels within a subpixel SP can be configured into a single pixel PXL. Figure 3 In this embodiment, pixel PXL may include three sub-pixels SP1, SP2, and SP3, but the implementation is not limited to this. For example, pixel PXL may include two sub-pixels. In the following text, for ease of description, it is assumed that pixel PXL may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3.

[0084] Each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can generate light of one of various colors, such as red, green, blue, cyan, magenta, and yellow. For clarity and brevity, it is assumed below that the first sub-pixel SP1 is configured to generate red light, the second sub-pixel SP2 is configured to generate green light, and the third sub-pixel SP3 is configured to generate blue light.

[0085] Each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may include at least one light-emitting element configured to generate light. In one embodiment, the light-emitting elements of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may generate light of different colors. For example, the light-emitting elements of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may generate red light, green light, and blue light, respectively. In other embodiments, the light-emitting elements of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may generate light of the same color. For example, the light-emitting elements of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may generate blue light.

[0086] As a display panel DP, a light-emitting diode (LED) display panel that uses micron- or nano-sized light-emitting diodes as light-emitting elements can be applied.

[0087] The components used to control the sub-pixel SP can be located in the non-display area NDA. Lines connected to the sub-pixel SP (e.g., Figure 1 The first gate line GL1 to the m-th gate line GLm, the first data line DL1 to the n-th data line DLn, the power line PL, and the pixel control line PXCL can be set in the non-display area NDA.

[0088] Figure 1 At least one of the gate driver 120, data driver 130, voltage generator 140, and controller 150 can be disposed in the non-display area NDA of the display panel DP. In this case, the data driver 130, voltage generator 140, and controller 150 can be implemented as follows: Figure 1 The driver integrated circuit (DIC) is separate from the display panel (DP), and the driver integrated circuit (DIC) can be connected to a line disposed in the non-display area (NDA). In other embodiments, the gate driver 120, together with the data driver 130, voltage generator 140, and controller 150, can be implemented as a single integrated circuit separate from the display panel (DP).

[0089] In implementations, the display area DA can have various shapes. The display area DA can have a closed-loop shape with sides including straight lines and / or curves. For example, within the spirit and scope of this disclosure, the display area DA can have shapes such as polygons, circles, semicircles, and ellipses.

[0090] In one embodiment, the display panel DP may have a flat display surface. In other embodiments, the display panel DP may have a display surface that is at least partially circular. In another embodiment, the display panel DP may be flexible, foldable, or rollable. In this case, the display panel DP and / or the substrate of the display panel DP may include a material with flexible properties.

[0091] Figure 4 This is a schematic plan view showing pixels according to an embodiment of the present disclosure.

[0092] refer to Figure 4 Pixel PXL can include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3.

[0093] The first sub-pixel SP1 may include a first light-emitting element LD1. The second sub-pixel SP2 may include a second light-emitting element LD2. The third sub-pixel SP3 may include a third light-emitting element LD3. The first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 may be set as a reference. Figure 2 The light-emitting element LD is described.

[0094] exist Figure 4 The diagram shows a first light-emitting element LD1, a second light-emitting element LD2, and a third light-emitting element LD3 that appear circular in a plan view. However, the shapes of the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 are not limited to this. According to the embodiment, the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 can have various shapes. For example, when the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 have a right-angled parallelepiped shape, a quadrilateral shape can be observed in the plan view.

[0095] Pixel PXL may include a reflective partition wall (or reflective wall) RPW. The reflective partition wall RPW may define a reflective aperture ROP. The reflective aperture ROP may include a first reflective aperture ROP1, a second reflective aperture ROP2, and a third reflective aperture ROP3. In a planar view, the first reflective aperture ROP1 may overlap with a first light-emitting element LD1. In a planar view, the second reflective aperture ROP2 may overlap with a second light-emitting element LD2. In a planar view, the third reflective aperture ROP3 may overlap with a third light-emitting element LD3.

[0096] In the plan view, the first reflective opening ROP1 can have a closed curve shape surrounding the first light-emitting element LD1. For example, as Figure 4 As shown, the first reflective opening ROP1 can have a quadrilateral shape in the plan view. Similarly, in the plan view, the second reflective opening ROP2 can have a closed curve shape surrounding the second light-emitting element LD2, and the third reflective opening ROP3 can have a closed curve shape surrounding the third light-emitting element LD3. However, the shapes of the first reflective opening ROP1, the second reflective opening ROP2, and the third reflective opening ROP3 are not limited to these.

[0097] Reflective partition walls (RPWs) can be placed between adjacent light-emitting elements. Therefore, RPWs can be used to prevent light mixing between adjacent sub-pixels.

[0098] Figure 5 It shows along Figure 4 The line I1-I1' intercepted Figure 4 A schematic cross-sectional view of the first embodiment of the pixels.

[0099] refer to Figure 4 and Figure 5 The pixel PXL may include a substrate SUB, a pixel circuit layer PCL, a display element layer DPL, and an optical function layer LFL.

[0100] In this implementation, the substrate SUB can be a silicon substrate. The substrate SUB can be fabricated using a silicon wafer in a semiconductor process. The substrate SUB may include a first sub-pixel circuit SPC1, a second sub-pixel circuit SPC2, and a third sub-pixel circuit SPC3. The first sub-pixel circuit SPC1 can be configured as the sub-pixel circuit SPC of the first sub-pixel SP1 (see reference). Figure 2 The second sub-pixel circuit SPC2 can be configured as the sub-pixel circuit SPC of the second sub-pixel SP2 (see reference). Figure 2 The third sub-pixel circuit SPC3 can be configured as the sub-pixel circuit SPC of the third sub-pixel SP3 (see reference). Figure 2 ).

[0101] The pixel circuit layer PCL can be disposed on the substrate SUB. The pixel circuit layer PCL may include an insulating layer and a conductive layer disposed between the insulating layers. In an embodiment, the pixel circuit layer PCL may include a first insulating layer IL1, a second insulating layer IL2 disposed on the first insulating layer IL1, and a first connection electrode CE1, a second connection electrode CE2, and a third connection electrode CE3 disposed between the first insulating layer IL1 and the second insulating layer IL2.

[0102] The first insulating layer IL1 and the second insulating layer IL2 may comprise insulating materials. In some embodiments, the first insulating layer IL1 and the second insulating layer IL2 may comprise inorganic insulating materials. For example, the first insulating layer IL1 and the second insulating layer IL2 may comprise inorganic insulating materials such as silicon oxide, silicon nitride, silicon nitride, aluminum oxide, or hafnium oxide.

[0103] The first connecting electrode CE1, the second connecting electrode CE2, and the third connecting electrode CE3 may include conductive materials. For example, the first connecting electrode CE1, the second connecting electrode CE2, and the third connecting electrode CE3 may include at least one material selected from copper (Cu), molybdenum (Mo), tungsten (W), aluminum (Al), titanium (Ti), and silver (Ag).

[0104] The first connecting electrode CE1 can be connected to the first sub-pixel circuit SPC1 through a through-hole passing through the first insulating layer IL1. The second connecting electrode CE2 can be connected to the second sub-pixel circuit SPC2 through a through-hole passing through the first insulating layer IL1. The third connecting electrode CE3 can be connected to the third sub-pixel circuit SPC3 through a through-hole passing through the first insulating layer IL1.

[0105] The pixel circuit layer (PCL) may also include various components such as lines and electrodes for configuring sub-pixels. In this case, as the number of layers required to form the lines, electrodes, etc., for configuring sub-pixels increases, the number of insulating and conductive layers included in the pixel circuit layer (PCL) can also increase.

[0106] The display element layer (DPL) can be disposed on the pixel circuit layer (PCL). The display element layer (DPL) may include a first pixel electrode AE1, a second pixel electrode AE2 and a third pixel electrode AE3, a first auxiliary electrode AUXE1, a second auxiliary electrode AUXE2 and a third auxiliary electrode AUXE3, a first light-emitting element LD1, a second light-emitting element LD2 and a third light-emitting element LD3, a first element insulating layer IIL1, a second element insulating layer IIL2 and a third element insulating layer IIL3, a first reflective layer RL1, a second reflective layer RL2 and a third reflective layer RL3, and a common electrode CE.

[0107] The first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 can be disposed on the second insulating layer IL2. The first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 can be spaced apart from each other. The first pixel electrode AE1 can be configured as the pixel electrode AE ​​of the first sub-pixel SP1 (see reference). Figure 2 The second pixel electrode AE2 can be set as the pixel electrode AE ​​of the second sub-pixel SP2 (see reference). Figure 2 ), and the third pixel electrode AE3 can be provided as the pixel electrode AE ​​of the third sub-pixel SP3 (see reference). Figure 2 ).

[0108] The first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may include conductive materials. For example, the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may include at least one of various conductive materials such as aluminum (Al), silver (Ag), indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), and indium tin zinc oxide (ITZO).

[0109] A first auxiliary electrode AUXE1 may be disposed on a first pixel electrode AE1. A second auxiliary electrode AUXE2 may be disposed on a second pixel electrode AE2. A third auxiliary electrode AUXE3 may be disposed on a third pixel electrode AE3. In an embodiment, the first auxiliary electrode AUXE1, the second auxiliary electrode AUXE2, and the third auxiliary electrode AUXE3 may be formed of a conductive material with selectable reflectivity. For example, the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may include metals and / or alloys thereof such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), and titanium (Ti). In an embodiment, the first auxiliary electrode AUXE1, the second auxiliary electrode AUXE2, and the third auxiliary electrode AUXE3 may include at least one of various transparent conductive materials such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), and indium tin zinc oxide (ITZO).

[0110] According to the implementation method, the first auxiliary electrode AUXE1, the second auxiliary electrode AUXE2, and the third auxiliary electrode AUXE3 can be omitted.

[0111] The first light-emitting element LD1 can be disposed on the first pixel electrode AE1. According to an embodiment, the first auxiliary electrode AUXE1 can be disposed between the first light-emitting element LD1 and the first pixel electrode AE1.

[0112] The first light-emitting element LD1 may include a first semiconductor layer S1, an active layer MQW, and a second semiconductor layer S2, which are stacked sequentially along the third direction DR3.

[0113] The first semiconductor layer S1 can be connected to the first pixel electrode AE1. The first semiconductor layer S1 may include a semiconductor material having a first polarity. In an embodiment, the first semiconductor layer S1 may include a P-type semiconductor layer, and in this case, the first semiconductor layer S1 may provide holes to the active layer MQW. For example, the first semiconductor layer S1 may include at least one semiconductor material selected from gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and indium nitride (InN), and may be a P-type semiconductor layer doped with P-type dopants such as magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), and barium (Ba).

[0114] The second semiconductor layer S2 can be connected to the common electrode CE. The second semiconductor layer S2 can include a semiconductor material having a second polarity different from the first polarity. In an embodiment, the second semiconductor layer S2 can include an N-type semiconductor layer, and in this case, the second semiconductor layer S2 can provide electrons to the active layer MQW. For example, the second semiconductor layer S2 can include at least one semiconductor material selected from gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and indium nitride (InN), and can be an N-type semiconductor layer doped with an N-type dopant such as silicon (Si), germanium (Ge), or tin (Sn).

[0115] An active quantum well (MQW) layer can be disposed between a first semiconductor layer S1 and a second semiconductor layer S2. The active quantum well MQW provides a region in which electrons and holes recombine. When electrons and holes recombine in the active quantum well MQW, they can transition to lower energy levels and generate light with a corresponding wavelength. The active quantum well MQW can be formed as a single quantum well structure or a multi-quantum well structure. In the case where the active quantum well MQW is formed as a multi-quantum well structure, units including a barrier layer, a strain-enhancing layer, and a well layer can be repeatedly stacked to form the active quantum well MQW. However, the active quantum well MQW is not limited to this.

[0116] The second light-emitting element LD2 and the third light-emitting element LD3 can be configured similarly to the first light-emitting element LD1. Therefore, overlapping descriptions can be omitted.

[0117] A first reflective layer RL1 can cover the side surface of the first light-emitting element LD1. A first element insulating layer IIL1 can be disposed between the first reflective layer RL1 and the first light-emitting element LD1. A second reflective layer RL2 can cover the side surface of the second light-emitting element LD2. A second element insulating layer IIL2 can be disposed between the second reflective layer RL2 and the second light-emitting element LD2. A third reflective layer RL3 can cover the side surface of the third light-emitting element LD3. A third element insulating layer IIL3 can be disposed between the third reflective layer RL3 and the third light-emitting element LD3.

[0118] The first reflective layer RL1, the second reflective layer RL2, and the third reflective layer RL3 can be formed of materials with selectable reflectivities. For example, the first reflective layer RL1, the second reflective layer RL2, and the third reflective layer RL3 can include metals and / or alloys thereof such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), and titanium (Ti). In this case, light emitted from the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 can be efficiently output toward the light functional layer LFL.

[0119] The first element insulating layer IIL1, the second element insulating layer IIL2, and the third element insulating layer IIL3 may comprise inorganic insulating materials. For example, within the spirit and scope of this disclosure, the first element insulating layer IIL1, the second element insulating layer IIL2, and the third element insulating layer IIL3 may comprise silicon nitride, silicon oxide, silicon oxynitride, etc.

[0120] In one embodiment, the first reflective layer RL1 may further cover the side surface of the first pixel electrode AE1 and the side surface of the first auxiliary electrode AUXE1. In this case, the first element insulating layer IIL1 may be disposed between the first reflective layer RL1 and the first pixel electrode AE1, and between the first reflective layer RL1 and the first auxiliary electrode AUXE1.

[0121] Similarly, the second reflective layer RL2 may also cover the side surface of the second pixel electrode AE2 and the side surface of the second auxiliary electrode AUXE2. The second element insulating layer IIL2 may be disposed between the second reflective layer RL2 and the second pixel electrode AE2, and between the second reflective layer RL2 and the second auxiliary electrode AUXE2. The third reflective layer RL3 may also cover the side surface of the third pixel electrode AE3 and the side surface of the third auxiliary electrode AUXE3. The third element insulating layer IIL3 may be disposed between the third reflective layer RL3 and the third pixel electrode AE3, and between the third reflective layer RL3 and the third auxiliary electrode AUXE3.

[0122] The first passivation layer PSV1 may be disposed between the pixel circuit layer PCL and the common electrode CE. The first passivation layer PSV1 may include an inorganic insulating layer containing inorganic materials and / or an organic insulating layer containing organic materials. The inorganic insulating layer may include at least one of metal oxides such as silicon oxide, silicon nitride, or aluminum oxide, and silicon nitrides. The organic insulating layer may include, for example, acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polystyrene ether resin, and benzocyclobutene resin.

[0123] A common electrode CE can be disposed on the first passivation layer PSV1, facing the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3. The common electrode CE can be connected to the second semiconductor layer S2 of the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3.

[0124] The common electrode CE can be configured to be substantially transparent or translucent to meet selectable light transmittance. For example, the common electrode CE may include at least one of a variety of transparent conductive materials such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), and indium tin zinc oxide (ITZO).

[0125] The light functional layer (LFL) can be disposed on the display element layer (DPL). The light functional layer (LFL) may include a second passivation layer (PSV2), a reflective partition wall (RPW), a first light extraction structure (or a first light extraction portion) (MLA1), a second light extraction structure (or a second light extraction portion) (MLA2), and a third light extraction structure (or a third light extraction portion) (MLA3).

[0126] The second passivation layer PSV2 can be disposed on the common electrode CE. The second passivation layer PSV2 may comprise a material substantially the same as or similar to the first passivation layer PSV1.

[0127] The reflective partition wall RPW can be configured to fill the groove GR that passes through the second passivation layer PSV2 and the common electrode CE in a direction opposite to the third-direction DR3. In this case, the reflective partition wall RPW can directly contact the upper surface of the first passivation layer PSV1.

[0128] Reflective partition walls (RPWs) can be used to prevent light mixing between adjacent sub-pixels. For example, a first light L1 emitted from a first light-emitting element LD1 can be totally internally reflected at the interface between a common electrode CE and layers (e.g., PSV1 and PSV2) in contact with the common electrode CE, and can be emitted in a direction facing a second sub-pixel SP2. The first light L1 can be reflected by the reflective partition wall (RPW). Therefore, mixing of the first light L1 with light emitted from a second light-emitting element LD2 can be prevented. As another example, a second light L2 emitted from the first light-emitting element LD1 can be totally internally reflected at the interface between a second passivation layer PSV2 and a layer (e.g., MLA1) in contact with the second passivation layer PSV2, and can be emitted in a direction facing another sub-pixel adjacent to the first sub-pixel SP1. The second light L2 can be reflected by the reflective partition wall (RPW). Therefore, mixing of the second light L2 with light emitted from another light-emitting element adjacent to the first light-emitting element LD1 can be prevented.

[0129] In this implementation, the reflective separator wall (RPW) can directly contact the common electrode (CE). In this case, the common electrode (CE) of the first sub-pixel SP1 and the common electrode (CE) of the second sub-pixel SP2 can be electrically connected through the reflective separator wall (RPW) between the first sub-pixel SP1 and the second sub-pixel SP2. Similarly, the common electrode (CE) of the second sub-pixel SP2 and the common electrode (CE) of the third sub-pixel SP3 can be electrically connected through the reflective separator wall (RPW) between the second sub-pixel SP2 and the third sub-pixel SP3.

[0130] In this embodiment, the reflective separator RPW can be spaced apart from the first pixel electrode AE1, the second pixel electrode AE2, the third pixel electrode AE3, and the first auxiliary electrode AUXE1, the second auxiliary electrode AUXE2, and the third auxiliary electrode AUXE3. Therefore, it is possible to prevent the first pixel electrode AE1, the second pixel electrode AE2, the third pixel electrode AE3, and the first auxiliary electrode AUXE1, the second auxiliary electrode AUXE2, and the third auxiliary electrode AUXE3 from being electrically connected to the common electrode CE through the reflective separator RPW.

[0131] In an embodiment, the reflective partition wall RPW may comprise a material with a light transmittance of about 5% or less, a light reflectance of about 60% or more, and a resistivity of about 10 Ω or less. For example, the reflective partition wall RPW may comprise copper (Cu).

[0132] The first light extraction structure MLA1 can be disposed on the second passivation layer PSV2. The first light extraction structure MLA1 can be disposed within the first reflection opening ROP1. For example, in a plan view, the first light extraction structure MLA1 can be surrounded by the first reflection opening ROP1. The first light extraction structure MLA1 can be configured to protrude on the third-direction DR3. The first light extraction structure MLA1 can be used to improve the light efficiency of light emitted from the first light-emitting element LD1.

[0133] The second light extraction structure MLA2 and the third light extraction structure MLA3 can be configured to be substantially the same as the first light extraction structure MLA1. For example, in a planar view, the second light extraction structure MLA2 can be surrounded by a second reflective opening ROP2. In a planar view, the third light extraction structure MLA3 can be surrounded by a third reflective opening ROP3.

[0134] Figure 6 It shows along Figure 4 The line I1-I1' intercepted Figure 4 A schematic cross-sectional view of the second embodiment of the pixels.

[0135] The following describes the reference. Figure 5 The differences compared to the first embodiment described above can be used to replace parts that can be omitted.

[0136] refer to Figure 4 and Figure 6 The groove GR can further extend through the first passivation layer PSV1 adjacent to the common electrode CE. For example, the distance from the lower surface of the groove GR to the upper surface of the pixel circuit layer PCL on the third-direction DR3 can be substantially the same as the distance from the upper surface of the pixel circuit layer PCL to the upper surface of the first auxiliary electrode AUXE1 on the third-direction DR3. The reflective partition wall RPW can be configured to fill the groove GR. Therefore, light mixing between adjacent sub-pixels can be prevented more efficiently by means of the reflective partition wall RPW.

[0137] Figure 7 It shows along Figure 4 The line I1-I1' intercepted Figure 4 A schematic cross-sectional view of the third embodiment of the pixels.

[0138] The following describes the reference. Figure 5 The differences compared to the first embodiment described above can be used to replace parts that can be omitted.

[0139] refer to Figure 4 and Figure 7The groove GR can further penetrate the first passivation layer PSV1 to expose the upper surface of the pixel circuit layer PCL. The reflective partition wall RPW can be configured to fill the groove GR. Therefore, light mixing between adjacent sub-pixels can be prevented more efficiently by using the reflective partition wall RPW.

[0140] Figure 8 It shows along Figure 4 The line I1-I1' intercepted Figure 4 A schematic cross-sectional view of the fourth embodiment of the pixels.

[0141] The following describes the reference. Figure 5 The differences compared to the first embodiment described above can be used to replace parts that can be omitted.

[0142] refer to Figure 4 and Figure 8 In the cross-sectional view, the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 can have an inverted conical shape with a width that gradually increases along the third direction DR3. In this case, in the cross-sectional view, the first reflective layer RL1, the second reflective layer RL2, and the third reflective layer RL3 covering the side surfaces of the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 can also have an inverted conical shape. Therefore, the light emitted from the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 can be reflected by the first reflective layer RL1, the second reflective layer RL2, and the third reflective layer RL3 and output towards the optical functional layer LFL more efficiently.

[0143] Figure 9 It shows along Figure 4 The line I1-I1' intercepted Figure 4 A schematic cross-sectional view of the fifth embodiment of the pixels.

[0144] The following describes the reference. Figure 5 The differences compared to the first embodiment described above can be used to replace parts that can be omitted.

[0145] refer to Figure 4 and Figure 9 References can be omitted. Figure 5 The description includes a first element insulating layer IIL1, a second element insulating layer IIL2, and a third element insulating layer IIL3, as well as a first reflective layer RL1, a second reflective layer RL2, and a third reflective layer RL3. In this configuration, the side surfaces of the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 can directly contact the first passivation layer PSV1.

[0146] In an implementation, the groove GR can be configured to pass through the second passivation layer PSV2, the common electrode CE, and the first passivation layer PSV1 in a direction opposite to the third-direction DR3.

[0147] In this implementation, the first distance D1 from the lower surface of the groove GR to the upper surface of the pixel circuit layer PCL on the third-direction DR3 can be smaller than the second distance D2 from the upper surface of the pixel circuit layer PCL to the upper surface of the first auxiliary electrode AUXE1 on the third-direction DR3. In this case, the third light L3 emitted from the first light-emitting element LD1 toward the first passivation layer PSV1 can be reflected by the reflective partition wall RPW filling the groove GR. Therefore, light mixing between adjacent sub-pixels can be prevented. For example, the reflective partition wall RPW can also be used as a reference. Figure 5 The first reflective layer RL1, the second reflective layer RL2, and the third reflective layer RL3 are described.

[0148] Figure 10 It shows along Figure 4 The line I1-I1' intercepted Figure 4 A schematic cross-sectional view of the sixth embodiment of the pixels.

[0149] The following describes the reference. Figure 9 The differences compared to the fifth embodiment described above can be replaced with the content described above, and the parts that can be omitted in the description can be replaced with the content described above.

[0150] refer to Figure 4 and Figure 10 The recess GR can expose the upper surface of the pixel circuit layer PCL. The reflective partition wall RPW can be configured to fill the recess GR. Therefore, the reflective partition wall RPW can more effectively prevent light mixing between adjacent sub-pixels.

[0151] Figures 11 to 15 This is a schematic plan view showing a reflective partition wall according to an embodiment of the present disclosure.

[0152] refer to Figures 11 to 15 In the plan view, the reflective partition wall RPW can have various shapes to correspond to the arrangement of the light-emitting elements LD1, LD2 and LD3 in the plan view.

[0153] The reflective opening ROP defined in the reflective partition wall RPW can be configured to correspond to the arrangement of light-emitting elements LD1, LD2, and LD3 in the plan view. For example, when the light-emitting elements LD1, LD2, and LD3 are arranged in a matrix in the plan view, the reflective partition wall RPW can have the following configuration in the plan view: Figure 11The shape shown is used. As another example, when the light-emitting elements LD1, LD2, and LD3 are arranged in a shape other than a matrix in a planar view, the reflective partition wall RPW can have the shape shown. Figures 12 to 15 The various shapes shown correspond to the arrangement of the light-emitting elements LD1, LD2, and LD3 in the plan view.

[0154] In a plan view, the reflective opening ROP defined within the reflective partition wall RPW can have various shapes. For example, the reflective opening ROP can have the following shapes in a plan view: Figure 11 and Figure 12 The quadrilateral shape shown. As another example, the reflective opening ROP can be represented in a plan view as follows. Figure 13 The circle shown. As another example, the reflective opening ROP can have a planar view as shown. Figure 14 and Figure 15 The polygonal shape shown.

[0155] Figure 16 This is a block diagram illustrating a display system according to an embodiment.

[0156] refer to Figure 16 The display system 1000 may include a processor 1100 and a display device 1200.

[0157] The processor 1100 can perform various tasks and calculations. In embodiments, within the spirit and scope of this disclosure, the processor 1100 may include an application processor, a graphics processor, a microprocessor, a central processing unit (CPU), etc. The processor 1100 can be connected to other components of the display system 1000 via a bus system to control those other components.

[0158] Processor 1100 can send image data IMG and control signal CTRL to display device 1200. Display device 1200 can display an image based on image data IMG and control signal CTRL. Display device 1200 can be similar to a reference... Figure 1 The display device DD is described in the configuration. In this case, the image data IMG and the control signal CTRL can be set to... Figure 1 The input image data is IMG and the control signal is CTRL.

[0159] Display system 1000 may include computing systems that provide image display capabilities, such as smartwatches, mobile phones, smartphones, portable computers, tablet PCs, watch phones, vehicle displays, smart glasses, portable multimedia players (PMPs), navigation devices, and ultra-mobile personal computers (UMPCs). Display system 1000 may include at least one of head-mounted display (HMD) devices, virtual reality (VR) devices, mixed reality (MR) devices, and augmented reality (AR) devices.

[0160] Figure 17 and Figure 18 It is shown Figure 16 A schematic 3D diagram illustrating an application example of the display system.

[0161] refer to Figure 17 , Figure 16 The display system 1000 can be applied to the smart glasses 2000. The smart glasses 2000 can be a wearable electronic device worn on a user's head. For example, the smart glasses 2000 can be a wearable device for augmented reality.

[0162] The smart glasses 2000 may include a frame 2100 and a lens unit 2200. The frame 2100 may include a housing 2110 supporting the lens unit 2200 and temple units 2120 for the user to wear. The temple units 2120 may be hinged to the housing 2110 and may be folded or unfolded relative to the housing 2110.

[0163] The battery, touchpad, microphone, camera, etc., can be built into the frame 2100. The projector that outputs light, the processor that controls the light signal, etc., can be built into the frame 2100.

[0164] The lens unit 2200 may include optical components that transmit or reflect light. For example, within the spirit and scope of this disclosure, the lens unit 2200 may include glass, transparent synthetic resin, etc.

[0165] To enable the user's eyes to recognize visual information, the lens unit 2200 can reflect an image formed by the light signal transmitted from the projector of the lens frame 2100 through its rear surface (e.g., the surface facing the user's eyes). For example, the user can recognize visual information such as time and date displayed on the lens unit 2200. In this case, the projector and / or lens unit 2200 can be a display device. The display device 1200 can be applied to the projector and / or lens unit 2200.

[0166] refer to Figure 18 , Figure 16 The display system 1000 can be applied to head-mounted display devices 3000.

[0167] The head-mounted display device 3000 can be a wearable electronic device that can be worn on a user's head. For example, the head-mounted display device 3000 can be a wearable device for virtual reality or mixed reality.

[0168] The head-mounted display device 3000 may include a headband 3100 and a display device housing 3200. The headband 3100 may be connected to the display device housing 3200. The headband 3100 may include a horizontal strap and / or a vertical strap for securing the head-mounted display device 3000 to a user's head. The horizontal strap may be configured to surround the side portion of the user's head, and the vertical strap may be configured to surround the upper portion of the user's head. However, the implementation is not limited thereto. For example, within the spirit and scope of this disclosure, the headband 3100 may be implemented in the form of eyeglass frames, helmets, etc.

[0169] Display device housing 3200 can accommodate display system 1000 and / or display device 1200.

[0170] Electronic devices can be at least one of the following: organic light-emitting display devices; inorganic light-emitting display devices; quantum dot light-emitting display devices; displays for portable electronic devices such as mobile phones, smartphones, tablet PCs, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs); and displays for televisions, notebooks, monitors, advertising panels, Internet of Things (IoT) devices, portable communication devices, smartphones, computer equipment, portable multimedia devices, portable medical devices, cameras, wearable devices, and home appliances.

[0171] Although described with reference to the above embodiments, it will be understood that those skilled in the art can make various modifications and changes to this disclosure without departing from the spirit and scope of the disclosure and the description in the following claims.

Claims

1. A display device, including: Pixel electrodes are disposed on the pixel circuit layer; The common electrode faces the pixel electrode; A light-emitting element, disposed between the pixel electrode and the common electrode, and comprising: A first semiconductor layer is connected to the pixel electrode. The second semiconductor layer is connected to the common electrode, and An active layer is disposed between the first semiconductor layer and the second semiconductor layer; A reflective layer covers the side surface of the light-emitting element; An insulating layer is disposed between the reflective layer and the light-emitting element; A first passivation layer is disposed between the pixel circuit layer and the common electrode; A second passivation layer is disposed on the common electrode; and The reflective wall, in the plan view, defines a reflective opening with a closed curved shape surrounding the light-emitting element. The reflective wall fills a groove that passes through the second passivation layer and the common electrode in the direction facing the pixel circuit layer.

2. The display device according to claim 1, wherein, The reflective wall is in direct contact with the common electrode.

3. The display device according to claim 1, wherein, The groove further penetrates the first passivation layer adjacent to the common electrode, and The groove exposes the upper surface of the pixel circuit layer.

4. The display device according to claim 1, further comprising: The light extraction portion is disposed on the second passivation layer, surrounded by the reflective opening in the plan view, and protrudes in a direction opposite to the direction facing the pixel circuit layer.

5. The display device according to claim 1, wherein, The reflective wall is spaced apart from the pixel electrode.

6. The display device according to claim 1, wherein, The reflective layer covers the side surface of the pixel electrode, and The insulating layer of the component is disposed between the pixel electrode and the reflective layer.

7. The display device according to claim 1, further comprising: An auxiliary electrode is disposed between the pixel electrode and the first semiconductor layer; The reflective wall is spaced apart from the auxiliary electrode.

8. The display device according to claim 1, wherein, The reflective wall comprises a material with a light transmittance of 5% or less, a light reflectance of 60% or more, and a resistance of 10Ω or less.

9. A display device, including: Pixel electrodes are disposed on the pixel circuit layer; The common electrode faces the pixel electrode; A light-emitting element, disposed between the pixel electrode and the common electrode, and comprising: A first semiconductor layer is connected to the pixel electrode. The second semiconductor layer is connected to the common electrode, and An active layer is disposed between the first semiconductor layer and the second semiconductor layer; A first passivation layer is disposed between the pixel circuit layer and the common electrode; A second passivation layer is disposed on the common electrode; and The reflective wall, in the plan view, defines a reflective opening with a closed curved shape surrounding the light-emitting element. The reflective wall fills a groove that passes through the second passivation layer, the common electrode, and the first passivation layer in the direction facing the pixel circuit layer.

10. Electronic devices, including: The processor provides the input image data; as well as The display device displays an image based on the input image. The display device includes: Pixel electrodes are disposed on the pixel circuit layer; The common electrode faces the pixel electrode; A light-emitting element is disposed between the pixel electrode and the common electrode, and includes a first semiconductor layer connected to the pixel electrode, a second semiconductor layer connected to the common electrode, and an active layer disposed between the first semiconductor layer and the second semiconductor layer; A reflective layer covers the side surface of the light-emitting element; An insulating layer is disposed between the reflective layer and the light-emitting element; A first passivation layer is disposed between the pixel circuit layer and the common electrode; A second passivation layer is disposed on the common electrode; and The reflective wall, in the plan view, defines a reflective opening with a closed curved shape surrounding the light-emitting element. The reflective wall fills a groove that passes through the second passivation layer and the common electrode in the direction facing the pixel circuit layer.

Images