Superconducting quantum computer, packaging structure and manufacturing method thereof

Abstract

The invention discloses a superconducting quantum computer, a packaging structure and a manufacturing method thereof, and belongs to the field of quantum equipment manufacturing. The packaging structure comprises a packaging box made of a metal material and a superconducting quantum chip packaged in the packaging box. The superconducting quantum chip comprises a substrate provided with a through hole, a first superconducting layer and a second superconducting layer which are formed on the front surface and the back surface of the substrate, and a superconducting filling body formed in the through hole. One end of the superconducting filling body is connected with the first superconducting layer, and the other end of the superconducting filling body is connected with the second superconducting layer. The first superconducting layer, the second superconducting layer and the superconducting filling body are integrally formed, and the second superconducting layer is in conductive contact with the inner bottom wall of the packaging box. According to the packaging structure, the superconducting quantum chip can be packaged with a higher cavity mode, so that the interference of the cavity mode on the bit frequency in the chip is avoided.

Description

Technical Field

[0001] This application belongs to the field of quantum information, especially the field of quantum device manufacturing. In particular, this application relates to a superconducting quantum computer, its packaging structure, and its manufacturing method. Background Technology

[0002] A superconducting quantum computer is a physical device that performs high-speed mathematical and logical operations, stores and processes quantum information in accordance with the laws of quantum mechanics. In a superconducting quantum computer, the superconducting quantum chip is the core component.

[0003] Due to the characteristics of their physical realization, superconducting quantum chips are quite sensitive to various types of noise. Therefore, they are usually encapsulated in packaging boxes. However, in actual implementation, superconducting quantum chips can still be adversely affected by noise in some situations. Summary of the Invention

[0004] This application provides an example of a superconducting quantum computer, a packaging structure, and a method for manufacturing the same. The packaging structure allows for the implementation of a superconducting quantum chip packaging scheme with higher cavity modes, thereby increasing the detuning between the cavity mode and the frequencies of the qubits in the chip, and thus reducing the impact of the cavity mode on the chip.

[0005] The solution presented in this application is implemented through the following steps.

[0006] In a first aspect, examples of this application disclose an encapsulation structure.

[0007] The packaging structure includes a metal enclosure and a superconducting quantum chip encapsulated within the enclosure. Furthermore, the superconducting quantum chip includes:

[0008] The substrate has a through-hole extending through the front and back sides of the substrate in the thickness direction;

[0009] A first superconducting layer is formed on the front side, and a second superconducting layer is formed on the back side;

[0010] A superconducting filler is formed in the through hole, one end of which is connected to the first superconducting layer and the other end of which is connected to the second superconducting layer.

[0011] The first superconducting layer, the second superconducting layer, and the superconducting filler are integrally formed, and the second superconducting layer is in conductive contact with the inner bottom wall of the encapsulation box.

[0012] According to some examples in this application, the superconducting filler is a solid cylinder or a hollow cylinder.

[0013] According to some examples of this application, the first superconducting layer, the second superconducting layer, and the superconducting filler are made of the same material, namely TiN, NbTiN, Al, or Ta.

[0014] According to some examples of this application, the first superconducting layer, the second superconducting layer, and the superconducting filler are all made of TiN material, and the resistance between the first superconducting layer and the superconducting filler is less than or equal to 200Ω; and / or, the first superconducting layer, the second superconducting layer, and the superconducting filler are all made of TiN material, and the resistance between the second superconducting layer and the superconducting filler is less than 200Ω.

[0015] In a second aspect, examples of this application disclose a method for manufacturing the aforementioned packaging structure.

[0016] The method includes: fabricating a superconducting quantum chip and encapsulating the superconducting quantum chip in a packaging box;

[0017] The methods for manufacturing superconducting quantum chips include:

[0018] A substrate with pre-formed through holes is supported in the vacuum chamber of the coating equipment using a support frame to ensure that the front and back sides of the substrate are exposed.

[0019] A coating is formed on the front and back sides of the substrate and the inner wall of the via by atomic layer deposition to form a first superconducting layer, a superconducting filler, and a second superconducting layer.

[0020] According to some examples of this application, the contact points between the support and the substrate are located around the perimeter of the substrate; or, the substrate is defined with concentric inner and outer ring regions, the inner ring region being configured as an operating area for transferring or moving the substrate by vacuum suction; the number of vias is multiple, and the distribution density of vias in the inner ring region is less than that in the outer ring region.

[0021] According to some examples of this application, the aspect ratio of the through hole is 2.4 to 5.6;

[0022] Alternatively, the diameter of the through-hole is 50 to 100 micrometers, and the depth of the through-hole is 260 ± 5 micrometers.

[0023] According to some examples of this application, the via has a first radius on the front side of the substrate and a second radius on the back side of the substrate, and the absolute value of the difference between the first radius and the second radius is not greater than 9 micrometers.

[0024] According to some examples of this application, the axis of the via is perpendicular to the front side of the substrate.

[0025] In a third aspect, examples of this application disclose a superconducting quantum computer including the aforementioned encapsulation structure or an encapsulation structure manufactured by implementing the aforementioned method.

[0026] In the above implementation scheme of this application, when the superconducting quantum chip is packaged into a packaging box, due to the structural design of the superconducting quantum chip, the ground planes on the front and back sides of the chip can be electrically connected to the packaging box, thereby achieving a common ground and increasing the cavity mode within the packaging box. Therefore, the distance between the cavity mode and the bit frequency in the chip is large, thereby reducing or even avoiding the impact on bit control and other operations. Attached Figure Description

[0027] To illustrate this more clearly, the accompanying drawings used in the description will be briefly introduced below.

[0028] Figure 1 This is a schematic diagram of the structure of the first type of superconducting quantum chip in this application example;

[0029] Figure 2 This is a schematic diagram of the structure of the second type of superconducting quantum chip in this application example;

[0030] Figure 3 This is a schematic diagram of the encapsulation structure in the example of this application;

[0031] Figure 4 A manufacturing process flow diagram of the packaging structure in the example of this application is disclosed.

[0032] Explanation of reference numerals in the attached figures:

[0033] 100-Superconducting quantum chip;

[0034] 201 - First superconducting layer; 202 - Second superconducting layer; 203 - Superconducting filler;

[0035] 300 - Superconducting quantum chip; 204 - Superconducting filler;

[0036] 400 - Package box; 401 - Spacer; 402 - Circuit board; 403 - Lead wire. Detailed Implementation

[0037] Superconducting quantum computing is currently the most advanced and best-developed solid-state quantum computing solution. The energy level structure of superconducting quantum circuits can be controlled by external electromagnetic signals, and the circuit design offers high controllability. Furthermore, thanks to existing mature integrated circuit processes and micro / nano fabrication technologies, superconducting quantum circuits possess scalability and advantages unmatched by other quantum bit physics systems.

[0038] A quantum chip based on superconducting quantum circuits includes superconducting circuit structures such as qubits and microwave resonant cavities. The qubits are two-level systems composed of a capacitor and a Josephson junction with nonlinear inductive properties.

[0039] In the aforementioned quantum bit system, there are various circuit structures with different functions around the quantum bits, such as readout resonant cavities and couplers for inter-quantum bit coupling connections.

[0040] The circuit structure also includes a drive control signal line (XY□ControlLine, also known as the xy control line or pulse modulation signal line) for performing XY rotation operations on the qubits. By applying a driving voltage signal to the circuit, the qubits can be excited by transitions; the voltage signal is associated with the qubits through capacitive coupling.

[0041] The circuit structure also includes a circuit structure for performing Z-rotation operations on the qubits, which is accomplished by a control signal line near the superconducting quantum interference device (squid); this is called the flux control line (Z□Control Line, also known as the z-control line or frequency control line). As mentioned above, the flux control line is arranged near the superconducting quantum interference device (squid), and its excitation current is inductively coupled to the superconducting quantum interference device (squid) through a magnetic field.

[0042] It should be noted that both flux control signal lines and drive control circuits can be used to control qubits, but their control methods and purposes are fundamentally different.

[0043] The driving control signal line applies a pulse to the quantum bit in the form of an electric field, which causes the energy level of the quantum bit to transition.

[0044] The signal transmitted via the flux-controlled signal line generates a magnetic field, which is applied to the squid region of the superconducting quantum interference device (SQID). Simultaneously, the magnetic flux passing through the SQID region causes a change in the squid's critical current. This change in critical current leads to a change in the frequency of the tunable qubit; that is, the frequency of the qubit can be controlled by the signal transmitted via the flux-controlled signal line.

[0045] When performing quantum computing, the frequency of the qubit is first adjusted to the working frequency (initial state creation) by using the magnetic flux control signal on the magnetic flux control signal line. Then, the quantum state control signal is applied to the qubit in the initial state by driving the control signal line to control the quantum state. Finally, the quantum state of the controlled qubit is read out by using a resonant cavity.

[0046] Specifically, the quantum state of a qubit can be determined by applying a readout detection signal (e.g., a microwave signal with a frequency of 4 GHz to 8 GHz) to the readout signal transmission line coupled to the resonant cavity, and then analyzing the readout feedback signal (the signal in response to the readout detection signal) output from the readout signal transmission line. The structures of the flux control signal line, drive control signal line, and readout signal transmission line can all adopt microwave transmission line structures, which will not be elaborated further here.

[0047] In summary, both the reading and control operations of qubits involve the transmission of various signals. Therefore, qubits are highly sensitive to a wide range of signals. Furthermore, a crucial property of qubits is their frequency. Quantum chips contain numerous qubits, and the frequencies of these qubits can be significantly different or even distinctly different.

[0048] As is known, when the frequency of a noise signal is close to or equal to that of a bit, it will severely affect bit operations, and thus adversely affect quantum computing.

[0049] Therefore, given that the quantum state of a qubit is easily corrupted by noise, its operating environment is quite demanding. In actual quantum computing device manufacturing, the quantum chip is installed inside a chip package. The package is equipped with corresponding signal ports that connect to the corresponding ports on the chip.

[0050] In practice, the applicant discovered that the packaging box may have a cavity pattern.

[0051] Specifically, cavity modes represent stable electromagnetic field distribution patterns formed when electromagnetic waves propagate and reflect within a closed or semi-closed space (cavity). These modes are linear, independent particular solutions of Maxwell's equations under specific boundary conditions, and they determine the resonant characteristics of the cavity.

[0052] The cavity mode determines the resonant frequency and quality factor Q of the microwave resonant cavity. Each mode has its specific resonant frequency, and when the frequency of the external electromagnetic wave matches this frequency, a standing wave can be formed in the cavity.

[0053] Generally, cavity modes can be divided into TE (transverse electric) modes and TM (transverse magnetic) modes. These two modes correspond to the distribution of electric and magnetic fields in specific directions, respectively. For example, the TE mode is characterized by an electric field Ez = 0, while the TM mode is characterized by a magnetic field Hz = 0. In addition, there are TEM (transverse electromagnetic) modes. TEM modes are common in transmission lines, but are special in cavities because the longitudinal components of both their electric and magnetic fields are zero.

[0054] In practical applications, the design of a resonant cavity needs to consider the mode's resonant frequency, quality factor Q, and field distribution. Furthermore, the size and shape of the resonant cavity directly affect the mode's characteristics and require careful selection during the design process to optimize performance.

[0055] Based on the above statements, the internal cavity of the packaging box used to encapsulate quantum chips also contains cavity modes. These cavity modes interact with the qubits. Therefore, when the frequency of the cavity mode is close to or equal to the frequency of the qubit, it can lead to a significant negative impact on bit readout and control operations.

[0056] Therefore, in some attempts, the frequency of the cavity mode is changed by adjusting the shape and size of the cavity in the package. For example, taking a cuboid cavity shape as an example, the frequency can be changed by altering its length and width.

[0057] Specifically, the cavity mode frequency can be increased to increase the distance between it and the frequency of the bits in the chip, thereby avoiding mutual interference. Increasing the cavity mode frequency provides greater operational flexibility.

[0058] Based on this understanding, the applicant discloses an encapsulation structure in this application, see reference. Figure 1 , Figure 2 and Figure 3 .

[0059] The packaging structure mainly includes a package 400 and a superconducting quantum chip 100. The chip and the package 400 are connected for communication via appropriate wiring. For example, they are connected via a signal port by bonding with a lead 403. The packaging structure also includes a circuit board 402. The circuit board 402 has holes for placing the chip; the chip is placed on the circuit board 402, and the circuit board 402 and the chip are connected via leads 403 to achieve signal communication. Figure 3 As shown.

[0060] Specifically, the superconducting quantum chip 100 includes a substrate, a first superconducting layer 201, a second superconducting layer 202, and a superconducting filler 203, such as Figure 1 and Figure 2 .

[0061] The substrate has vias formed therein. These vias extend along the thickness direction of the substrate and penetrate both the upper (front) and lower (back) surfaces. The substrate can be of various forms, such as silicon, germanium, gallium arsenide, silicon carbide, or gallium nitride. Currently, in superconducting quantum chips 100, the substrate can be selected, for example, as high-resistivity silicon (with a resistivity of 5000 Ω / cm or higher, such as 10T). 4 Ω / cm), or sapphire.

[0062] In terms of the cross-sectional shape of a through hole, a through hole is a cylindrical hole with a circular cross-sectional shape, or a prism hole with a polygonal cross-sectional shape (such as a regular hexagon).

[0063] Preferably, the via extends perpendicularly to both the front and back sides. That is, the axis of the via is parallel to the thickness direction of the substrate. In other words, the axis of the via is perpendicular to the front side of the substrate. Alternatively, appropriately, considering the difficulty of fabrication, the perpendicularity of the via can be adjusted to some extent. For example, there can be a certain angle between the axis of the via and the thickness direction of the substrate, such as within 2 degrees.

[0064] In other examples, the through hole can be a straight through hole; that is, the diameter is the same throughout the axial direction of the through hole. Alternatively, the through hole can be an angled through hole; for example, the cross-sectional shape of the through hole along the axial direction is a trapezoidal structure.

[0065] In an optional specific example, the via has a first radius on the front side of the substrate and a second radius on the back side of the substrate, and the absolute value of the difference between the first radius and the second radius is no greater than 9 micrometers.

[0066] Furthermore, in some examples, the number of vias can also be designed. For example, the number of vias can be one, two, three, or even more. Further, for cases with multiple vias, the distribution of these vias can also be designed. For example, all vias on the substrate can be grouped by region, such that some vias are located in one region, while the remaining vias are located in another region.

[0067] For example, the substrate is defined with concentric inner and outer ring regions. There are multiple vias, divided into two groups; each group contains the same number of vias (this may differ in other examples). Furthermore, the via density in the inner ring region is less than (or vice versa) the via density in the outer ring region.

[0068] By grouping and distributing vias by region, the placement of other components within the chip can be facilitated in some examples. For instance, in areas with higher via density, less space is reserved for other components; conversely, in areas with lower via density, more space is reserved for other components, allowing for easier placement and reducing the difficulty of their layout, as well as potential signal interference issues when placed in confined spaces due to limited space.

[0069] In addition, when multiple through holes exist, the shape and structural dimensions of each through hole can be designed to be the same, or different as needed. Designing all through holes to be the same can reduce the difficulty of manufacturing processes; while designing them to have different shapes and / or structural dimensions can meet different needs.

[0070] The above content mainly discussed the relevant characteristics of the substrate. The following section will explain the superconducting structure formed on the substrate surface.

[0071] As mentioned above, the superconducting structure in the encapsulation structure includes a first superconducting layer 201, a second superconducting layer 202, and a superconducting filler 203.

[0072] The first superconducting layer 201 is formed on the front side of the substrate; the second superconducting layer 202 is formed on the back side of the substrate. A superconducting filler 203 is filled into the via; and one end of the superconducting filler 203 is connected to the first superconducting layer 201, and the other end of the superconducting filler 203 is connected to the second superconducting layer 202.

[0073] Specifically, the first superconducting layer 201, the second superconducting layer 202, and the superconducting filler 203 are integrally formed. That is, the first superconducting layer 201, the second superconducting layer 202, and the superconducting filler 203 are prepared in one piece to avoid the formation of an oxide layer at the junction of the superconducting filler and the first or second superconducting layer, so as to ensure conductivity (the continuity resistance is sufficiently small, such as 200Ω as described below).

[0074] It is understood that the first superconducting layer 201, the second superconducting layer 202, and the superconducting filler 203 can be made of the same material, or they can have the same composition but with appropriate variations in the content of specific components. For example, the first superconducting layer 201, the second superconducting layer 202, and the superconducting filler 203 can be made of the same material, specifically TiN (titanium nitride), NbTiN (niobium titanium nitride), Al (aluminum), or Ta (tantalum). Alternatively, in other instances, such as applications using non-superconducting quantum computers, the first superconducting layer 201, the second superconducting layer 202, and the superconducting filler 203 can be selected from superconductors of other compositions, such as elemental, alloy, or compound superconductors.

[0075] From a usage perspective, the second superconducting layer 202 formed on the back side of the substrate makes conductive contact with the inner bottom wall of the package 400 (it can be understood that the package 400 is made of a metal material, such as aluminum). Therefore, it can be understood that the first superconducting layer 201 and the superconducting filler 203 are also correspondingly conductively connected to the inner bottom wall of the package 400. To achieve conductive connection between the chip and the package 400, a pad 401 can be provided inside the package 400, or a bump can be provided on the inner bottom wall of the package 400. The chip is supported by the pad 401 and the bump. See [reference needed]. Figure 3 .

[0076] Because the solution in this application example connects the superconducting layers (i.e., the first superconducting layer 201 and the second superconducting layer 202) on the front and back sides of the chip through a superconducting filler 203, and makes conductive contact between the second superconducting layer 202 and the package box through a pad, it avoids making conductive contact between the chip and the package box from the front, thus preventing damage to the components on the front side of the chip from being squeezed. Furthermore, since there are many components on the front side of the chip, making conductive contact between the superconducting layer on the front side of the chip and the package box would present significant alignment difficulties and complexity. The solution in this application example eliminates contact between the chip and the package box from the front side, thereby avoiding the aforementioned problems.

[0077] In particular, the superconducting quantum chips in this application can also be stacked. That is, multiple superconducting quantum chips can be stacked layer by layer to form a multi-chip stacked structure. Using this scheme, the upper and lower surfaces of different layers of chips are connected, enabling signal transmission across multiple stacked chips. This allows different circuits or components distributed in a plane to be distributed across different layers of chips, resulting in fewer circuits and components in any given layer without excessive crowding.

[0078] The first superconducting layer 201 and the second superconducting layer 202 are constructed, for example, in the form of thin films, and therefore have relatively small thickness dimensions. The superconducting filler 203 can be a hollow cylindrical structure (in other examples, the superconducting quantum chip 300 in the encapsulation structure can also be a solid cylinder, i.e., the superconducting filler 204; and can be achieved by first fabricating a hollow cylinder and then filling it with a solid structure), such as... Figure 1 and Figure 2 As shown.

[0079] The hollow cylinder has a relatively thin wall thickness. For example, the wall thickness of the hollow cylinder can be the same as the thickness of the first superconducting layer 201; or, the wall thickness of the hollow cylinder can be the same as the thickness of the second superconducting layer 202. Similarly, the thicknesses of the first superconducting layer 201 and the second superconducting layer 202 can be the same, or in other examples, they can be different.

[0080] Specifically, the first superconducting layer 201, the second superconducting layer 202, and the superconducting filler 203 can all be made of TiN (titanium nitride), and the resistance between the first superconducting layer 201 and the superconducting filler 203 can be controlled to be less than or equal to 200Ω. Similarly, the first superconducting layer 201, the second superconducting layer 202, and the superconducting filler 203 can all be made of TiN, and the resistance between the second superconducting layer 202 and the superconducting filler 203 is below 200Ω. Preferably, the first resistance between the first superconducting layer 201 and the superconducting filler 203 is the same as the second resistance between the second superconducting layer 202 and the superconducting filler 203.

[0081] The foregoing primarily discussed the encapsulation structure. As an example of its application, this application also discloses a superconducting quantum computer with the aforementioned encapsulation structure. Furthermore, the superconducting quantum computer may also include a measurement and control system, etc.

[0082] To facilitate the implementation of the example packaging structure, a method for manufacturing the above packaging structure is also provided below.

[0083] The manufacturing method includes: manufacturing a superconducting quantum chip 100, and encapsulating the superconducting quantum chip 100 in a packaging box 400.

[0084] The packaging box 400 can adopt an existing packaging box 400 structure. The method for manufacturing the superconducting quantum chip 100 can employ micro-nano fabrication techniques. Specifically, see [link to relevant documentation]. Figure 4 The method for manufacturing the superconducting quantum chip 100 also includes the following steps.

[0085] Step S101: Use a support to support the substrate with pre-formed through holes in the vacuum chamber of the coating equipment to ensure that the front and back sides of the substrate are exposed.

[0086] Step S102: A film is formed on the front side, back side and inner wall of the via of the substrate by atomic layer deposition to form a first superconducting layer 201, a superconducting filler 203 and a second superconducting layer 202.

[0087] In step S101 above, the contact points between the support structure and the substrate can be designed so that they are located around the perimeter of the substrate. For example, the support can be a single, integrated structure with four support portions, through which it contacts the chip substrate. Alternatively, there can be four independent supports, each supporting the substrate separately.

[0088] Considering the handling or movement of the substrate between different devices, concentric inner and outer ring regions can be defined on the substrate. The inner ring region is configured as an operating area for transferring or moving the substrate via vacuum suction (e.g., using a chuck). To facilitate vacuum suction operations, the number of vias in the substrate can be multiple, and the via density in the inner ring region is less than that in the outer ring region. That is, fewer vias are set in the vacuum suction operating area.

[0089] For example, multiple chips can be planned on a substrate and distributed across multiple regions within the substrate. For instance, multiple chips can be arranged in a cross-sectional array. In this way, some or all chips in the aforementioned inner region can have fewer or no vias to facilitate adsorption during manufacturing. Simultaneously, some or all chips in the aforementioned outer region can have one or more vias as needed to provide space for forming a superconducting filler that connects the superconducting layers on the front and back sides of the chip.

[0090] One of the methods for creating vias on a substrate can be achieved using etching techniques such as deep silicon etching machines or plasma cutting etching machines.

[0091] The superconducting layer can be fabricated using ALD (atomic layer deposition). During deposition, the substrate is elevated, leaving some areas suspended. Therefore, the heating method for the ALD equipment can be selected as thermal radiation heating, and the temperature can be controlled and filtered to achieve the same heating effect as contact heating.

[0092] Furthermore, atomic layer deposition can also be replaced by plasma-enhanced atomic layer deposition. This method offers the following advantages.

[0093] Surface cleaning: Plasma treatment can effectively clean the substrate surface, removing impurities such as surface oxides and organic residues, making the substrate surface purer and conducive to film growth and adhesion.

[0094] Enhanced reactivity: Plasma energy can activate precursor molecules and promote their adsorption and reaction on the surface, thereby increasing the reaction rate and efficiency, which helps to achieve precise control of atomic layer deposition.

[0095] The fabrication of the packaging structure (especially the superconducting quantum chip 100) provided in the embodiments of this application may require the deposition of one or more materials, such as superconductors, dielectrics and / or metals.

[0096] Depending on the materials chosen, these materials can be deposited using deposition processes such as chemical vapor deposition, physical vapor deposition (e.g., evaporation or sputtering), epitaxial techniques, and other deposition processes, exemplary of which include ion beam assisted deposition (IBAD), vacuum evaporation, molecular beam epitaxy (MBE), pulsed laser deposition (PLD), chemical vapor deposition (CVD), sol-gel, and magnetron sputtering.

[0097] The processes described in this application may require the removal of one or more materials from a device during the manufacturing process. Depending on the material to be removed, the removal process may include, for example, wet etching, dry etching, or lift-off processes. The materials forming the circuit elements herein can be patterned using known lithographic techniques (e.g., photolithography or electron beam lithography).

[0098] For the sake of brevity, conventional techniques related to the fabrication of semiconductor and / or superconducting devices and integrated circuits (ICs) may or may not be described in detail herein. Furthermore, various tasks and process steps described herein may be incorporated into more comprehensive procedures or processes with additional steps or functionalities not described in detail herein. In particular, the various steps in the fabrication of semiconductor and / or superconducting devices and semiconductor / superconductor-based ICs are well-known; therefore, for the sake of brevity, many conventional steps will be mentioned only briefly or will be omitted entirely without providing well-known process details.

[0099] The embodiments described above with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0100] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, one or more embodiments have been described above with reference to the accompanying drawings. Throughout the description, similar reference numerals are used to denote similar components. In the foregoing description, numerous specific details have been set forth for illustrative purposes in order to provide a more thorough understanding of one or more embodiments. However, it will be apparent that one or more embodiments may be practiced in various circumstances without these specific details, and the embodiments may be combined with and referenced to each other without contradiction.

[0101] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in sequences other than those illustrated or described herein.

[0102] Furthermore, the terms “comprising” and “having”, and any variations thereof, are intended to cover non-exclusive inclusion, such that a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units that are explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to such process, method, product, or apparatus.

[0103] The above description of the structure, features and effects of this application is based on the embodiments shown in the drawings. The above are only preferred embodiments of this application. However, this application does not limit the scope of implementation to what is shown in the drawings. Any changes made in accordance with the concept of this application, or modifications to equivalent embodiments, that do not exceed the spirit covered by the specification and drawings, should be within the protection scope of this application.

Claims

1. A packaging structure comprising a metal packaging box and a superconducting quantum chip packaged within the packaging box, characterized in that, The superconducting quantum chip includes: The substrate has a through-hole extending through the front and back sides of the substrate in the thickness direction; A first superconducting layer is formed on the front side, and a second superconducting layer is formed on the back side; A superconducting filler formed in a through-hole, one end of which is connected to a first superconducting layer and the other end of which is connected to a second superconducting layer; The first superconducting layer, the second superconducting layer, and the superconducting filler are integrally formed, and the second superconducting layer is in conductive contact with the inner bottom wall of the encapsulation box.

2. The packaging structure according to claim 1, characterized in that, The superconducting filler is a solid cylinder or a hollow cylinder.

3. The packaging structure according to claim 1 or 2, characterized in that, The first superconducting layer, the second superconducting layer, and the superconducting filler are made of the same material, namely TiN, NbTiN, Al, or Ta.

4. The packaging structure according to claim 1, characterized in that, The first superconducting layer, the second superconducting layer, and the superconducting filler are all made of TiN material, and the resistance between the first superconducting layer and the superconducting filler is less than or equal to 200Ω; And / or, the first superconducting layer, the second superconducting layer, and the superconducting filler are all made of TiN material, and the resistance between the second superconducting layer and the superconducting filler is below 200Ω.

5. A method for manufacturing the packaging structure according to any one of claims 1 to 4, characterized in that, The method includes: manufacturing the superconducting quantum chip, and encapsulating the superconducting quantum chip in the encapsulation box; The method for manufacturing the superconducting quantum chip includes: A substrate with pre-formed through holes is supported in the vacuum chamber of the coating equipment using a support frame to ensure that the front and back sides of the substrate are exposed. Atomic layer deposition is used to form a coating on the front and back sides of the substrate and the inner wall of the via, thereby forming the first superconducting layer, the superconducting filler and the second superconducting layer.

6. The method according to claim 5, characterized in that, The contact point between the support and the substrate is located around the perimeter of the substrate; Alternatively, the substrate may define concentric inner and outer ring regions, the inner ring region being configured as an operating area for transferring or moving the substrate by vacuum suction; the number of vias may be multiple, with the via density in the inner ring region being less than the via density in the outer ring region.

7. The packaging structure according to claim 5 or 6, characterized in that, The aspect ratio of the through hole is 2.4 to 5.6; Alternatively, the diameter of the through hole is 50 micrometers to 100 micrometers, and the depth of the through hole is 260 ± 5 micrometers.

8. The packaging structure according to claim 5, characterized in that, The via has a first radius on the front side of the substrate and a second radius on the back side of the substrate, and the absolute value of the difference between the first radius and the second radius is no greater than 9 micrometers.

9. The packaging structure according to claim 5 or 8, characterized in that, The axis of the through hole is perpendicular to the front side of the substrate.

10. A superconducting quantum computer, characterized in that, Includes the packaging structure as described in any one of claims 1 to 4, or a packaging structure manufactured by implementing the method described in any one of claims 5 to 9.

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