Fin type vertical interposer fan-out packaging structure and method

Abstract

The invention provides a fin-type vertical interposer fan-out packaging method, which belongs to the technical field of semiconductor packaging and comprises the steps of fin-type vertical structure preparation, glass substrate processing, conductive layer construction, fin-type vertical structure installation, flip chip bonding, packaging, top layer structure arrangement and the like. A PI layer is formed through spin coating, and a copper wiring layer and a copper column are manufactured through copper electroplating or PVD; selecting a glass wafer as a temporary carrier, and constructing a conductive layer containing three passivation layers and two metal layers; after the fin type vertical structure and the flip chip are accurately installed on the conductive layer, urea formaldehyde resin is adopted for packaging, and the surface is ground; and finally preparing a top layer structure, removing the glass substrate, and implanting BGA balls. According to the method, a high-aspect-ratio TSV complex process is avoided, the process difficulty and the failure risk are reduced, the production yield is improved, and the requirements of heterogeneous integration for high bandwidth and high I / O density are met.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of semiconductor packaging, in particular to an advanced fan-out package structure applied to 2.5D / 3D integration and a manufacturing method, in particular to a fan-out package structure combining a re-distribution layer (RDL) and a fin-type vertical interconnection interposer. BACKGROUND

[0002] With the continuous reduction of the size of semiconductor chips, 2.5D / 3D stacked packaging technology has emerged. This technology stacks multiple dies on a substrate, such as the CoWoS technology, which interconnects logic chips and high-bandwidth memory (HBM) through an interposer, effectively reducing space occupation, power consumption and cost. In such a structure, the interposer is a key component for integrating and vertically interconnecting electrical signals between different chips.

[0003] Traditional 2.5D packaging technology generally uses through-silicon via (TSV) technology to make vertical interconnections in the interposer. The TSV process is complex, including deep hole drilling on a silicon wafer, depositing a dielectric layer and a barrier layer, electroplating a conductive material (such as copper), and chemical mechanical polishing. Although TSV technology can achieve high-density vertical interconnections (such as fabricating 100,000 to 1,000,000 TSVs in an area of 1 square millimeter), it has inherent technical difficulties and cost problems: 1. High process difficulty: In the vertical direction, it is extremely challenging to control the uniformity of the upper and lower critical dimensions of the deep hole. The subsequent copper electroplating filling process, especially at the bottom of the hole, is prone to defects, resulting in a high failure rate. The most advanced silicon etching equipment also cannot break through the limitation of micron-level width deep hole etching, and the filling depth is limited.

[0004] 2. High cost: The special materials, equipment and maintenance costs required for TSV deep hole electroplating process are much higher than those of conventional electroplating process, with a total cost of about 2-3 times that of general electroplating. Even in large-scale production on a 12-inch wafer, the unit cost is still significantly higher than that of conventional electroplating. SUMMARY

[0005] The purpose of the application is to overcome the above-mentioned defects of the existing TSV interposer technology and provide a fan-out package structure and method combining RDL and fin-type vertical interconnection interposer.

[0006] The purpose of the application is achieved by the following technical solutions: A fin-type vertical interposer fan-out packaging method, comprising the following steps: S1, preparing a fin-type vertical structure, specifically comprising: S11, selecting a silicon wafer of appropriate specification as a base material, and forming a first PI layer on the surface of the silicon wafer by spin coating; S12. On the surface of the first PI layer, a copper layer is formed by copper electroplating or physical vapor deposition, and a pattern of interconnection patterns is defined on the copper layer by photolithography to form a copper wiring layer. S13. Cover the copper layer with a photoresist layer, form an opening on the photoresist layer corresponding to the position of the copper pillar through a photolithography step, and electroplate copper at the opening to form several copper pillars, with the copper pillars corresponding to the ports of the copper wiring layer. S14. A second PI layer is formed on the surface of the copper layer and copper pillar by spin coating, and surface acoustic wave process is introduced to suppress high frequency noise to obtain a multi-layer electroplated board. A fin-type vertical structure is obtained by vertical cutting. S2. Glass substrate preparation and conductive layer construction, specifically including: selecting a glass wafer with good flatness as a temporary carrier, cleaning it to form a glass substrate; spin-coating a temporary bonding adhesive on the surface of the glass substrate to form a temporary bonding adhesive layer; preparing a conductive layer on the glass substrate, the conductive layer consisting of 3 passivation layers and 2 metal layers, the passivation layers using polyimide material, and the metal layers forming interconnect lines by electroplating copper or sputtering aluminum. S3. The mounting and flip-chip bonding of the fin vertical structure specifically includes: screen printing solder paste on the conductive layer surface to form pads; vertically placing the fin vertical structure on the conductive layer pads to ensure close contact between the copper layer on the fin vertical structure and the metal layer on the conductive layer; placing the flip chip at the corresponding position on the conductive layer and achieving bump bonding between the flip chip and the conductive layer through reflow soldering. S4, Fin Vertical Structure and Flip Chip Packaging, specifically includes: selecting urea-formaldehyde resin as the packaging material, mixing it to form urea-formaldehyde resin adhesive; using dispensing or spraying methods to cover the urea-formaldehyde resin adhesive onto the conductive layer surface, fin vertical structure and flip chip, and curing to form a UF packaging layer. S5, UF package layer surface treatment and top layer structure setting, specifically including: fine grinding of the UF package layer surface to expose the copper layer on the fin vertical structure; preparation of a 3P2M top layer structure on the ground UF package layer surface, the top layer structure using 3 layers of copper and 2 layers of dielectric alternately stacked, and achieving reliable conduction with the exposed copper layer on the fin vertical structure through thermo-press bonding and other methods. S6. Glass substrate removal and BGA ball implantation, specifically including: according to the characteristics of the temporary bonding adhesive layer, the temporary bonding adhesive layer is activated by heating or ultraviolet light irradiation to achieve separation of the glass substrate and the wafer; the BGA balls are precisely implanted into the designated position at the bottom of the conductive layer using a ball implantation machine.

[0007] As a further improvement to one embodiment of the invention, in step S1 of preparing the fin-type vertical structure, the copper layer is formed by either copper electroplating or physical vapor deposition, and the copper pillars are formed at the opening of the photoresist layer by copper electroplating.

[0008] As a further improvement to one embodiment of the invention, in step S2 of preparing the glass substrate and constructing the conductive layer, the three passivation layers of the conductive layer are made of polyimide material and are covered layer by layer by spin coating, and the two metal layers form interconnect lines by electroplating copper or sputtering aluminum.

[0009] As a further improvement to one embodiment of the invention, in step S4 of mounting the fin-type vertical structure and bonding the flip chip, reliable bonding between the flip chip and the conductive layer bumps is achieved by precisely controlling the temperature profile of the reflow soldering equipment.

[0010] A fin-type vertical interposer fan-out package structure is fabricated using the packaging method described above. Its core component is a fin-type vertical interconnect interposer layer, which contains multiple fin-type vertical structures. A top layer structure and a conductive layer are respectively disposed on the upper and lower end faces, and a BGA ball is disposed at the bottom.

[0011] As a further improvement to one embodiment of the invention, the fin-type vertical structure is distributed in a regular or specific arrangement to provide a three-dimensional and efficient channel for signal transmission; the top layer structure adopts a 3P2M structure with 3 layers of copper and 2 layers of dielectric alternately stacked, and the conductive layer is composed of 3 layers of passivation layer and 2 layers of metal layer, which are precisely connected to the copper layer in the fin-type vertical structure.

[0012] As a further improvement to one embodiment of the invention, the BGA ball is precisely implanted into a designated position at the bottom of the conductive layer using a ball-planting machine, serving as a connection bridge between the packaging structure and the external circuit, thereby achieving efficient electrical interconnection between the packaging structure and the external system.

[0013] The above technical solution offers the following advantages: By employing planar copper wiring technology to fabricate a fin-type vertical structure and applying this fin-type vertical structure 1 to an interposer fan-out package structure, the complex and challenging process steps of deep-hole etching, dielectric / barrier layer deposition, and deep-hole electroplating filling for high aspect ratio TSVs are completely avoided. This significantly reduces process complexity and potential failure risks, thereby improving production yield. Combined with RDL technology, this invention enables high-density electrical interconnection in both horizontal and vertical directions while providing excellent fan-out capability, meeting the demands of heterogeneous integration for high bandwidth and high I / O density. Attached Figure Description

[0014] To more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings in the following description are merely exemplary, and those skilled in the art can derive other embodiments based on the provided drawings without creative effort.

[0015] The structures, proportions, sizes, etc. shown in this specification are only used to complement the content disclosed in the specification for those skilled in the art to understand and read, and are not intended to limit the conditions under which the invention can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportional relationships, or adjustments to the size should still fall within the scope of the technical content disclosed in the invention, provided that they do not affect the effects and purposes that the invention can produce.

[0016] Figure 1 A flowchart provided for the invention.

[0017] Figure 2 This is a schematic diagram of the fabrication process of the fin-type vertical structure in this invention.

[0018] Figure 3 This is a schematic diagram of the fin-type vertical interposer fan-out packaging structure in this invention.

[0019] In the picture: 1. Fin-type vertical structure; 11. Silicon wafers; 12. First PI layer; 13. Copper layer; 14. Copper pillar; 15. Second PI layer; 2. Glass substrate; 3. Bonding adhesive layer; 4. Conductive layer; 5. Flip-chip; 6. UF encapsulation layer; 7. Top-level structure; 8. BGA ball. Detailed Implementation

[0020] In this invention, unless otherwise stated, directional terms such as "upper," "lower," "top," and "bottom" are generally used in relation to the direction shown in the accompanying drawings, or in relation to the vertical, perpendicular, or gravitational direction of the component itself; similarly, for ease of understanding and description, "inner" and "outer" refer to the inner and outer contours of each component itself, but the above directional terms are not used to limit the invention.

[0021] First embodiment, such as Figure 1 and Figure 2 As shown, a fin-type vertical interposer fan-out packaging method includes the following steps: Step 1: Prepare the fin-type vertical structure, specifically including: Step 11: Select a silicon wafer 11 of appropriate specifications as the substrate material, and then form the first PI layer 12 (polyimide layer) on the surface of the silicon wafer 11 by spin coating. Step 12: Forming the copper layer and interconnect wiring: A copper layer 13 is formed on the surface of the first PI layer 12 using copper electroplating or physical vapor deposition (PVD). If copper electroplating is used, the silicon wafer 11 with the first PI layer 12 is placed as the cathode in an electroplating solution containing copper ions. By applying a suitable current, copper ions are reduced and deposited on the surface of the first PI layer 12 to form the copper layer 13. If physical vapor deposition (PVD) is used, copper atoms are deposited on the surface of the first PI layer 12 under vacuum by heating a copper target to evaporate it, forming the copper layer 13. Then, using photolithography, an interconnect pattern is defined on the copper layer 13 to form a copper wiring layer.

[0022] Step 13: Fabrication of copper pillars: A photoresist layer is deposited on the copper layer 13. Through photolithography steps such as exposure and development, openings corresponding to the positions of the copper pillars are formed on the photoresist layer. Under the protection of the photoresist layer, copper pillars 14 are formed at the openings by electroplating, and the copper pillars 14 correspond to the ports of the copper wiring layer. After the copper pillars 14 are fabricated, the photoresist layer is stripped using a suitable solvent.

[0023] Step 14: Forming the second PI layer and subsequent processing: A second PI layer 15 is formed on the surfaces of copper layer 13 and copper pillar 14 by spin coating. After the second PI layer 15 is completed, a surface acoustic wave (SAW) process is introduced to suppress high-frequency noise introduced by the copper wiring layer. This yields a multilayer electroplated board. The multilayer electroplated board is then vertically cut to obtain the desired fin-type vertical structure 1.

[0024] Step 2, glass substrate preparation and conductive layer construction, are detailed below: A glass wafer with good flatness and no obvious defects is selected as a temporary carrier. Its surface is cleaned to remove any dust, impurities, etc., and then a glass substrate 1 is formed.

[0025] By spin coating, an appropriate amount of temporary bonding adhesive is evenly dropped onto the surface of the glass substrate 2. By setting a suitable rotation speed and time, the temporary bonding adhesive is evenly spread on the surface of the glass substrate 2 to form a temporary bonding adhesive layer 3.

[0026] A conductive layer 4 is fabricated on the prepared glass substrate 2. This conductive layer 4 consists of three passivation layers (3P) and two metal layers (2M). For the three passivation layers, polyimide (PI) material can be selected. A spin-coating method is used to coat the copper wiring layer by layer, providing mechanical protection, insulation, and stress buffering for the copper wiring, while effectively preventing moisture and contaminant intrusion. For the two metal layers, copper can be electroplated by applying a suitable current in a specific electroplating solution to reduce and deposit copper ions at corresponding locations to form interconnects; alternatively, aluminum can be sputtered in a vacuum environment by bombarding an aluminum target with high-energy particles to deposit aluminum atoms and form interconnects. This achieves high-density electrical connections between the chip and the substrate, supporting high-frequency signal transmission.

[0027] Step 3: Mounting of the fin-type vertical structure and flip-chip bonding, as follows: On the surface of the prepared conductive layer 4, an appropriate amount of solder paste is evenly printed onto the designated positions of the conductive layer 4 using screen printing to form pads. During the printing process, parameters such as the spacing between the screen and the conductive layer 4, the printing pressure, and the viscosity of the solder paste must be strictly controlled to ensure that the pad size is accurate and the thickness is uniform.

[0028] The fin-type vertical structure 1 obtained in step S1 is precisely placed on the pad of the conductive layer 4 in a vertical orientation to ensure that the copper layer on the fin-type vertical structure 1 is in close contact with the metal layer on the conductive layer 4, so as to achieve conduction between the two.

[0029] Next, the flip chip 5 is placed at the corresponding position on the conductive layer 4, with the bumps on the bottom of the flip chip 5 precisely aligned with the conductive layer 4. Then, the entire assembly is placed in a reflow soldering machine, and by precisely controlling the temperature profile, the solder paste melts and then solidifies, achieving bump bonding between the flip chip 5 and the conductive layer 4, thus completing the fixed installation of the flip chip 5 on the conductive layer 4 and ensuring the stability and reliability of the electrical connection.

[0030] Step 4, Fin-type vertical structure and flip-chip packaging, the specific method is as follows: Urea-formaldehyde resin (UF), known for its stable performance, was selected as the encapsulation material. An appropriate amount of urea-formaldehyde resin powder was mixed with a solvent in a specific ratio and thoroughly stirred at a suitable temperature and stirring speed to prepare a uniform urea-formaldehyde resin solution with a certain degree of fluidity.

[0031] The prepared urea-formaldehyde resin adhesive is uniformly coated onto the surface of the conductive layer 4, the finned vertical structure 1, and the flip chip 5 using either dispensing or spraying methods. During dispensing, the amount and location of the adhesive are controlled using precision dispensing equipment; during spraying, the pressure and spraying angle of the spraying equipment are adjusted to ensure uniform adhesion of the adhesive.

[0032] The entire assembly is then placed in a curing oven to allow the urea-formaldehyde resin to gradually harden, forming the UF encapsulation layer 6. This UF encapsulation layer 6 tightly wraps around the internal structure, effectively isolating it from external moisture, dust, and other interfering factors, providing excellent encapsulation protection for the internal structure. Furthermore, its high strength provides reliable reinforcement and support for the fin-type vertical structure 1 and the flip chip 5, enhancing the overall stability of the encapsulation structure.

[0033] Step 5: Surface treatment of the UF encapsulation layer and setting of the top layer structure, the specific method is as follows: Select appropriate grit sandpaper or grinding equipment to finely grind the surface of the UF packaging layer 6. During the grinding process, strictly control the grinding pressure, speed, and time to ensure uniform removal of the surface material of the UF packaging layer 6, accurately exposing the copper layer on the fin vertical structure 1, while avoiding excessive damage to the copper layer.

[0034] After polishing, a 3P2M top layer structure 7 is fabricated on the polished UF packaging layer 6. This 3P2M structure uses an alternating stacking of 3 copper layers and 2 dielectric layers. The dielectric layers can be deposited sequentially by spin coating, and then the copper layer can be formed using physical vapor deposition (PVD).

[0035] When constructing the top layer structure 7, the position and size of each layer are precisely designed to ensure that the exposed copper layer on the fin-type vertical structure 1 is in close contact with the corresponding copper layer in the top layer structure 7. Through reasonable process treatment, such as thermo-bonding, reliable conduction between the two is achieved, providing a stable channel for subsequent circuit connection and signal transmission.

[0036] Step 6: Glass substrate removal and BGA ball implantation, the specific method is as follows: Based on the characteristics of the temporary bonding adhesive layer 3, if it is a pyrolytic adhesive, it is de-adhesive by heating to a specific temperature; if it is a photolytic adhesive, it is irradiated with ultraviolet light of a specific wavelength. By activating the temporary bonding adhesive layer 3 in the above manner, a smooth and non-destructive separation of the glass substrate 2 and the temporarily bonded wafer can be achieved.

[0037] After removing the glass substrate 2, a ball-mounting machine is used to precisely implant the BGA balls 8 into the designated positions at the bottom of the conductive layer 4. The ball-mounting machine ensures that the BGA balls 8 accurately land on the preset pads by precisely controlling the ball supply, pickup, and placement actions, thus completing the circuit board connection and ensuring stable signal transmission.

[0038] like Figure 3 As shown, a fin-type vertical interposer fan-out package structure is fabricated using the above-described process. Its core component is a fin-type vertical interconnect interposer layer, within which multiple fin-type vertical structures 1 are cleverly arranged. These fin-type vertical structures 1 are distributed in a regular or specific arrangement, providing a three-dimensional and efficient channel for signal transmission.

[0039] On the upper and lower surfaces of the fin-type vertical interconnect interposer, a top layer structure 7 and a conductive layer 4 are respectively disposed. The top layer structure 7 adopts a 3P2M structure with three copper layers and two dielectric layers stacked alternately. This structure not only has good electrical performance but also provides a certain degree of mechanical support. The conductive layer 4 consists of three passivation layers and two metal layers. The three passivation layers are made of polyimide (PI) material, which provides reliable protection, insulation, and stress buffering for the internal circuitry. The two metal layers form interconnect lines through electroplated copper or sputtered aluminum, achieving high-density electrical connections and supporting high-frequency signal transmission.

[0040] The top layer 7 and conductive layer 4 are precisely connected to the copper layer in the fin-type vertical structure 1. Through specific processes, such as thermosetting bonding, a stable, low-impedance electrical connection is ensured between the layers, guaranteeing efficient signal transmission within the package structure.

[0041] BGA balls 8 are placed at the bottom of conductive layer 4. These BGA balls 8 are precisely implanted into designated positions using a ball-mounting machine. Their size and spacing are strictly designed to meet the requirements for reliable connection with external circuit boards. As a bridge connecting the package structure and external circuits, the BGA balls 8 realize efficient electrical interconnection between the package structure and external systems, providing a stable and reliable signal transmission path for the entire electronic system.

[0042] This invention utilizes a planar copper wiring process to fabricate a fin-type vertical structure 1, which is then applied to an interposer fan-out package structure. This completely avoids the complex and challenging process steps of deep-hole etching, dielectric / barrier layer deposition, and deep-hole electroplating filling for high aspect ratio TSVs, thereby significantly reducing process complexity and potential failure risks, and improving production yield. Combined with RDL technology, this invention enables high-density electrical interconnection in both horizontal and vertical directions, while providing excellent fan-out capability, meeting the demands of heterogeneous integration for high bandwidth and high I / O density.

[0043] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0044] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in sequences other than those illustrated or described herein.

[0045] The above description is merely a preferred embodiment of the invention and is not intended to limit the invention. Various modifications and variations can be made by those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the invention should be included within the scope of protection of the invention.

Claims

1. A fin-type vertical interposer fan-out packaging method, characterized in that, Includes the following steps: S1. Fabrication of the fin-type vertical structure, specifically including: S11. Select a silicon wafer of appropriate specifications as the substrate material, and form the first PI layer on the surface of the silicon wafer by spin coating. S12. On the surface of the first PI layer, a copper layer is formed by copper electroplating or physical vapor deposition, and a pattern of interconnection patterns is defined on the copper layer by photolithography to form a copper wiring layer. S13. Cover the copper layer with a photoresist layer, form an opening on the photoresist layer corresponding to the position of the copper pillar through a photolithography step, and electroplate copper at the opening to form several copper pillars, with the copper pillars corresponding to the ports of the copper wiring layer. S14. A second PI layer is formed on the surface of the copper layer and copper pillar by spin coating, and surface acoustic wave process is introduced to suppress high frequency noise to obtain a multi-layer electroplated board. A fin-type vertical structure is obtained by vertical cutting. S2. Glass substrate preparation and conductive layer construction, specifically including: selecting a glass wafer with good flatness as a temporary carrier, cleaning it to form a glass substrate; spin-coating a temporary bonding adhesive on the surface of the glass substrate to form a temporary bonding adhesive layer; preparing a conductive layer on the glass substrate, the conductive layer consisting of 3 passivation layers and 2 metal layers, the passivation layers using polyimide material, and the metal layers forming interconnect lines by electroplating copper or sputtering aluminum. S3. The mounting and flip-chip bonding of the fin vertical structure specifically includes: screen printing solder paste on the conductive layer surface to form pads; vertically placing the fin vertical structure on the conductive layer pads to ensure close contact between the copper layer on the fin vertical structure and the metal layer on the conductive layer; placing the flip chip at the corresponding position on the conductive layer and achieving bump bonding between the flip chip and the conductive layer through reflow soldering. S4, Fin Vertical Structure and Flip Chip Packaging, specifically includes: selecting urea-formaldehyde resin as the packaging material, mixing it to form urea-formaldehyde resin adhesive; using dispensing or spraying methods to cover the urea-formaldehyde resin adhesive onto the conductive layer surface, fin vertical structure and flip chip, and curing to form a UF packaging layer. S5, UF package layer surface treatment and top layer structure setting, specifically including: fine grinding of the UF package layer surface to expose the copper layer on the fin vertical structure; preparation of a 3P2M top layer structure on the ground UF package layer surface, the top layer structure using 3 copper layers and 2 dielectric layers stacked alternately, and achieving reliable conduction with the exposed copper layer on the fin vertical structure through thermo-press bonding. S6. Glass substrate removal and BGA ball implantation, specifically including: according to the characteristics of the temporary bonding adhesive layer, the temporary bonding adhesive layer is activated by heating or ultraviolet light irradiation to achieve separation of the glass substrate and the wafer; the BGA balls are precisely implanted into the designated position at the bottom of the conductive layer using a ball implantation machine.

2. The fin-type vertical interposer fan-out packaging method according to claim 1, characterized in that, In step S1 of preparing the fin-type vertical structure, the copper layer is formed by either copper electroplating or physical vapor deposition, and the copper pillars are formed at the opening of the photoresist layer by copper electroplating.

3. The fin-type vertical interposer fan-out packaging method according to claim 1, characterized in that, In step S2 of preparing the glass substrate and constructing the conductive layer, the three passivation layers of the conductive layer are made of polyimide material and are covered layer by layer by spin coating. The two metal layers form interconnect lines by electroplating copper or sputtering aluminum.

4. The fin-type vertical interposer fan-out packaging method according to claim 1, characterized in that, In the mounting and flip chip bonding step S4 of the fin-type vertical structure, reliable bonding between the flip chip and the conductive layer bumps is achieved by precisely controlling the temperature profile of the reflow soldering equipment.

5. A fin-type vertical interposer fan-out package structure, characterized in that, It is prepared by the packaging method described in any one of claims 1 to 4, and its core component is a fin vertical interconnect interposer layer. Multiple fin vertical structures are disposed inside the interposer layer, and a top layer structure and a conductive layer are disposed on the upper and lower end faces respectively, and a BGA ball is disposed at the bottom.

6. The fin-type vertical interposer fan-out packaging structure according to claim 5, characterized in that, The fin-type vertical structure is distributed in a regular or specific arrangement, providing a three-dimensional and efficient channel for signal transmission; the top layer structure adopts a 3P2M structure with 3 layers of copper and 2 layers of dielectric alternately stacked, and the conductive layer consists of 3 layers of passivation layer and 2 layers of metal layer, which are precisely connected to the copper layer in the fin-type vertical structure.

7. The fin-type vertical interposer fan-out packaging structure according to claim 5, characterized in that, The BGA ball is precisely implanted into a designated position at the bottom of the conductive layer using a ball-mounting machine, serving as a connection bridge between the package structure and the external circuit, thereby achieving efficient electrical interconnection between the package structure and the external system.

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