Method of manufacturing semiconductor device

Abstract

A method of manufacturing a semiconductor device includes forming a substrate and a wiring layer; forming a first interlayer insulating layer on the wiring layer; forming an etch stop layer covering a portion of an upper surface of the first interlayer insulating layer; forming a compensation insulating layer on the first interlayer insulating layer and the etching stop layer; planarizing the compensation insulating layer to form a compensation insulating pattern; forming a second interlayer insulating layer on the etching stop layer; and bonding the second interlayer insulating layer and the bonding wafer. Planarizing the compensation insulating layer includes removing a portion of the compensation insulating layer to expose the etch stop layer.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor device, and more specifically, to a method for manufacturing a semiconductor device comprising a bonding structure in which wafers are bonded. Background Technology

[0002] Semiconductor devices are valued as key components in the electronics industry due to their characteristics such as small size, versatility, and / or low manufacturing cost. Semiconductor devices can include semiconductor memory devices for storing logic data, semiconductor logic devices for calculating logic data, and hybrid semiconductor devices that include both storage and logic elements. To integrate semiconductor devices, bonding structures in which multiple wafers are joined have been proposed, and research is underway to improve the yield of semiconductor device manufacturing processes while mitigating or reducing voids in wafer edge regions. Summary of the Invention

[0003] The purpose of this invention is to provide a method for manufacturing semiconductor devices that improves manufacturing yield.

[0004] The problems to be solved by the present invention are not limited to those mentioned above, and those skilled in the art will clearly understand from the following description other problems not mentioned.

[0005] A method for manufacturing a semiconductor device according to some embodiments of the present invention may include: forming a substrate and a wiring layer; forming a first interlayer insulating layer on the wiring layer; forming an etch stop layer covering a portion of the upper surface of the first interlayer insulating layer; forming a compensation insulating layer on the first interlayer insulating layer and the etch stop layer; planarizing the compensation insulating layer to form a compensation insulating pattern; forming a second interlayer insulating layer on the etch stop layer; and bonding the second interlayer insulating layer and bonding a wafer, wherein planarizing the compensation insulating layer includes removing a portion of the compensation insulating layer to expose the etch stop layer.

[0006] A method for manufacturing a semiconductor device according to some embodiments of the present invention may include: preparing a sacrificial wafer; forming a substrate and a wiring layer on the sacrificial wafer; forming an insulating structure and an etch stop layer on the wiring layer, the insulating structure including a first interlayer insulating layer and a compensating insulating pattern; forming a second interlayer insulating layer on the insulating structure and the etch stop layer; and bonding the second interlayer insulating layer and bonding the wafer, wherein forming the insulating structure and the etch stop layer includes: forming the first interlayer insulating layer on the wiring layer; forming the etch stop layer on the first interlayer insulating layer; forming a compensating insulating layer to cover the etch stop layer; and removing a portion of the compensating insulating layer to form a compensating insulating pattern, wherein removing the portion of the compensating insulating layer includes removing the portion of the compensating insulating layer such that the vertical level of the upper surface of the compensating insulating layer is lower than the vertical level of the upper surface of the etch stop layer.

[0007] A method of manufacturing a semiconductor device according to some embodiments of the present invention may include: forming a first stacked structure; forming a second stacked structure; and bonding the first stacked structure and the second stacked structure, wherein forming the first stacked structure includes: preparing a sacrificial wafer; forming a substrate and a wiring layer on the sacrificial wafer; forming a first interlayer insulating layer on the wiring layer; forming an etch stop layer on the first interlayer insulating layer; forming a compensation insulating layer on the first interlayer insulating layer and the etch stop layer; planarizing the compensation insulating layer until the etch stop layer is exposed to form a compensation insulating pattern; forming a second interlayer insulating layer on the etch stop layer; bonding the second interlayer insulating layer and bonding the wafer; and performing a dicing process on the sacrificial wafer, the substrate, the wiring layer, the first interlayer insulating layer and the second interlayer insulating layer, wherein the compensation insulating pattern has a circular shape, and wherein the dicing process is performed at intervals of 1.8 mm to 2.2 mm from the edge of the sacrificial wafer toward the center region of the sacrificial wafer. Attached Figure Description

[0008] The exemplary embodiments will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings. The drawings illustrate non-limiting exemplary embodiments as described herein.

[0009] Figure 1 This is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention.

[0010] Figure 2 , Figure 3 , Figure 4A , Figure 4B , Figure 5 , Figure 6A , Figure 6B , Figure 7 and Figure 8 A method for manufacturing a semiconductor device according to an embodiment of the present invention is shown. Detailed Implementation

[0011] In the following, the inventive concept will be described in detail by referring to the accompanying drawings and illustrating exemplary embodiments thereof.

[0012] Figure 1 This is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention.

[0013] refer to Figure 1 A semiconductor device according to some embodiments of the present invention may include a first stacked structure SR1 and a second stacked structure SR2 stacked on the first stacked structure SR1. The first stacked structure SR1 and the second stacked structure SR2 may be part of a wafer or die.

[0014] A first stacked structure SR1 may be provided. The first stacked structure SR1 may include a substrate 100, a wiring layer 150, a first interlayer insulating layer 200, an etch stop layer 300, and a second interlayer insulating layer 400.

[0015] Substrate 100 may be a semiconductor substrate. Substrate 100 may be, for example, a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a single-crystal epitaxial layer grown on a single-crystal silicon substrate.

[0016] A device isolation pattern ST defining the active region can be provided in the substrate 100. The device isolation pattern ST may include at least one of silicon oxide and silicon nitride.

[0017] A gate structure GST may be disposed on a substrate 100. The gate structure GST may include a gate insulating layer GI, a gate electrode GE on the gate insulating layer GI, a gate cap pattern GC on the gate electrode GE, and a gate spacer GS covering or surrounding the sidewalls of each of the gate insulating layer GI, the gate electrode GE, and the gate cap pattern GC.

[0018] The gate insulating layer GI may include a silicon oxide layer, a silicon oxide nitride layer, and / or a high-k layer. The high-k layer may include a high-k material having a higher dielectric constant than silicon oxide, such as hafnium oxide, hafnium silicon oxide, and hafnium zirconium oxide.

[0019] The gate cap pattern GC and gate spacer GS may include at least one of silicon nitride, silicon oxide nitride, and silicon oxycarbonitride.

[0020] A pair of impurity regions IR can be provided in the substrate 100. Each of the pair of impurity regions IR can correspond to a source / drain region. The pair of impurity regions IR can be spaced apart from each other in the substrate 100, with the gate structure GST between them or as the center.

[0021] The gate structure GST and the pair of impurity regions IR can form a transistor TR. The transistor TR can be, for example, a transistor used to drive memory devices such as dynamic random access memory (DRAM) or flash memory. The type and arrangement of the transistor TR are not limited to this and can be combined and changed in various ways depending on the type of semiconductor device.

[0022] Wiring layer 150 may be disposed on substrate 100. Wiring layer 150 may include first insulating layer 110, second insulating layer 120, wiring pattern ML and conductive path VA.

[0023] The first insulating layer 110 and the second insulating layer 120 may comprise, for example, silicon oxide. A conductive path VA may penetrate or extend through the first insulating layer 110. A wiring pattern ML may be provided in the second insulating layer 120. The conductive path VA may electrically connect the transistor TR and the wiring pattern ML. The wiring pattern ML and the conductive path VA may comprise a metallic material. For example, the wiring pattern ML and the conductive path VA may comprise at least one of aluminum, copper, tungsten, molybdenum, ruthenium, and cobalt.

[0024] The first interlayer insulating layer 200 may be provided on the wiring layer 150. The first interlayer insulating layer 200 may include silicon oxide. For example, the first interlayer insulating layer 200 may be tetraethyl orthosilicate (TEOS, Si(OC2H5)4).

[0025] An etch stop layer 300 may be provided on the first interlayer insulating layer 200. That is, the first interlayer insulating layer 200 may be disposed between the wiring layer 150 and the etch stop layer 300. The etch stop layer 300 may include a material having etch selectivity relative to the first interlayer insulating layer 200 and the second interlayer insulating layer 400. The etch stop layer 300 may include, for example, a silicon nitride.

[0026] The second interlayer insulating layer 400 can be provided on the etch stop layer 300. That is, the etch stop layer 300 can be disposed between the first interlayer insulating layer 200 and the second interlayer insulating layer 400. The second interlayer insulating layer 400 can include silicon oxide. For example, the second interlayer insulating layer 400 can be tetraethyl orthosilicate (TEOS, Si(OC2H5)4).

[0027] A second stacked structure SR2 may be provided on a first stacked structure SR1. The second stacked structure SR2 may have a similar configuration to the first stacked structure SR1. That is, the second stacked structure SR2 may include a substrate 100', a wiring layer 150', a first interlayer insulating layer 200', an etch stop layer 300', and a second interlayer insulating layer 400', as described in the first stacked structure SR1. The substrate 100', wiring layer 150', first interlayer insulating layer 200', etch stop layer 300', and second interlayer insulating layer 400' included in the second stacked structure SR2 may be sequentially stacked on the first stacked structure SR1.

[0028] According to some embodiments of the present invention, the first stacked structure SR1 may include cell circuits such as memory integrated circuits. The cell circuits may include, for example, transistors TR as described in the first stacked structure SR1. The second stacked structure SR2 may include various peripheral circuits required for the operation of the cell circuits, and the peripheral circuits may be electrically connected to the cell circuits. The peripheral circuits may include, for example, transistors TR' of the second stacked structure SR2.

[0029] A bonding oxide layer 130 may be provided between a first stacked structure SR1 and a second stacked structure SR2. The bonding oxide layer 130 may bond the first stacked structure SR1 and the second stacked structure SR2. The bonding oxide layer 130 may be a natural oxide layer formed from the substrate of each of the stacked structures SR1 and SR2.

[0030] The connection structure (also referred to as a "through electrode") 250 may penetrate or extend through at least a portion of the first stacked structure SR1 and the second stacked structure SR2. Specifically, the connection structure 250 may penetrate the second stacked structure SR2, penetrate a portion of the first stacked structure SR1, and extend to the wiring layer 150 of the first stacked structure SR1. The connection structure 250 may have a bottom surface disposed at different levels.

[0031] The connection structure 250 described above can electrically connect the first stacked structure SR1 and the second stacked structure SR2 by contacting the wiring pattern ML of the first stacked structure SR1 and the wiring pattern ML of the second stacked structure SR2. The connection structure 250 may include, for example, a metallic material, such as titanium or tungsten.

[0032] Figure 2 , Figure 3 , Figure 4A , Figure 4B , Figure 5 , Figure 6A , Figure 7 and Figure 8 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. Specifically, Figure 4B yes Figure 4A A magnified view of part of the "CU". Figure 6B yes Figure 6A The floor plan. For simplicity, the details can be omitted. Figure 1 Overlapping descriptions.

[0033] refer to Figure 2 A sacrificial wafer SW may be provided. The sacrificial wafer SW may be, for example, a bare silicon wafer. In this case, the sacrificial wafer SW may have a first width W1 in the first direction D1. The first width W1 may be, for example, 300 mm to 320 mm.

[0034] In this specification, the first direction D1 is defined as a direction parallel to the upper surface of the sacrificial wafer SW. The second direction D2 is defined as a direction parallel to the upper surface of the sacrificial wafer SW and perpendicular to the first direction D1. The third direction D3 is defined as a direction perpendicular to the upper surface of the sacrificial wafer SW.

[0035] A substrate 100 can be formed on the sacrificial wafer SW. A device isolation pattern ST can be formed in the substrate 100, and a transistor TR can be formed on the substrate 100. Subsequently, a wiring layer 150 can be formed on the substrate 100. The wiring layer 150 may include a first insulating layer 110, a second insulating layer 120, a wiring pattern ML, and a conductive path VA.

[0036] A first interlayer insulating layer 200 can be formed on the wiring layer 150. The first interlayer insulating layer 200 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc.

[0037] In this configuration, due to the dispersed accumulation of the substrate 100 and wiring layer 150, the first interlayer insulating layer 200 may have a recessed portion CO in the edge region. Because of the recessed portion CO, the first interlayer insulating layer 200 may not have a constant thickness in the third direction D3. That is, the first interlayer insulating layer 200 may have an edge roll-off region. In this specification, an edge roll-off region refers to a recessed portion in the edge region of the interlayer insulating layer.

[0038] An etch stop layer 300 can be formed on the first interlayer insulating layer 200. Edge regions of the first interlayer insulating layer 200 can be exposed from the etch stop layer 300. That is, the etch stop layer 300 can cover a portion of the upper surface of the first interlayer insulating layer 200. The etch stop layer 300 can have a second width W2 in the first direction D1. The second width W2 of the etch stop layer 300 can be smaller than the first width W1 of the sacrificial wafer SW. The second width W2 can be, for example, 260 mm to 298 mm. The thickness TH of the etch stop layer 300 can be... Up to 1μm.

[0039] refer to Figure 3 A compensating insulating layer 201 can be formed to at least partially cover the side and top surfaces of the etch stop layer 300 and the edge region of the first interlayer insulating layer 200. Specifically, the compensating insulating layer 201 can fill... Figure 2 The recessed portion CO described in the specification. That is, in this specification, "compensation" can mean filling the recessed portion of the edge region of the first interlayer insulating layer 200 with insulating material. The compensation insulating layer 201 may have a first height H1 in the third direction D3 on the etch stop layer 300. The maximum value of the first height H1 may be, for example, 1 μm to 3 μm. The compensation insulating layer 201 may include the same material as the first interlayer insulating layer. The compensation insulating layer 201 may include silicon oxide. For example, the compensation insulating layer 201 may be tetraethyl orthosilicate (TEOS, Si(OC2H5)4).

[0040] refer to Figure 4A and Figure 4B A planarization process can be performed on the compensation insulating layer 201 until the upper surface 300a of the etch stop layer 300 is exposed. That is, the planarization process can include removing a portion of the compensation insulating layer 201 until the upper surface of the etch stop layer 300 is exposed. Due to this process, a portion of the compensation insulating layer 201 can be removed, thereby forming a compensation insulating pattern 201P that can be formed from the compensation insulating layer 201. Removing a portion of the compensation insulating layer 201 can include removing the compensation insulating layer 201 such that the vertical level of the upper surface of the compensation insulating layer 201 is lower than the vertical level of the upper surface of the etch stop layer 300.

[0041] The compensating insulation pattern 201P can be provided on the edge region of the first interlayer insulation layer 200. The compensating insulation pattern 201P can have a circular shape. As a result of performing a planarization process, an insulation structure 202 including the first interlayer insulation layer 200 and the compensating insulation pattern 201P can be formed. The planarization process can include, for example, a chemical mechanical planarization (CMP) process.

[0042] refer to Figure 4B The insulating structure 202 may include a central region CE and edge regions ED connected to the central region CE. The central region CE may be provided between the edge regions ED. The edge regions ED may be regions corresponding to the two sides of the insulating structure 202. Due to the planarization process, the edge regions ED of the insulating structure 202 may have a rounded shape. That is, the two sides of the insulating structure 202 may have edge roll-off regions.

[0043] The thickness of the edge region ED in the third direction D3 can be less than the thickness of the central region CE in the third direction D3. The thickness of the edge region ED in the third direction D3 can increase as the edge region approaches the central region CE in the first direction D1. The central region CE can be covered by the etch stop layer 300. The edge region ED can be exposed from the etch stop layer 300.

[0044] In this configuration, the edge region ED may include a first portion RE1 and a second portion RE2 on the first portion RE1. The first portion RE1 and the second portion RE2 may correspond to the lower and upper portions of the edge region ED, respectively. The first portion RE1 may have a third width W3 in the first direction D1. The third width W3 may be constant regardless of vertical or horizontal orientation. The second portion RE2 may have a fourth width W4 in the first direction D1. The fourth width W4 may decrease as the second portion RE2 approaches the etch stop layer 300 in the third direction D3. The second portion RE2 may have a second height H2 in the third direction D3. The second height H2 may increase as the second portion RE2 approaches the central region CE in the first direction D1. The maximum value of the second height H2 may be, for example, 0.2 μm to 0.4 μm. That is, the degree of recess in the edge region ED of the insulating structure 202 may be at most 0.2 μm to 0.4 μm.

[0045] refer to Figure 4A , Figure 4B and Figure 5 A second interlayer insulating layer 400 can be formed on the insulating structure 202 and the etch stop layer 300. That is, the etch stop layer 300 can be disposed between the first interlayer insulating layer 200 and the second interlayer insulating layer 400. The second interlayer insulating layer 400 can at least partially cover the compensating insulating pattern 201P and the etch stop layer 300.

[0046] The shape of the second interlayer insulation layer 400 can be similar to Figure 4B The shape of the insulating structure 202 described herein. Specifically, due to the planarization process used to compensate for the insulating layer 201, the edge region of the second interlayer insulating layer 400 formed on the insulating structure 202 can also have a rounded shape, corresponding to the rounded shape of the compensating insulating pattern 201P. That is, the two sides of the second interlayer insulating layer 400 can have edge roll-off regions. The second interlayer insulating layer 400 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0047] refer to Figure 6A and Figure 6B The bonding wafer BW can be bonded to a portion of the second interlayer insulating layer 400. The bonding wafer BW can be, for example, a bare silicon wafer. Specifically, such as... Figure 5 As described above, since the edge region of the second interlayer insulating layer 400 has an edge roll-off area, the edge region of the second interlayer insulating layer 400 may not be bonded to the bonding wafer BW. The length or width UBL of the unbonded area of ​​the second interlayer insulating layer 400 and the bonding wafer BW may be, for example, 1.5 mm to 1.7 mm.

[0048] On the edge region of the second interlayer insulating layer 400, the maximum separation distance between the second interlayer insulating layer 400 and the bonded wafer BW in the third direction D3 can have a first distance DS1. The first distance DS1 can be, for example, 0.2 μm to 0.4 μm.

[0049] Subsequently, a removal process can be performed on the sacrificial wafer SW, substrate 100, wiring layer 150, first interlayer insulating layer 200, and second interlayer insulating layer 400. The removal process may include, for example, a dicing process (such as laser trimming). The removal process can be performed along a dicing line TL. The dicing line TL can be formed at a portion of the sacrificial wafer SW that moves a second distance DS2 from the edge in a first direction D1 towards the central region. When viewed in a plan view, as... Figure 6B As shown, the dicing line TL can have a circular shape. The second distance DS2 can be from 1.8 mm to 2.2 mm. According to some embodiments, the second distance DS2 can be 1.9 mm. Since the second distance DS2 is formed to be 2.2 mm or less, components included in the substrate 100 and wiring layer 150 can be removed without damage, thereby improving the yield of the semiconductor device manufacturing process.

[0050] As a result of performing the above-described removal process, the widths of the sacrificial wafer SW, substrate 100, wiring layer 150, first interlayer insulating layer 200, and second interlayer insulating layer 400 in the first direction D1 can be reduced. According to some embodiments, the compensation insulating pattern 201P can also be partially or completely removed by the removal process.

[0051] refer to Figure 7 The sacrificial wafer SW, substrate 100, wiring layer 150, first interlayer insulating layer 200, etch stop layer 300, second interlayer insulating layer 400, and bonding wafer BW can be flipped so that the bottom surface of the sacrificial wafer SW is exposed. The sacrificial wafer SW can then be removed. Removal of the sacrificial wafer SW can be performed, for example, by a polishing process. With the removal of the sacrificial wafer SW, substrate 100 can be exposed, and a first stacked structure SR1 including substrate 100, wiring layer 150, first interlayer insulating layer 200, etch stop layer 300, second interlayer insulating layer 400, and bonding wafer BW can be formed.

[0052] refer to Figure 8 The second stacked structure SR2 can be bonded to the first stacked structure SR1. The components of the second stacked structure SR2 can be similar to those of the first stacked structure SR1. That is, the second stacked structure SR2 can also include a substrate 100', a wiring layer 150', a first interlayer insulating layer 200', an etch stop layer 300', a second interlayer insulating layer 400', and a bonding wafer BW. The second stacked structure SR2 can be bonded to the first stacked structure SR1. Figures 2 to 7The process for forming the first stacked structure SR1 is basically the same or similar to that used in the process.

[0053] After that, return to the reference. Figure 1 The bonding wafers BW on the first stacked structure SR2 and the second stacked structure SR2 can be removed. After removing the bonding wafers BW, a connection structure 250 penetrating a portion of the first stacked structure SR1 and the second stacked structure SR2 can be formed, thereby completing a semiconductor device according to some embodiments of the present invention.

[0054] According to the method for manufacturing a comparative example semiconductor device, a planarization process is performed on the interlayer insulating layer before bonding the wafer to it. However, in this process, voids are generated at the bonding portions, leading to chipping and breakage of the wafer within them. To eliminate voids, even when the edge region of the interlayer insulating layer is recessed, the degree of recess in the edge region is 1 μm or more due to factors such as wafer stacking dispersion. As a result, the length of the unbonded portion between the interlayer insulating layer and the wafer increases. Consequently, since a dicing process must be performed within the unbonded portion between the interlayer insulating layer and the wafer, the yield of the semiconductor device manufacturing process is reduced.

[0055] On the other hand, a method for manufacturing a semiconductor device according to an embodiment of the present invention may include forming an etch stop layer on an interlayer insulating layer, forming a compensation insulating layer to cover the etch stop layer, and performing a planarization process on the compensation insulating layer. In this case, the edge region of the interlayer insulating layer can be exposed from the etch stop layer, and the width of the etch stop layer can be smaller than the width of the wafer. Due to the etch stop layer and the compensation insulating layer, the step difference of the edge region of the interlayer insulating layer can be adjusted, and the degree of recess in the edge region can be adjusted to the range of 0.2 μm to 0.4 μm. As a result, the generation of voids near the bonding between the interlayer insulating layer and the wafer can be prevented, and the length of the unbonded region between the interlayer insulating layer and the wafer can be reduced, thereby improving the yield of the semiconductor device manufacturing process.

[0056] A method for manufacturing a semiconductor device according to an embodiment of the present invention may include forming an etch stop layer on an interlayer insulating layer, forming a compensation insulating layer to cover the etch stop layer, and performing a planarization process on the compensation insulating layer. In this case, the edge region of the interlayer insulating layer can be exposed from the etch stop layer, and the width of the etch stop layer can be smaller than the width of the wafer. Due to the etch stop layer and the compensation insulating layer, the step difference of the edge region of the interlayer insulating layer can be adjusted, and the degree of recess in the edge region can be adjusted to the range of 0.2 μm to 0.4 μm. As a result, voids near the bonding between the interlayer insulating layer and the wafer can be prevented, and the length of the unbonded region between the interlayer insulating layer and the wafer can be reduced, thereby increasing the yield of the semiconductor device manufacturing process.

[0057] While exemplary embodiments have been described above, those skilled in the art will understand that many modifications and variations can be made without departing from the spirit and scope of the inventive concept as defined in the appended claims. Therefore, the exemplary embodiments of the inventive concept should be considered illustrative rather than restrictive in all respects, wherein the spirit and scope of the inventive concept are indicated by the appended claims.

[0058] This application claims priority to Korean Patent Application No. 10-2024-0106388, filed on August 8, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: Forming a substrate and wiring layer; A first interlayer insulation layer is formed on the wiring layer; An etch stop layer is formed covering a portion of the upper surface of the first interlayer insulating layer; A compensation insulating layer is formed on the first interlayer insulating layer and the etch stop layer; Planarize the compensation insulation layer to form a compensation insulation pattern; A second interlayer insulating layer is formed on the etch stop layer; as well as Join the second interlayer insulating layer and the bonding wafer. Planarizing the compensation insulating layer includes removing a portion of the compensation insulating layer to expose the etch stop layer.

2. The method according to claim 1, wherein the compensating insulation pattern is on the edge region of the first interlayer insulation layer, and The compensation insulation pattern therein has a circular shape.

3. The method of claim 2, wherein the second interlayer insulating layer covers the upper surface of the compensating insulating pattern and the etch stop layer.

4. The method according to claim 2, wherein the edge region of the second interlayer insulating layer has a rounded shape.

5. The method of claim 1, wherein the etch stop layer has A thickness of up to 1 μm.

6. The method of claim 1, wherein the first interlayer insulating layer, the compensating insulating layer, and the second interlayer insulating layer comprise silicon oxide, and The etch stop layer comprises silicon nitride.

7. The method of claim 1, wherein forming the compensation insulating layer comprises forming the compensation insulating layer to have a height of 1 μm to 3 μm on the etch stop layer.

8. The method according to claim 1, further comprising: Prepare the sacrificial wafer before forming the wiring layer; as well as The substrate is placed on the sacrificial wafer.

9. The method of claim 8, wherein the sacrificial wafer has a first width in a first direction parallel to the upper surface of the substrate. The etch stop layer has a second width in the first direction, and The second width is smaller than the first width.

10. The method of claim 9, wherein the second width is 260 mm to 298 mm.

11. A method for manufacturing a semiconductor device, the method comprising: Prepare to sacrifice the chip; A substrate and a wiring layer are formed on the sacrificial wafer; An insulating structure and an etch stop layer are formed on the wiring layer, the insulating structure including a first interlayer insulating layer and a compensating insulating pattern; A second interlayer insulating layer is formed on the insulating structure and the etch stop layer; as well as Join the second interlayer insulating layer and the bonding wafer. The formation of the insulating structure and the etch stop layer includes: The first interlayer insulation layer is formed on the wiring layer; The etch stop layer is formed on the first interlayer insulating layer; A compensating insulating layer is formed to cover the etch stop layer; and A portion of the compensation insulation layer is removed to form the compensation insulation pattern, and The removal of the portion of the compensation insulating layer includes removing such a portion that the vertical level of the upper surface of the compensation insulating layer is lower than the vertical level of the upper surface of the etch stop layer.

12. The method of claim 11, wherein the insulating structure comprises a central region and an edge region connected to the central region. The edge region includes a first portion and a second portion on the first portion. The second portion has a first width in the first direction. Wherein the first width decreases as the second portion approaches the etch stop layer, and The maximum height of the second part is 0.2 μm to 0.4 μm.

13. The method of claim 12, wherein the central region is covered by the etch stop layer, and The edge region is exposed from the etch stop layer.

14. The method of claim 12, wherein the first portion has a second width in the first direction, and in, The second width is constant regardless of whether it is vertical or horizontal.

15. The method of claim 12, wherein the height of the second portion increases as the second portion approaches the central region in the first direction.

16. A method for manufacturing a semiconductor device, the method comprising: Forming the first stacked structure; Forming a second stacked structure; as well as By combining the first stacked structure and the second stacked structure, The formation of the first stacked structure includes: Prepare to sacrifice the chip; A substrate and a wiring layer are formed on the sacrificial wafer; A first interlayer insulation layer is formed on the wiring layer; An etch stop layer is formed on the first interlayer insulating layer; A compensation insulating layer is formed on the first interlayer insulating layer and the etch stop layer; Planarize the compensation insulation layer until the etch stop layer is exposed to form a compensation insulation pattern; A second interlayer insulating layer is formed on the etch stop layer; Joining the second interlayer insulating layer and the bonding wafer; and A dicing process is performed on the sacrificial wafer, the substrate, the wiring layer, the first interlayer insulating layer, and the second interlayer insulating layer. The compensation insulation pattern has a circular shape, and The cutting process is performed at a point where the wafer moves 1.8 mm to 2.2 mm from the edge toward the center of the wafer.

17. The method of claim 16, wherein forming the first stacked structure further comprises flipping the sacrificial wafer and removing the sacrificial wafer after the dicing process.

18. The method of claim 17, further comprising forming a through electrode penetrating the first stacked structure and the second stacked structure.

19. The method of claim 16, wherein the etch stop layer is disposed between the first interlayer insulating layer and the second interlayer insulating layer.

20. The method of claim 16, wherein the edge region of the second interlayer insulating layer has a rounded shape, and The maximum distance between the bonding wafers on the edge region of the second interlayer insulating layer and the second interlayer insulating layer is 0.2 μm to 0.4 μm.

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