Board-level packaging method and product thereof

Abstract

The invention discloses a board-level packaging method and a product thereof. The board-level packaging method comprises the following steps: step 1, manufacturing a rewiring layer and a micro-bump on a chip as required; step 2, mounting a plurality of chips or mounting the chips and the middle chip on the carrier plate; step 3, performing plastic package on the semi-finished product obtained in the step 2 to form a plastic package body, and selectively manufacturing a plastic package material through hole; 4, removing the carrier plate, and manufacturing a rewiring layer structure and a bump on the surface of the plastic package body; and step 5, cutting. According to the invention, system-level integration with larger size and higher cost performance can be realized, the packaging efficiency is high, the manufacturing cost is low, and a technical scheme is provided for ultra-large single-chip or multi-chip system integration.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor packaging technology, specifically relating to a board-level packaging method and its products. Background Technology

[0002] System-in-package (SiP) is an advanced semiconductor packaging technology that integrates multiple chips and passive devices with different functions into a single package, assembling them into a complete, independently functioning system or subsystem. However, existing SiP technologies primarily rely on traditional organic packaging boards (OPCWs) or printed circuit boards (PCBs) as the core carriers for multi-chip integration and interconnection. Traditional OPCWs or PCBs are limited by subtractive manufacturing processes, restricting I / O density and interconnect capabilities, making it difficult to meet the ever-increasing demands of high-performance computing. Summary of the Invention

[0003] To address the problems in the prior art, the present invention aims to provide a board-level packaging method and its products.

[0004] To achieve the above objectives and technical effects, the technical solution adopted by this invention is as follows: A board-level packaging method includes the following steps: Step 1: Fabricate a redistribution layer and microbumps on the chip as needed; Step 2: Mount several chips or chips and intermediate chips onto a carrier board; Step 3: The semi-finished product obtained in Step 2 is encapsulated to form an encapsulated body, and then selectively through-holes for the encapsulating material are made; Step 4: Remove the carrier board and create a redistribution layer structure and bumps on the surface of the molding compound; Step 5: Cutting.

[0005] Furthermore, in step one, the thickness of the redistribution layer is 2 to 6 micrometers.

[0006] Furthermore, in step two, the carrier plate is made of silicon wafer, glass, or steel plate.

[0007] Furthermore, in step four, the thickness of the redistribution layer structure is 2 to 6 micrometers.

[0008] Furthermore, in step two, several chips are directly bonded onto the carrier board.

[0009] Furthermore, in step two, a high-precision pick-and-place machine is used to pick up known qualified chips and bond the chips back to back together directly with bonding adhesive to complete the three-dimensional stacking and mounting.

[0010] Furthermore, in step three, after laser drilling during the molding stage, metal is electroplated to create through-holes for the molding compound, or the copper pillar structure is molded together with the chip and intermediate chip during the molding stage to form through-holes for the molding compound.

[0011] Furthermore, in step three, after laser drilling during the molding stage, metal is electroplated to create through-holes for the molding compound, or the copper pillar structure is molded together with the chip during the molding stage to form through-holes for the molding compound. The through-holes for the molding compound are bonded to the chip via wire bonding.

[0012] Furthermore, in step four, the molding compound is debonded to the carrier board, and then a redistribution layer structure and bumps are fabricated on the surface of the molding compound.

[0013] The present invention also discloses a board-level packaging structure prepared by a board-level packaging method.

[0014] Compared with the prior art, the beneficial effects of the present invention are as follows: This invention enables larger-size, more cost-effective system-level integration with high packaging efficiency and low manufacturing cost, providing a technical solution for ultra-large single-chip or multi-chip system integration. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the structure of Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of the structure of Embodiment 2 of the present invention; Figure 3 This is a schematic diagram of the structure of Embodiment 3 of the present invention. Detailed Implementation

[0016] The present invention will now be described in detail so that its advantages and features can be more easily understood by those skilled in the art, thereby providing a clearer and more explicit definition of the scope of protection of the present invention.

[0017] The following provides a brief overview of one or more aspects to offer a basic understanding of them. This overview is not an exhaustive summary of all conceived aspects, nor is it intended to identify key or decisive elements of all aspects, nor to define the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form to prepare for the more detailed descriptions that follow.

[0018] This invention discloses a board-level packaging method, comprising the following steps: Step 1: Fabricate a redistribution layer 2 and microbumps on chip 1 as needed. The redistribution layer 2 consists of a dielectric layer and a metal layer, with a thickness of 2-6 micrometers. Microbumps, composed of copper and solder balls, are fabricated on its top layer. Chip 1 can be a chip or functional module with different process technologies, materials, and functions, such as advanced digital logic chips, analog / RF chips, memory, MEMS sensors, or passive devices. Step 2: Mount several chips 1 or chips 1 and intermediate chip 6 onto a carrier board. The carrier board may be made of silicon wafers, glass, or steel. Step 3: The semi-finished product obtained in Step 2 is encapsulated with a molding compound to form a molded body 5, and then selectively fabricates through holes 10 for the molding compound. Step 4: Debond the molding compound 5 to the carrier board, and then fabricate a redistribution layer structure 3 and bumps 4 on the surface of the molding compound 5. The redistribution layer structure 3 consists of a dielectric layer and a metal layer with a thickness of 2-6 micrometers. The topmost layer is made of bumps 4, which are composed of copper and solder balls. Step 5: Cutting.

[0019] In some implementations, in step two, several chips 1 are directly bonded to the carrier board.

[0020] In some implementations, in step two, a high-precision pick-and-place machine is used to pick up known qualified chips 1, and two chips 1 are directly bonded back to back together with bonding adhesive 11 to complete the three-dimensional stacking and mounting.

[0021] In some embodiments, in step three, after laser drilling in the molding stage, metal is electroplated to create molding compound through-holes 10, or the copper pillar structure is molded together with chip 1 and intermediate chip 6 in the molding stage to form molding compound through-holes 10.

[0022] In some embodiments, in step three, after laser drilling in the molding stage, metal is electroplated to create molding compound through-holes 10, or the copper pillar structure is molded together with the chip 1 in the molding stage to form molding compound through-holes 10, and the molding compound through-holes 10 and the chip 1 are bonded together by leads 12.

[0023] In step four, the molding compound 5 is unbonded from the carrier plate, and the redistribution layer structure 3 and bump 4 are fabricated on the side away from the molding compound 5.

[0024] The present invention also discloses a board-level packaging structure prepared by the board-level packaging method described above.

[0025] Example 1 like Figure 1 As shown, a board-level packaging method includes the following steps: Step 1: Fabricate a redistribution layer 2 and microbumps on chip 1. The redistribution layer 2 consists of a dielectric layer and a metal layer, with a thickness of 2 micrometers. The top layer is fabricated with microbumps composed of copper and solder balls. Chip 1 can be a chip or functional module with different process technology, materials, and functions, such as: advanced digital logic chips, analog / RF chips, memory, MEMS sensors, or passive devices. Step 2: Use a high-precision pick-and-place machine to pick up known qualified chips 1, and directly bond and mount several chips 1 onto a carrier board. The carrier board is a silicon wafer. Step 3: The semi-finished product obtained in Step 2 is encapsulated with a molding compound to form a molded body 5; Step 4: Debond the molding compound 5 to the carrier board, and then fabricate a redistribution layer structure 3 and bumps 4 on the surface of the molding compound 5. The redistribution layer structure 3 consists of a dielectric layer and a metal layer, with a thickness of 2 micrometers. The topmost layer is made of bumps 4, which are composed of copper and solder balls. Step 5: Cutting.

[0026] This embodiment also discloses a board-level packaging structure prepared by the board-level packaging method described above, including a molding compound 5, a chip 1 encapsulated inside the molding compound 5, a redistribution layer 2 and microbumps fabricated on the chip 1, and a redistribution layer structure 3 and bumps 4 fabricated on the surface of the molding compound 5.

[0027] Example 2 like Figure 2 As shown, a board-level packaging method includes the following steps: Step 1: Fabricate a redistribution layer 2 and microbumps on chip 1. The redistribution layer 2 consists of a dielectric layer and a metal layer, with a thickness of 6 micrometers. The top layer is fabricated with microbumps composed of copper and solder balls. Chip 1 can be a chip or functional module with different process technology, materials, and functions, such as: advanced digital logic chips, analog / RF chips, memory, MEMS sensors, or passive devices. Step 2: Using a high-precision pick-and-place machine, pick up the known qualified chip 1 and intermediate chip 6 and mount them onto the carrier board. The carrier board is a silicon wafer. The microbumps on chip 1 are precisely aligned with the second microbumps 8 on the second wiring layer of intermediate chip 6. The mechanical and electrical connection between chip 1 and intermediate chip 6 is completed by reflow soldering. Then, underfill 9 is applied. The underfill material includes, but is not limited to, epoxy resin. This completes the three-dimensional stacking. Step 3: The semi-finished product obtained in Step 2 is encapsulated with a molding compound to form a molded body 5; Laser drilling followed by metal plating during the molding process creates through-holes 10 in the molding compound. Step 4: Debond the molding compound 5 to the carrier board, and then fabricate a redistribution layer structure 3 and bumps 4 on the surface of the molding compound 5. The redistribution layer structure 3 consists of a dielectric layer and a metal layer, with a thickness of 6 micrometers. The topmost layer is made of bumps 4, which are composed of copper and solder balls. Step 5: Cutting.

[0028] This embodiment also discloses a board-level packaging structure prepared by the board-level packaging method described above, comprising a molding compound 5, which encapsulates a chip 1, an intermediate chip 6, and molding compound vias 10. A redistribution layer 2 and microbumps are fabricated on the chip 1, and a redistribution layer structure 3 and bumps 4 are fabricated on the surface of the molding compound 5. The first microbump on the first redistribution layer 7 of the intermediate chip 6 is precisely aligned with the redistribution layer structure 3.

[0029] Example 3 like Figure 3 As shown, a board-level packaging method includes the following steps: Step 1: Fabricate a redistribution layer 2 and microbumps on chip 1. The redistribution layer 2 consists of a dielectric layer and a metal layer, with a thickness of 4 micrometers. The top layer is fabricated with microbumps composed of copper and solder balls. Chip 1 can be a chip or functional module with different process technology, materials, and functions, such as: advanced digital logic chips, analog / RF chips, memory, MEMS sensors, or passive devices. Step 2: Use a high-precision pick-and-place machine to pick up the known qualified chips 1, and bond two chips 1 together back to back using bonding adhesive 11 to complete the three-dimensional stacking and mounting. Step 3: The semi-finished product obtained in Step 2 is encapsulated with a molding compound to form a molded body 5; After laser drilling during the molding process, metal is electroplated to create molding compound through-holes 10. The molding compound through-holes 10 are bonded to the chip 1 via leads 12. Step 4: Debond the molding compound 5 to the carrier board, and then fabricate a redistribution layer structure 3 and bumps 4 on the surface of the molding compound 5. The redistribution layer structure 3 consists of a dielectric layer and a metal layer, with a thickness of 4 micrometers. The topmost layer is made of bumps 4, which are composed of copper and solder balls. Step 5: Cutting.

[0030] This embodiment also discloses a board-level packaging structure prepared by the board-level packaging method described above, comprising a molding compound 5, a chip 1 and molding compound vias 10 encapsulated within the molding compound 5, a redistribution layer 2 and microbumps fabricated on the chip 1, and a redistribution layer structure 3 and bumps 4 fabricated on the surface of the molding compound 5.

[0031] Any parts or structures not specifically described in this invention can be made using existing technologies or products, and will not be elaborated upon here.

[0032] The above description is merely an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention specification, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A board-level packaging method, characterized in that, Includes the following steps: Step 1: Fabricate a redistribution layer and microbumps on the chip as needed; Step 2: Mount several chips or chips and intermediate chips onto a carrier board; Step 3: The semi-finished product obtained in Step 2 is encapsulated to form an encapsulated body, and then selectively through-holes for the encapsulating material are made; Step 4: Remove the carrier board and create a redistribution layer structure and bumps on the surface of the molding compound; Step 5: Cutting.

2. The board-level packaging method according to claim 1, characterized in that, In step one, the thickness of the redistribution layer is 2 to 6 micrometers.

3. The board-level packaging method according to claim 1, characterized in that, In step two, the carrier plate is made of silicon wafer, glass, or steel plate.

4. The board-level packaging method according to claim 1, characterized in that, In step four, the thickness of the redistribution layer structure is 2 to 6 micrometers.

5. A board-level packaging method according to claim 1, characterized in that, In step two, several chips are directly bonded onto the carrier board.

6. The board-level packaging method according to claim 1, characterized in that, In step two, a high-precision pick-and-place machine is used to pick up known qualified chips and bond the chips back to back together directly with bonding adhesive to complete the three-dimensional stacking and mounting.

7. A board-level packaging method according to claim 1, characterized in that, In step three, after laser drilling during the molding stage, metal is electroplated to create through-holes for the molding compound, or the copper pillar structure is molded together with the chip and intermediate chip during the molding stage to form through-holes for the molding compound.

8. A board-level packaging method according to claim 1, characterized in that, In step three, after laser drilling during the molding stage, metal is electroplated to create through-holes for the molding compound, or the copper pillar structure is molded together with the chip during the molding stage to form through-holes for the molding compound. The through-holes for the molding compound are then bonded to the chip via wire bonding.

9. A board-level packaging method according to claim 1, characterized in that, In step four, the molding compound is debonded to the carrier board, and then a redistribution layer structure and bumps are fabricated on the surface of the molding compound.

10. The board-level packaging structure prepared by the board-level packaging method according to claim 1.

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