Ultrasonic imaging probe

Abstract

The invention relates to an ultrasound imaging probe (100) comprising a first circuit (110), a second circuit (120) and a third circuit (130), in which:-the first circuit (110) is an ultrasound transduction circuit comprising an array of substantially ultrasound transduction chips (111), each substantially ultrasound transduction chip comprising an array of substantially ultrasound transducers (113); -the second circuit (120) is a transceiver circuit comprising, for each base ultrasound transduction chip (111), a base transceiver chip (121); and-the third circuit (130) is a digital pre-processing circuit comprising, for each base transceiver chip (121), a base digital pre-processing chip (131).

Description

[0001] This application is based on and claims priority to French Patent Application No. 23 / 06703, filed on June 27, 2023, entitled “Ultrasound imaging probe”, which is incorporated herein by reference within the limits of the law. TECHNICAL FIELD

[0002] The present disclosure relates to the field of ultrasound imaging, and more specifically aims to provide an ultrasound imaging probe, which is intended to be connected via a cable to an external control and processing system, which combines a plurality of ultrasound transducers and electronic circuits for controlling these transducers. PRIOR ART

[0003] Various architectures of ultrasound imaging probes have been provided.

[0004] It is desirable to improve at least partly certain aspects of known ultrasound imaging probes.

[0005] Formations of ultrasound imaging probes are here considered more specifically, which are adapted to implement digital and / or analog processing operations, such as for example microbeamforming, in the vicinity of the ultrasound sensors, for example in the context of an ultrafast acquisition scenario. SUMMARY

[0006] One embodiment provides an ultrasound imaging probe comprising a first circuit, a second circuit and a third circuit, wherein:

[0007] - the first circuit is an ultrasound transduction circuit comprising an array of elementary ultrasound transduction chips, each chip comprising an array of elementary ultrasound transducers;

[0008] - the second circuit is a transceiver circuit comprising, for each elementary ultrasound transduction chip, a corresponding specific elementary transceiver chip comprising, for each elementary ultrasound transducer of the elementary ultrasound transduction chip, an elementary transceiver cell electrically connected to an electrode of the transducer;

[0009] - in each elementary transceiver chip, the elementary transceiver cells of the chip are distributed into a plurality of elementary transceiver groups, each elementary transceiver group comprising N elementary transceiver cells, with N being an integer greater than or equal to 1;

[0010] - for each elementary transceiver chip, for each elementary transceiver group of the chip, the probe comprises an analog pre-processing circuit comprising N input terminals and M output terminals, the N input terminals being respectively connected to the output terminals of each elementary transceiver cell of the elementary transceiver group, with M being less than or equal to N;

[0011] - the probe comprises, for each elementary transceiver group of each elementary transceiver chip, M analog-to-digital converters each having an input terminal and an output terminal, the input terminals of the M analog-to-digital converters being connected to the M output terminals of the analog pre-processing circuit of the elementary transceiver group, respectively;

[0012] - the third circuit is a digital pre-processing circuit comprising, for each elementary transceiver chip, a corresponding specific elementary digital pre-processing chip comprising, for each elementary transceiver group of the elementary transceiver chip, M elementary digital pre-processing units connected to the output terminals of the M analog-to-digital converters associated with the elementary transceiver group, respectively;

[0013] - each elementary digital pre-processing chip comprises one or more binary connection elements each intended to provide a serialized digital signal coupled to all the elementary digital pre-processing units of the chip via one or more serialization circuits,

[0014] wherein each elementary digital pre-processing unit comprises an elementary storage circuit and a computation unit,

[0015] and wherein each elementary digital pre-processing chip comprises a global control circuit connected to the respective control nodes of the MxN elementary digital pre-processing units of the chip and adapted to control the elementary digital pre-processing units of the chip to perform a series of operations.

[0016] According to one embodiment, in each elementary digital pre-processing unit, the elementary storage circuit is adapted to store, during a reception time window following the emission of an ultrasound wave, the complete signal provided by the corresponding analog-to-digital converter.

[0017] According to one embodiment, each analog pre-processing circuit is a selector-combiner circuit adapted to provide, on each of its M output terminals, an analog sum or superposition of all or part of the signals applied to its N input terminals.

[0018] According to one embodiment, each transceiver unit comprises an emission circuit adapted to generate an electrical excitation signal applied to the electrodes of the associated elementary transducer.

[0019] According to one embodiment, each transceiver unit comprises a receiver circuit comprising an amplifier having an input node coupled to an electrode of the elementary transducer and an output node coupled to an output terminal of the transceiver unit.

[0020] According to one embodiment, in each transceiver unit, the reception circuit further comprises a delay circuit configured to apply a delay with adjustable duration to the electrical output signal of the transducer.

[0021] According to an embodiment, each basic digital pre-processing unit comprises a data input-output port which enables the exchange of data between the basic memory circuit of the unit and the basic memory circuit of an adjacent basic unit.

[0022] According to an embodiment, the first circuit, the second circuit and the third circuit are vertically stacked, the second circuit being arranged between the first circuit and the third circuit.

[0023] According to an embodiment, two of the first circuit, the second circuit and the third circuit are vertically stacked, and the remaining circuit of the first circuit, the second circuit and the third circuit is laterally offset.

[0024] According to an embodiment, M is less than N.

[0025] Another embodiment provides an ultrasound imaging system comprising an ultrasound imaging probe as defined above, an external processing device and a digital data transmission channel coupling the probe to the external processing device.

[0026] According to an embodiment, the digital data transmission channel comprises one or more electrical or optical data transmission line elements per digital pre-processing basic chip, which are respectively electrically connected to said one or more binary connection elements of the basic chip.

[0027] According to an embodiment, the external processing device is configured to apply a delay and combine the signals originating from the analog-to-digital converters. BRIEF DESCRIPTION OF DRAWINGS

[0028] These and other features and advantages will be described in the following detailed description of specific embodiments, provided by way of example, and not intended to be limiting, in which:

[0029] Figure 1 is a perspective view schematically and partially illustrating an example of an ultrasound imaging system according to an embodiment;

[0030] Figure 2 is an example of an embodiment of a transceiver circuit of an ultrasound imaging probe according to an embodiment, schematically and partially illustrated;

[0031] Figure 3 is an example of an embodiment of a digital pre-processing circuit of an ultrasound imaging probe according to an embodiment, schematically and partially illustrated;

[0032] Figure 4 is a perspective view schematically and partially illustrating a variant of an ultrasound imaging system according to an embodiment; and

[0033] Figure 5 is a cross-sectional view schematically and partially illustrating another variant of an ultrasound imaging system according to an embodiment. Detailed Implementation

[0034] In the various figures, the same elements are represented by the same reference numerals. In particular, structural and / or functional elements common to different embodiments may have the same reference numerals and may have exactly the same structure, dimensions, and material properties.

[0035] For clarity, only those steps and elements that aid in understanding the described embodiments are shown and described in detail. In particular, the various possible applications of the described ultrasound imaging probe and system have not been detailed, and the embodiments are compatible with common applications of ultrasound imaging probes. Furthermore, the characteristics (frequency, shape, amplitude, etc.) of the electrical excitation signal applied to the ultrasound transducer have not been detailed, and the described embodiments are compatible with excitation signals commonly used in ultrasound imaging systems, which can be selected according to the application under consideration, particularly the nature of the subject to be analyzed and the type of information desired to be acquired. Similarly, the various processing operations applied to the electrical signals provided by the ultrasound transducer and read by the control circuitry to extract useful information related to the subject to be analyzed have not been detailed, and the described embodiments are compatible with processing operations commonly used in ultrasound imaging systems. Moreover, the formation of the ultrasound transducer and the electronic circuitry for controlling the transducer is not described in detail; based on the indications of this disclosure, known ultrasound transducer and electronic circuitry manufacturing techniques are used, and detailed implementations of these elements are within the capabilities of those skilled in the art.

[0036] Unless otherwise stated, when referring to two elements being connected to each other, it means a direct connection without any intermediate elements other than a conductor; and when referring to two elements being coupled to each other, it means that the two elements can be connected directly or via one or more other elements.

[0037] In the following description, when referring to absolute position qualifiers, such as the terms “front,” “back,” “top,” “bottom,” “left,” “right,” etc., or relative position qualifiers, such as the terms “top,” “bottom,” “up,” “down,” etc., or direction qualifiers, such as “horizontal,” “vertical,” etc., reference should be made to the orientation of the accompanying drawings unless otherwise stated.

[0038] Unless otherwise stated, expressions such as “approximately,” “roughly,” “basically,” and “about” indicate plus or minus 10%, and preferably plus or minus 5%.

[0039] Figure 1 This is a perspective view schematically and partially illustrating an example of an ultrasound imaging system according to an embodiment.

[0040] Figure 1The system comprises an ultrasound imaging probe 100 intended to be electrically coupled to an external control and processing device 160, for example a computer, via an electrical connection cable 150.

[0041] The probe 100 comprises a plurality of elementary ultrasound transducers and electronic circuits for controlling the transducers.

[0042] In operation, all the ultrasound transducers of the probe are arranged in front of the subject whose image is desired to be acquired. The electronic control circuit is configured to apply electrical excitation signals to the transducers so as to cause them to emit ultrasound waves towards the subject to be analyzed. The ultrasound waves emitted by the transducers are totally or partially reflected by the subject to be analyzed (by its internal and / or surface structure) and then return to the transducers which convert them back into electrical signals. These electrical response signals are read, digitized and pre-processed by the electronic control circuit. The digital output signals of the electronic control circuit are transmitted to the external device 160 via the connection cable 150. These signals can be stored and analyzed by the external device 160 to obtain information related to the subject under study.

[0043] For example, the probe 100 is a portable probe intended to be manually positioned and moved on the patient.

[0044] In the example of Figure 1 The ultrasound imaging probe 100 comprises a stack of an ultrasound transduction circuit 110, a transceiver circuit 120 and a digital pre-processing circuit 130.

[0045] For example, the circuits 110, 120 and 130 are arranged together in a housing (not shown) of the probe.

[0046] The ultrasound transduction circuit 110 comprises a plurality of elementary ultrasound transducers (not shown in detail in the drawings), for example arranged in an array of rows and columns. As an example, the ultrasound transduction circuit 110 comprises several thousands to several hundreds of thousands of individually addressable elementary ultrasound transducers, for example approximately one hundred thousand elementary ultrasound transducers.

[0047] More specifically, in this example, the ultrasound transduction circuit 110 comprises an array of AxB identical (within manufacturing dispersion) or similar elementary ultrasound transduction chips 111. In the illustrated example, A=B=4. The described embodiments are not limited to this particular case. As a variant, A can be different from B, A and B can be different from 4. As an example, A can be greater than 10, for example in the range of 10 to 100, or even greater than 100. Similarly, B can be greater than 10, for example between 10 and 100, or even greater than 100. As an example, A=120 and B=60.

[0048] Each chip 111 comprises an array of CxD identical (within the manufacturing dispersion) or similar elementary transducers 113, which are bonded on the sides and on the top of a same support substrate made for example of silicon. As an example, each chip 111 comprises from several tens to several thousands of elementary ultrasonic transducers 113. For example, C=D=32, so that each elementary chip 111 comprises 1024 elementary ultrasonic transducers.

[0049] As an example, in each elementary chip 111, the pitch between transducers is of the order of several tens to several hundreds of micrometers in the row direction and in the column direction, for example of the order of 150 pm in the row direction and in the column direction.

[0050] The elementary chips 111 are preferably bonded together so as to maintain the same or substantially the same pitch between transducers as the internal pitch of the chip in the considered direction between two adjacent transducers of two adjacent elementary chips 111.

[0051] The elementary transducers of the chip 111 are for example transducers of the CMUT (Capacitive Micromachined Ultrasonic Transducer) type, piezoelectric transducers of the PMUT (Piezoelectric Micromachined Ultrasonic Transducer) type, piezoelectric crystal transducers or any other type of ultrasonic transducer.

[0052] Each elementary transducer comprises two electrodes which enable the application of an electrical excitation signal to the transducer and the reading of an electrical response signal of the transducer. As an example, the elementary transducers of each chip 111 are individually controllable. To this end, each elementary chip 111 comprises a CxD array of individual contact metallizations, for example electrically insulated from each other, connected respectively to a first electrode of each of the CxD elementary transducers of the chip. Each chip 111 can also comprise a common contact metallization connected to a second electrode of each of the CxD elementary transducers of the chip.

[0053] In the illustrated example, the ultrasonic transducer circuit 110 comprises a support and interconnection structure 115, for example a rigid or flexible printed circuit board, on which the elementary ultrasonic transducer chips 110 are attached and electrically connected. As an example, the elementary chips 111 are surface-mount chips (or flip-chips) whose all contact metallizations are arranged on one side of a same surface of the chip, called connection surface, the lower surface in the example of the figure. Figure 1 The support and interconnection structure 115 is for example a board made of a stack of metal and insulating layers (not detailed in the figure) in which conductive elements forming an interconnection network (not shown in the figure) are formed. The structure 115 comprises for example on one side of the surface (the lower surface in the example of the figure) a CxD array of individual contact metallizations, for example pads, connected to the contact metallizations of the elementary chips 111. Figure 1A set of contact metallizations (on the upper surface of the chip 111) is designed to attach and electrically connect to the contact metallizations of the chip 111. As an example, the chip 111 is formed parallel to the interior and / or top of one or more semiconductor substrates (e.g., made of silicon), and then the one or more substrates are cut to separate the chip 111. The chip 111 is then attached and electrically connected to the structure 115 via its contact metallizations, for example, by using a pick-and-place tool. During this step, the contact metallizations of the chip 111 are positioned relative to the corresponding contact metallizations on the upper surface of the support and interconnect structure 115.

[0054] For each basic ultrasonic transducer chip 111, the transceiver circuit 120 includes a basic transceiver chip 121. For each basic ultrasonic transducer 113 of chip 111, chip 121 includes a basic transceiver unit 123 electrically connected to the electrodes of the basic ultrasonic transducer to allow individual control of the transducer during transmission and reception. The following will be combined with... Figure 2 Examples of embodiments of the basic transceiver unit 123 are described in more detail below.

[0055] Therefore, circuit 120 includes an array of AxB basic transceiver chips 121, each basic chip 121 including an array CxD of basic transceiver units 123.

[0056] As an example, each basic transceiver chip 121 on the first connection surface ( Figure 1 The upper surface of the transceiver chip 111 includes an array of CxD contact metallizations (not shown), which are connected to the CxD base transducers of the corresponding chip 111 via support and interconnect structures 115. For example, transceiver chip 121 is attached to and electrically connected to the surface of structure 115 opposite to chip 111, i.e., on the upper surface of the transceiver chip 121. Figure 1 The lower surface is represented in the diagram. As an example, structure 115 includes a conductive via for each basic transceiver of circuit 110, which individually electrically connects the electrodes of the transceiver to the corresponding basic transceiver unit of circuit 120.

[0057] In each basic transceiver chip, basic transceiver unit 123 is divided into multiple basic transceiver groups, each basic transceiver group comprising N basic transceiver units, where N is an integer, for example, greater than or equal to 4. In this example, each basic transceiver unit 123 belongs to one and only one basic transceiver group. Therefore, in this example, each basic transceiver chip 121 comprises CxD / N basic groups, each basic group consisting of N basic units. For example, the N basic units in each group are adjacent. For example, the N basic units in each group are arranged in rows, columns, or arrays. As a non-limiting example, N equals 16.

[0058] Each basic chip 121 also includes a switching circuit 125 for each basic group.Figure 2 ), i.e. a CxD / N switch circuit 125. The switch circuit 125 comprises a programmable switch array network with N inputs to M outputs, where M is an integer, for example greater than or equal to 2 and less than N. As an example, M is equal to 4. For example, the switch circuit 125 is adapted to supply on each of its M output terminals an analog sum or superposition of all or part of the signals applied to its N input terminals. In other words, the circuit 125 implements a selector-combiner function. In this example, the input and output signals of the switch circuit 125 are analog signals, for example voltages.

[0059] Each basic transceiver chip 121 also comprises M analog-to-digital conversion circuits 127 per sum circuit 125 Figure 2 ), the M analog-to-digital conversion circuits 127 being connected respectively to the M output terminals of the switch circuit. Thus, each transceiver chip 121 comprises (CxD / N)xM analog-to-digital conversion circuits 127 (ADC). Each analog-to-digital conversion circuit comprises an analog input terminal coupled (for example connected) to an output terminal of the switch circuit 125 and a digital output terminal providing a serialized binary digital signal, for example over 8, 10 or 12 bits, representative of the signal applied to its analog input terminal. Thus, each basic transceiver chip 121 comprises (CxD / N)xM digital output terminals.

[0060] As an example, each basic transceiver chip 121 comprises, on one side of the lower surface of the second connection surface (S2) Figure 1 , (CxD / N)xM contact metallizations e2 coupled (for example connected) to the digital output terminals of the (CxD / N)xM analog-to-digital converters 127 of the chip. Each chip 121 comprises for example a silicon substrate, for example monocrystalline, the inside and the top of which are integrated with the chip components, electrically conductive vias extending vertically through the substrate laterally insulated (TSV - Through Silicon Via) and coupling the lower surface metallization e2 to the upper surface metallization of the chip.

[0061] As an example, the transceiver chips 121 are formed in parallel inside and / or on the top of one or more semiconductor substrates, for example made of silicon, after which the one or more substrates are cut into basic chips 121. The chips 121 are then attached and electrically connected to the lower surface of the structure 115 by their contact metallizations, for example by using a pick-and-place tool. During this step, the contact metallizations on the upper surface of the chips 121 are positioned relative to the corresponding contact metallizations of the lower surface of the support and interconnection structure 115.

[0062] For each basic transceiver chip 121 of the analog transceiver circuit 120, the digital pre-processing circuit 130 comprises a basic digital pre-processing chip 131.

[0063] For each basic transceiver group of the corresponding basic transceiver chip 121, each chip 131 includes M basic digital preprocessing units 133, which are respectively coupled (e.g., respectively connected) to the output terminals e2 of the M analog-to-digital converters associated with the basic transceiver group.

[0064] Therefore, circuit 130 includes an array of AxB basic digital preprocessing chips 131, each basic chip 131 including a set of (CxD / N)xM basic digital preprocessing units 133, for example arranged in an array.

[0065] The following will combine Figure 3 Examples of embodiments of the basic digital preprocessing chip 131 are described in more detail below.

[0066] In this example, each basic digital preprocessing chip 131 includes a single output terminal e3 ( Figure 3 ), designed to provide serialized binary digital signals. Each chip 131 also includes a serialization circuit 301 ( Figure 3 ), which couples each output node of the (CxD / N)xM basic units 133 of the chip to a single digital output terminal of the chip.

[0067] As an example, each basic digital preprocessing chip 131 is on the first connection surface ( Figure 1 The upper surface of the chip 121 includes an array (not shown) of (CxD / N)xM contact metallized terminals e2 of the (CxD / N)xM analog-to-digital converters respectively connected to the corresponding chip 121. Each analog preprocessing chip 131 is, for example, directly attached to and electrically connected to the lower surface of the associated transceiver chip 121. As an example, the spacing between chips 121 (the center-to-center distance between two adjacent chips 121) is the same as the spacing between chips 131 in both the row and column directions.

[0068] In each basic digital preprocessing chip 131, the chip's digital output terminal e3 is connected, for example, to a contact metallization disposed on the side of the chip opposite to the analog transceiver chip 121 (i.e., on the lower surface of chip 131). Each chip 131 includes, for example, a silicon substrate, such as a single crystal, in which chip components are integrated internally and on top, and TSV-type lateral insulating conductive vias extend vertically through the substrate and couple the lower surface metallization of the chip to the upper surface metallization.

[0069] As an example, the digital pre-processing chips 131 are formed in parallel inside and / or on top of one or more semiconductor substrates, for example made of silicon, after which the one or more substrates are cut into the elementary chips 131. Then, the chips 131 are attached and electrically connected to the lower surface of the chip 121 via their contact metallization. During this step, the contact metallization on the upper surface of the chips 131 is positioned opposite the corresponding contact metallization on the lower surface of the chip 121.

[0070] The probe 100 is intended to be electrically coupled to an external control and processing device 160, for example a computer, via a digital data transmission channel, for example an electrical connection cable 150. More particularly, in this example, the electrical connection cable 150 comprises a single wire per elementary digital pre-processing chip 131 for transmitting serialized 1-bit digital data 151, the wire being electrically connected to the digital output terminal e3 of the chip. As a variant, the terminal e3 can be replaced by any other connection element adapted to provide a 1-bit serialized digital signal, for example a pair of differential terminals. The wire 151 can be replaced by any wired element for transmitting 1-bit serialized digital data, for example a shielded coaxial cable or a twisted pair. As a variant, the digital data transmission wire can be replaced by an optical fiber. In this case, an electrical-to-optical conversion assembly can be provided between the terminal e3 and the wire 151, for example via the card 115.

[0071] Thus, in this example, the cable 150 comprises only AxB elementary wires for transmitting the digital output data 151 from the probe, the AxB elementary wires being respectively connected to the digital output terminals e3 of the AxB elementary digital pre-processing chips 131 of the probe.

[0072] The cable 150 can also comprise wires for transmitting signals to power the circuits of the probe 100.

[0073] The cable 150 can also comprise wires for transmitting electrical control signals for the circuits of the probe 100.

[0074] Preferably, the electrical signals for controlling the probe and the digital output data signals of the probe are transmitted by the same AxB wires 151 and are transmitted by the digital pre-processing chips 131.

[0075] Figure 2 An example of an embodiment of the circuit of the elementary chip 121 of the analog transceiver circuit 120 of the probe 100 is schematically and partially illustrated Figure 1

[0076] Figure 2 ​A basic transceiver unit 123, a switching circuit 125 and an analog-to-digital converter 127 are shown. As mentioned above, each chip 121 actually comprises CxD basic units 123, CxD / N switching circuits 125 and (CxD / N)xM analog-to-digital converters 127.

[0077] In this example, each basic transceiver unit 123 comprises a transmit circuit 210, a receive circuit 220 and a switching circuit 230 (T / R SW).

[0078] The transmit circuit 210 is adapted to apply an electrical excitation signal to the corresponding basic transducer 113 during an ultrasonic wave transmission phase. The receive circuit 220 is adapted to condition and amplify the electrical response signal generated by the transducer 113 during an ultrasonic wave reception phase.

[0079] The transmit circuit 210 comprises an output terminal nl, which is intended to be coupled (e.g. connected) to the electrode el of the associated transducer 113. In this example, the transmit circuit 210 comprises a pulse generator TX having an input node in, which is intended to receive a logic control signal, and an output node out, which is coupled (e.g. connected) to the terminal nl. The input node in of the pulse generator TX can be coupled (e.g. connected) to an output node of a control logic circuit (not shown) of the probe. When the logic signal applied to the input node in of the generator TX is in a first state, the generator TX provides a high level voltage on its output node out, while when the logic signal applied to the node in of the generator TX is in a second state, the generator TX provides a low level voltage to its output node out. The output signal of the pulse generator TX corresponds to the signal for exciting the transducer 113, which can be directly applied to the electrode el of the transducer.

[0080] As a variant, the pulse generator TX is adapted to provide on its output node a plurality of different voltage levels generated from the same supply voltage HV. Then, the pulse generator TX is adapted to generate an excitation signal, the shape of which can be controlled by a control signal applied on a plurality of bits of its input end in.

[0081] The receive circuit 220 comprises an input terminal n2, which is intended to be coupled (e.g. connected) to the electrode el of the transducer 113, and an output node n3, which is intended to be coupled (e.g. connected) to one of the N input nodes of the switching circuit 125 of the basic transceiver group to which the unit 123 belongs.

[0082] In this example, the receiver circuit 220 comprises a receive amplifier 221, preferably a low noise amplifier (LNA), having an input node coupled to terminal n2 and an output node coupled to terminal n3. The amplifier 221 is, for example, a linear amplifier. Moreover, in this example, the receive circuit 220 further comprises a time gain control (TGC) circuit 223 between terminal n2 and the input of amplifier 221. The circuit 223 is configured to apply a time-varying analog gain to the transducer response signal applied to terminal n2 during the reception phase. More particularly, during the phase in which the transducer 113 receives the returning ultrasound waves, the circuit 223 applies a gain to the transducer response signal that gradually increases over time, and thus as a function of the depth of the probe region, to compensate for the attenuation of the ultrasound signal by the probe medium. This enables to fully exploit the dynamic characteristics of the analog-to-digital converter 127 during the entire reception phase, thereby limiting the quantization noise introduced by the analog-to-digital converter 127, in particular for the farthest ultrasound echoes. As a variant, not shown, the time gain control circuit 223 can be placed between the output of amplifier 221 and the output terminal n3 of the receive circuit 220. In another variant, not shown, the time gain control circuit can be omitted and the amplifier 221 can be replaced by a non-linear amplifier.

[0083] In Figure 2 In the example shown, the transmit circuit 210 further comprises a transmit pulse shaper 212, for example a low-pass filter, coupled between the output terminal n1 of the pulse generator TX and the input of the amplifier 221. As a variant, the transmit pulse shaper 212 can be placed between the output of the amplifier 221 and the output terminal n1 of the transmit circuit 210.

[0084] In each elementary transceiver unit 123, the switch circuit 205 is adapted to electrically connect the electrode el of the associated elementary transducer 113 either to the output terminal n1 of the transmit circuit 210 or to the input terminal n2 of the receive circuit 220. As an example, the switch circuit 205 comprises a first switch K1 having a first conductive node coupled, for example connected, to the electrode el and a second conductive node coupled, for example connected, to terminal n1, and a second switch K2 having a first conductive node coupled, for example connected, to the electrode el and a second conductive node coupled, for example connected, to terminal n2.

[0085] The signal for controlling the shape of the transmit pulse applied to the input end in of the pulse generator TX is, for example, generated by a control circuit (not shown) internal to the probe 100, or transmitted by a dedicated wire (not shown) of the cable 150.

[0086] As a variant, the pulse shape control signal applied to the input end in of the pulse generator TX is transmitted via the data transmission line 151 (not shown) of the cable 150. Figure 1), the basic digital pre-processing chip 131 and the switching circuit 125. To this end, additional routing circuitry, not described in detail, can be provided in the transceiver chip 121, in particular in the basic transceiver unit 123.

[0087] Similarly, the signal for controlling the delay applied by the analog circuit 225 to the electrical response signal of the ultrasound transducer is generated, for example, by a control circuit (not shown) internal to the probe 100, or is transmitted by a dedicated wire (not shown) of the cable 150. Similarly, the signal for controlling the circuit 223 can be generated by a control circuit (not shown) internal to the probe 100, or is transmitted by a dedicated wire (not shown) of the cable 150.

[0088] As a variant, the signal for controlling the delay applied by the analog circuit 225 is transmitted by the data transmission line 151 (D) Figure 1 ), the basic digital pre-processing chip 131 and the switching circuit 125, to limit the number of wires in the cable 150.

[0089] Figure 3 An example of an embodiment of the basic digital pre-processing chip 131 of the digital pre-processing circuit 130 of the probe 100 is schematically and partially shown Figure 1 .

[0090] Figure 3 The basic chip 131 comprises a plurality of basic digital pre-processing units 133 (PE). In Figure 3 , 16 basic units 133 arranged in an array are shown. In practice, each basic chip 131 comprises (CxD / N)xM basic units 133, for example arranged in an array.

[0091] Figure 3 A zoomed and more detailed view of a unit 133 is further shown in

[0092] The basic chip 131 further comprises a serialization circuit 301 (SERDES) coupling the individual output nodes of the (CxD / N)xM basic units 133 of the chip to a single digital output terminal e3 of the chip. As an example, each basic unit 133 comprises a digital output node n4 coupled, for example connected, to a specific input terminal of the circuit 301 via a data transmission bus 305. The circuit 301 thus receives in parallel the digital signals provided by the (CxD / N)xM basic units 133 on their respective nodes n4 and provides a serialized digital signal to the single output terminal e3 of the chip.

[0093] The circuit 301 can also be adapted to implement a deserialization function to transmit in parallel on the nodes n4 of the (CxD / N)xM basic units 133 of the chip the serialized control signal applied to the terminal e3.

[0094] The basic chip 131 also comprises a global control circuit 303 (GCTRL) coupled (e.g. connected) via one or more control buses 307 to the respective control nodes n5 of the (CxD / N)xM basic units 133. The global control circuit 303 is adapted to control the execution of a sequence of operations by the digital pre-processing basic units 133 according to a program specified in a memory of the circuit 303. The circuit 303 sends the signals necessary for the basic units 133 to perform the requested operations.

[0095] Each digital pre-processing element unit 133 comprises a basic storage circuit 311 (MEM) adapted to store, for example, control data and data supplied by the analog-to-digital converter 127 connected to the unit 131. By way of example, the basic storage circuit 311 is adapted to store data read from the nodes e2, n4 and / or n5 of the unit, or to write data to the nodes e2, n4 and / or n5 of the unit.

[0096] Each basic digital pre-processing unit 133 can also comprise a basic computation unit 313 adapted to implement a computation operation having as operands data stored in the basic storage circuit 311 of the unit. By way of example, the basic computation unit 313 is adapted to implement a computation operation of the type of a sum, a difference, a product, a quotient or other types of operations, such as minimum or maximum type operations. Figure 3 In the example shown, the basic computation unit 313 is an arithmetic and logic unit adapted to implement various arithmetic computation operations, such as addition, subtraction, multiplication, division or other types of operations, such as minimum or maximum type operations.

[0097] In this example, each basic digital pre-processing unit 133 also comprises a data input / output port 315, so as to enable the exchange of data between the basic storage circuit 311 of the unit and the basic storage circuit 311 of an adjacent basic unit 133 of the unit, for example according to a sequence controlled by the global control circuit 303 of the chip. Here, an adjacent unit means a unit adjacent in the direction considered or separated by a number of units significantly smaller than the total number of units of the circuit 131, for example a unit separated by at most one unit (i.e. a direct neighbor of a direct neighbor) or at most two units (i.e. a direct neighbor of a direct neighbor of a direct neighbor).

[0098] In combination with the above-described advantages, the described ultrasound imaging probe 100 has the advantage of combining a compact electronic control circuit, which enables the implementation of microbeamforming within the framework of an ultrarapid acquisition scenario, thereby greatly limiting the number of wires necessary to couple the probe to an external processing device (e.g. a computer). Figures 1 to 3 By way of example, during the phase of acquisition of the data features of the subject to be analyzed, ultrasound waves are first transmitted to the subject to be analyzed during a transmission phase, and then the return ultrasound waves reflected by the subject to be analyzed are measured during a reception phase.

[0099]

[0100] ​During the transmit phase, the transceiver units 123 are controlled in parallel, for example, to transmit an ultrasonic excitation pulse, for example, in the form of a plane wave, to the body to be analyzed. As an example, during the transmit phase, also referred to as ultrasonic wave transmission, all elementary transducers 113 can be controlled simultaneously in the same way (via the respective associated transmit circuit 210).

[0101] During the receive phase, within a predetermined duration of an acquisition time window, the acoustic signals reflected by the surface or internal structure of the body to be analyzed are measured by means of each elementary transducer 113 (via the respective associated receive circuit 220).

[0102] The sum of the response signals provided on the output nodes n3 of the receive circuits 220 of the transceiver units 123 of each elementary transducer group of each chip 121 is achieved by the switching circuit 125, thereby performing a micro-beamforming at the elementary group level. For example, the delay law applied in the different elementary groups by the circuit 225 of each group is the same. This results in a relatively low memory storage requirement for storing the delays.

[0103] After digitization by the analog-digital conversion circuit 127, the signals provided by the various combiner circuits 125 can undergo various conditioning processing operations in the digital pre-processing chip 131 before being transmitted to a processing device outside the probe via the cable 150. As an example, in each elementary digital pre-processing unit 133, the storage circuit 311 of this unit is adapted to store several hundred samples of the output signal of the associated analog-digital converter 127, for example, more than 256 samples, for example, from several thousand to several ten-thousand samples, for example, from 1000 to 100000 samples. As an example, the storage circuit 311 is adapted to store the complete signal provided by the analog-digital converter 127 during the reception window following the ultrasonic wave transmission. The storage circuit 311 can be adapted to store the complete signals provided by the analog-digital converter 127 during a plurality of reception windows following a respective plurality of ultrasonic wave transmissions.

[0104] The external processing device 160 outside the probe 100 can apply further delays, referred to as macro delays, to perform a macro-beamforming operation by combining the signals provided by the various analog-digital converters 127.

[0105] As an example, each elementary group of transceiver units 123 addresses one and only one column of ultrasonic transducers 113 of the associated ultrasonic transducer chip 111. For example, the delay law applied in the different elementary groups is the same. In each column, the delay law applied by the circuit 225 of this column is selected, for example, to direct or focus the reception in a fixed elevation point in the plane of this column. As an example, the reception is focused in the same elevation in all columns.

[0106] Then, after the acquisition outside the probe (macro-beamforming operation), other combinations can be performed with the aid of the external device 160 to focus the reception on different azimuths of the elevation line set at the time of acquisition.

[0107] Therefore, implementing the micro-beamforming operation inside the probe enables to trade-off the amount of data to be transmitted outside the probe, implementing various complete acquisition scenarios with great flexibility.

[0108] It should be noted that the described embodiments are not limited to the example in which the above-mentioned ultrasound transduction circuit 110, transceiver circuit 120 and digital pre-processing circuit 130 are vertically stacked.

[0109] In view of the large number of electrical connections between the circuits 110 and 120, the circuits 110 and 120 are preferably vertically stacked on either side of the interconnection structure 115. The digital pre-processing circuit 130 can be laterally offset.

[0110] Figure 4 is a cross-sectional view schematically and partially showing an alternative embodiment of the ultrasound imaging system of Figure 1 .

[0111] In this variant, the ultrasound transduction circuit 110 and the transceiver circuit 120 are vertically stacked on either side of the interconnection support 115, similarly to what described above in connection with Figure 1 .

[0112] In the variant of Figure 4 , the interconnection support 115 laterally extends beyond the circuits 110 and 120. The digital pre-processing circuit 130 is attached and electrically connected to the surface of the interconnection support 115, close to the circuit 110 or 120. In the example shown, the circuit 130 is on the same side of the support 115 as the circuit 120, that is, on the lower surface side of the support 15 in the orientation of the drawing. The circuit 130 is coupled to the circuit 120 through the electrically conductive tracks of the interconnection support 115.

[0113] The conductors 151 of the cable 150 are connected, for example, on the side of the surface of the substrate 115 opposite the circuit 130, in perpendicular alignment with the circuit 130.

[0114] In the example shown, the interconnection support 115 is substantially planar. As a variant not shown, the interconnection support 115 can be folded so that the connection plane of the circuit 130 forms an angle, for example of about 90°, with the connection planes of the circuits 110 and 120. This allows different arrangements of the circuits, for example to facilitate heat dissipation.

[0115] Figure 5 is a cross-sectional view schematically and partially showing another variant of the ultrasound imaging system of Figure 1 .

[0116] In this variant, the digital pre-processing circuit 130 is attached next to the transceiver circuit 120, on the same surface of the interconnection support 115 as the transceiver circuit 120, similarly to the combination Figure 4 described. The interconnection support 115 is then folded by 180° so as to place the circuit 130 opposite the circuit 120 and obtain a vertical stack of the circuits 110, 120 and 130.

[0117] Various embodiments and variants have been described. The person skilled in the art will understand that certain features of these various embodiments and variants can be combined, other variants will become apparent to the person skilled in the art. In particular, the described embodiments are not limited to the numerical examples mentioned in the present specification.

[0118] Moreover, as a variant, the analog-to-digital converter 127 can be incorporated in the base chip 131 of the circuit 130, instead of the base chip 121 of the circuit 120.

[0119] Moreover, as a variant, the number N of base transceiver units 123 in each base transceiver group of each base transceiver chip 121 can be less than 4, even equal to 1 (i.e. a single base transceiver unit 123 per base group).

[0120] Moreover, as a variant, in each base transceiver chip 121, the number M of outputs of the switching circuit 125 can be equal to N.

[0121] In the above example, the analog pre-processing circuit integrated in each transceiver chip 121, in particular comprising the switch 125, implements an analog beamforming process enabling to reduce the number of input channels of the digital pre-processing circuit 131. As a variant, other analog processing operations can be implemented within the chip 121, in replacement or in complement of the beamforming processing. In the case where N is equal to 1, the switching circuit 125 can be omitted. In the case where N is equal to 1, the analog pre-processing circuit can be integrated in the base chip 131 of the digital pre-processing circuit 130.

[0122] Moreover, in the above example, each base chip 131 of the digital pre-processing circuit comprises a single output terminal or a single element e3 for providing a binary data signal. The described embodiments are not limited to this particular case. As a variant, the number of output terminals or binary connection elements e3 of each base chip 131 can be different from 1. Preferably, the number of output terminals or binary connection elements e3 of each base chip 131 is less than the number of base digital pre-processing units 133 of the chip.

Claims

1. An ultrasonic imaging probe (100), comprising a first circuit (110), a second circuit (120), and a third circuit (130), wherein: - The first circuit (110) is an ultrasonic transducer circuit including an array of basic ultrasonic transducer chips (111), each basic ultrasonic transducer chip including an array of basic ultrasonic transducers (113). - The second circuit (120) is a transceiver circuit. For each basic ultrasonic transducer chip (111), the transceiver circuit includes a corresponding specific basic transceiver chip (121). For each basic ultrasonic transducer (113) of the basic ultrasonic transducer chip (111), the specific basic transceiver chip includes a basic transceiver unit (123) electrically connected to an electrode (e1) of the transducer (113). - In each basic transceiver chip (121), the basic transceiver units (123) of the chip are distributed into multiple basic transceiver groups, each basic transceiver group including N basic transceiver units (123), where N is an integer greater than or equal to 1; - For each basic transceiver chip (121), for each basic transceiver group of the chip, the probe includes an analog preprocessing circuit (125), the analog preprocessing circuit including N input terminals and M output terminals, the N input terminals being respectively connected to the output terminals (n3) of each basic transceiver unit (123) of the basic transceiver group, where M is less than or equal to N; - For each basic transceiver group of each basic transceiver chip, the probe includes M analog-to-digital converters (127), each having an input terminal and an output terminal (e2), the input terminals of the M analog-to-digital converters (127) being connected to the M output terminals of the analog preprocessing circuit (125) of the basic transceiver group respectively; - The third circuit (130) is a digital preprocessing circuit. For each basic transceiver chip (121), the digital preprocessing circuit includes a corresponding specific basic digital preprocessing chip (131). For each basic transceiver group of the basic transceiver chips (121), the specific basic digital preprocessing chip includes M basic digital preprocessing units (133). The M basic digital preprocessing units are respectively connected to the output terminals of the M analog-to-digital converters (127) associated with the basic transceiver group. - Each basic digital preprocessing chip (131) includes one or more binary connection elements (e3), each binary connection element being designed to provide serialized digital signals coupled to all basic digital preprocessing units of the chip via one or more serialization circuits (301). Each basic digital preprocessing unit (133) includes a basic storage circuit (311) and a computing unit (313). Furthermore, each basic digital preprocessing chip (131) includes a global control circuit (303) connected to the corresponding control nodes of the MxN basic digital preprocessing units (133) of the chip (131) and adapted to control the execution of the basic digital preprocessing units (133) of the chip (131) for a sequence of operations.

2. The probe (100) according to claim 1, wherein, In each basic digital preprocessing unit (133), the basic storage circuit (311) is adapted to store the complete signal provided by the corresponding analog-to-digital converter (127) during the reception time window after the ultrasonic wave is emitted.

3. The probe (100) according to claim 1 or 2, wherein, Each analog preprocessing circuit (125) is a selector-combiner circuit adapted to provide, on each of its M output terminals, all or part of the analog sum or superposition of the signals applied to its N input terminals.

4. The probe (100) according to any one of claims 1 to 3, wherein, Each transceiver unit (123) includes a transmitting circuit (210) adapted to generate an electrical excitation signal applied to the electrode (e1) of the associated basic transducer (113).

5. The probe (100) according to any one of claims 1 to 4, wherein, Each transceiver unit (123) includes a receiving circuit (220) which includes an amplifier (221) having an input node coupled to an electrode (e1) of the basic transducer (113) and an output node coupled to an output terminal (n3) of the transceiver unit (123).

6. The probe (100) according to claim 5, wherein, In each transceiver unit (123), the receiving circuit (220) further includes a delay circuit (225) configured to apply a delay with an adjustable duration to the electrical output signal of the transducer (113).

7. The probe (100) according to claim 6, wherein, Each basic digital preprocessing unit (133) includes a data input-output port (315) that enables the exchange of data between the basic storage circuit (311) of the unit and the basic storage circuit (311) of the adjacent basic unit (133).

8. The probe (100) according to any one of claims 1 to 7, wherein, The first circuit (110), the second circuit (120) and the third circuit (130) are stacked vertically, with the second circuit (120) arranged between the first circuit (110) and the third circuit (130).

9. The probe according to any one of claims 1 to 7, wherein, Two circuits (110, 120) in the first circuit (110), the second circuit (120) and the third circuit (130) are stacked vertically, and the remaining circuit (130) in the first circuit (110), the second circuit (120) and the third circuit (130) are offset laterally.

10. The probe (100) according to any one of claims 1 to 9, wherein, M is strictly less than N.

11. An ultrasound imaging system comprising an ultrasound imaging probe (100) according to any one of claims 1 to 10, an external processing device (160), and a digital data transmission channel (150) coupling the probe to the external processing device (160).

12. The system according to claim 11, wherein, The digital data transmission channel (150) includes one or more electrical or optical data transmission line elements (151) of each basic digital preprocessing chip (131), which are electrically connected to the one or more binary connection elements (e3) of the basic chip, respectively.

13. The system according to claim 11 or 12, wherein, The external processing device (160) is configured to apply a delay and combine signals originating from the analog-to-digital converter (127).

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