Display substrate, working method thereof and display device

Abstract

A display substrate, a working method thereof, and a display device, the display substrate comprising a plurality of sub-pixels, at least one local driving circuit (60), at least one column control line (C-Gate), and at least one row control line (N-Gate), at least part of the sub-pixels may comprise a light emitting device and a pixel driving circuit (50) for driving the light emitting device to emit light, the pixel driving circuit (50) is connected with one of the local driving circuits (60); the local driving circuit (60) can be connected with at least one pixel driving circuit (50), one column control line (C-Gate) and one row control line (N-Gate), and is set to control the pixel driving circuit (50) connected with the local driving circuit (60) to work under the control of the column control line (C-Gate) and the row control line (N-Gate); the pixel driving circuit (50) is controlled by the local driving circuit (60) to drive the corresponding light-emitting device to maintain the original brightness or refresh the brightness.

Description

Display substrate, operating method thereof, and display device Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a working method thereof, and a display device. Background Art

[0002] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] In a first aspect, embodiments of the present disclosure provide a display substrate comprising a plurality of sub-pixels, at least one local drive circuit, at least one column control line, and at least one row control line, wherein at least some of the sub-pixels include light-emitting devices and a pixel drive circuit for driving the light-emitting devices to emit light, and the pixel drive circuit is connected to one of the local drive circuits;

[0006] The local driving circuit is connected to at least one pixel driving circuit, one of the column control lines and one of the row control lines, and is configured to control the operation of the pixel driving circuit connected thereto under the control of the column control line and the row control line; the pixel driving circuit drives the corresponding light-emitting device to maintain the original brightness or refresh the brightness under the control of the local driving circuit.

[0007] In an exemplary embodiment, the pixel driving circuits in the plurality of sub-pixels form a plurality of rows and a plurality of columns, the local driving circuit is located between two adjacent rows of pixel driving circuits, and the local driving circuit is connected to at least part of the pixel driving circuits in at least one row;

[0008] There are multiple local drive circuits, and the multiple local drive circuits form multiple rows and multiple columns. The row control line is connected to at least one row of local drive circuits and is configured to provide a row control signal to the local drive circuit connected thereto; the column control line is connected to at least one column of local drive circuits and is configured to provide a column control signal to the local drive circuit connected thereto.

[0009] In an exemplary embodiment, the local driving circuit is connected to n adjacent pixel driving circuits in a row of pixel driving circuits, where n is a positive integer; the row control line is connected to multiple local driving circuits in a row of local driving circuits; and the column control line is connected to multiple local driving circuits in a column of local driving circuits.

[0010] In an exemplary embodiment, the pixel driving circuit includes a compensation transistor, and the local driving circuit is configured to control the compensation transistor to be turned on or off under the control of the column control line and the row control line.

[0011] In an exemplary embodiment, the local driving circuit includes a first control transistor, a control electrode of the first control transistor is connected to the column control line, a first electrode of the first control transistor is connected to the row control line, and a second electrode of the first control transistor is connected to the control electrode of the compensation transistor.

[0012] In an exemplary embodiment, the local driving circuit is configured to provide a signal of the row control line to a control electrode of the compensation transistor or control the control electrode of the compensation transistor to maintain an original potential under the control of the column control line.

[0013] In an exemplary embodiment, the first control transistor is a P-type transistor, and the compensation transistor is an N-type transistor;

[0014] When the signal of the column control line is at the first level, the local driving circuit provides the signal of the row control line to the control electrode of the compensation transistor, and the compensation transistor is turned on or off under the control of the signal of the row control line. The pixel driving circuit drives the corresponding light-emitting device to maintain the original brightness or refresh the brightness under the control of the signal of the row control line;

[0015] When the signal of the column control line is at the second level, the compensation transistor is turned off under the control of the original potential, and the pixel driving circuit drives the corresponding light-emitting device to maintain the original brightness.

[0016] In an exemplary embodiment, the first control transistor and the compensation transistor are N-type transistors;

[0017] When the signal of the column control line is at the second level, the local driving circuit provides the signal of the row control line to the control electrode of the compensation transistor, and the pixel driving circuit drives the corresponding light-emitting device to maintain the original brightness or refresh the brightness under the control of the signal of the row control line;

[0018] When the signal of the column control line is at the first level, the compensation transistor is turned off under the control of the original potential, and the pixel driving circuit drives the corresponding light-emitting device to maintain the original brightness.

[0019] In an exemplary embodiment, the local driving circuit further includes a first capacitor, a first end of the first capacitor is connected to the constant voltage power line, and a second end of the first capacitor is connected to the second electrode of the first control transistor.

[0020] In an exemplary embodiment, the display substrate further includes a low-voltage power line, and the local driving circuit further includes a second control transistor, wherein a control electrode of the second control transistor is connected to the column control line, a second electrode of the second control transistor is connected to the control electrode of the compensation transistor, and a first electrode of the second control transistor is connected to the low-voltage power line;

[0021] The local driving circuit is configured to provide a signal of the row control line or a signal of the low-voltage power line to a control electrode of the compensation transistor under the control of the column control line.

[0022] In an exemplary embodiment, the first control transistor is a P-type transistor, and the compensation transistor and the second control transistor are N-type transistors;

[0023] When the signal of the column control line is at the first level, the local driving circuit provides the signal of the row control line to the control electrode of the compensation transistor, and the compensation transistor is turned on or off under the control of the signal of the row control line. The pixel driving circuit drives the corresponding light-emitting device to maintain the original brightness or refresh the brightness under the control of the signal of the row control line;

[0024] When the signal of the column control line is at the second level, the local driving circuit provides the signal of the low-voltage power line to the control electrode of the compensation transistor, the compensation transistor is disconnected under the control of the signal of the low-voltage power line, and the pixel driving circuit drives the corresponding light-emitting device to maintain the original brightness.

[0025] In an exemplary embodiment, when the signal of the column control line is at a first level and the row control line is at a second level during the reset phase and the threshold compensation phase of one working frame of the pixel driving circuit, the local driving circuit provides the signal of the row control line to the control electrode of the compensation transistor during the reset phase and the threshold compensation phase of one working frame of the pixel driving circuit. The compensation transistor is turned on under the control of the signal of the row control line, and the pixel driving circuit drives the corresponding light-emitting device to refresh the brightness in this working frame.

[0026] When the signal of the column control line is at the first level and the row control line is at the first level in an operating frame of the pixel driving circuit, the local driving circuit provides the signal of the row control line to the control electrode of the compensation transistor, and the compensation transistor is disconnected under the control of the signal of the row control line. The pixel driving circuit drives the corresponding light-emitting device to maintain the original brightness in this operating frame.

[0027] In an exemplary embodiment, the first control transistor and the compensation transistor are N-type transistors, and the second control transistor is a P-type transistor;

[0028] When the signal of the column control line is at the second level, the local driving circuit provides the signal of the row control line to the control electrode of the compensation transistor, and the compensation transistor is turned on or off under the control of the signal of the row control line. The pixel driving circuit drives the corresponding light-emitting device to maintain the original brightness or refresh the brightness under the control of the signal of the row control line;

[0029] When the signal of the column control line is at the first level, the local driving circuit provides the signal of the low-voltage power line to the control electrode of the compensation transistor, the compensation transistor is disconnected under the control of the low-voltage power line, and the pixel driving circuit drives the corresponding light-emitting device to maintain the original brightness.

[0030] In an exemplary embodiment, when the signal of the column control line is at the second level and the row control line is at the second level during the reset phase and the threshold compensation phase of one working frame of the pixel driving circuit, the local driving circuit provides the signal of the row control line to the control electrode of the compensation transistor during the reset phase and the threshold compensation phase of one working frame of the pixel driving circuit. The compensation transistor is turned on under the control of the signal of the row control line, and the pixel driving circuit drives the corresponding light-emitting device to refresh the brightness in this working frame.

[0031] When the signal of the column control line is at the second level and the row control line is at the first level in an operating frame of the pixel driving circuit, the local driving circuit provides the signal of the row control line to the control electrode of the compensation transistor, and the compensation transistor is disconnected under the control of the signal of the row control line. The pixel driving circuit drives the corresponding light-emitting device to maintain the original brightness in this operating frame.

[0032] In an exemplary embodiment, the display substrate further includes a low voltage power supply line, and the local driving circuit includes a first control transistor and a second control transistor;

[0033] The control electrode of the first control transistor is connected to the row control line, the first electrode of the first control transistor is connected to the column control line, and the second electrode of the first control transistor is connected to the control electrode of the compensation transistor;

[0034] The control electrode of the second control transistor is connected to the row control line, the first electrode of the second control transistor is connected to a low voltage power line, and the second electrode of the second control transistor is connected to the control electrode of the compensation transistor.

[0035] In an exemplary embodiment, the local driving circuit is configured to provide a signal of the column control line or a signal of the low voltage power line to a control electrode of the compensation transistor under the control of the row control line to control the compensation transistor to be turned on or off.

[0036] In an exemplary embodiment, the first control transistor is a P-type transistor, and the compensation transistor and the second control transistor are N-type transistors;

[0037] When the signal of the column control line is at the second level, the pixel driving circuit drives the corresponding light-emitting device to maintain the original brightness or refresh the brightness under the control of the row control line and the local driving circuit;

[0038] When the signal of the column control line is at the first level, the compensation transistor is turned off under the control of the signal of the column control line or the low voltage power line, and the pixel driving circuit drives the corresponding light emitting device to maintain the original brightness.

[0039] In an exemplary embodiment, when the signal of the column control line is at the second level and the row control line is at the first level during the reset phase and the threshold compensation phase of one working frame of the pixel driving circuit, the local driving circuit provides the signal of the column control line to the control electrode of the compensation transistor during the reset phase and the threshold compensation phase of one working frame of the pixel driving circuit. The compensation transistor is turned on under the control of the column control line, and the pixel driving circuit drives the corresponding light-emitting device to refresh the brightness in this working frame.

[0040] When the signal of the column control line is at the second level and the row control line is at the second level in an operating frame of the pixel driving circuit, the local driving circuit drops the signal of the low-voltage power line under the control of the row control line and provides it to the control electrode of the compensation transistor. The compensation transistor is disconnected under the control of the signal of the low-voltage power line, and the pixel driving circuit drives the corresponding light-emitting device to maintain the original brightness in this operating frame.

[0041] In an exemplary embodiment, the first control transistor and the compensation transistor are N-type transistors, and the second control transistor is a P-type transistor;

[0042] When the signal of the column control line is at the second level, the pixel driving circuit drives the corresponding light-emitting device to maintain the original brightness or refresh the brightness under the control of the row control line and the local driving circuit;

[0043] When the signal of the column control line is at the first level, the compensation transistor is turned off under the control of the signal of the column control line or the low voltage power line, and the pixel driving circuit drives the corresponding light emitting device to maintain the original brightness.

[0044] In an exemplary embodiment, when the signal of the column control line is at the second level and the row control line is at the second level during the reset phase and the threshold compensation phase of one working frame of the pixel driving circuit, the local driving circuit provides the signal of the column control line to the control electrode of the compensation transistor during the reset phase and the threshold compensation phase of one working frame of the pixel driving circuit. The compensation transistor is turned on under the control of the signal of the column control line, and the pixel driving circuit drives the corresponding light-emitting device to refresh the brightness in this working frame.

[0045] When the signal of the column control line is at the second level and the row control line is at the first level in an operating frame of the pixel driving circuit, the local driving circuit drops the signal of the low-voltage power line under the control of the row control line and provides it to the control electrode of the compensation transistor. The compensation transistor is disconnected under the control of the signal of the low-voltage power line, and the pixel driving circuit drives the corresponding light-emitting device to maintain the original brightness in this operating frame.

[0046] In an exemplary embodiment, the display substrate further includes a column additional control line and a high voltage power supply line, and the local driving circuit includes a first control transistor and a second control transistor;

[0047] The control electrode of the first control transistor is connected to the column control line, the first electrode of the first control transistor is connected to the row control line, and the second electrode of the first control transistor is connected to the control electrode of the compensation transistor;

[0048] The control electrode of the second control transistor is connected to the column additional control line, the first electrode of the second control transistor is connected to the high voltage power line, and the second electrode of the second control transistor is connected to the control electrode of the compensation transistor.

[0049] In an exemplary embodiment, the local driving circuit is configured to provide a signal of the row control line or a signal of the high-voltage power line to the control electrode of the compensation transistor under the control of the column control line and the column additional control line, thereby controlling the compensation transistor to be turned off or on, and the signal provided by the column control line is opposite to the signal provided by the column additional control line.

[0050] In an exemplary embodiment, the first control transistor, the second control transistor, and the compensation transistor are P-type transistors;

[0051] When the signal of the column control line is at the first level and the signal of the column additional control line is at the second level, the local driving circuit provides the signal of the row control line to the control electrode of the compensation transistor, and the compensation transistor is turned on or off under the control of the signal of the row control line. The pixel driving circuit drives the corresponding light-emitting device to maintain the original brightness or refresh the brightness under the control of the signal of the row control line;

[0052] When the signal of the column control line is at the second level and the signal of the column additional control line is at the first level, the local driving circuit provides the signal of the high-voltage power line to the control electrode of the compensation transistor, the compensation transistor is disconnected, and the pixel driving circuit drives the corresponding light-emitting device to maintain the original brightness.

[0053] In an exemplary embodiment, when the signal of the column control line is at the first level and the row control line is at the first level during the reset phase and the threshold compensation phase of one working frame of the pixel driving circuit, the local driving circuit provides the signal of the row control line to the control electrode of the compensation transistor during the reset phase and the threshold compensation phase of one working frame of the pixel driving circuit. The compensation transistor is turned on under the control of the signal of the row control line, and the pixel driving circuit drives the corresponding light-emitting device to refresh the brightness in this working frame.

[0054] When the signal of the column control line is at the first level and the row control line is at the second level in an operating frame of the pixel driving circuit, the local driving circuit provides the signal of the row control line to the control electrode of the compensation transistor, and the compensation transistor is disconnected under the control of the signal of the row control line. The pixel driving circuit drives the corresponding light-emitting device to maintain the original brightness in this operating frame.

[0055] In an exemplary embodiment, the display substrate further includes a row additional control line further including a high voltage power supply line, and the local driving circuit includes a first control transistor and a second control transistor;

[0056] The control electrode of the first control transistor is connected to the row control line, the first electrode of the first control transistor is connected to the column control line, and the second electrode of the first control transistor is connected to the control electrode of the compensation transistor;

[0057] The control electrode of the second control transistor is connected to the row additional control line, the first electrode of the second control transistor is connected to the high voltage power line, and the second electrode of the second control transistor is connected to the control electrode of the compensation transistor.

[0058] In an exemplary embodiment, the local driving circuit is configured to provide a signal of the column control line or a signal of the high-voltage power supply line to the control electrode of the compensation transistor under the control of the row control line and the row additional control line, thereby controlling the compensation transistor to be turned on or off, and the signal provided by the row control line is opposite to the signal provided by the row additional control line.

[0059] In an exemplary embodiment, the first control transistor, the second control transistor, and the compensation transistor are P-type transistors;

[0060] When the signal of the column control line is at the first level, the pixel driving circuit drives the corresponding light-emitting device to maintain the original brightness or refresh the brightness under the control of the row control line, the row additional control line and the local driving circuit;

[0061] When the signal of the column control line is at the second level, the compensation transistor is turned off under the control of the signal of the column control line or the high voltage power line, and the pixel driving circuit drives the corresponding light emitting device to maintain the original brightness.

[0062] In an exemplary embodiment, when the signal of the column control line is at the first level and the row control line is at the first level during the reset phase and the threshold compensation phase of one working frame of the pixel driving circuit, the local driving circuit provides the signal of the column control line to the control electrode of the compensation transistor during the reset phase and the threshold compensation phase of one working frame of the pixel driving circuit. The compensation transistor is turned on under the control of the signal of the column control line, and the pixel driving circuit drives the corresponding light-emitting device to refresh the brightness in this working frame.

[0063] When the signal of the column control line is at the first level and the row control line is at the second level in one working frame of the pixel driving circuit, the local driving circuit provides the signal of the high-voltage power line to the control electrode of the compensation transistor, the compensation transistor is disconnected under the control of the signal of the high-voltage power line, and the pixel driving circuit drives the corresponding light-emitting device to maintain the original brightness.

[0064] In an exemplary embodiment, the column control line is configured to control the refresh brightness of sub-pixels controlled by one or more column local drive circuits connected thereto; the row control line is configured to control the refresh brightness of sub-pixels controlled by one or more row local drive circuits connected thereto, the row control signal provided by the row control line includes a refresh brightness control signal and a maintain brightness control signal, and the column control signal provided by the column control line includes a refresh brightness control signal and a maintain brightness control signal;

[0065] The pixel driving circuit drives the corresponding light-emitting device to refresh the brightness when the row control signal of the row control line and the column control signal of the column control line connected to the local driving circuit are both control signals for refreshing the brightness; the pixel driving circuit drives the corresponding light-emitting device to maintain the original brightness when at least one of the row control signal of the row control line and the column control signal of the column control line connected to the local driving circuit is a control signal for maintaining the brightness.

[0066] In a second aspect, embodiments of the present disclosure provide an operating method for a display substrate, which is applied to the display substrate described in any of the above embodiments, wherein the display substrate includes a plurality of sub-pixels, at least one local driving circuit, at least one column control line, and at least one row control line, at least some of the sub-pixels include light-emitting devices and pixel driving circuits for driving the light-emitting devices to emit light, the pixel driving circuit being connected to one of the local driving circuits; the local driving circuit being connected to at least one pixel driving circuit, one of the column control lines, and one of the row control lines, the method comprising:

[0067] The local driving circuit controls the pixel driving circuit connected thereto to operate under the control of the column control line and the row control line. The pixel driving circuit drives the corresponding light-emitting device to maintain the original brightness or refresh the brightness under the control of the local driving circuit.

[0068] In a third aspect, an embodiment of the present disclosure provides a display device comprising the display substrate described in any of the above embodiments.

[0069] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0070] The accompanying drawings are intended to provide a further understanding of the technical solutions of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation of the technical solutions of the present disclosure. The shapes and sizes of each component in the drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure.

[0071] FIG1 is a schematic structural diagram of a display device;

[0072] FIG2 is a schematic structural diagram of a display device;

[0073] FIG3 is a schematic diagram showing a partial cross-sectional structure of a display area of ​​a display substrate;

[0074] FIG4 shows an equivalent circuit diagram of a pixel circuit;

[0075] FIG5 shows an equivalent circuit diagram of a pixel circuit;

[0076] FIG6 a is a schematic diagram showing a connection structure between a pixel driving circuit and a local driving circuit in a display substrate provided by an embodiment of the present disclosure;

[0077] FIG6 b is a schematic diagram showing a connection structure between a pixel driving circuit and a local driving circuit in a display substrate provided by an embodiment of the present disclosure;

[0078] FIG7 is an equivalent circuit diagram of a pixel driving device provided by an exemplary embodiment of the present disclosure;

[0079] FIG8 is a working timing diagram of a pixel driving device provided by an exemplary embodiment of the present disclosure;

[0080] FIG9 a is an equivalent circuit diagram of a pixel driving device provided by an exemplary embodiment of the present disclosure;

[0081] FIG9 b is an equivalent circuit diagram of a pixel driving device provided by an exemplary embodiment of the present disclosure;

[0082] FIG9 c is an equivalent circuit diagram of a pixel driving device provided by an exemplary embodiment of the present disclosure;

[0083] FIG10 is a working timing diagram of a pixel driving device provided by an exemplary embodiment of the present disclosure;

[0084] FIG11 is an equivalent circuit diagram of a pixel driving device provided by an exemplary embodiment of the present disclosure;

[0085] FIG12a is an equivalent circuit diagram of a pixel driving device provided by an exemplary embodiment of the present disclosure;

[0086] FIG12 b is an equivalent circuit diagram of a pixel driving device provided by an exemplary embodiment of the present disclosure;

[0087] FIG13 is a timing diagram showing an operation of a pixel driving device according to an exemplary embodiment of the present disclosure;

[0088] FIG14a is an equivalent circuit diagram of a pixel driving device provided by an exemplary embodiment of the present disclosure;

[0089] FIG14 b is a working timing diagram of a pixel driving device provided by an exemplary embodiment of the present disclosure;

[0090] FIG15 a is an equivalent circuit diagram of a pixel driving device provided by an exemplary embodiment of the present disclosure;

[0091] FIG15 b is a working timing diagram of a pixel driving device provided by an exemplary embodiment of the present disclosure;

[0092] FIG15c is an equivalent circuit diagram of a pixel driving device provided by an exemplary embodiment of the present disclosure;

[0093] FIG15 d is a working timing diagram of a pixel driving device provided by an exemplary embodiment of the present disclosure;

[0094] FIG15e is a working timing diagram of a pixel driving device provided by an exemplary embodiment of the present disclosure;

[0095] FIG16 is a schematic diagram showing a partial screen refresh method provided by an exemplary embodiment of the present disclosure;

[0096] FIG17 is a schematic diagram showing a flickering and split screen image in a display substrate;

[0097] FIG18a is a schematic diagram showing a basic connection structure between a pixel driving circuit and a local driving circuit in a display substrate provided by an exemplary embodiment of the present disclosure;

[0098] FIG18b is a schematic diagram showing a connection between a pixel driving circuit and a local driving circuit in a display substrate in a 1-drive-1 structure, provided by an exemplary embodiment of the present disclosure;

[0099] FIG18c is a schematic diagram showing a connection between a pixel driving circuit and a local driving circuit in a display substrate in a 1-drive-2 structure, provided by an exemplary embodiment of the present disclosure;

[0100] FIG18d is a schematic diagram showing a connection between a pixel driving circuit and a local driving circuit in a display substrate in a 1-drive-4 structure, provided by an exemplary embodiment of the present disclosure;

[0101] FIG18e is a schematic diagram showing a connection between a pixel driving circuit and a local driving circuit in a display substrate in a 1-drive-8 structure, provided by an exemplary embodiment of the present disclosure;

[0102] FIG18f is a schematic diagram showing a connection structure between a pixel driving circuit and a local driving circuit in a display substrate provided by an exemplary embodiment of the present disclosure;

[0103] FIG18g is a schematic diagram showing a connection structure between a pixel driving circuit and a local driving circuit in a display substrate provided by an exemplary embodiment of the present disclosure;

[0104] FIG19a is a schematic diagram showing a connection structure between a pixel driving circuit and a local driving circuit in a display substrate provided by an exemplary embodiment of the present disclosure;

[0105] FIG19 b is a schematic diagram showing a connection structure between a pixel driving circuit and a local driving circuit in a display substrate provided by an exemplary embodiment of the present disclosure;

[0106] FIG20 is a schematic diagram of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0107] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person skilled in the art can easily understand that the method and content can be transformed into other forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other in any manner.

[0108] In the drawings, the size of one or more components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of one or more components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0109] In this specification, ordinal numbers such as "first," "second," and "third" are provided to avoid confusion among constituent elements, and are not intended to limit the number. "Multiple" in this disclosure means two or more.

[0110] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the orientation of the constituent elements being described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced depending on the circumstances.

[0111] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed connections, removable connections, or integral connections; they can refer to mechanical connections or connections; they can refer to direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the meaning of these terms in this disclosure based on the circumstances.

[0112] In this specification, a transistor refers to a device that includes at least three terminals: a gate (gate electrode), a drain, and a source. A transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the drain, channel region, and source. In this specification, the channel region refers to the region through which current primarily flows.

[0113] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or the first electrode can be a source electrode and the second electrode can be a drain electrode. In addition, the gate electrode can also be called a control electrode. In cases where transistors with opposite polarity are used or the direction of current changes during circuit operation, the functions of "source electrode" and "drain electrode" are sometimes interchangeable. Therefore, in this specification, "source electrode" and "drain electrode" can be interchangeable. In the embodiments of the present disclosure, the gate electrode can be called a control electrode.

[0114] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables transmission of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with multiple functions.

[0115] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0116] In this specification, circles, ellipses, triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate circles, approximate ellipses, approximate triangles, approximate rectangles, approximate trapezoids, approximate pentagons or approximate hexagons, etc. There may be some small deformations caused by tolerances, such as chamfers, arc edges and deformations.

[0117] In this specification, "about" and "substantially" are used without strict limits and allow for process and measurement errors. In this disclosure, "substantially the same" means that the numerical values ​​differ by less than 10%.

[0118] In this specification, "A extends along direction B" means that A may include a main portion and a secondary portion connected to the main portion, the main portion being a line, line segment, or strip, extending along direction B, and the length of the main portion extending along direction B being greater than the length of the secondary portion extending along other directions. Throughout this specification, "A extends along direction B" means "the main portion of A extends along direction B."

[0119] As used herein, "A and B are in the same layer" means that A and B are formed simultaneously through the same patterning process. "Same layer" does not always mean that the thickness or height of the layer is the same in a cross-sectional view. "The orthographic projection of A includes the orthographic projection of B" means that the orthographic projection of B falls within the orthographic projection of A, or that the orthographic projection of A covers the orthographic projection of B.

[0120] FIG1 is a schematic diagram of the outer shape of a display device, which has a rectangular shape with rounded corners. The display device may include: a display substrate. In some examples, the display substrate may be a closed polygon including linear edges, a circle or ellipse including curved edges, or a semicircle or semi-ellipse including linear edges and curved edges. In some examples, when the substrate has linear edges, at least some of the corners of the substrate may be curved. When the substrate has a rectangular shape, the portion where adjacent linear edges meet may be replaced with a curve having a predetermined curvature. The curvature may be set according to the position of the curve. For example, the curvature may be varied according to the position where the curve begins, the length of the curve, etc.

[0121] In some examples, as shown in Figure 1, the display substrate may include a display area AA and a peripheral area BB located around the display area. In some examples, the display area AA may include a first edge (lower edge) and a second edge (upper edge) arranged relative to each other in the second direction Y, and a third edge (left edge) and a fourth edge (right edge) arranged relative to each other in the first direction X. Adjacent edges may be connected by arc-shaped chamfers to form a quadrilateral shape with rounded corners. In some examples, the peripheral area BB may include: a first frame (lower frame) B1 and a second frame (upper frame) B2 arranged relative to each other in the second direction Y, and a third frame (left frame) B3 and a fourth frame (right frame) B4 arranged relative to each other in the first direction X. The first frame B1 is connected to the third frame B3 and the fourth frame B4, and the second frame B2 is connected to the third frame B3 and the fourth frame B4.

[0122] In some examples, as shown in FIG1 , the display area AA includes at least a plurality of sub-pixels PX, a plurality of gate lines G, and a plurality of data lines D. The plurality of gate lines G may extend along a first direction X, and the plurality of data lines D may extend along a second direction Y. The orthographic projections of the plurality of gate lines G and the plurality of data lines D on the substrate intersect to form a plurality of sub-pixel regions, with a sub-pixel PX disposed in each sub-pixel region. The plurality of data lines D are electrically connected to the plurality of sub-pixels PX, and the plurality of data lines D may be configured to provide data signals to the plurality of sub-pixels PX. The plurality of gate lines G are electrically connected to the plurality of sub-pixels PX, and the plurality of gate lines G may be configured to provide gate control signals to the plurality of sub-pixels PX. In some examples, the gate control signals may include scan signals and light-emitting control signals.

[0123] 1 , the first direction X may be the extending direction (row direction) of the gate lines G in the display area, and the second direction Y may be the extending direction (column direction) of the data lines D in the display area. The first direction X and the second direction Y may be perpendicular to each other.

[0124] In some examples, a pixel unit in display area AA may include three sub-pixels, where the three sub-pixels are red, green, and blue. However, this embodiment is not limited to this. In some examples, a pixel unit may include four sub-pixels, where the four sub-pixels are red, green, blue, and white.

[0125] In some examples, the shape of the sub-pixels can be a rectangle, a diamond, a pentagon, or a hexagon. When a pixel unit includes three sub-pixels, the three sub-pixels can be arranged horizontally, vertically, or in a triangular pattern; when a pixel unit includes four sub-pixels, the four sub-pixels can be arranged horizontally, vertically, or in a square pattern. However, this embodiment is not limited to this.

[0126] In some examples, a sub-pixel may include: a pixel circuit and a light-emitting element connected to the pixel circuit. The pixel circuit may include multiple transistors and at least one capacitor. For example, the pixel circuit may have a 3T1C (i.e., 3 transistors and 1 capacitor) structure, a 7T1C (i.e., 7 transistors and 1 capacitor) structure, a 5T1C (i.e., 5 transistors and 1 capacitor) structure, an 8T1C (i.e., 8 transistors and 1 capacitor) structure, or an 8T2C (i.e., 8 transistors and 2 capacitors) structure.

[0127] In some examples, the light-emitting element may be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including mini-LED or micro-LED), etc. For example, the light-emitting element may be an OLED, and the light-emitting element may emit red light, green light, blue light, or white light, etc. when driven by its corresponding pixel circuit. The color of the light emitted by the light-emitting element may be determined as needed. In some examples, the light-emitting element may include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element may be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited to this.

[0128] FIG2 is a schematic diagram of the structure of a display device. In some examples, as shown in FIG2 , the display device may include: a timing controller 201, a data driver 202, a scan driver circuit 203, a light-emitting driver circuit 204, and a display substrate 205. In some examples, the display area of ​​the display substrate 205 may include a plurality of regularly arranged sub-pixels PX. The scan driver circuit 203 may be configured to provide scan signals to the sub-pixels PX along scan lines; the data driver 202 may be configured to provide data voltages to the sub-pixels PX along data lines; the light-emitting driver circuit 204 may be configured to provide light-emitting control signals to the sub-pixels PX along light-emitting control lines; and the timing controller 201 may be configured to control the scan driver circuit 203, the light-emitting driver circuit 204, and the data driver 202.

[0129] In some examples, the timing controller 201 can provide grayscale values ​​and control signals suitable for the specifications of the data driver 202 to the data driver 202. The timing controller 201 can also provide scan clock signals, scan start signals, etc. suitable for the specifications of the scan driver circuit 203 to the scan driver circuit 203. The timing controller 201 can also provide light-emission clock signals, light-emission start signals, etc. suitable for the specifications of the light-emission driver circuit 204 to the light-emission driver circuit 204. The data driver 202 can use the grayscale values ​​and control signals received from the timing controller 201 to generate data voltages to be provided to the data lines D1 to Dn. For example, the data driver 202 can sample grayscale values ​​using clock signals and apply data voltages corresponding to the grayscale values ​​to the data lines D1 to Dn in units of sub-pixel rows. The scan driver circuit 203 can generate scan signals to be provided to the scan lines S1 to Sm using the scan clock signals, scan start signals, etc. received from the timing controller 201. For example, the scan driver circuit 203 can sequentially provide scan signals having on-level pulses to the scan lines. In some examples, the scan driver circuit 203 can include a shift register that can sequentially transmit scan start signals provided in the form of on-level pulses to the next-stage circuit under the control of a scan clock signal to generate scan signals. The light-emitting driver circuit 204 can generate light-emitting control signals to be provided to the light-emitting control lines E1 to Eo based on the light-emitting clock signal, light-emitting start signal, etc. received from the timing controller 201. For example, the light-emitting driver circuit 204 can sequentially provide light-emitting start signals having off-level pulses to the light-emitting control lines. The light-emitting driver circuit 204 can include a shift register that can sequentially transmit light-emitting start signals provided in the form of off-level pulses to the next-stage circuit under the control of the light-emitting clock signal to generate light-emitting control signals. Where n, m, and o are all natural numbers.

[0130] In some examples, the scan driver circuit and the light driver circuit can be directly disposed on the display substrate. For example, the scan driver circuit can be disposed on the third frame of the display substrate, and the light driver circuit can be disposed on the fourth frame of the display substrate; alternatively, the scan driver circuit and the light driver circuit can be disposed on both the third frame and the fourth frame of the display substrate. In some examples, the scan driver circuit and the light driver circuit can be formed together with the sub-pixels during the process of forming the sub-pixels.

[0131] In some examples, the data driver can be provided on a separate chip or printed circuit board to be connected to the sub-pixels via signal access pins on the display substrate. For example, the data driver can be formed using a chip on glass, a chip on plastic, a chip on film, etc. to form a first frame provided on the display substrate to be connected to the signal access pins. The timing controller can be provided separately from the data driver or integrated with the data driver. However, this embodiment is not limited to this. In some examples, the data driver can be provided directly on the display substrate.

[0132] Figure 3 is a schematic cross-sectional view of a display substrate, illustrating the structure of three sub-pixels of an OLED display substrate. As shown in Figure 3, in a plane perpendicular to the display substrate, the display substrate may include a drive circuit layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on the side of the drive circuit layer 102 facing away from the substrate 101, and an encapsulation layer 104 disposed on the side of the light-emitting structure layer 103 facing away from the substrate 101. In some possible implementations, the display substrate may include other film layers, such as spacers, etc., which are not limited in this disclosure.

[0133] In an exemplary embodiment, the substrate 101 may be a flexible substrate or a rigid substrate. The driving circuit layer 102 of each sub-pixel may include multiple transistors and storage capacitors that constitute the pixel driving circuit. The light-emitting structure layer 103 may include an anode 301, an organic light-emitting layer 302, and a cathode 303. The anode 301 is connected to the drain electrode of the driving transistor 210 through a via, the organic light-emitting layer 302 is connected to the anode 301, and the cathode 303 is connected to the organic light-emitting layer 302. The organic light-emitting layer 302 emits light of a corresponding color under the drive of the anode 301 and the cathode 303. The encapsulation layer 104 may include a stacked first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403. The first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials, and the second encapsulation layer 402 may be made of organic materials. The second encapsulation layer 402 is disposed between the first encapsulation layer 401 and the third encapsulation layer 403 to ensure that external water vapor cannot enter the light-emitting structure layer 103.

[0134] In an exemplary embodiment, the organic light-emitting layer 302 may include a stacked hole injection layer (HIL), a hole transport layer (HTL), an electron block layer (EBL), an emitting layer (EML), a hole block layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the hole injection layers of all sub-pixels may be a common layer connected together, the electron injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the electron transport layers of all sub-pixels may be a common layer connected together, and the hole blocking layers of all sub-pixels may be a common layer connected together. The light-emitting layers of adjacent sub-pixels may have a small overlap or may be isolated, and the electron blocking layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0135] In an exemplary embodiment, the pixel driving circuit may have a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. FIG4 is a schematic diagram of an equivalent circuit of a pixel driving circuit. As shown in FIG4 , the pixel driving circuit may include seven transistors (a first transistor T1 to a seventh transistor T7) and a storage capacitor C. The pixel driving circuit may be connected to seven signal lines (a data signal line D, a first scan signal line S1, a second scan signal line S2, a light emitting signal line E, an initial signal line INIT, a first power line VDD, and a second power line VSS).

[0136] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. The first node N1 is connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the second electrode of the fifth transistor T5, respectively. The second node N2 is connected to the second electrode of the first transistor T1, the first electrode of the second transistor T2, the control electrode of the third transistor T3, and the second end of the storage capacitor C, respectively. The third node N3 is connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6, respectively.

[0137] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first power line VDD, and a second end of the storage capacitor C is connected to the second node N2 , ie, the second end of the storage capacitor C is connected to the control electrode of the third transistor T3 .

[0138] The control electrode of the first transistor T1 is connected to the second scan signal line S2, the first electrode of the first transistor T1 is connected to the initialization signal line INIT, and the second electrode of the first transistor is connected to the second node N2. When an on-level scan signal is applied to the second scan signal line S2, the first transistor T1 transmits an initialization voltage to the control electrode of the third transistor T3, thereby initializing the charge amount of the control electrode of the third transistor T3.

[0139] The control electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3. When the on-level scan signal is applied to the first scan signal line S1, the second transistor T2 connects the control electrode of the third transistor T3 to the second electrode.

[0140] The control electrode of the third transistor T3 is connected to the second node N2, that is, the control electrode of the third transistor T3 is connected to the second end of the storage capacitor C. The first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be called a driving transistor. The third transistor T3 determines the amount of driving current flowing between the first power line VDD and the second power line VSS based on the potential difference between the control electrode and the first electrode.

[0141] The control electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 can be called a switching transistor, a scan transistor, etc. When an on-level scan signal is applied to the first scan signal line S1, the fourth transistor T4 inputs the data voltage of the data signal line D to the pixel driving circuit.

[0142] The control electrode of the fifth transistor T5 is connected to the light-emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. The control electrode of the sixth transistor T6 is connected to the light-emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting device. The fifth transistor T5 and the sixth transistor T6 can be referred to as light-emitting transistors. When an on-level light-emitting signal is applied to the light-emitting signal line E, the fifth transistor T5 and the sixth transistor T6 form a drive current path between the first power line VDD and the second power line VSS, causing the light-emitting device to emit light.

[0143] The control electrode of the seventh transistor T7 is connected to the first scan signal line S1, the first electrode of the seventh transistor T7 is connected to the initialization signal line INIT, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting device. When the on-level scan signal is applied to the first scan signal line S1, the seventh transistor T7 transmits an initialization voltage to the first electrode of the light-emitting device to initialize or release the charge accumulated in the first electrode of the light-emitting device.

[0144] In an exemplary embodiment, the second electrode of the light-emitting device is connected to a second power line VSS. The signal on the second power line VSS is a low-level signal, while the signal on the first power line VDD is a continuously high-level signal. The first scan signal line S1 is a scan signal line in the pixel driving circuit for the current display row, and the second scan signal line S2 is a scan signal line in the pixel driving circuit for the previous display row. That is, for the nth display row, the first scan signal line S1 is S(n), and the second scan signal line S2 is S(n-1). The second scan signal line S2 for the current display row is the same as the first scan signal line S1 in the pixel driving circuit for the previous display row. This can reduce the number of signal lines on the display panel, achieving a narrow bezel on the display panel.

[0145] In an exemplary embodiment, the first scan signal line S1, the second scan signal line S2, the emission signal line E, and the initial signal line INIT extend in a horizontal direction, and the second power line VSS, the first power line VDD, and the data signal line D extend in a vertical direction.

[0146] In an exemplary embodiment, the light emitting device may be an organic light emitting diode (OLED) including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked.

[0147] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be a P-type transistor (as shown in FIG4 ), or may be an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include a P-type transistor and an N-type transistor. As shown in FIG5 , it is a schematic diagram of an equivalent circuit of a pixel driving circuit, in which the second transistor T2 is an N-type transistor (i.e., an oxide thin film transistor), the first transistor T1, the third transistor T3 to the eighth transistor T8 are P-type transistors (i.e., low-temperature polycrystalline silicon thin film transistors), the active layer of the low-temperature polycrystalline silicon thin film transistor adopts low-temperature polysilicon (Low Temperature Poly-Silicon, abbreviated as LTPS), and the active layer of the oxide thin film transistor adopts oxide semiconductor (Oxide). Low-temperature polysilicon thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. By integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate, the advantages of both can be utilized to achieve low-frequency driving, reduce the repeated refreshing of static images to reduce driving power consumption, reduce power consumption, and improve display quality. As shown in Figure 5, the pixel driving circuit may include 8 transistors (first transistor T1 to eighth transistor T8) and 1 storage capacitor C. The pixel driving circuit may be connected to 11 signal lines (data signal line D, first scan signal line S1, second scan signal line S2, third scan signal line S3, fourth scan signal line S4, light-emitting signal line E, first initial signal line INIT1, second initial signal line INIT2, third initial signal line INIT3, first power line VDD, and second power line VSS). Compared with Figure 4, the difference of Figure 5 is that: an eighth transistor T8, a third initial signal line INIT3, a third scan signal line S3 and a fourth scan signal line S4 are newly added, the third scan signal line S3 is connected to the control electrode of the second transistor T2, and the fourth scan signal line S4 is connected to the control electrode of the fourth transistor T4; the second transistor T2 is an N-type transistor, the first scan signal line S1 is also electrically connected to the control electrode of the eighth transistor T8, the first electrode of the eighth transistor T8 is connected to the third initial signal line INIT3, and the second electrode of the eighth transistor T8 is connected to the first node N; the first electrode of the first transistor T1 is connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected to the third node N3.

[0148] In some examples, the first power line VDD can be configured to provide a constant second voltage signal to the pixel circuit, the second power line VSS can be configured to provide a constant second voltage signal to the pixel circuit, and the first voltage signal can be greater than the second voltage signal. The first scan line S1 can be configured to provide a first scan signal to the pixel circuit, the second scan line S2 can be configured to provide a second scan signal to the pixel circuit, the third scan line S3 can be configured to provide a third scan signal to the pixel circuit, and the fourth scan line S4 can be configured to provide a fourth scan signal to the pixel circuit. The data line D can be configured to provide a data signal to the pixel circuit, and the emission control line E can be configured to provide an emission control signal to the pixel circuit.

[0149] In some examples, the first initial signal line INIT1 can be configured to provide a first initial signal to the pixel circuit, and the second initial signal line INIT2 can be configured to provide a second initial signal to the pixel circuit. For example, the first initial signal can be different from the second initial signal. The first initial signal and the second initial signal can be constant voltage signals, and their magnitudes can be, for example, between the first voltage signal and the second voltage signal, but are not limited thereto. In other examples, the first initial signal and the second initial signal can be the same, and only the first initial signal line can be provided to provide the first initial signal.

[0150] During image updates, the OLED display substrate initializes and writes voltages to all pixels within a frame. For images that are rarely updated, such as Always On Display (AOD) and static images, most pixel voltages in the display substrate do not require updating, allowing low-leakage LTPO transistors (TFTs) to maintain the original display brightness. In actual OLED display products, pixel voltages corresponding to these rarely updated images still need to be repeatedly refreshed during image updates, resulting in high power consumption.

[0151] The present disclosure provides a display substrate, which may include a plurality of sub-pixels, at least one local driving circuit, at least one column control line, and at least one row control line. At least some of the sub-pixels may include a light-emitting device and a pixel driving circuit for driving the light-emitting device to emit light. The pixel driving circuit is connected to one of the local driving circuits.

[0152] The local driving circuit can be connected to at least one pixel driving circuit, one of the column control lines and one of the row control lines, and is configured to control the operation of the pixel driving circuit connected thereto under the control of the column control line and the row control line; the pixel driving circuit drives the corresponding light-emitting device to maintain the original brightness or refresh the brightness under the control of the local driving circuit.

[0153] In the display substrate provided by the embodiment of the present disclosure, the local driving circuit is configured to control the operation of the pixel driving circuit connected thereto under the control of the column control line and the row control line. Under the control of the local driving circuit, the pixel driving circuit drives the corresponding light-emitting device to maintain the original brightness or refresh the brightness, thereby reducing power consumption.

[0154] As shown in FIG6a and FIG6b, the display substrate provided in the embodiment of the present disclosure may include a plurality of sub-pixels, at least one local driving circuit 60, at least one column control line C-Gate, and at least one row control line N-Gate. At least some of the sub-pixels may include a light-emitting device and a pixel driving circuit 50 for driving the light-emitting device to emit light. The pixel driving circuit 50 is connected to one of the local driving circuits 60.

[0155] The local driving circuit 60 can be connected to at least one pixel driving circuit 50, one of the column control lines C-Gate and one of the row control lines N-Gate, and is configured to control the pixel driving circuit 50 connected thereto to operate under the control of the column control line C-Gate and the row control line N-Gate; the pixel driving circuit 50 drives the corresponding light-emitting device to maintain the original brightness or refresh the brightness under the control of the local driving circuit 60.

[0156] In an exemplary embodiment, the pixel driving circuits 50 in the plurality of sub-pixels may form multiple rows and columns, and the local driving circuits 60 may be located between two adjacent rows of pixel driving circuits 50. The local driving circuits 60 are connected to at least some of the pixel driving circuits 50 in at least one row. There are multiple local driving circuits 60, forming multiple rows and columns. A row control line N-Gate may be connected to at least one row of local driving circuits 60 and configured to provide a row control signal to the local driving circuits 60 connected thereto. A column control line C-Gate may be connected to at least one column of local driving circuits 60 and configured to provide a column control signal to the local driving circuits 60 connected thereto. FIG. 6 a shows that the row control line N-Gate is connected to one row of local driving circuits 60, and the column control line C-Gate is connected to one column of local driving circuits 60. FIG. 6 b shows that the row control line N-Gate is connected to two rows of local driving circuits 60, and the column control line C-Gate is connected to two columns of local driving circuits 60.

[0157] In an exemplary embodiment, as shown in Figure 6a, the local driving circuit 60 can be connected to n adjacent pixel driving circuits 50 in a row of pixel driving circuits 50, where n is a positive integer; the row control line N-Gate is connected to multiple local driving circuits 60 in a row of local driving circuits 60; and the column control line C-Gate is connected to multiple local driving circuits 60 in a column of local driving circuits 60.

[0158] In an exemplary embodiment, the column control line C-Gate can be configured to control the refresh brightness of the sub-pixels controlled by one or more columns of local driving circuits 60 connected thereto (which can be simply referred to as column refresh); the row control line N-Gate can be configured to control the refresh brightness of the sub-pixels controlled by one or more rows of local driving circuits 60 connected thereto (which can be simply referred to as row refresh), and the row control signal provided by the row control line N-Gate may include a row control signal for refreshing the brightness and a row control signal for maintaining the brightness (i.e., the row control signal may include a control signal for refreshing the brightness and a control signal for maintaining the brightness), and the column control signal provided by the column control line C-Gate may include a column control signal for refreshing the brightness and a column control signal for maintaining the brightness (i.e., the column control signal may include a control signal for refreshing the brightness and a control signal for maintaining the brightness). The pixel driving circuit 50 can drive the corresponding light-emitting device to refresh the brightness when the row control signal of the row control line N-Gate and the column control signal of the column control line C-Gate connected to the local driving circuit 60 are both control signals for refreshing the brightness; the pixel driving circuit 50 can drive the corresponding light-emitting device to maintain the original brightness when at least one of the row control signal of the row control line N-Gate and the column control signal of the column control line C-Gate connected to the local driving circuit 60 is a control signal for maintaining the brightness.

[0159] In an exemplary embodiment, the multiple pixel driving circuits 50 in the display substrate can drive the corresponding light-emitting devices L to emit light under the control of the row control signal of the row control line N-Gate and the column control signal of the column control line C-Gate connected to the local driving circuit 60. The sub-pixels in the display substrate can be controlled by the signals provided by the row control line N-Gate and the column control line C-Gate to achieve local refresh, that is, the local screen of the display substrate can be updated, while the remaining screens do not need multiple charging and discharging (for example, screen-off display technology, static screens, etc. do not require multiple charging and discharging, and most of the pixel voltages in the display substrate do not need to be updated), which can further reduce the power consumption of the display substrate, or ultra-low power consumption of the display product can be achieved by partially updating the display screen, for example, ultra-low power consumption of OLED display products such as wearable display devices, mobile display devices (mobile), and notebook computers (NB) can be achieved.

[0160] In an exemplary embodiment, the pixel driving circuit 50 may include a compensation transistor T2 , and the local driving circuit 60 may be configured to control the compensation transistor T2 to be turned on or off under the control of the column control line C-Gate and the row control line N-Gate.

[0161] In an exemplary embodiment, as shown in Figures 9a to 9c, the local driving circuit 60 may include a first control transistor T9, wherein a control electrode of the first control transistor T9 is connected to the column control line C-Gate, a first electrode of the first control transistor T9 is connected to the row control line N-Gate, and a second electrode of the first control transistor T9 is connected to the control electrode of the compensation transistor T2. As shown in Figures 9a to 9c, the ninth transistor T9 in the pixel driving circuit 50 may serve as the first control transistor, and the second transistor T2 may serve as the compensation transistor.

[0162] In an exemplary embodiment, the local driving circuit 60 is configured to provide a signal of the row control line N-Gate to the gate electrode of the compensation transistor T2 or control the gate electrode of the compensation transistor T2 to maintain an original potential under the control of the column control line C-Gate.

[0163] In an exemplary embodiment, as shown in FIG9 a , the first control transistor T9 is a P-type transistor, and the compensation transistor T2 may be an N-type transistor;

[0164] When the signal of the column control line C-Gate is at the first level, the local driving circuit 60 provides the signal of the row control line N-Gate to the control electrode of the compensation transistor T2. The compensation transistor T2 is turned on or off under the control of the signal of the row control line N-Gate. The pixel driving circuit 50 drives the corresponding light-emitting device to maintain the original brightness or refresh the brightness under the control of the signal of the row control line N-Gate.

[0165] When the signal of the column control line C-Gate is at the second level, the compensation transistor T2 is turned off under the control of the original potential, and the pixel driving circuit 50 drives the corresponding light-emitting device to maintain the original brightness.

[0166] In an exemplary embodiment, as shown in FIG9 b , the first control transistor T9 and the compensation transistor T2 may be N-type transistors;

[0167] When the signal of the column control line C-Gate is at the second level, the local driving circuit 60 provides the signal of the row control line N-Gate to the control electrode of the compensation transistor T2. Under the control of the signal of the row control line N-Gate, the pixel driving circuit 50 drives the corresponding light-emitting device to maintain the original brightness or refresh the brightness.

[0168] When the signal on the column control line C-Gate is at a first level, the compensation transistor T2 is disconnected under control of the original potential, and the pixel driving circuit 50 drives the corresponding light-emitting device to maintain the original brightness. In an exemplary embodiment, as shown in FIG9c , the local driving circuit 60 may further include a first capacitor C1, with a first end of the first capacitor C1 connected to the constant voltage power line VX, and a second end of the first capacitor C1 connected to the second electrode of the first control transistor T9. In an exemplary embodiment, the first capacitor C1 can maintain a stable potential at the fifth node N5 during the period when the column control line C-Gate turns off the first control transistor T9, and can prevent large voltage fluctuations at the fifth node N5 caused by leakage from the first control transistor T9. The first capacitor C1 can also be added to the structure of FIG9b to maintain a stable potential at the fifth node N5. In an exemplary embodiment, the constant voltage power line VX can be a DC signal. For example, the constant voltage power line VX can be one of the first power line VDD, the initial signal line INIT (for example, it can be one of the first initial signal line INIT1, the second initial signal line INIT2, and the third initial signal line INIT3), the low voltage power line VGL, and the high voltage power line VGH, that is, one of the first power line VDD, the first initial signal line INIT1, the second initial signal line INIT2, the third initial signal line INIT3, the low voltage power line VGL, and the high voltage power line VGH can serve as the constant voltage power line VX.

[0169] In the equivalent circuit diagrams shown in Figures 9a and 9c, the first level of the signal on the column control line C-Gate can be a control signal for refreshing brightness, and the second level can be a control signal for maintaining brightness. In the equivalent circuit diagram shown in Figure 9b, the second level of the signal on the column control line C-Gate can be a control signal for refreshing brightness, and the first level can be a control signal for maintaining brightness.

[0170] In an exemplary embodiment, as shown in FIG7 and FIG11 , the local driving circuit 60 may further include a second control transistor T10 , wherein a control electrode of the second control transistor T10 is connected to the column control line C-Gate, a second electrode of the second control transistor T10 is connected to the control electrode of the compensation transistor T2 , and a first electrode of the second control transistor T10 is connected to the low voltage power line;

[0171] The local driving circuit 60 is configured to provide a signal of the row control line N-Gate or a signal of the low voltage power line to the control electrode of the compensation transistor T2 under the control of the column control line C-Gate.

[0172] In an exemplary embodiment, the tenth transistor T10 in the pixel driving circuit 50 may function as a second control transistor.

[0173] In an exemplary embodiment, as shown in FIG7 , the first control transistor T9 may be a P-type transistor, and the compensation transistor T2 and the second control transistor T10 may be N-type transistors;

[0174] When the signal of the column control line C-Gate is at the first level, the local driving circuit 60 provides the signal of the row control line N-Gate to the control electrode of the compensation transistor T2. The compensation transistor T2 is turned on or off under the control of the signal of the row control line N-Gate. The pixel driving circuit 50 drives the corresponding light-emitting device to maintain the original brightness or refresh the brightness under the control of the signal of the row control line N-Gate.

[0175] When the signal of the column control line C-Gate is at the second level, the local driving circuit 60 provides the signal of the low-voltage power line to the control electrode of the compensation transistor T2. The compensation transistor T2 is turned off under the control of the signal of the low-voltage power line, and the pixel driving circuit 50 drives the corresponding light-emitting device to maintain the original brightness.

[0176] In the equivalent circuit diagram shown in FIG7 , in the signal of the column control line C-Gate, the first level may be a control signal for refreshing brightness, and the second level may be a control signal for maintaining brightness.

[0177] In an exemplary embodiment, in the equivalent circuit diagrams shown in FIG7 and FIG9 a , when the signal of the column control line C-Gate is at a first level and the row control line N-Gate is at a second level during the reset phase and the threshold compensation phase of an operating frame of the pixel driving circuit 50, during the reset phase and the threshold compensation phase of an operating frame of the pixel driving circuit 50, the local driving circuit 60 provides the signal of the row control line N-Gate to the control electrode of the compensation transistor T2. The compensation transistor T2 is turned on under the control of the signal of the row control line N-Gate, and the pixel driving circuit 50 drives the corresponding light-emitting device to refresh the brightness in this operating frame.

[0178] When the signal of the column control line C-Gate is at the first level and the row control line N-Gate is at the first level in an operating frame of the pixel driving circuit 50, the local driving circuit 60 provides the signal of the row control line N-Gate to the control electrode of the compensation transistor T2. The compensation transistor T2 is turned off under the control of the signal of the row control line N-Gate, and the pixel driving circuit 50 drives the corresponding light-emitting device to maintain the original brightness in this operating frame.

[0179] In Figures 7 and 9a, during the reset phase and threshold compensation phase of an operating frame of the pixel driving circuit 50, the second level of the signal on the row control line N-Gate is a control signal for refreshing the brightness, and the first level is a control signal for maintaining the brightness. The operating timing diagrams of the equivalent circuit diagrams shown in Figures 7 and 9a can be shown in Figure 8, and the operating timing diagram of the equivalent circuit diagram shown in Figure 9b can be shown in Figure 10.

[0180] In an exemplary embodiment, as shown in FIG11 , the first control transistor T9 and the compensation transistor T2 are N-type transistors, and the second control transistor T10 is a P-type transistor;

[0181] When the signal of the column control line C-Gate is at the second level, the local driving circuit 60 provides the signal of the row control line N-Gate to the control electrode of the compensation transistor T2. The compensation transistor T2 is turned on or off under the control of the signal of the row control line N-Gate. The pixel driving circuit 50 drives the corresponding light-emitting device to maintain the original brightness or refresh the brightness under the control of the signal of the row control line N-Gate.

[0182] When the signal of the column control line C-Gate is at the first level, the local driving circuit 60 provides the signal of the low-voltage power line to the control electrode of the compensation transistor T2. The compensation transistor T2 is disconnected under the control of the low-voltage power line, and the pixel driving circuit 50 drives the corresponding light-emitting device to maintain the original brightness.

[0183] In the equivalent circuit diagram shown in FIG11 , in the signal of the column control line C-Gate, the second level may be a control signal for refreshing brightness, and the first level may be a control signal for maintaining brightness.

[0184] In an exemplary embodiment, when the signal of the column control line C-Gate is at the second level and the row control line N-Gate is at the second level during the reset phase and the threshold compensation phase of one working frame of the pixel driving circuit 50, the local driving circuit 60 provides the signal of the row control line N-Gate to the control electrode of the compensation transistor T2 during the reset phase and the threshold compensation phase of one working frame of the pixel driving circuit 50. The compensation transistor T2 is turned on under the control of the signal of the row control line N-Gate, and the pixel driving circuit 50 drives the corresponding light-emitting device to refresh the brightness in this working frame.

[0185] When the signal of the column control line C-Gate is at the second level and the row control line N-Gate is at the first level in an operating frame of the pixel driving circuit 50, the local driving circuit 60 provides the signal of the row control line N-Gate to the control electrode of the compensation transistor T2. The compensation transistor T2 is turned off under the control of the signal of the row control line N-Gate, and the pixel driving circuit 50 drives the corresponding light-emitting device to maintain the original brightness in this operating frame.

[0186] In Figures 9b and 11 , during the reset phase and threshold compensation phase of an operating frame of the pixel driving circuit 50, the second level of the signal on the row control line N-Gate is a control signal for refreshing brightness, while the first level is a control signal for maintaining brightness. The operating timing diagrams of the equivalent circuit diagrams shown in Figures 9b and 11 can be shown in Figure 10 .

[0187] In an exemplary embodiment, as shown in FIG. 12 a and FIG. 12 b , the display substrate may further include a low voltage power supply line, and the local driving circuit 60 may include a first control transistor T9 and a second control transistor T10 ;

[0188] The control electrode of the first control transistor T9 is connected to the row control line N-Gate, the first electrode of the first control transistor T9 is connected to the column control line C-Gate, and the second electrode of the first control transistor T9 is connected to the control electrode of the compensation transistor T2;

[0189] The control electrode of the second control transistor T10 is connected to the row control line N-Gate, the first electrode of the second control transistor T10 is connected to the low voltage power line, and the second electrode of the second control transistor T10 is connected to the control electrode of the compensation transistor T2.

[0190] In an exemplary embodiment, in the structure shown in Figures 12a and 12b, the local driving circuit 60 can be configured to provide a signal of the column control line C-Gate or a signal of the low-voltage power line to the control electrode of the compensation transistor T2 under the control of the row control line N-Gate, thereby controlling the compensation transistor T2 to be turned on or off.

[0191] In an exemplary embodiment, as shown in FIG12 a , the first control transistor T9 may be a P-type transistor, and the compensation transistor T2 and the second control transistor T10 may be N-type transistors;

[0192] When the signal of the column control line C-Gate is at the second level, the pixel driving circuit 50 drives the corresponding light-emitting device to maintain the original brightness or refresh the brightness under the control of the row control line N-Gate and the local driving circuit 60;

[0193] When the signal of the column control line C-Gate is at the first level, the compensation transistor T2 is turned off under the control of the signal of the column control line C-Gate or the low voltage power line, and the pixel driving circuit 50 drives the corresponding light emitting device to maintain the original brightness.

[0194] In the equivalent circuit diagram shown in FIG12 a , in the signal of the column control line C-Gate, the second level may be a control signal for refreshing brightness, and the first level may be a control signal for maintaining brightness.

[0195] In an exemplary embodiment, in the structure shown in FIG12 a , when the signal of the column control line C-Gate is at the second level and the row control line N-Gate is at the first level during the reset phase and the threshold compensation phase of one working frame of the pixel driving circuit 50 , the local driving circuit 60 provides the signal of the column control line C-Gate to the control electrode of the compensation transistor T2 during the reset phase and the threshold compensation phase of one working frame of the pixel driving circuit 50 . The compensation transistor T2 is turned on under the control of the column control line C-Gate, and the pixel driving circuit 50 drives the corresponding light-emitting device to refresh the brightness during this working frame.

[0196] When the signal of the column control line C-Gate is at the second level and the row control line N-Gate is at the second level in an operating frame of the pixel driving circuit 50, the local driving circuit 60, under the control of the row control line N-Gate, reduces the signal of the voltage power line and provides it to the control electrode of the compensation transistor T2. The compensation transistor T2 is turned off under the control of the signal of the low-voltage power line, and the pixel driving circuit 50 drives the corresponding light-emitting device to maintain the original brightness in this operating frame.

[0197] In FIG12a , during the reset and threshold compensation phases of an operating frame of the pixel driving circuit 50, the first level of the signal on the row control line N-Gate is a control signal for refreshing brightness, and the second level is a control signal for maintaining brightness. An operating timing diagram of the equivalent circuit diagram shown in FIG12a can be shown in FIG13 .

[0198] In an exemplary embodiment, as shown in FIG12 b , the first control transistor T9 and the compensation transistor T2 may be N-type transistors, and the second control transistor T10 may be a P-type transistor;

[0199] When the signal of the column control line C-Gate is at the second level, the pixel driving circuit 50 drives the corresponding light-emitting device to maintain the original brightness or refresh the brightness under the control of the row control line N-Gate and the local driving circuit 60;

[0200] When the signal of the column control line C-Gate is at the first level, the compensation transistor T2 is turned off under the control of the signal of the column control line C-Gate or the low voltage power line, and the pixel driving circuit 50 drives the corresponding light emitting device to maintain the original brightness.

[0201] In the equivalent circuit diagram shown in FIG12 b , in the signal of the column control line C-Gate, the second level may be a control signal for refreshing brightness, and the first level may be a control signal for maintaining brightness.

[0202] In an exemplary embodiment, in the structure shown in FIG12 b , when the signal of the column control line C-Gate is at the second level and the row control line N-Gate is at the second level during the reset phase and the threshold compensation phase of one operating frame of the pixel driving circuit 50, the local driving circuit 60 provides the signal of the column control line C-Gate to the control electrode of the compensation transistor T2 during the reset phase and the threshold compensation phase of one operating frame of the pixel driving circuit 50. The compensation transistor T2 is turned on under the control of the signal of the column control line C-Gate, and the pixel driving circuit 50 drives the corresponding light-emitting device to refresh the brightness in this operating frame.

[0203] When the signal of the column control line C-Gate is at the second level and the row control line N-Gate is at the first level in an operating frame of the pixel driving circuit 50, the local driving circuit 60, under the control of the row control line N-Gate, reduces the signal of the voltage power line and provides it to the control electrode of the compensation transistor T2. The compensation transistor T2 is turned off under the control of the signal of the low-voltage power line. The pixel driving circuit 50 drives the corresponding light-emitting device to maintain the original brightness in this operating frame.

[0204] In FIG12b , during the reset phase and threshold compensation phase of an operating frame of the pixel driving circuit 50, the second level of the signal on the row control line N-Gate is a control signal for refreshing brightness, while the first level is a control signal for maintaining brightness. The operating timing diagram of the equivalent circuit diagram shown in FIG12b can be shown in FIG10 .

[0205] In an exemplary embodiment, as shown in FIG14 a , the display substrate may further include a column additional control line C-Gate-N and a high voltage power line, and the local driving circuit 60 may include a first control transistor T9 and a second control transistor T10 ;

[0206] The control electrode of the first control transistor T9 is connected to the column control line C-Gate, the first electrode of the first control transistor T9 is connected to the row control line N-Gate, and the second electrode of the first control transistor T9 is connected to the control electrode of the compensation transistor T2;

[0207] The control electrode of the second control transistor T10 is connected to the column additional control line C-Gate-N, the first electrode of the second control transistor T10 is connected to the high voltage power line, and the second electrode of the second control transistor T10 is connected to the control electrode of the compensation transistor T2.

[0208] In an exemplary embodiment, in the structure shown in FIG14 a, the local driving circuit 60 can be configured to provide a signal of the row control line N-Gate or a signal of the high-voltage power line to the control electrode of the compensation transistor T2 under the control of the column control line C-Gate and the column additional control line C-Gate-N, thereby controlling the compensation transistor T2 to be turned off or on. The signal provided by the column control line C-Gate is opposite to the signal provided by the column additional control line C-Gate-N.

[0209] In an exemplary embodiment, in the structure shown in FIG14 a , the first control transistor T9 , the second control transistor T10 , and the compensation transistor T2 may be P-type transistors;

[0210] When the signal of the column control line C-Gate is at the first level and the signal of the column additional control line C-Gate-N is at the second level, the local driving circuit 60 provides the signal of the row control line N-Gate to the control electrode of the compensation transistor T2. The compensation transistor T2 is turned on or off under the control of the signal of the row control line N-Gate. The pixel driving circuit 50 drives the corresponding light-emitting device to maintain the original brightness or refresh the brightness under the control of the signal of the row control line N-Gate.

[0211] When the signal of the column control line C-Gate is at the second level and the signal of the column additional control line C-Gate-N is at the first level, the local driving circuit 60 provides the signal of the high voltage power line to the control electrode of the compensation transistor T2, the compensation transistor T2 is turned off, and the pixel driving circuit 50 drives the corresponding light-emitting device to maintain the original brightness.

[0212] In an exemplary embodiment, in the structure shown in FIG14 a , when the signal of the column control line C-Gate is at the first level and the row control line N-Gate is at the first level during the reset phase and the threshold compensation phase of one working frame of the pixel driving circuit 50 , the local driving circuit 60 provides the signal of the row control line N-Gate to the control electrode of the compensation transistor T2 during the reset phase and the threshold compensation phase of one working frame of the pixel driving circuit 50 . The compensation transistor T2 is turned on under the control of the signal of the row control line N-Gate, and the pixel driving circuit 50 drives the corresponding light-emitting device to refresh the brightness in this working frame.

[0213] When the signal of the column control line C-Gate is at the first level and the row control line N-Gate is at the second level in an operating frame of the pixel driving circuit 50, the local driving circuit 60 provides the signal of the row control line N-Gate to the control electrode of the compensation transistor T2. The compensation transistor T2 is turned off under the control of the signal of the row control line N-Gate, and the pixel driving circuit 50 drives the corresponding light-emitting device to maintain the original brightness in this operating frame.

[0214] In the equivalent circuit diagram shown in FIG14a , the second level of the signal on the column control line C-Gate can be a control signal for refreshing brightness, while the first level can be a control signal for maintaining brightness. During the reset phase and threshold compensation phase of an operating frame of the pixel driving circuit 50 , the first level of the signal on the row control line N-Gate can be a control signal for refreshing brightness, while the second level can be a control signal for maintaining brightness. The operating timing diagram of the equivalent circuit diagram shown in FIG14a can be shown in FIG14b .

[0215] In an exemplary embodiment, as shown in FIG15 a , the display substrate may further include a row additional control line N-Gate-N and a high voltage power supply line, and the local driving circuit 60 may include a first control transistor T9 and a second control transistor T10 ;

[0216] The control electrode of the first control transistor T9 is connected to the row control line N-Gate, the first electrode of the first control transistor T9 is connected to the column control line C-Gate, and the second electrode of the first control transistor T9 is connected to the control electrode of the compensation transistor T2;

[0217] The control electrode of the second control transistor T10 is connected to the row additional control line N-Gate-N, the first electrode of the second control transistor T10 is connected to the high voltage power line, and the second electrode of the second control transistor T10 is connected to the control electrode of the compensation transistor T2.

[0218] In an exemplary embodiment, in the structure shown in FIG15 a, the local driving circuit 60 is configured to provide a signal of the column control line C-Gate or a signal of the high-voltage power line to the control electrode of the compensation transistor T2 under the control of the row control line N-Gate and the row additional control line N-Gate-N, thereby controlling the compensation transistor T2 to be turned on or off. The signal provided by the row control line N-Gate is opposite to the signal provided by the row additional control line N-Gate-N.

[0219] In an exemplary embodiment, in the structure shown in FIG15 a , the first control transistor T9 , the second control transistor T10 , and the compensation transistor T2 may be P-type transistors;

[0220] When the signal of the column control line C-Gate is at the first level, the pixel driving circuit 50 drives the corresponding light-emitting device to maintain the original brightness or refresh the brightness under the control of the row control line N-Gate, the row additional control line N-Gate-N and the local driving circuit 60;

[0221] When the signal of the column control line C-Gate is at the second level, the compensation transistor T2 is turned off under the control of the signal of the column control line C-Gate or the high voltage power line, and the pixel driving circuit 50 drives the corresponding light emitting device to maintain the original brightness.

[0222] In an exemplary embodiment, in the structure shown in FIG15 a , when the signal of the column control line C-Gate is at the first level and the row control line N-Gate is at the first level during the reset phase and the threshold compensation phase of one working frame of the pixel driving circuit 50, the local driving circuit 60 provides the signal of the column control line C-Gate to the control electrode of the compensation transistor T2 during the reset phase and the threshold compensation phase of one working frame of the pixel driving circuit 50. The compensation transistor T2 is turned on under the control of the signal of the column control line C-Gate, and the pixel driving circuit 50 drives the corresponding light-emitting device to refresh the brightness in this working frame.

[0223] When the signal of the column control line C-Gate is at the first level and the row control line N-Gate is at the second level in one working frame of the pixel driving circuit 50, the local driving circuit 60 provides the signal of the high-voltage power line to the control electrode of the compensation transistor T2. The compensation transistor T2 is turned off under the control of the signal of the high-voltage power line, and the pixel driving circuit 50 drives the corresponding light-emitting device to maintain the original brightness.

[0224] In the equivalent circuit diagram shown in FIG15a , the first level of the signal on the column control line C-Gate can be a control signal for refreshing brightness, and the second level can be a control signal for maintaining brightness. During the reset phase and threshold compensation phase of an operating frame of the pixel driving circuit 50, the first level of the signal on the row control line N-Gate can be a control signal for refreshing brightness, and the second level can be a control signal for maintaining brightness. The operating timing diagram of the equivalent circuit diagram shown in FIG15a can be shown in FIG15b .

[0225] In an exemplary embodiment, in the working timings shown in Figures 8, 10, 13, 14b and 15b, each working timing diagram may include the timings of four working frames, and the working processes of the timings of the four working frames are: P11 to P15, P21 to P25, P31 to P35, and P41 to P45, respectively. Among them, the reset phase and the threshold compensation phase of the pixel driving circuit 50 in one working frame are: P11 to P13, P21 to P23, P31 to P33, and P41 to P43, respectively.

[0226] In an exemplary embodiment, the first level may be a low-level signal, and the second level may be a high-level signal. The second transistor T2 in the pixel driving circuit 50 may serve as a compensation transistor, the ninth transistor T9 in the local driving circuit 60 may serve as a first control transistor, and the tenth transistor T10 may serve as a second control transistor.

[0227] In an exemplary embodiment, the pixel driving circuit 50 and the local driving circuit 60 connected thereto constitute a pixel driving device, and the pixel driving circuit 50 and the local driving circuit 60 in the pixel driving device drive the corresponding light emitting device L to emit light.

[0228] In an exemplary embodiment, in the equivalent circuit diagrams shown in Figures 7, 9a to 9c, 11 to 12b, 14a and 15a, the first control transistor T9 is isolated from the first node N1 by the compensation transistor T2 and the fifth node N5. When the control electrode of the ninth transistor T9 jumps, it will briefly affect the voltage of the fifth node N5, but will not affect the voltage of the first node N1, so it will not cause the current of the driving transistor (i.e., the third transistor T3) to change. In the process of the pixel driving circuit 50 driving the corresponding light-emitting device L to emit light, flickering or split screen will not occur.

[0229] In an exemplary embodiment, the structure of the pixel driving circuit 50 may not be limited to that shown in Figures 4, 5, 7, 9a to 9c, 11 to 12b, 14a and 15a. As long as the compensation transistor (i.e., the transistor connected to the driving transistor T3) in the pixel driving circuit 50 is controlled to be turned on or off by the local driving circuit 60, thereby controlling the threshold compensation of the control electrode of the driving transistor T3, the equivalent circuit diagram of the pixel driving circuit 50 may be as shown in Figures 15c to 15d.

[0230] As shown in FIG15c , the pixel driving circuit 50 may include a second transistor T2 (serving as a compensation transistor), a third transistor T3 (serving as a driving transistor), a fourth transistor T4 (serving as a data writing transistor), and a storage capacitor C. The control electrode of the second transistor T2 is connected to the fifth node N5 of the local driving circuit 60, the first electrode of the second transistor T2 is connected to the first node N1, and the second electrode of the second transistor T2 is connected to the third node N3. The control electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3. The control electrode of the fourth transistor T4 is connected to the first scan line Gate1, the first electrode of the fourth transistor T4 is connected to the data line Data, and the second electrode of the fourth transistor T4 is connected to the second node N2. The second node N2 may be connected to the first power line VDD. The local driving circuit 60 may control the second transistor T2 based on the fourth transistor T4 to perform threshold compensation on the first node N1 and write the threshold voltage vth of the driving transistor T3.

[0231] As shown in FIG15d , the local area circuit 60 may include a first local driving circuit 601 to a fourth local driving circuit 604, and the pixel driving circuit 50 may include a first transistor T1 (as an initial row transistor), a second transistor T2 (as a compensation transistor), a third transistor T3 (as a driving transistor), a fourth transistor T4 (as a data writing transistor), a fifth transistor T5 (as a light emitting transistor), a sixth transistor T6 (as a light emitting transistor), a seventh transistor T7 (as an initial row transistor), an eighth transistor T8, an eleventh transistor T11, a first capacitor C11, and a second capacitor C12; wherein the control electrode of the first transistor T1 is connected to the first local area circuit 601 to the fourth local area circuit 604, and the pixel driving circuit 50 may include a first transistor T1 (as an initial row transistor), a second transistor T2 (as a compensation transistor), a third transistor T3 (as a driving transistor), a fourth transistor T4 (as a data writing transistor), a fifth transistor T5 (as a light emitting transistor), a sixth transistor T6 (as a light emitting transistor), a seventh transistor T7 (as an initial row transistor), an eighth transistor T8, an eleventh transistor T11, a first capacitor C11, and a second capacitor C12; The first electrode of the first transistor T1 is connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is connected to the first node N1; the control electrode of the second transistor T2 is connected to the second local driving circuit 602, the first electrode of the second transistor T2 is connected to the first node N1, and the second electrode of the second transistor T2 is connected to the third node N3; the control electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3; the control electrode of the fourth transistor T4 is connected to the third local driving circuit 603, and the first electrode of the fourth transistor T4 is connected to the data line INIT1. The control electrode of the fifth transistor T5 is connected to the light emitting line E, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the second node N2; the control electrode of the sixth transistor T6 is connected to the light emitting line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the fourth node N4; the control electrode of the seventh transistor T7 is connected to the first reset line Reset1, the first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is connected to the fourth node N4; the eighth transistor T7 is connected to the first reset line Reset1, the first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is connected to the fourth node N4; A control electrode of the transistor T8 is connected to the first reset line Reset1, a first electrode of the eighth transistor T8 is connected to the bias line Vbias, and a second electrode of the eighth transistor T8 is connected to the second node N2; a control electrode of the eleventh transistor T11 is connected to the fourth local driving circuit 604, a first electrode of the eleventh transistor T11 is connected to the reference voltage line Vref, and a second electrode of the eleventh transistor T11 is connected to the sixth node N6; a first end of the first capacitor C11 is connected to the first power supply line VDD, and a second end of the first capacitor C11 is connected to the sixth node N6; a first end of the second capacitor C12 is connected to the sixth node N6, and a second end of the second capacitor C12 is connected to the first node N1.The first to fourth local driving circuits 601 to 604 may be the local driving circuits 60 described in any of the above embodiments. The circuit structures of the first to third local driving circuits 601 to 604 may be the same or different. In an exemplary embodiment, the first to fourth local driving circuits 601 to 604 may be the same local driving circuit 60, respectively connected to the control electrodes of the first transistor T1, the second transistor T2, the fourth transistor T4, and the eleventh transistor T11. The local driving circuit 60 may control the eighth transistor T8 based on the fourth transistor T4 to perform threshold compensation on the first node N1 and write the threshold voltage vth of the driving transistor T3.

[0232] As shown in Figure 15e, the local area circuit 60 may include a first local driving circuit 601 to a third local driving circuit 603, and the pixel driving circuit 50 may include a first transistor T1 (as an initial row transistor), a second transistor T2 (as an initialization transistor), a third transistor T3 (as a driving transistor), a fourth transistor T4 (as a data writing transistor), a fifth transistor T5 (as a light-emitting transistor) and a capacitor C; wherein the control electrode of the first transistor T1 is connected to the first local driving circuit 601, the first electrode of the first transistor T1 is connected to the first low-voltage power supply line VSS1, and the second electrode of the first transistor T1 is connected to the third node N3; the control electrode of the second transistor T2 is connected to the second local driving circuit 602, and the first electrode of the second transistor T2 is connected to the first low-voltage power supply line VSS1. The second low voltage power supply line VSS2 is connected, the second electrode of the second transistor T2 is connected to the first node N1; the control electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3; the control electrode of the fourth transistor T4 is connected to the third local driving circuit 603, the first electrode of the fourth transistor T4 is connected to the data line Data, and the second electrode of the fourth transistor T4 is connected to the first node N1; the control electrode of the fifth transistor T5 is connected to the light emitting line E, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the second node N2; the first end of the capacitor C is connected to the first node N1, and the second end of the capacitor C1 is connected to the third node N3. The first to third local driver circuits 601 to 603 may be the local driver circuits 60 described in any of the above embodiments. The circuit structures of the first to third local driver circuits 601 to 603 may be the same or different. In an exemplary embodiment, the first to third local driver circuits 601 to 603 may be the same local driver circuit 60, connected to the control electrodes of the first transistor T1, the second transistor T2, and the fourth transistor T4, respectively. The local driver circuit 60 may perform threshold compensation on the first node N1 based on the control of the fourth transistor T4 to write the threshold voltage vth of the driver transistor T3.

[0233] As can be seen from the above, the local driving circuit 60 can control the control electrode of the transistor connected to the driving transistor T3 in the pixel driving circuit 50 to control the threshold compensation of the control electrode of the driving transistor T3, thereby controlling the refresh of the pixels in the local area of ​​the display substrate.

[0234] The technical solutions of the embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0235] FIG7 is an equivalent circuit diagram of a pixel driving device provided by an embodiment of the present disclosure. The pixel driving device may include a pixel driving circuit 50 and a local driving circuit 60. As shown in FIG7 , the pixel driving circuit 50 may be connected to the local driving circuit and 10 signal lines (data line Data, first scan line Gate1, first reset line Reset1, second reset line Reset2, emission line E, first initial signal line INIT1, second initial signal line INIT2, third initial signal line INIT3, first power line VDD, and second power line VSS). The gate lines include: first scan line Gate1, first reset line Reset1, second reset line Reset2, and emission line E.

[0236] As shown in FIG7 , the pixel driving circuit 50 may include first to eighth transistors T1 to T8 and a capacitor C (which may be referred to as a storage capacitor). The control electrode of the first transistor T1 is connected to the first reset line Reset1, the first electrode of the first transistor T1 is connected to the first initial signal line INIT1, and the second electrode of the first transistor is connected to the third node N3. The control electrode of the second transistor T2 is connected to the local driving circuit, the first electrode of the second transistor T2 is connected to the first node N1, and the second electrode of the second transistor T2 is connected to the third node N3. The control electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3. The control electrode of the fourth transistor T4 is connected to the first scan line Gate1, the first electrode of the fourth transistor T4 is connected to the data line Data, and the second electrode of the fourth transistor T4 is connected to the second node N2. The control electrode of the fifth transistor T5 is connected to the emission line E, the first electrode of the fifth transistor T5 is connected to the first power line VDD, and the second electrode of the fifth transistor T5 is connected to the second node N2. A control electrode of the sixth transistor T6 is connected to the emission line E, a first electrode of the sixth transistor T6 is connected to the third node N3, and a second electrode of the sixth transistor T6 is connected to the fourth node N4. A control electrode of the seventh transistor T7 is connected to the second reset line Reset2, a first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and a second electrode of the seventh transistor T7 is connected to the fourth node N4. A control electrode of the eighth transistor T8 is connected to the second reset line Reset2, a first electrode of the eighth transistor T8 is connected to the third initial signal line INIT3, and a second electrode of the eighth transistor T8 is connected to the second node N2. A first end of the storage capacitor C is connected to the first power supply line VDD, and a second end of the storage capacitor C is connected to the first node N1.

[0237] In an exemplary embodiment, a first electrode of the light emitting device is electrically connected to the fourth node N4 , and a second electrode of the light emitting device is connected to the second power line VSS.

[0238] In an exemplary embodiment, the signal of the second power line VSS may be a low-level signal, and the signal of the first power line VDD may be a high-level signal.

[0239] 7 , the local driving circuit 60 may be connected to at least one pixel driving circuit 50 , the column control line C-Gate, and the row control line N-Gate. The local driving circuit 60 may include a ninth transistor T9 and a tenth transistor T10.

[0240] The control electrode of the ninth transistor T9 is connected to the column control line C-Gate, and the first electrode of the ninth transistor T9 is connected to the row control line N-Gate; the control electrode of the tenth transistor T10 is connected to the column control line C-Gate, the first electrode of the tenth transistor T10 is connected to the row control line N-Gate, and the second electrode of the tenth transistor T10 is connected to the low-voltage power supply line VGL.

[0241] Transistors can be divided into N-type transistors and P-type transistors according to their characteristics. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltages), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltages). When the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltages), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltages).

[0242] In an exemplary embodiment, as shown in FIG7 , the first transistor T1, the third transistor T3 to the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 may be P-type transistors (which may be low-temperature polysilicon thin-film transistors or low-temperature polysilicon transistors), and the second transistor T2 may be an N-type transistor (which may be an oxide thin-film transistor or an oxide transistor). Low-temperature polysilicon thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate can leverage the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0243] In an exemplary embodiment, the first reset line Reset1 and the second reset line Reset2 may be one signal line or share one signal.

[0244] FIG8 is a timing diagram illustrating an operation process of the pixel driving device provided in FIG7. In an exemplary embodiment, the pixel driving device may include four operation processes: a first operation process is a row refresh, column hold frame; a second operation process is a row refresh, column refresh frame; a third operation process is a row hold, column hold frame; and a fourth operation process is a row hold, column refresh frame. In each of the four operation processes, the potential of the fifth node N5 may be controlled by the local driving circuit 60, thereby controlling the conduction or disconnection of the second transistor T2 in the pixel driving circuit.

[0245] The first operation process of the pixel driving device shown in FIG8 may include a first stage P11 to a fifth stage P15 (this process may be referred to as a row refresh and column hold frame). In the first operation process, the signal of the column control line C-Gate is a high-level signal, the ninth transistor T9 is turned off, and the tenth transistor T10 is turned on. The low-level signal of the low-voltage power line VGL is transmitted to the fifth node N5 via the tenth transistor T10. Since the ninth transistor T9 is turned off, the signal of the row control line N-Gate cannot be written to the fifth node N5. The signal of the fifth node N5 is a low-level signal, and the second transistor T2 is turned off. The first operation process is as follows:

[0246] The first phase P11 is called a reset phase. The signals on the first reset line Reset1 and the second reset line Reset2 are low-level signals, and the signals on the first scan line Gate1 and the light-emitting line E are high-level signals. The signals on the first reset line Reset1 and the second reset line Reset2 are low-level signals, turning on the first transistor T1, the seventh transistor T7, and the eighth transistor T8. The signal on the first initial signal line INIT1 is supplied to the third node N3 to initialize (reset) the third node N3 and clear the original charge in the third node N3. The signal on the second initial signal line INIT2 is supplied to the fourth node N4 to initialize (reset) the first electrode of the light-emitting device L and clear the original charge in the first electrode of the light-emitting device L. The signal on the third initial signal line INIT3 is supplied to the second node N2 to initialize (reset) the second node N2 and clear the original charge in the second node N2. Because the second transistor T2 is turned off, the signal at the third node N3 cannot be transmitted to the first node N1 via the second transistor T2, and the signal at the first node N1 is not initially transmitted. The first node N1 maintains a low level. During this stage, the second end of the storage capacitor C is at a low level, and the third transistor T3 is turned on. The signals at the first scan line Gate1 and the emission line E are high, and the first transistor T1, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned off. During this stage, the light-emitting device L does not emit light.

[0247] In the second phase P12, known as the data writing phase or threshold compensation phase, the signal on the first scan line Gate1 is low, while the signals on the first reset line Reset1, the second reset line Reset2, and the light-emitting line E are high. The low signal on the first scan line Gate1 turns on the fourth transistor T4, and the data voltage on the data line Data is written to the second node N2 via the fourth transistor T4. Because the second transistor T2 is off, the signals on the second node N2 and the third node N3 cannot be written to the first node N1 via the second transistor T2. The first node N1 remains low, and the third transistor T3 remains on. The data voltage on the data line Data cannot be delivered to the first node N1 via the turned-on fourth transistor T4, the second node N2, the turned-on third transistor T3, the third node N3, and the second transistor T2. Consequently, the difference between the data voltage on the data line Data and the threshold voltage of the third transistor T3 cannot be charged into the storage capacitor C. The second end of the storage capacitor C maintains its original potential. During this phase, no data is written to the first node N1, and no threshold compensation is performed on the third transistor T3. The signals of the first reset line Reset1, the second reset line Reset2 and the light emitting line E are high level signals, and the first transistor T1, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 are turned off. In this stage, the light emitting device L does not emit light.

[0248] In the third phase P13, known as the continuous compensation phase, the signals on the first reset line Reset1, the second reset line Reset2, the first scan line Gate1, and the emission line E are high-level signals. Because the second transistor T2 is disconnected, the signals on the second node N2 and the third node N3 cannot be written to the first node N1 via the second transistor T2. The signals on the first scan line Gate1, the first reset line Reset1, the second reset line Reset2, and the emission line E are high-level signals. The first transistor T1, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are disconnected. Because the second transistor T2 is disconnected, the signal on the data line Data is not written to the first node N1, and the threshold voltage of the third transistor T3 is not compensated.

[0249] In the fourth phase P14, the signal on the second reset line Reset2 is low, while the signals on the first reset line Reset1, the first scan line Gate1, and the light-emitting line E are high. The signals on the first scan line Gate1, the first reset line Reset1, and the light-emitting line E are high, and the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are all turned off. During this phase, the light-emitting device L does not emit light.

[0250] The fifth stage P15, which can be called the light-emitting stage, is characterized by a low-level signal on the light-emitting line E, and a high-level signal on the first reset line Reset1, the second reset line Reset2, and the first scan line Gate1. The low-level signal on the light-emitting signal line E turns on the fifth transistor T5 and the sixth transistor T6. The power supply voltage output by the first power supply line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fifth transistor T5, the third transistor T3, and the sixth transistor T6, driving the light-emitting device L to emit light. The brightness of the light remains unchanged from the previous frame.

[0251] During the row refresh and column hold frame, during the blanking phase (Blank region) between this frame and the previous frame, the column control line C-Gate (also known as the column gate line, or Column Gate in English) can be switched to control the ninth transistor T9 to be off and the tenth transistor T10 to be on. The low-level signal of the low-voltage power line VGL is written to the fifth node N5 via the tenth transistor T10, and the second transistor T2 is in the off state. The pixel driving circuit 50 does not initialize the potential of the first node N1 during the reset phase, nor does it perform threshold compensation on the first node N1 during the threshold compensation phase. The pixel's luminous brightness remains unchanged from the previous frame. In this frame, since the ninth transistor T9 is off, the signal on the row control line N-Gate does not affect the potential of the fifth node N5.

[0252] The second operation process may include a first stage P21 to a fifth stage P25 (this state may be referred to as a row refresh or column refresh frame). In the second operation process, the signal of the column control line C-Gate is a low-level signal, the ninth transistor T9 is turned on, and the tenth transistor T10 is turned off. The low-level signal of the low-voltage power line VGL cannot be transmitted to the fifth node N5 via the tenth transistor T10. Since the ninth transistor T9 is turned on, the signal of the row control line N-Gate may be written into the fifth node N5 via the ninth transistor T9. The signal of the fifth node N5 changes with the signal of the row control line N-Gate. The second operation process is as follows:

[0253] The first phase P21 is called the reset phase. The signals of the first reset line Reset1 and the second reset line Reset2 are low-level signals, and the signals of the row control line N-Gate, the first scan line Gate1, and the light-emitting line E are high-level signals. The signals of the first reset line Reset1 and the second reset line Reset2 are low-level signals, turning on the first transistor T1, the seventh transistor T7, and the eighth transistor T8. The signal of the first initial signal line INIT1 is provided to the third node N3 to initialize (reset) the third node N3 and clear the original charge in the third node N3. The signal of the second initial signal line INIT2 is provided to the fourth node N4 to initialize (reset) the first electrode of the light-emitting device L and clear the original charge in the first electrode of the light-emitting device L. The signal of the third initial signal line INIT3 is provided to the second node N2 to initialize (reset) the second node N2 and clear the original charge in the second node N2. Since the high-level signal on the row control line N-Gate can be written to the fifth node N5 via the ninth transistor T9, the fifth node N5 is at a high level, turning on the second transistor T2. The signals on the second node N2 and the third node N3 can be provided to the first node N1 via the second transistor T2, initializing (resetting) the first node N1. The first node N1 is at a low level, turning on the third transistor T3. The signals on the first scan line Gate1 and the emission line E are high-level signals, and the first transistor T1, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned off. At this stage, the light-emitting device L does not emit light.

[0254] In the second phase P22, known as the data writing phase or threshold compensation phase, the signal on the first scan line Gate1 is low, while the signals on the row control line N-Gate, the first reset line Reset1, the second reset line Reset2, and the emission line E are high. The low signal on the first scan line Gate1 turns on the fourth transistor T4, and the data voltage on the data line Data is written to the second node N2 via the fourth transistor T4. Because the voltage across the storage capacitor C does not suddenly change, the voltage on the first node N1 remains at the low level of the previous phase, and the third transistor T3 remains on. Since the high-level signal of the row control line N-Gate can be written to the fifth node N5 via the ninth transistor T9, the fifth node N5 is at a high level, the second transistor T2 is turned on, and the data voltage output by the data line Data can be provided to the first node N1 via the turned-on fourth transistor T4, the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage output by the data line Data and the threshold voltage of the third transistor T3 is charged into the storage capacitor C. The voltage at the second end of the storage capacitor C (the first node N1) is Vd-|Vth|, where Vd is the data voltage output by the data line Data and Vth is the threshold voltage of the third transistor T3. The signals of the first reset line Reset1, the second reset line Reset2, and the emission line E are high-level signals, and the first transistor T1, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off. At this stage, the light-emitting device L does not emit light.

[0255] In the third phase P23, referred to as the continuous compensation phase, the signals on the row control line N-Gate, the first reset line Reset1, the second reset line Reset2, the first scan line Gate1, and the emission line E are all high-level signals. Since the high-level signal on the row control line N-Gate can be written into the fifth node N5 via the ninth transistor T9, the fifth node N5 is at a high level, the second transistor T2 is turned on, and the signals on the second node N2 and the third node N3 can be written into the first node N1 via the second transistor T2. The signals on the first scan line Gate1, the first reset line Reset1, the second reset line Reset2, and the emission line E are all high-level signals, and the first transistor T1, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off. Although the signal of the data line Data stops being written, the second node N2 can still be provided to the first node N1 through the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2, and the threshold voltage of the third transistor T3 is continuously compensated. Finally, the potential of the first node N1 is VN1=Vdata+Vth=Vdata-|Vth|.

[0256] In the fourth phase P24, the signal on the row control line N-Gate is low, while the signals on the first reset line Reset1, the second reset line Reset2, the first scan line Gate1, and the light-emitting line E are high. The low signal on the row control line N-Gate is written to the fifth node N5 via the ninth transistor T9, causing the fifth node N5 to be low and the second transistor T2 to be off. The signals on the first scan line Gate1, the first reset line Reset1, and the light-emitting line E are high, and the first transistor T1, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are all off. During this phase, the light-emitting device L does not emit light.

[0257] In the fifth phase P25, known as the light-emitting phase, the signals on the row control line N-Gate and the light-emitting line E are low-level signals, while the signals on the first reset line Reset1, the second reset line Reset2, and the first scan line Gate1 are high-level signals. The low-level signal on the row control line N-Gate is written to the fifth node N5 via the ninth transistor T9, causing the fifth node N5 to be low-level and the second transistor T2 to be off. The signal on the light-emitting signal line E is low-level, turning on the fifth transistor T5 and the sixth transistor T6. The power supply voltage output from the first power line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fifth transistor T5, the third transistor T3, and the sixth transistor T6, driving the light-emitting device L to emit light.

[0258] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the third transistor T3 is: I=K*(Vgs-Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd)] 2

[0259] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light-emitting device L, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data line D, and Vdd is the power supply voltage output by the first power supply line VDD.

[0260] It can be seen from the derivation results of the above current formula that in the light-emitting stage, the driving current of the third transistor T3 is no longer affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, ensuring uniform display brightness of the display product and improving the display effect of the entire display product.

[0261] During the working process of the row refresh and column refresh frames, in the blanking stage (Blank area) of this frame and the previous frame, the column control line C-Gate can be switched to control the ninth transistor T9 to be turned on and the tenth transistor T10 to be turned off. The signal of the row control line N-Gate is written into the fifth node N5 via the ninth transistor T9. Under the control of the signal of the row control line N-Gate, the second transistor T2 is turned on in the reset stage and the threshold compensation stage of the pixel driving circuit 50. The pixel driving circuit 50 initializes the potential of the first node N1 in the reset stage and performs threshold compensation on the first node N1 in the threshold compensation stage. The pixel driving circuit 50 drives the corresponding light-emitting device L to refresh the brightness.

[0262] The third operation process may include a first stage P31 to a fifth stage P35 (this process may be referred to as a row hold and column hold frame). In the third operation process, the signal of the column control line C-Gate is a high-level signal, the ninth transistor T9 is turned off, and the tenth transistor T10 is turned on. The low-level signal of the low-voltage power line VGL is transmitted to the fifth node N5 via the tenth transistor T10. Since the ninth transistor T9 is turned off, the signal of the row control line N-Gate cannot be written to the fifth node N5. The signal of the fifth node N5 is a low-level signal, and the second transistor T2 is turned off. The third operation process is as follows:

[0263] The first phase P31 is called the reset phase. The signals of the first reset line Reset1 and the second reset line Reset2 are low-level signals, and the signals of the first scan line Gate1 and the light-emitting line E are high-level signals. The signals of the first reset line Reset1 and the second reset line Reset2 are low-level signals, turning on the first transistor T1, the seventh transistor T7, and the eighth transistor T8. The signal of the first initial signal line INIT1 is provided to the third node N3 to initialize (reset) the third node N3 and clear the original charge in the third node N3. The signal of the second initial signal line INIT2 is provided to the fourth node N4 to initialize (reset) the first electrode of the light-emitting device L and clear the original charge in the first electrode of the light-emitting device L. The signal of the third initial signal line INIT3 is provided to the second node N2 to initialize (reset) the second node N2 and clear the original charge in the second node N2. Because the second transistor T2 is turned off, the signal at the third node N3 cannot be transmitted to the first node N1 via the second transistor T2. The first node N1 maintains a low level. During this phase, the potential of the first node N1 is not initialized. The second end of the storage capacitor C is at a low level, and the third transistor T3 is turned on. The signals at the first scan line Gate1 and the light-emitting line E are high-level signals, and the first transistor T1, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned off. During this phase, the light-emitting device L does not emit light.

[0264] In the second phase P32, known as the data writing phase or threshold compensation phase, the signal on the first scan line Gate1 is low, while the signals on the first reset line Reset1, the second reset line Reset2, and the light-emitting line E are high. The low signal on the first scan line Gate1 turns on the fourth transistor T4, and the data voltage on the data line Data is written to the second node N2 via the fourth transistor T4. Because the second transistor T2 is off, the signals on the second node N2 and the third node N3 cannot be written to the first node N1 via the second transistor T2. The first node N1 remains low, and the third transistor T3 remains on. The data voltage output by Data cannot be delivered to the first node N1 via the turned-on fourth transistor T4, the second node N2, the turned-on third transistor T3, the third node N3, and the second transistor T2. Consequently, the difference between the data voltage output by the data line Data and the threshold voltage of the third transistor T3 cannot be charged into the storage capacitor C. The second end of the storage capacitor C (the first node N1) maintains its original potential. During this phase, no data is written to the first node N1, and no threshold compensation is performed on the third transistor T3. The signals of the first reset line Reset1, the second reset line Reset2 and the light emitting line E are high level signals, and the first transistor T1, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 are turned off. In this stage, the light emitting device L does not emit light.

[0265] In the third phase P33, the signals on the first reset line Reset1, the second reset line Reset2, the first scan line Gate1, and the emission line E are all high-level signals. Because the second transistor T2 is disconnected, the signals on the second node N2 and the third node N3 cannot be written to the first node N1 via the second transistor T2. The signals on the first scan line Gate1, the first reset line Reset1, the second reset line Reset2, and the emission line E are all high-level signals. The first transistor T1, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are all disconnected. Because the second transistor T2 is disconnected, the signal on the data line Data is not written to the first node N1, and the threshold voltage of the third transistor T3 is not compensated.

[0266] In the fourth phase P34, the signals on the second reset line Reset2, the first scan line Gate1, and the light-emitting line E are all high-level signals. The signals on the first scan line Gate1, the first reset line Reset1, and the light-emitting line E are all high-level signals, and the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are all turned off. During this phase, the light-emitting device L does not emit light.

[0267] In the fifth phase P35, referred to as the light-emitting phase, the signal on the light-emitting line E is a low-level signal, while the signals on the first reset line Reset1, the second reset line Reset2, and the first scan line Gate1 are high-level signals. The signal on the light-emitting signal line E is a low-level signal, turning on the fifth transistor T5 and the sixth transistor T6. The power supply voltage output by the first power supply line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fifth transistor T5, the third transistor T3, and the sixth transistor T6, driving the light-emitting device L to emit light. The brightness of the light emission can be maintained unchanged from the brightness of the previous frame.

[0268] During the operation of the row hold and column hold frames, in the blanking phase (Blank region) between this frame and the previous frame, the column control line C-Gate can be switched to control the ninth transistor T9 to be off and the tenth transistor T10 to be on. The low-level signal of the low-voltage power line VGL is written to the fifth node N5 via the tenth transistor T10, and the second transistor T2 is in the off state. The pixel driving circuit 50 does not initialize the potential of the first node N1 during the reset phase, nor does it perform threshold compensation on the first node N1 during the threshold compensation phase. The brightness of the pixel can maintain the brightness of the previous frame unchanged. In this frame, since the ninth transistor T9 is off, the signal of the row control line N-Gate does not affect the potential of the fifth node N5.

[0269] The fourth working process may include a first stage P41 to a fifth stage P45 (this state may be referred to as a row hold and column refresh frame). In the fourth working process, the signal of the column control line C-Gate and the signal of the row control line N-Gate are low-level signals, the ninth transistor T9 is turned on, and the tenth transistor T10 is turned off. The low-level signal of the low-voltage power supply line VGL cannot be transmitted to the fifth node N5 via the tenth transistor T10. Since the ninth transistor T9 is turned on, the low-level signal of the row control line N-Gate can be written to the fifth node N5 via the ninth transistor T9. The signal of the fifth node N5 is a low-level signal, and the second transistor T2 is turned off. The second working process is as follows:

[0270] The first phase P41 is called a reset phase. The signals of the first reset line Reset1 and the second reset line Reset2 are low-level signals, and the signals of the first scan line Gate1 and the light-emitting line E are high-level signals. The signals of the first reset line Reset1 and the second reset line Reset2 are low-level signals, turning on the first transistor T1, the seventh transistor T7, and the eighth transistor T8. The signal of the first initial signal line INIT1 is provided to the third node N3 to initialize (reset) the third node N3 and clear the original charge in the third node N3. The signal of the second initial signal line INIT2 is provided to the fourth node N4 to initialize (reset) the first electrode of the light-emitting device L and clear the original charge in the first electrode of the light-emitting device L. The signal of the third initial signal line INIT3 is provided to the second node N2 to initialize (reset) the second node N2 and clear the original charge in the second node N2. Because the second transistor T2 is turned off, the signals at the second node N2 and the third node N3 cannot be provided to the first node N1 via the second transistor T2. The potential of the first node N1 is not initialized, and the first node N1 can maintain a low level. The third transistor T3 is turned on. The signals at the first scan line Gate1 and the light-emitting line E are high-level signals, and the first transistor T1, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned off. At this stage, the light-emitting device L does not emit light.

[0271] In the second phase P42, known as the data writing phase or threshold compensation phase, the signal on the first scan line Gate1 is low, while the signals on the first reset line Reset1, the second reset line Reset2, and the light-emitting line E are high. The low signal on the first scan line Gate1 turns on the fourth transistor T4, and the data voltage on the data line Data is written to the second node N2 via the fourth transistor T4. Because the voltage across the storage capacitor C does not undergo a sudden change, the voltage on the first node N1 remains low, and the third transistor T3 remains on. Because the second transistor T2 is off, the data voltage on the data line Data cannot pass through the turned-on fourth transistor T4, the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2 to the first node N1. Consequently, the difference between the data voltage on the data line Data and the threshold voltage of the third transistor T3 cannot be charged into the storage capacitor C. The second end of the storage capacitor C (the first node N1) maintains its original potential. During this phase, no data is written to the first node N1, and no threshold compensation is performed on the third transistor T3. The signals of the first reset line Reset1, the second reset line Reset2 and the light emitting line E are high level signals, and the first transistor T1, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 are turned off. In this stage, the light emitting device L does not emit light.

[0272] The third phase P43, known as the continuous compensation phase, is characterized by high-level signals on the first reset line Reset1, the second reset line Reset2, the first scan line Gate1, and the emission line E. Because the second transistor T2 is disconnected, the signals on the second node N2 and the third node N3 cannot be written to the first node N1 via the second transistor T2. The first node N1 remains at a low level, and the third transistor T3 remains on. The signals on the first scan line Gate1, the first reset line Reset1, the second reset line Reset2, and the emission line E are high-level signals, and the first transistor T1, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are disconnected. Because the second transistor T2 is disconnected, the signal on the data line Data is not written to the first node N1, and the threshold voltage of the third transistor T3 is not compensated.

[0273] In the fourth phase P44, the signals on the first reset line Reset1, the second reset line Reset2, the first scan line Gate1, and the light-emitting line E are all high-level signals. Because the signals on the first scan line Gate1, the first reset line Reset1, the second reset line Reset2, and the light-emitting line E are all high-level signals, the first transistor T1, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are all turned off. During this phase, the light-emitting device L does not emit light.

[0274] In the fifth phase P45, referred to as the light-emitting phase, the signal on the light-emitting line E is a low-level signal, while the signals on the first reset line Reset1, the second reset line Reset2, and the first scan line Gate1 are high-level signals. The signal on the light-emitting signal line E is a low-level signal, turning on the fifth transistor T5 and the sixth transistor T6. The power supply voltage output by the first power supply line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fifth transistor T5, the third transistor T3, and the sixth transistor T6, driving the light-emitting device L to emit light. The brightness of the light can be maintained at the brightness of the previous frame.

[0275] During the operation of the row hold and column refresh frames, in the blanking phase (Blank area) between this frame and the previous frame, the column control line C-Gate can be switched to control the ninth transistor T9 to be turned on and the tenth transistor T10 to be turned off. The signal of the row control line N-Gate is a low-level signal. The low-level signal of the row control line N-Gate is written to the fifth node N5 via the ninth transistor T9. The second transistor T2 is in the off state. The pixel driving circuit 50 will not initialize the potential of the first node N1 in the reset phase and will not perform threshold compensation on the first node N1 in the threshold compensation phase. The pixel luminous brightness can maintain the brightness of the previous frame unchanged.

[0276] In an exemplary embodiment, as shown in Figures 9a to 9c, equivalent circuit diagrams of three other pixel driving devices are shown. The pixel driving circuit 50 in the pixel driving devices shown in Figures 9a to 9c can be the same as the pixel driving circuit shown in Figure 7. As shown in Figures 9a and 9b, the local driving circuit 60 can include a ninth transistor T9. As shown in Figure 9a, the ninth transistor T9 can be a P-type transistor (which can be a low-temperature polysilicon thin-film transistor or a low-temperature polysilicon transistor). As shown in Figure 9b, the ninth transistor T9 can be an N-type transistor. As shown in Figure 9c, based on Figure 9a, the local driving circuit 60 can include a first capacitor C1, with a first end of the first capacitor C1 connected to the constant voltage power line VX, and a second end of the first capacitor C1 connected to the fifth node N5. The operation process of the pixel driving device of Figures 9a and 9c can be the same as the operation timing shown in Figure 8. The working timing of Figure 9b can be shown in Figure 10. The difference between the working timing shown in Figure 10 and the working timing described in Figure 8 is that the signal of the column control line C-Gate is opposite. For example, the column control line C-Gate is at a high level in the working timing shown in Figure 8, and is at a low level in the working timing shown in Figure 10. In the pixel driving device shown in Figures 9a to 9c, in the row refresh and column hold frame (the first working process) and in the row hold and column hold working process (the third working process), the column control line C-Gate controls the ninth transistor T9 to be turned off, the fifth node N5 is at a low level, the second transistor T2 is in a disconnected state, the pixel driving circuit 50 does not initialize the potential of the first node N1 in the reset phase, and does not perform threshold compensation on the first node N1 in the threshold compensation phase. The brightness of the pixel light remains unchanged at the brightness of the previous frame. Since the ninth transistor T9 is turned off, the signal of the row control line N-Gate does not affect the potential of the fifth node N5; in the row refresh and column refresh frame working process (the above-mentioned second working process), the column control line C-Gate controls the ninth transistor T9 to be turned on, and the potential of the fifth node N5 is consistent with the row control line C-Gate. The potential of the control line N-Gate signal is consistent, the pixel driving circuit 50 initializes the potential of the first node N1 in the reset stage, and performs threshold compensation on the first node N1 in the threshold compensation stage. The pixel driving circuit 50 can drive the corresponding light-emitting device to refresh the brightness; in the row hold and column refresh frame working process (the fourth working process), the column control line C-Gate controls the ninth transistor T9 to be turned on, and the low-level signal of the row control line N-Gate is provided to the fifth node N5 via the ninth transistor T9. The fifth node N5 is at a low level, and the second transistor T2 is in a disconnected state. The pixel driving circuit 50 will not initialize the potential of the first node N1 in the reset stage, and will not perform threshold compensation on the first node N1 in the threshold compensation stage. The pixel light-emitting brightness maintains the brightness of the previous frame unchanged (that is, the brightness of the light-emitting device will not be refreshed).

[0277] In an exemplary embodiment, FIG11 is an equivalent circuit diagram of another pixel driving device. The pixel driving circuit 50 in the pixel driving device shown in FIG11 may be the same as the pixel driving circuit 50 shown in FIG7 . The difference is that in the local driving circuit 60, the ninth transistor T9 is an N-type transistor, and the tenth transistor T10 is a P-type transistor. The operating timing diagram of the pixel driving device shown in FIG11 may be as shown in FIG10 . In the pixel driving device shown in FIG11 , in the row refresh and column hold frame (the first working process) and in the row hold and column hold working process (the third working process), the column control line C-Gate controls the ninth transistor T9 to be turned off, the fifth node N5 is at a low level, the second transistor T2 is in a disconnected state, the pixel driving circuit 50 does not initialize the potential of the first node N1 in the reset phase, and does not perform threshold compensation on the first node N1 in the threshold compensation phase. The brightness of the pixel light remains unchanged from the brightness of the previous frame. Since the ninth transistor T9 is turned off, the signal of the row control line N-Gate does not affect the potential of the fifth node N5. In the row refresh and column refresh frame working process (the above-mentioned second working process), the column control line C-Gate controls the ninth transistor T9 to be turned on, the fifth node N5 is at a low level, and the second transistor T2 is in a disconnected state. The pixel driving circuit 50 does not initialize the potential of the first node N1 in the reset phase, and does not perform threshold compensation on the first node N1 in the threshold compensation phase. The brightness of the pixel light remains unchanged from the brightness of the previous frame. Since the ninth transistor T9 is turned off, the signal of the row control line N-Gate does not affect the potential of the fifth node N5. In the row refresh and column refresh frame working process (the above-mentioned second working process), the column control line C-Gate controls the ninth transistor T9 to be turned on, the fifth node N 5 is consistent with the potential of the row control line N-Gate signal. The pixel driving circuit 50 initializes the potential of the first node N1 in the reset stage and performs threshold compensation on the first node N1 in the threshold compensation stage. The pixel driving circuit 50 can drive the corresponding light-emitting device to refresh the brightness; in the row hold and column refresh frame working process (the fourth working process), the column control line C-Gate controls the ninth transistor T9 to be turned on, and the low-level signal of the row control line N-Gate is provided to the fifth node N5 via the ninth transistor T9. The fifth node N5 is at a low level, and the second transistor T2 is in a disconnected state. The pixel driving circuit 50 will not initialize the potential of the first node N1 in the reset stage and will not perform threshold compensation on the first node N1 in the threshold compensation stage. The pixel light-emitting brightness maintains the brightness of the previous frame unchanged.

[0278] In an exemplary embodiment, as shown in FIG. 12 a and FIG. 12 b , which are equivalent circuit diagrams of two other pixel driving devices, the pixel driving circuit 50 in the pixel driving devices shown in FIG. 12 a and FIG. 12 b may be the same as the pixel driving circuit 50 shown in FIG. 7 . The difference between the local driving circuit of Figure 12a and the local control circuit 60 of Figure 7 is that the first electrode of the ninth transistor T9 is connected to the column control line C-Gate, and the control electrodes of the ninth transistor T9 and the tenth transistor T10 are connected to the row control line N-Gate. The working timing diagram of the pixel driving device shown in Figure 12a can be shown in Figure 13. The difference between Figure 13 and Figure 8 is that the signal of the column control line C-Gate in Figure 13 is opposite to the signal of the column control line C-Gate in Figure 8, and the signal of the row control line N-Gate in Figure 13 is opposite to the signal of the row control line N-Gate in Figure 8. For example, the column control line C-Gate is at a high level in the working timing shown in Figure 8, and is at a low level in the working timing shown in Figure 13; the row control line N-Gate is at a low level in the working timing shown in Figure 13 when it is at a high level in the working timing shown in Figure 8. The difference between the local driving circuit of Figure 12b and the local control circuit 60 of Figure 11 is that the first electrode of the ninth transistor T9 is connected to the column control line C-Gate, and the control electrodes of the ninth transistor T9 and the tenth transistor T10 are connected to the row control line N-Gate. The operating timing diagram of the pixel driving device shown in Figure 12b can be shown in Figure 10.In the pixel driving device shown in Figures 12a and 12b, in the row refresh and column hold frame (the first working process) and in the row hold and column hold working process (the third working process), the signal of the column control line C-Gate is a low-level signal. Regardless of whether the row control line N-Gate controls the ninth transistor T9 to be turned on or off, the potential of the fifth node N5 is in a low-level state, the second transistor T2 is in a disconnected state, the pixel driving circuit 50 does not initialize the potential of the first node N1 in the reset phase, and does not perform threshold compensation on the first node N1 in the threshold compensation phase, and the pixel luminous brightness maintains the brightness of the previous frame unchanged; in the row refresh and column refresh frame working process (the above-mentioned second working process), the signal of the column control line C-Gate is a high-level signal. In the stage where the row control line N-Gate controls the ninth transistor T9 to be turned on, the fifth node N5 is in a low-level state. It is a high level, the pixel driving circuit 50 initializes the potential of the first node N1 in the reset phase and performs threshold compensation on the first node N1 in the threshold compensation phase, and the pixel driving circuit 50 can drive the corresponding light-emitting device to refresh the brightness; in the row hold and column refresh frame working process (the fourth working process), the row control line N-Gate controls the ninth transistor T9 to be disconnected and the tenth transistor T10 to be turned on, and the potential of the fifth node N5 will not be affected by the column control line C-Gate. The low-level signal of the low-voltage power line VGL is provided to the fifth node N5 via the tenth transistor T10. The fifth node N5 is a low level, and the second transistor T2 is in a disconnected state. The pixel driving circuit 50 will not initialize the potential of the first node N1 in the reset phase, and will not perform threshold compensation on the first node N1 in the threshold compensation phase. The pixel light-emitting brightness maintains the brightness of the previous frame unchanged.

[0279] In an exemplary embodiment, FIG14a shows an equivalent circuit diagram of another pixel driving device, and FIG14b shows an operation timing diagram of the pixel driving device shown in FIG14a. The difference between the pixel driving circuit 50 in the pixel driving device shown in FIG14a and the pixel driving circuit 50 shown in FIG7 is that the second transistor T2 is a P-type transistor. The difference between the local driving circuit 60 in FIG14a and the local control circuit 60 in FIG7 is that the tenth transistor T10 is a P-type transistor, the control electrode of the tenth transistor T10 is connected to the column additional control line C-Gate-N, and the first electrode of the tenth transistor T10 is connected to the high voltage power line VGH. The difference between FIG14b and FIG8 is that the signal of the row control line N-Gate in FIG14b is opposite to the signal of the row control line N-Gate in FIG8, and the signal of the fifth node N5 in FIG14b is opposite to the signal of the fifth node N5 in FIG8. The signal of the node N5 is opposite. For example, the row control line N-Gate is at a high level in the working timing shown in Figure 8, but is at a low level in the working timing shown in Figure 14b. The signal of the fifth node N5 is at a high level in the working timing shown in Figure 8, but is at a low level in the working timing shown in Figure 14b. Figure 14b has a timing of an additional column control line C-Gate-N in addition to Figure 8. In Figure 14b, the signal of the additional column control line C-Gate-N is opposite to the signal of the column control line C-Gate.In the pixel driving device shown in FIG14a, in the row refresh and column hold frame (the first working process) and in the row hold and column hold working process (the third working process), the signal of the column additional control line C-Gate-N is a low-level signal, the signal of the column control line C-Gate is a high-level signal, the tenth transistor T10 is turned on, the ninth transistor T9 is turned off, the potential of the fifth node N5 is in a high-level state (not affected by the row control line N-Gate), the second transistor T2 is in a disconnected state, the pixel driving circuit 50 does not initialize the potential of the first node N1 in the reset phase, and does not perform threshold compensation on the first node N1 in the threshold compensation phase, and the pixel luminous brightness maintains the brightness of the previous frame unchanged; in the row refresh and column refresh frame working process (the above-mentioned second working process), the signal of the column control line C-Gate is a low-level signal, the signal of the column additional control line C-Gate-N is a high-level signal, the ninth transistor T9 is turned on, the tenth transistor T10 is turned off, and the tenth transistor T10 is turned off. The transistor T10 is disconnected, and the potential of the fifth node N5 is consistent with the signal of the row control line N-Gate. The pixel driving circuit 50 initializes the potential of the first node N1 in the reset phase and performs threshold compensation on the first node N1 in the threshold compensation phase. The pixel driving circuit 50 can drive the corresponding light-emitting device to refresh the brightness; in the row hold and column refresh frame working process (the fourth working process), the signal of the column control line C-Gate is a low-level signal, and the signal of the column additional control line C-Gate-N is a high-level signal. The ninth transistor T9 is turned on and the tenth transistor T10 is disconnected. The high-level signal of the row control line N-Gate is provided to the fifth node N5 via the ninth transistor T9. The fifth node N5 is at a high level, and the second transistor T2 is in a disconnected state. The pixel driving circuit 50 will not initialize the potential of the first node N1 in the reset phase and will not perform threshold compensation on the first node N1 in the threshold compensation phase. The pixel light-emitting brightness maintains the brightness of the previous frame unchanged.

[0280] In an exemplary embodiment, as shown in FIG15a, an equivalent circuit diagram of another pixel driving device is shown, and FIG15b is an operation timing diagram of the pixel driving device shown in FIG15a. The difference between the pixel driving circuit 50 in the pixel driving device shown in FIG15a and the pixel driving circuit 50 shown in FIG7 is that the second transistor T2 is a P-type transistor. The difference between the local driving circuit 60 in FIG15a and the local control circuit 60 in FIG7 is that the tenth transistor T10 is a P-type transistor, the control electrode of the tenth transistor T10 is connected to the row additional control line N-Gate-N, the first electrode of the tenth transistor T10 is connected to the high voltage power line VGH, the first electrode of the ninth transistor T9 is connected to the column control line C-Gate, and the control electrode of the ninth transistor T9 is connected to the row control line N-Gate. The difference between FIG15b and FIG8 is that the row control line N-Gate in FIG15b is connected to the row control line N-Gate. The signal of te is opposite to the signal of the row control line N-Gate in Figure 8, and the signal of the fifth node N5 in Figure 15b is opposite to the signal of the fifth node N5 in Figure 8. For example, the row control line N-Gate is at a high level in the working timing shown in Figure 8, and is at a low level in the working timing shown in Figure 15b. Figure 15b has a timing of an additional row control line N-Gate-N in addition to Figure 8. In Figure 15b, the signal of the additional row control line N-Gate-N is opposite to the signal of the row control line N-Gate.In the pixel driving device shown in FIG15a, in the row refresh and column hold frame (the first working process) and in the row hold and column hold working process (the third working process), the signal of the column control line C-Gate is a high-level signal. When the row control line N-Gate controls the ninth transistor T9 to be turned on or the row additional control line N-Gate-N controls the tenth transistor T10 to be turned on, the potential of the fifth node N5 is in a high-level state, the second transistor T2 is in a disconnected state, the pixel driving circuit 50 does not initialize the potential of the first node N1 in the reset phase, and does not perform threshold compensation on the first node N1 in the threshold compensation phase, and the pixel luminous brightness maintains the brightness of the previous frame unchanged; in the row refresh and column refresh frame working process (the above-mentioned second working process), the signal of the column control line C-Gate is a low-level signal. When the row control line N-Gate controls the ninth transistor T9 to be turned on and the row additional control line N-Gate-N controls the tenth transistor T10 to be turned on, the potential of the fifth node N5 is in a high-level state, the second transistor T2 is in a disconnected state, the pixel driving circuit 50 does not initialize the potential of the first node N1 in the reset phase, and does not perform threshold compensation on the first node N1 in the threshold compensation phase, and the pixel luminous brightness maintains the brightness of the previous frame unchanged; in the row refresh and column refresh frame working process (the above-mentioned second working process), the signal of the column control line C-Gate is a low-level signal. In the stage where the transistor T10 is disconnected, the fifth node N5 is at a low level, the pixel driving circuit 50 initializes the potential of the first node N1 in the reset stage, and performs threshold compensation on the first node N1 in the threshold compensation stage, and the pixel driving circuit 50 can drive the corresponding light-emitting device to refresh the brightness; in the row hold and column refresh frame working process (the fourth working process), the row control line N-Gate controls the ninth transistor T9 to be disconnected, and the row additional control line N-Gate-N controls the tenth transistor T10 to be turned on, the potential of the fifth node N5 will not be affected by the column control line C-Gate, the high-level signal of the high-voltage power supply line VGH is provided to the fifth node N5 via the tenth transistor T10, the fifth node N5 is at a high level, the second transistor T2 is in a disconnected state, the pixel driving circuit 50 will not initialize the potential of the first node N1 in the reset stage, and will not perform threshold compensation on the first node N1 in the threshold compensation stage, and the pixel light-emitting brightness maintains the brightness of the previous frame unchanged.

[0281] In an exemplary embodiment, the plurality of transistors in the pixel driving device may be low-temperature polysilicon thin film transistors, or oxide thin film transistors, or both. The active layer of the low-temperature polysilicon thin film transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide thin film transistor is made of oxide semiconductor.

[0282] In an exemplary embodiment, using the same type of transistors in the pixel driving device can simplify the process flow, reduce the process difficulty of the display panel, and improve the product yield. As shown in Figures 14a and 15a, the multiple transistors in the pixel driving device are all P-type transistors; the present disclosure is not limited to this. For example, the multiple transistors in the pixel driving device can all be N-type transistors (i.e., low-temperature polysilicon thin-film transistors), or, as shown in Figures 7, 9a to 9c, and 11 to 12b, some transistors are N-type transistors and others are P-type transistors. The second transistor T2 in the pixel driving circuit 50 uses an N-type transistor (IGZO TFT) that can reduce the leakage of the first node N1. When using low-frequency display, the N-type transistor can ensure that the voltage of the storage capacitor C is maintained for a longer period of time, thereby reducing the repeated charging and discharging of the data line Data and reducing power consumption.

[0283] In the pixel circuit 50, the first scan line Gate1 is set to control the data voltage (Vdata) on the data line Data to be written into the second node N2; the fifth node N5 is set to control the reset of the storage capacitor C (that is, control the reset of the first node N1), extract the threshold voltage (Vth) and the data voltage (Vdata) of the driving transistor (the third transistor T3) and write them into the first node N1, the second reset line Reset2 is set to control the reset of the second node N2 and the fourth node N4 (the anode Anode of the light-emitting device L), and the first reset line Reset1 is set to control the reset of the first node N1 and the third node N3.

[0284] The local driving circuit 60 may include a ninth transistor T9 and a tenth transistor T10. As shown in FIG7 and FIG11 , the ninth transistor T9 or the tenth transistor T10 is turned on by controlling the column control line C-Gate, thereby controlling the potential of the fifth node N5 to select the low-voltage signal of the low-voltage power line VGL or the signal of the row control line N-Gate. This can prevent the column control line C-Gate from affecting the potential of the first node N1, thereby preventing screen splitting (e.g., pulse screen splitting) and flickering.

[0285] In FIG12a and FIG12b, the ninth transistor T9 or the tenth transistor T10 is turned on by controlling the row control line N-Gate, thereby controlling the potential of the fifth node N5 to select the low voltage signal of the low voltage power line VGL or the signal of the column control line C-Gate. This can avoid the influence of the row control line N-Gate on the potential of the first node N1, thereby preventing the occurrence of screen splitting (for example, pulse screen splitting) and flickering.

[0286] In FIG9a to FIG9c, the ninth transistor T9 is controlled to be turned on or off by the column control line C-Gate, thereby controlling the potential of the fifth node N5 to maintain a low voltage signal or to select the signal of the row control line N-Gate; when the control electrode of the ninth transistor T9 jumps, it will temporarily affect the voltage of the fifth node N5, but will not affect the voltage of the first node N1, so the current of the driving transistor (i.e., the third transistor T3) will not change. When the pixel driving circuit 50 drives the corresponding light-emitting device L to emit light, no flickering or split screen phenomenon will occur;

[0287] In FIG14a , the column control line C-Gate and the additional column control line C-Gate-N are used to control the ninth transistor T9 or the tenth transistor T10 to be turned on, thereby controlling the potential of the fifth node N5 to select the high voltage signal of the high voltage power line VGH or the signal of the row control line N-Gate. This can avoid the influence of the column control line C-Gate and the additional column control line C-Gate-N on the potential of the first node N1, thereby preventing the occurrence of screen splitting (e.g., pulse screen splitting) and flickering.

[0288] In Figure 15a, the ninth transistor T9 or the tenth transistor T10 is turned on by the row control line N-Gate and the row additional control line N-Gate-N, thereby controlling the potential of the fifth node N5 to select the high voltage signal of the high voltage power line VGH or the signal of the row control line N-Gate, which can avoid the influence of the row control line N-Gate and the row additional control line N-Gate-N on the potential of the first node N1, and prevent the occurrence of split screen (such as pulse split screen), flickering and other defects.

[0289] The solution provided by the embodiment of the present disclosure can control the sub-pixels in the display substrate to achieve local refresh through the local driving circuit 60, that is, the local screen of the display substrate can be updated, while the remaining screens do not need multiple charging and discharging (for example, screen-off display technology, static screens, etc. do not require multiple charging and discharging, and most of the pixel voltages in the display substrate do not need to be updated), which can further reduce the power consumption of the display substrate, or ultra-low power consumption of OLED display products such as wearable display devices, mobile display devices (mobile), and notebook computers (NB) can be achieved through local update of the display screen.

[0290] As shown in FIG16 , a schematic diagram of local refresh (which can be called partition refresh or local drive) of a display substrate under the control of a local drive circuit 60 is shown. The high refresh and low refresh in the row direction are controlled by a VCT signal (VCT Pulse), and the high refresh and low refresh in the column direction are controlled by an HCT signal (HCT Pulse). By combining the high and low refresh in the rows and columns, different refresh rates can be achieved in different areas, minimizing power consumption. The row-direction VCT signal and the column-direction HCT signal can be provided by a driver chip (driver IC) or other control signals, such as an enable signal EN, or a GOA. The row-direction VCT signal can be used to control a gate driver circuit (e.g., a first gate driver circuit N-Gate GOA) to generate a row control signal and provide the row control signal to the row control line N-Gate; the column-direction HCT signal can be used to control a gate driver circuit (e.g., a second gate driver circuit C-Gate GOA) to generate a column control signal and provide the column control signal to the column control line C-Gate. In an exemplary embodiment, in the first area A1 to the ninth area A9 shown in Figure 16, the working states of the pixel driving devices of the first area A1, the third area A3, the seventh area A7, and the ninth area A9 can be the "row hold + column hold" working process in Figure 8, the working states of the pixel driving devices of the second area A2 and the eighth area A8 in Figure 16 can be the "row hold + column refresh" working process in Figure 8, the working states of the pixel driving devices of the fourth area A4 and the sixth area A6 in Figure 16 can be the "row refresh + column hold" working process in Figure 8, and the working state of the pixel driving device of the fifth area A5 in Figure 16 can be the "row refresh + column refresh" working process in Figure 8.

[0291] In the disclosed embodiment, taking FIG7 as an example and referring to FIG16 , for example, in the area where the HCT pulse controls the column high refresh, the IC provides a low-voltage signal to the C-Gate GOA, causing the C-Gate GOA to control T9 to turn on in the corresponding column area, thereby enabling Ngate control of T2. In specific implementations, the IC can input the low-voltage signal into the data signal and transmit the corresponding signal to the C-Gate GOA via the data line. For example, in the area where the VCT pulse controls the row high refresh, the control signal provides a valid signal to the N-gate GOA in the corresponding area, thereby controlling T2 to turn on and achieving refresh in the row direction.

[0292] In the exemplary embodiment, the four operating processes in the operating timing diagrams shown in Figures 8, 10, 13, 14b, and 15b are connected for illustrative purposes only. In actual operation of a display substrate, two consecutive operating frames may be the same operating process, or two consecutive operating frames may be different operating processes, depending on the actual situation. The order of the four operating processes is not limited to the order shown in Figures 8, 10, 13, 14b, and 15b and can be adjusted according to actual circumstances. In other words, the four operating processes are independent operating processes, and one or more of the four operating processes can be used to control the refresh of pixels in a local area during operation of the display substrate, depending on the actual situation. As shown in Figure 17, when the ninth transistor T9 is not isolated from the first node N1 (i.e., the fifth node N5 is not isolated from the second transistor T2, and the ninth transistor T9 is directly connected to the first node N1), the column control line C-Gate directly affects the voltage of the first node N1 through the parasitic capacitance of the ninth transistor T9, resulting in flickering and a split screen. When the ninth transistor T9 is isolated from the first node N1 through the second transistor T2 and the fifth node N5, when the control electrode of the ninth transistor T9 jumps, it will briefly affect the voltage of the fifth node N5, but will not affect the voltage of the first node N1, so it will not cause the current of the driving transistor (i.e., the third transistor T3) to change. In the process of the pixel driving circuit 50 driving the corresponding light-emitting device L to emit light, no flickering or split screen phenomenon will occur.

[0293] As shown in Figure 18a, a schematic diagram of the basic connection architecture between the pixel driving circuit 50 (pixel unit) and the local driving circuit 60 (column unit) is shown; Figure 18b shows a schematic diagram of the connection between the pixel driving circuit 50 and the local driving circuit 60 in a 1-drive-1 structure, that is, one local driving circuit 60 is connected to one pixel driving circuit 50 in a row; Figure 18c shows a schematic diagram of the connection between the pixel driving circuit 50 and the local driving circuit 60 in a 1-drive-2 structure, that is, one local driving circuit 60 is connected to two pixel driving circuits 50 in a row; Figure 18d shows a schematic diagram of the connection between the pixel driving circuit 50 and the local driving circuit 60 in a 1-drive-4 structure, that is, one local driving circuit 60 is connected to four pixel driving circuits 50 in a row; Figure 18e shows a schematic diagram of the connection between the pixel driving circuit 50 and the local driving circuit 60 in a 1-drive-8 structure, that is, one local driving circuit 60 is connected to eight pixel driving circuits 50 in a row. In an exemplary embodiment, one local driving circuit 60 may drive n pixel driving circuits 50 , where n is a positive integer. For example, n may be 1 to 10,000.

[0294] As shown in FIG. 18 b to FIG. 18 f , each row control line N-Gate may extend along the row direction and be connected to a plurality of local driving circuits 60 located in at least one row, and be configured to provide a row control signal to the plurality of local driving circuits 60 in at least one row.

[0295] As shown in Figure 18f , each column control line C-Gate can extend along the column direction and be connected to a local driver circuit 60 located in at least one column, configured to provide column control signals to multiple local driver circuits 60 in at least one column. Figure 18f shows that each local driver circuit 60 is connected to at least some sub-pixels in one row, while Figure 18g shows that each local driver circuit 60 is connected to at least some sub-pixels in two rows.

[0296] In exemplary embodiments, the pixel driving devices shown in Figures 7, 9a to 9c, and 11 to 12b may be adapted for the connection architectures shown in Figures 18a to 18f; the pixel driving device shown in Figure 14a may be adapted for the connection architecture shown in Figure 19a; and the pixel driving device shown in Figure 15a may be adapted for the connection architecture shown in Figure 19b. Compared to Figures 18a to 18f, Figure 19a includes additional column control lines C-Gate-N. Each additional column control line C-Gate-N extends along the column direction and is located on one side of the corresponding column control line C-Gate in the row direction. It is connected to the local driving circuit 60 in at least one column and is configured to provide additional column control signals to the multiple local driving circuits 60 in at least one column. Compared to Figures 18a to 18f, Figure 19b includes additional row control lines N-Gate-N. Each additional row control line N-Gate-N extends along the row direction and is located on one side of the corresponding row control line N-Gate in the column direction. It is configured to provide additional row control signals to the multiple local driving circuits 60 in at least one row.

[0297] An embodiment of the present disclosure provides an operating method for a display substrate, which is applied to the display substrate described in any of the above embodiments. The display substrate includes a plurality of sub-pixels, at least one local driving circuit, at least one column control line, and at least one row control line. At least some of the sub-pixels include light-emitting devices and pixel driving circuits for driving the light-emitting devices to emit light. The pixel driving circuit is connected to one of the local driving circuits; the local driving circuit is connected to at least one pixel driving circuit, one of the column control lines, and one of the row control lines. The method includes:

[0298] The local driving circuit controls the pixel driving circuit connected thereto to operate under the control of the column control line and the row control line. The pixel driving circuit drives the corresponding light-emitting device to maintain the original brightness or refresh the brightness under the control of the local driving circuit.

[0299] The present disclosure provides a display device, as shown in FIG20 , which may include a display substrate according to any of the aforementioned embodiments. The display device may be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system.

[0300] In the substrate, operating method thereof, and display device provided by the embodiments of the present disclosure, a local driving circuit is configured to control the operation of a pixel driving circuit connected thereto under the control of a column control line and a row control line. The pixel driving circuit, under the control of the local driving circuit, drives the corresponding light-emitting device to maintain the original brightness or refresh the brightness, thereby reducing power consumption.

[0301] The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures may refer to general designs.

[0302] In the absence of conflict, the embodiments of the present disclosure, i.e., features in the embodiments, can be combined with each other to form new embodiments.

[0303] Although the embodiments disclosed in the present disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the present disclosure and are not intended to limit the present disclosure. Any person skilled in the art of the present disclosure may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the present disclosure. However, the scope of patent protection of the present disclosure shall still be based on the scope defined by the attached claims.

Claims

1. A display substrate comprising a plurality of sub-pixels, at least one local drive circuit, at least one column control line, and at least one row control line, wherein at least some of the sub-pixels include light-emitting devices and a pixel drive circuit for driving the light-emitting devices to emit light, and the pixel drive circuit is connected to one of the local drive circuits; The local driving circuit is connected to at least one pixel driving circuit, one of the column control lines and one of the row control lines, and is configured to control the operation of the pixel driving circuit connected thereto under the control of the column control line and the row control line; the pixel driving circuit drives the corresponding light-emitting device to maintain the original brightness or refresh the brightness under the control of the local driving circuit.

2. The display substrate according to claim 1, wherein The pixel driving circuits in the plurality of sub-pixels form a plurality of rows and a plurality of columns, the local driving circuit is located between two adjacent rows of pixel driving circuits, and the local driving circuit is connected to at least part of the pixel driving circuits in at least one row; There are multiple local drive circuits, and the multiple local drive circuits form multiple rows and multiple columns. The row control line is connected to at least one row of local drive circuits and is configured to provide a row control signal to the local drive circuit connected thereto; the column control line is connected to at least one column of local drive circuits and is configured to provide a column control signal to the local drive circuit connected thereto.

3. The display substrate according to claim 2, wherein: The local driving circuit is connected to n adjacent pixel driving circuits in a row of pixel driving circuits, where n is a positive integer; the row control line is connected to multiple local driving circuits in a row of local driving circuits; and the column control line is connected to multiple local driving circuits in a column of local driving circuits.

4. The display substrate according to claim 1, wherein: The pixel driving circuit includes a compensation transistor, and the local driving circuit is configured to control the compensation transistor to be turned on or off under the control of the column control line and the row control line.

5. The display substrate according to claim 4, wherein: The local driving circuit includes a first control transistor, a control electrode of the first control transistor is connected to the column control line, a first electrode of the first control transistor is connected to the row control line, and a second electrode of the first control transistor is connected to the control electrode of the compensation transistor. The display substrate according to claim 5 , wherein: The local driving circuit is configured to provide the signal of the row control line to the control electrode of the compensation transistor or control the control electrode of the compensation transistor to maintain an original potential under the control of the column control line.

7. The display substrate according to claim 6, wherein: The first control transistor is a P-type transistor, and the compensation transistor is an N-type transistor; When the signal of the column control line is at the first level, the local driving circuit provides the signal of the row control line to the control electrode of the compensation transistor, and the compensation transistor is turned on or off under the control of the signal of the row control line. The pixel driving circuit drives the corresponding light-emitting device to maintain the original brightness or refresh the brightness under the control of the signal of the row control line; When the signal of the column control line is at the second level, the compensation transistor is turned off under the control of the original potential, and the pixel driving circuit drives the corresponding light-emitting device to maintain the original brightness.

8. The display substrate according to claim 6, wherein: The first control transistor and the compensation transistor are N-type transistors; When the signal of the column control line is at the second level, the local driving circuit provides the signal of the row control line to the control electrode of the compensation transistor, and the pixel driving circuit drives the corresponding light-emitting device to maintain the original brightness or refresh the brightness under the control of the signal of the row control line; When the signal of the column control line is at the first level, the compensation transistor is turned off under the control of the original potential, and the pixel driving circuit drives the corresponding light-emitting device to maintain the original brightness.

9. The display substrate according to claim 5, wherein: The local driving circuit further includes a first capacitor, a first end of the first capacitor is connected to the constant voltage power line, and a second end of the first capacitor is connected to the second electrode of the first control transistor.

10. The display substrate according to claim 5 , further comprising a low-voltage power line, the local driving circuit further comprising a second control transistor, wherein a control electrode of the second control transistor is connected to the column control line, a second electrode of the second control transistor is connected to the control electrode of the compensation transistor, and a first electrode of the second control transistor is connected to the low-voltage power line; The local driving circuit is configured to provide a signal of the row control line or a signal of the low-voltage power line to a control electrode of the compensation transistor under the control of the column control line.

11. The display substrate according to claim 10, wherein: The first control transistor is a P-type transistor, and the compensation transistor and the second control transistor are N-type transistors; When the signal of the column control line is at the first level, the local driving circuit provides the signal of the row control line to the control electrode of the compensation transistor. The compensation transistor is turned on or off under the control of the signal of the row control line. The pixel driving circuit drives the corresponding light emitting device to maintain the state of the pixel driving circuit under the control of the signal of the row control line. Original brightness or refresh brightness; When the signal of the column control line is at the second level, the local driving circuit provides the signal of the low-voltage power line to the control electrode of the compensation transistor, the compensation transistor is disconnected under the control of the signal of the low-voltage power line, and the pixel driving circuit drives the corresponding light-emitting device to maintain the original brightness.

12. The display substrate according to claim 7 or 11, wherein: When the signal of the column control line is at the first level and the row control line is at the second level during the reset phase and the threshold compensation phase of one working frame of the pixel driving circuit, the local driving circuit provides the signal of the row control line to the control electrode of the compensation transistor during the reset phase and the threshold compensation phase of one working frame of the pixel driving circuit. The compensation transistor is turned on under the control of the signal of the row control line, and the pixel driving circuit drives the corresponding light-emitting device to refresh the brightness in this working frame. When the signal of the column control line is at the first level and the row control line is at the first level in an operating frame of the pixel driving circuit, the local driving circuit provides the signal of the row control line to the control electrode of the compensation transistor, and the compensation transistor is disconnected under the control of the signal of the row control line. The pixel driving circuit drives the corresponding light-emitting device to maintain the original brightness in this operating frame.

13. The display substrate according to claim 10, wherein: The first control transistor and the compensation transistor are N-type transistors, and the second control transistor is a P-type transistor; When the signal of the column control line is at the second level, the local driving circuit provides the signal of the row control line to the control electrode of the compensation transistor, and the compensation transistor is turned on or off under the control of the signal of the row control line. The pixel driving circuit drives the corresponding light-emitting device to maintain the original brightness or refresh the brightness under the control of the signal of the row control line; When the signal of the column control line is at the first level, the local driving circuit provides the signal of the low-voltage power line to the control electrode of the compensation transistor, the compensation transistor is disconnected under the control of the low-voltage power line, and the pixel driving circuit drives the corresponding light-emitting device to maintain the original brightness.

14. The display substrate according to claim 8 or 13, wherein: When the signal of the column control line is at the second level and the row control line is at the second level during the reset phase and the threshold compensation phase of one working frame of the pixel driving circuit, the local driving circuit provides the signal of the row control line to the control electrode of the compensation transistor during the reset phase and the threshold compensation phase of one working frame of the pixel driving circuit. The compensation transistor is turned on under the control of the signal of the row control line, and the pixel driving circuit drives the corresponding light-emitting device to refresh the brightness in this working frame. When the signal of the column control line is at the second level and the row control line is at the first level in an operating frame of the pixel driving circuit, the local driving circuit provides the signal of the row control line to the control electrode of the compensation transistor, and the compensation transistor is disconnected under the control of the signal of the row control line. The pixel driving circuit drives the corresponding light-emitting device to maintain the original brightness in this operating frame.

15. The display substrate according to claim 4, further comprising a low voltage power supply line, wherein the local driving circuit comprises a first control transistor and a second control transistor; The control electrode of the first control transistor is connected to the row control line, the first electrode of the first control transistor is connected to the column control line, and the second electrode of the first control transistor is connected to the control electrode of the compensation transistor; The control electrode of the second control transistor is connected to the row control line, the first electrode of the second control transistor is connected to a low voltage power line, and the second electrode of the second control transistor is connected to the control electrode of the compensation transistor.

16. The display substrate according to claim 15, wherein: The local driving circuit is configured to provide a signal of the column control line or a signal of the low voltage power line to the control electrode of the compensation transistor under the control of the row control line, thereby controlling the compensation transistor to be turned on or off.

17. The display substrate according to claim 16, wherein: The first control transistor is a P-type transistor, and the compensation transistor and the second control transistor are N-type transistors; When the signal of the column control line is at the second level, the pixel driving circuit drives the corresponding light-emitting device to maintain the original brightness or refresh the brightness under the control of the row control line and the local driving circuit; When the signal of the column control line is at the first level, the compensation transistor is turned off under the control of the signal of the column control line or the low voltage power line, and the pixel driving circuit drives the corresponding light emitting device to maintain the original brightness.

18. The display substrate according to claim 17, wherein: When the signal of the column control line is at the second level and the row control line is at the first level during the reset phase and the threshold compensation phase of one working frame of the pixel driving circuit, the local driving circuit provides the signal of the column control line to the control electrode of the compensation transistor during the reset phase and the threshold compensation phase of one working frame of the pixel driving circuit. The compensation transistor is turned on under the control of the column control line, and the pixel driving circuit drives the corresponding light-emitting device to refresh the brightness in this working frame. When the signal of the column control line is at the second level and the row control line is at the second level in an operating frame of the pixel driving circuit, the local driving circuit drops the signal of the low-voltage power line under the control of the row control line and provides it to the control electrode of the compensation transistor. The compensation transistor is disconnected under the control of the signal of the low-voltage power line, and the pixel driving circuit drives the corresponding light-emitting device to maintain the original brightness in this operating frame.

19. The display substrate according to claim 16, wherein: The first control transistor and the compensation transistor are N-type transistors, and the second control transistor is a P-type transistor; When the signal of the column control line is at the second level, the pixel driving circuit drives the corresponding light-emitting device to maintain the original brightness or refresh the brightness under the control of the row control line and the local driving circuit; When the signal of the column control line is at the first level, the compensation transistor is turned off under the control of the signal of the column control line or the low voltage power line, and the pixel driving circuit drives the corresponding light emitting device to maintain the original brightness.

20. The display substrate according to claim 19, wherein When the signal of the column control line is at the second level and the row control line is at the second level during the reset phase and the threshold compensation phase of one working frame of the pixel driving circuit, the local driving circuit provides the signal of the column control line to the control electrode of the compensation transistor during the reset phase and the threshold compensation phase of one working frame of the pixel driving circuit. The compensation transistor is turned on under the control of the signal of the column control line, and the pixel driving circuit drives the corresponding light-emitting device to refresh the brightness in this working frame. When the signal of the column control line is at the second level and the row control line is at the first level in an operating frame of the pixel driving circuit, the local driving circuit drops the signal of the low-voltage power line under the control of the row control line and provides it to the control electrode of the compensation transistor. The compensation transistor is disconnected under the control of the signal of the low-voltage power line, and the pixel driving circuit drives the corresponding light-emitting device to maintain the original brightness in this operating frame.

21. The display substrate according to claim 4, further comprising a column additional control line and a high voltage power supply line, wherein the local driving circuit comprises a first control transistor and a second control transistor; The control electrode of the first control transistor is connected to the column control line, the first electrode of the first control transistor is connected to the row control line, and the second electrode of the first control transistor is connected to the control electrode of the compensation transistor; The control electrode of the second control transistor is connected to the column additional control line, the first electrode of the second control transistor is connected to the high voltage power line, and the second electrode of the second control transistor is connected to the control electrode of the compensation transistor.

22. The display substrate according to claim 21, wherein The local driving circuit is configured to provide the signal of the row control line or the signal of the high-voltage power line to the control electrode of the compensation transistor under the control of the column control line and the column additional control line, thereby controlling the compensation transistor to be disconnected or turned on. The signal provided by the column control line is opposite to the signal provided by the column additional control line.

23. The display substrate according to claim 22, wherein: The first control transistor, the second control transistor and the compensation transistor are P-type transistors; When the signal of the column control line is at the first level and the signal of the column additional control line is at the second level, The local driving circuit provides the signal of the row control line to the control electrode of the compensation transistor, and the compensation transistor is turned on or off under the control of the signal of the row control line. The pixel driving circuit drives the corresponding light-emitting device to maintain the original brightness or refresh the brightness under the control of the signal of the row control line; When the signal of the column control line is at the second level and the signal of the column additional control line is at the first level, the local driving circuit provides the signal of the high-voltage power line to the control electrode of the compensation transistor, the compensation transistor is disconnected, and the pixel driving circuit drives the corresponding light-emitting device to maintain the original brightness.

24. The display substrate according to claim 23, wherein: When the signal of the column control line is at the first level and the row control line is at the first level during the reset phase and the threshold compensation phase of one working frame of the pixel driving circuit, the local driving circuit provides the signal of the row control line to the control electrode of the compensation transistor during the reset phase and the threshold compensation phase of one working frame of the pixel driving circuit, the compensation transistor is turned on under the control of the signal of the row control line, and the pixel driving circuit drives the corresponding light-emitting device to refresh the brightness in this working frame; When the signal of the column control line is at the first level and the row control line is at the second level in an operating frame of the pixel driving circuit, the local driving circuit provides the signal of the row control line to the control electrode of the compensation transistor, and the compensation transistor is disconnected under the control of the signal of the row control line. The pixel driving circuit drives the corresponding light-emitting device to maintain the original brightness in this operating frame.

25. The display substrate according to claim 4, further comprising a row additional control line further comprising a high voltage power supply line, wherein the local driving circuit comprises a first control transistor and a second control transistor; The control electrode of the first control transistor is connected to the row control line, the first electrode of the first control transistor is connected to the column control line, and the second electrode of the first control transistor is connected to the control electrode of the compensation transistor; The control electrode of the second control transistor is connected to the row additional control line, the first electrode of the second control transistor is connected to the high voltage power line, and the second electrode of the second control transistor is connected to the control electrode of the compensation transistor.

26. The display substrate according to claim 25, wherein: The local driving circuit is configured to provide the signal of the column control line or the signal of the high-voltage power line to the control electrode of the compensation transistor under the control of the row control line and the row additional control line, thereby controlling the compensation transistor to be turned on or off. The signal provided by the row control line is opposite to the signal provided by the row additional control line.

27. The display substrate according to claim 26, wherein: The first control transistor, the second control transistor and the compensation transistor are P-type transistors; When the signal of the column control line is at the first level, the pixel driving circuit Under the control of the additional control line and the local driving circuit, the corresponding light-emitting device is driven to maintain the original brightness or refresh the brightness; When the signal of the column control line is at the second level, the compensation transistor is turned off under the control of the signal of the column control line or the high voltage power line, and the pixel driving circuit drives the corresponding light emitting device to maintain the original brightness.

28. The display substrate according to claim 27, wherein: When the signal of the column control line is at the first level and the row control line is at the first level during the reset phase and the threshold compensation phase of one working frame of the pixel driving circuit, the local driving circuit provides the signal of the column control line to the control electrode of the compensation transistor during the reset phase and the threshold compensation phase of one working frame of the pixel driving circuit. The compensation transistor is turned on under the control of the signal of the column control line, and the pixel driving circuit drives the corresponding light-emitting device to refresh the brightness in this working frame. When the signal of the column control line is at the first level and the row control line is at the second level in one working frame of the pixel driving circuit, the local driving circuit provides the signal of the high-voltage power line to the control electrode of the compensation transistor, the compensation transistor is disconnected under the control of the signal of the high-voltage power line, and the pixel driving circuit drives the corresponding light-emitting device to maintain the original brightness.

29. The display substrate according to claim 2, wherein: The column control line is configured to control the refresh brightness of the sub-pixels controlled by one or more column local drive circuits connected thereto; the row control line is configured to control the refresh brightness of the sub-pixels controlled by one or more row local drive circuits connected thereto, the row control signal provided by the row control line includes a refresh brightness control signal and a maintain brightness control signal, and the column control signal provided by the column control line includes a refresh brightness control signal and a maintain brightness control signal; The pixel driving circuit drives the corresponding light-emitting device to refresh the brightness when the row control signal of the row control line and the column control signal of the column control line connected to the local driving circuit are both control signals for refreshing the brightness; the pixel driving circuit drives the corresponding light-emitting device to maintain the original brightness when at least one of the row control signal of the row control line and the column control signal of the column control line connected to the local driving circuit is a control signal for maintaining the brightness.

30. A method for operating a display substrate, applied to the display substrate according to any one of claims 1 to 29, the display substrate comprising a plurality of sub-pixels, at least one local drive circuit, at least one column control line, and at least one row control line, at least some of the sub-pixels comprising light-emitting devices and pixel drive circuits for driving the light-emitting devices to emit light, the pixel drive circuit being connected to one of the local drive circuits; the local drive circuit being connected to at least one pixel drive circuit, one of the column control lines, and one of the row control lines, the method comprising: The local driving circuit controls the pixel driving circuit connected thereto to operate under the control of the column control line and the row control line. The pixel driving circuit drives the corresponding light emitting device to maintain the state under the control of the local driving circuit. Original brightness or refresh brightness.

31. A display device comprising the display substrate according to any one of claims 1 to 29.

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