Display device

Abstract

In the organic EL display device (1), a lead-out wire (40h) extending from the display region (DA) so as to intersect with the bonding portion (SZ) of the sealing film (80) and led out to the terminal portion (TP) is provided on the lower layer side of the sealing film (80) in the frame region (FA). The lead wire includes a first wiring layer (41) and a second wiring layer (42) laminated on the first wiring layer with a first interlayer insulating film (26) therebetween. The first wiring layer and the second wiring layer are connected via a pair of first contact holes (Ha) formed in the first interlayer insulating film. A bonding portion is provided between the pair of first contact holes in plan view.

Description

Technical Field

[0001] This disclosure relates to display devices. Background Technology

[0002] In recent years, organic EL display devices using organic electroluminescent (EL) elements have been put into practical use. Multiple organic EL elements are arranged in a prescribed pattern to form a display area for image display. A border area is set outside the display area as a non-display area. The border area contains drive circuits or power lines and leads that control the image display.

[0003] Organic EL elements are susceptible to degradation due to moisture. Therefore, in organic EL display devices, a sealing technique is employed where the organic EL elements are covered by a sealing film. Thin Film Encapsulation (TFE) technology is known as such. TFE technology aims to achieve high moisture barrier properties while maintaining flexibility by alternately layering inorganic and organic barrier layers to create a sealing film.

[0004] Furthermore, the organic EL display device includes a circuit board for mounting driving circuitry and other components. The circuit board comprises a surface insulating film, which includes an inorganic insulating material, and a planarization film disposed on the surface insulating film. The surface insulating film is provided in a manner that extends into the bezel area. A sealing film forms a frame-shaped joint in the bezel area, where the inorganic barrier layer and the surface insulating film meet. Because the planarization film includes an organic resin material, it has low moisture barrier properties, but it is surrounded by the joint along with the organic EL elements. This prevents external moisture from being guided into the display area through the planarization film.

[0005] On the outer side of the joint in the bezel area, a terminal portion for connection to external circuitry is provided. In the bezel area between the display area and the terminal portion, multiple leads connected to source lines, etc., are provided. Each of these leads extends from the display area, intersecting the joint, and is led to the terminal portion from the lower layer of the sealing film. It is known in the past that these leads are arranged in a stacked structure.

[0006] For example, Patent Document 1 discloses a method in which the lead wires in an organic EL display device are formed as a stack comprising a gate metal layer and a source metal layer. An interlayer insulating layer is disposed on top of the gate metal layer. A source metal layer is disposed on top of the interlayer insulating layer. An opening for contact is formed in the interlayer insulating layer. The source metal layer is connected to the gate metal layer through the opening. Existing technical documents Patent documents

[0007] Patent Document 1: International Publication No. 2018 / 229876 Summary of the Invention The problem the invention aims to solve

[0008] In the organic EL display device of Patent Document 1, the contact opening formed in the interlayer insulating layer extends along the length of the gate metal layer to the inner and outer sides of the junction. The surface of the gate metal layer exposed from the contact opening becomes roughened due to the etching process during the formation of the opening, easily becoming uneven. Therefore, a path for external moisture intrusion can sometimes be created within the contact opening, penetrating the junction. When moisture intrudes into the display area along the lead wires through this path, it can lead to the deterioration of the organic EL element, causing a decrease in the display quality or reliability of the organic EL display device.

[0009] The purpose of this disclosure is to prevent moisture from entering the display area along the lead-out lines. Solution for solving the problem

[0010] This disclosure pertains to a display device. The display device includes: a circuit board; a plurality of light-emitting elements disposed on the circuit board; and a sealing film disposed to cover the plurality of light-emitting elements. The plurality of light-emitting elements constitute a display area for displaying an image. A border area is provided outside the display area as a non-display area where no image is displayed. The circuit board includes: a substrate; and a laminated insulating film, which is formed by laminating inorganic insulating materials and is disposed on the substrate extending into the border area. The sealing film has an inorganic barrier layer comprising an inorganic insulating material. The border area includes: a frame-shaped joint portion where a portion of the inorganic barrier layer along its periphery contacts the laminated insulating film; and a terminal portion located outside the joint portion. A lead wire is provided on the lower side of the sealing film in the border area, extending from the display area in a manner intersecting the joint portion and being led out to the terminal portion. The lead wire includes: a first wiring layer; and a second wiring layer laminated on the first wiring layer with a first inorganic insulating film as a barrier. The first wiring layer and the second wiring layer are connected via a pair of first contact holes formed in the first inorganic insulating film. Furthermore, when viewed from above, a joint is provided between the pair of first contact holes. Invention Effects

[0011] According to the display device disclosed herein, it is possible to prevent moisture from entering the display area along the lead wire. Attached Figure Description

[0012] Figure 1 This is a top view illustrating the general configuration of the organic EL display device according to Embodiment 1. Figure 2 yes Figure 1 A cross-sectional view of an organic EL display device at line II-II. Figure 3 This is a top view illustrating the pixels and various wiring in the display area of ​​an organic EL display device. Figure 4 yes Figure 3 A cross-sectional view of an organic EL display device at line IV-IV. Figure 5 This is an example Figure 1 A top view of the main part of an organic EL display device surrounded by a V. Figure 6 yes Figure 5 A cross-sectional view of the main part of the organic EL display device at the VI-VI line. Figure 7 yes Figure 5 A cross-sectional view of the main part of the organic EL display device at line VII-VII. Figure 8 This is a cross-sectional view illustrating the manufacturing process of the organic EL display device according to Embodiment 1. Figure 9A This is a top view showing the main parts of the organic EL display device during light emission inspection according to Embodiment 1. Figure 9B This is a top view showing the main parts of the organic EL display device used in the comparative example during a light emission inspection. Figure 10 It is equivalent to the organic EL display device in Embodiment 2. Figure 4 A top view of the part. Figure 11 yes Figure 10 A cross-sectional view of the main part of the organic EL display device at the XI-XI line. Figure 12 yes Figure 10 A cross-sectional view of the main part of the organic EL display device at the XII-XII line. Figure 13 yes Figure 10 A cross-sectional view of the main part of the organic EL display device at line XIII-XIII. Figure 14 This is a cross-sectional view illustrating the manufacturing process of the organic EL display device according to Embodiment 2. Figure 15 It is equivalent to the organic EL display device in embodiment 3. Figure 5 A top view of the part. Figure 16 yes Figure 15A cross-sectional view of the main part of the organic EL display device at the XVI-XVI line. Figure 17 yes Figure 15 A cross-sectional view of the main part of the organic EL display device at line XVII-XVII. Figure 18 This is a cross-sectional view illustrating the manufacturing process of the organic EL display device according to Embodiment 3. Figure 19A This is a cross-sectional view illustrating the structure of the lead wire in the example reference. Figure 19B This is a cross-sectional view illustrating the structure of the lead wire in the example reference. Figure 20 This is a cross-sectional view illustrating the general configuration of an organic EL display device according to other embodiments. Detailed Implementation

[0013] Hereinafter, exemplary embodiments will be described in detail based on the accompanying drawings. In the following embodiments, an organic EL display device will be described as an example of the display device involved in this disclosure. Furthermore, the drawings are used to conceptually illustrate the technology of this disclosure. Therefore, in the drawings, in order to facilitate understanding of the technology of this disclosure, dimensions, proportions, or quantities are sometimes exaggerated or simplified.

[0014] In the following embodiments, "first direction" refers to the horizontal direction of the screen facing the specified usage state of the display device. "Second direction" refers to the direction orthogonal to the first direction, meaning the vertical direction of the screen facing the specified usage state of the display device. A row of constituent elements such as subpixels refers to the horizontal arrangement of multiple constituent elements forming a column in the first direction. A column of constituent elements such as subpixels refers to the vertical arrangement of multiple constituent elements forming a column in the second direction.

[0015] In the following embodiments, the description of providing or forming other membranes, layers, elements, or other constituent elements on a certain membrane or layer or element means not only that there are other constituent elements directly above a certain constituent element, but also that other membranes, layers, elements, or other constituent elements are located between the two constituent elements.

[0016] In the following embodiments, unless otherwise specified, a description of a component being connected to another component means an electrical connection. This description, without departing from the technical spirit of this disclosure, means not only direct connections but also indirect connections via other components. The description also includes cases where a component is integrated with other components, that is, a part of one component constitutes another component.

[0017] In the following embodiments, the description that a component is a layer of the same type as other components means that the component is formed by the same process as the other components. The description that a component is a lower layer of other components means that the component is formed by a process preceding the other components or by a film formed in an earlier process. The description that a component is an upper layer of other components means that the component is formed by a process following the other components or by a film formed in a later process.

[0018] In the following embodiments, the description that a certain component is the same as or equal to other components does not only mean that a certain component is completely identical or completely equal to other components, but also includes that a certain component is substantially identical or substantially equal to other components in that the components vary within the range of manufacturing deviations or tolerances.

[0019] In the following implementation, the terms 1, 2, 3... are used to distinguish the statements to which these terms are given, and do not limit even the number or order of the statements.

[0020] Implementation Method 1 The OLED display device 1 of this embodiment is used as a display for mobile devices such as multi-function telephones or tablet terminals, also known as smartphones. The OLED display device 1 can also be used as a display for various other devices such as personal computers (PCs) and television devices.

[0021] -Composition of Organic EL Display Device- Organic EL display device 1 is a display device that uses organic EL elements 65, also known as OLEDs (Organic Light Emitting Diodes). Organic EL display device 1 employs an active matrix driving method and is configured for full-color display. For example... Figure 1 and Figure 2 As shown, the organic EL display device 1 has a display area DA and a border area FA.

[0022] The display area DA is the area where the image is displayed, constituting the screen. The display area DA can be set to a rectangular shape, for example. The display area DA can also be a shape with at least one rounded side, at least one rounded corner, or a shape with a cutout on at least one side, or any other arbitrary shape.

[0023] like Figure 3As shown, the display area DA is composed of multiple pixels PX. These pixels PX are arranged in a matrix. Each pixel PX consists of three sub-pixels SP. The three sub-pixels SP are a red-emitting sub-pixel SPr, a green-emitting sub-pixel SPg, and a blue-emitting sub-pixel SPb. These three sub-pixels SP are arranged, for example, in a strip.

[0024] The display area DA contains multiple organic EL elements 65 and multiple pixel circuits PC. Each organic EL element 65 corresponds to a multiple sub-pixel SP. Each sub-pixel SP is composed of organic EL elements 65. The pixel circuit PC is a circuit operating on a sub-pixel basis, controlling the light emission of the organic EL elements 65 that constitute the corresponding sub-pixel SP.

[0025] like Figure 1 and Figure 2 As shown, the border area FA is the area that constitutes the non-display portion outside the screen. The border area FA is set as a rectangular frame around the display area DA, for example. The border area FA can also be a frame shape other than a rectangle. The border area FA includes a joint portion SZ, a terminal portion TP, and a bending portion BP.

[0026] The junction SZ is the portion along the periphery of the first inorganic barrier layer 81 constituting the sealing film 80 described later, which is in contact with the laminated insulating film 36 included in the circuit board 5. Figure 1 (The area marked with a shaded line). The laminated insulating film 36 is a laminate of inorganic insulating films made of laminated inorganic insulating materials. The joint SZ is formed in a frame shape to surround the display area DA, thus blocking external moisture from intruding into the display area DA.

[0027] The terminal section TP is used to connect to external circuits such as display control circuitry (source driver). The terminal section TP is located near the outer edge of the portion of the frame area FA that extends along the first direction Dx, extending along that side. The terminal section TP is located outside the joint portion SZ. A wiring board CB, such as an FPC (Flexible Printed Circuit), is connected to the terminal section TP.

[0028] The bending portion BP is located between the terminal portion TP and the display area DA, and extends horizontally along the entire length of the first direction Dx of the bezel area FA. The bezel area FA is bent at the bending portion BP in a U-shape, for example, at a 180° angle. Figure 2 (Indicated by double-dotted lines). Thus, the terminal portion TP is disposed on the back side of the organic EL display device 1.

[0029] A drive circuit (not shown) is provided in the frame area FA. The drive circuit is positioned in the frame area FA on the side adjacent to the side where the terminal portion TP is located. Figure 1 The middle section (comprising the left and right sides) is a portion of the TFT layer 20, which will be described later. The driving circuit is formed as a monolithic chip. The driving circuit includes a gate driver and an emitter driver.

[0030] Additionally, although not shown, a first border line and a second border line are provided in the border area FA. Both the first and second border lines are power supply lines, formed to surround the display area DA, and extend to the terminal portion TP. The first border line is supplied with a high-level power supply voltage (ELVDD) via the wiring board CB. The second border line is supplied with a low-level power supply voltage (ELVSS) via the wiring board CB.

[0031] Multiple leads 40h are provided in the bezel area FA. These leads 40h are each led out from the display area DA and extend to the terminal section TP. The end of each lead 40h located in the terminal section TP and the ends of the first and second bezel lines respectively constitute a terminal. The terminal section TP has these multiple terminals.

[0032] <Layered Structure of Organic EL Display Devices> like Figure 2 As shown, the organic EL display device 1 includes a circuit board 5, a light-emitting element layer 60, and a sealing film 80. The circuit board 5 is composed of a substrate layer 10 and a TFT layer 20 (thin-film transistor layer). The circuit board 5 includes multiple circuit elements disposed in the display area DA.

[0033] <Substrate Layer> Substrate layer 10 is an example of a substrate. In this example, substrate layer 10 is a flexible resin substrate. Substrate layer 10 is formed of organic resin materials such as polyimide resin, polyamide resin, and epoxy resin. Substrate layer 10 may also be composed of an organic insulating layer including an organic resin material as described above and an inorganic insulating layer such as silicon dioxide (SiO2). A protective film 11 is attached to the back side of substrate layer 10.

[0034] <TFT layer> The TFT layer 20 is disposed on the substrate layer 10. In addition to the aforementioned driving circuit, the TFT layer 20 also includes... Figure 3 and Figure 4 The diagram shows a base coating 21, various wirings 40, and multiple pixel circuits PC. The driving circuit, wirings 40, and pixel circuits PC are disposed on the base coating 21. The base coating 21 is disposed on the substrate layer 10 and extends over the entire surface of the substrate layer 10.

[0035] The various wirings 40 include the first border line, the second border line, and the lead-out line 40h mentioned above. In addition to these, the various wirings 40 also include multiple gate lines 40g, multiple light-emitting control lines 40e, multiple initialization lines 40i, multiple power lines 40p, and multiple source lines 40s. Each gate line 40g, each light-emitting control line 40e, each initialization line 40i, each power line 40p, and each source line 40s is located in the display area DA.

[0036] Multiple gate lines 40g are wirings that transmit gate signals to the pixel circuit PC. The multiple gate lines 40g are arranged with open intervals between each other in the second direction Dy and extend parallel to each other in the first direction Dx. As gate lines 40g, a first gate line 40ga and a second gate line 40gb are provided.

[0037] The first gate line 40ga is a gate line 40g used for control of the P-channel TFT 50. The second gate line 40gb is a gate line 40g used for control of the N-channel TFT 50. The first gate line 40ga and the second gate line 40gb are arranged in each row of the sub-pixel SP. Each first gate line 40ga and each second gate line 40gb is led out to the bezel area FA and connected to the gate driver of the driving circuit.

[0038] Multiple light-emitting control lines 40e are wirings that transmit emission signals to the pixel circuit PC. The multiple light-emitting control lines 40e are arranged with spacing between each other in the second direction Dy and extend parallel to each other in the first direction Dx. The light-emitting control lines 40e are arranged in each row of sub-pixels SP. Each light-emitting control line 40e is led out to the border area FA and connected to the emission driver of the driving circuit.

[0039] Multiple initialization lines 40i are wirings that apply initialization voltages to the pixel circuit PC. The multiple initialization lines 40i are spaced apart from each other in the second direction Dy and extend parallel to each other in the first direction Dx. The initialization lines 40i are arranged for each row of sub-pixels SP. Each initialization line 40i is led out to the border area FA and connected to the drive circuit or the second border line.

[0040] Multiple power lines 40p are wirings that apply a specified high-level power supply voltage (ELVDD) to the pixel circuit PC. The power lines 40p are spaced apart from each other in the first direction Dx and extend parallel to each other in the second direction Dy. The power lines 40p are arranged in each column of the sub-pixels SP. Each power line 40p is led out to the border area FA and connected to the first border line.

[0041] Multiple source lines 40s are wirings that transmit source signals to the pixel circuit PC. The multiple source lines 40s are arranged with open intervals between each other in the first direction Dx and extend parallel to each other in the second direction Dy. The source lines 40s are arranged in each column of the sub-pixels SP. Each source line 40s is led out as a lead-out line 40h to the terminal section TP and connected to the display control circuit (source driver) via the wiring board CB.

[0042] The first gate line 40ga, the light-emitting control line 40e, and the initialization line 40i are formed in the same layer as the first gate electrode 24 described later. The second gate line 40gb is formed in the same layer as the second gate electrode 33 and the second capacitor electrode 30 described later. The power line 40p and the source line 40s are formed in the same layer as the first terminal electrode 37 and the second terminal electrode 38 described later.

[0043] The first gate line 40ga, the second gate line 40gb, the light emission control line 40e, the initialization line 40i, the power supply line 40p, and the source line 40s are connected to each pixel circuit PC. Each pixel circuit PC operates based on the signals and voltages supplied by these various wirings 40. In each frame, after resetting the charge stored in the pixel electrode 61, it supplies a drive current corresponding to the source signal to the organic EL element 65.

[0044] like Figures 4-7 As shown, the pixel circuit PC includes multiple TFTs 50 and capacitors 55. These TFTs 50 and capacitors 55 are examples of circuit elements. The multiple TFTs 50 constituting the pixel circuit PC include a first TFT 50A and a second TFT 50B. The first TFT 50A, the second TFT 50B, and the capacitors 55 are arranged correspondingly to multiple sub-pixels SP, and the pixel circuit PC is constituted for each sub-pixel SP.

[0045] The first TFT50A is a P-channel TFT50 configured as a top-gate type with a top-contact structure. The first TFT50A has a first semiconductor layer 22, a first gate insulating film 23, a first gate electrode 24, an interlayer insulating film 35, a first terminal electrode 37, and a second terminal electrode 38.

[0046] The first semiconductor layer 22 is arranged in an island shape on the base coating film 21 and is continuously disposed among a plurality of first TFTs 50A. The first semiconductor layer 22 can also be separated individually for each first TFT 50A. The first semiconductor layer 22 includes a first channel region 22a and a pair of first conductor regions 22b. The first channel region 22a is disposed between the pair of first conductor regions 22b. The pair of first conductor regions 22b are disposed separately from each other, sandwiching the first channel region 22a.

[0047] The first gate insulating film 23 is continuously disposed in a plurality of first TFTs 50A in such a manner that it covers a plurality of first semiconductor layers 22. Alternatively, the first gate insulating film 23 may be disposed in an island shape on each of the first semiconductor layers 22, and separated individually for each first TFT 50A. A first gate electrode 24 is disposed on the first gate insulating film 23. The first gate electrode 24 overlaps with the first channel region 22a of the first semiconductor layer 22 across the first gate insulating film 23.

[0048] The interlayer insulating film 35 is disposed such that it covers a plurality of first gate electrodes 24. The interlayer insulating film 35 is formed by stacking a first interlayer insulating film 26 and a second interlayer insulating film 34 on a first gate insulating film 23 in this order. A plurality of third contact holes Hc are formed in the interlayer insulating film 35.

[0049] The third contact holes Hc are configured as a pair for each first TFT 50A. Each pair of third contact holes Hc extends to a corresponding, distinct first conductor region 22b of the first semiconductor layer 22. The first terminal electrode 37 and the second terminal electrode 38 are disposed at mutually separated positions on the interlayer insulating film 35. The first terminal electrode 37 and the second terminal electrode 38 are connected to the first conductor region 22b of the first semiconductor layer 22 via the distinct third contact holes Hc.

[0050] The second TFT50B is an N-channel TFT50 configured as a top-gate type with a bottom contact structure. The second TFT50B has a third terminal electrode 28, a fourth terminal electrode 29, a second semiconductor layer 31, a second gate insulating film 32, and a second gate electrode 33.

[0051] The third terminal electrode 28 and the fourth terminal electrode 29 are disposed at mutually separated positions on the first interlayer insulating film 26. A fourth contact hole Hd is formed on the second interlayer insulating film 34, corresponding to the designated second TFT 50B. The fourth contact hole Hd extends to either the third terminal electrode 28 or the fourth terminal electrode 29 in the designated second TFT 50B. A relay line 40r and other wiring are provided on the second interlayer insulating film 34 for each pixel circuit PC. The relay line 40r is connected to the third terminal electrode 28 or the fourth terminal electrode 29 via the fourth contact hole Hd.

[0052] The second semiconductor layer 31 is arranged in an island shape on the first interlayer insulating film 26 and is continuously disposed among the plurality of second TFTs 50B. The second semiconductor layer 31 can also be separated individually for each second TFT 50B. The second semiconductor layer 31 includes a second channel region 31a and a pair of second conductor regions 31b. The second channel region 31a is disposed between the pair of second conductor regions 31b. The pair of second conductor regions 31b are disposed separately from each other, sandwiching the second channel region 31a.

[0053] One of the second conductor regions 31b in the second semiconductor layer 31 partially overlaps with the third terminal electrode 28, and the other second conductor region 31b partially overlaps with the fourth terminal electrode 29. The second gate insulating film 32 is formed in an island shape on the first interlayer insulating film 26 and is continuously disposed in the plurality of second TFTs 50B. The second gate insulating film 32 can also be separated individually for each second TFT 50B.

[0054] The second gate insulating film 32 is disposed such that it partially covers the plurality of second semiconductor layers 31. The second gate insulating film 32 overlaps with the second channel region 31a of each second semiconductor layer 31, exposing the second conductor region 31b. The second gate electrode 33 is disposed on the second gate insulating film 32. The second gate electrode 33 overlaps with the second channel region 31a of the second semiconductor layer 31 through the second gate insulating film 32.

[0055] The capacitor 55 is configured to include a first capacitor electrode 25, a second capacitor electrode 30, and a second gate insulating film 32. The first capacitor electrode 25, the third terminal electrode 28, and the fourth terminal electrode 29 are formed of the same material on the same layer and disposed on the first interlayer insulating film 26. The second capacitor electrode 30 is disposed on the second gate insulating film 32. The first capacitor electrode 25 and the second capacitor electrode 30 overlap each other through the second gate insulating film 32.

[0056] The base coating 21, the first gate insulating film 23, the first interlayer insulating film 26, the second gate insulating film 32, and the second interlayer insulating film 34 respectively comprise inorganic insulating materials such as silicon oxide (SiO2), silicon nitride (SiNx), and silicon oxynitride. These various inorganic insulating films can be composed of single-layer films or laminated films.

[0057] A base coating 21, a first gate insulating film 23, a first interlayer insulating film 26, a second gate insulating film 32, and a second interlayer insulating film 34 are stacked together to form a stacked insulating film 36. That is, the stacked insulating film 36 is formed by stacking inorganic insulating materials. The stacked insulating film 36 is disposed on the substrate layer 10 in such a manner that it extends to both the entire display area DA and the bezel area FA. The circuit board 5 includes such a stacked insulating film 36.

[0058] The aforementioned wiring 40 and electrodes include, for example, metallic materials such as aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta), chromium (Cr), titanium (Ti), and copper (Cu). These wiring 40 and electrodes can be composed of a single-layer film or a multilayer film.

[0059] The first semiconductor layer 22 comprises polycrystalline silicon. The polycrystalline silicon constituting the first semiconductor layer 22 is, for example, low-temperature polycrystalline silicon (LTPS). The second semiconductor layer 31 comprises an oxide semiconductor. The oxide semiconductor constituting the second semiconductor layer 31 is, for example, an In-Ga-Zn-O based semiconductor.

[0060] The TFT layer 20 also includes a planarization film 59. The planarization film 59 is disposed on the second interlayer insulating film 34 in such a way that it covers the various wirings 40, multiple TFTs 50, and multiple capacitors 55 in the display area DA. The planarization film 59 extends over the entire display area DA. The surface of the TFT layer 20 is planarized by the planarization film 59.

[0061] In the planarization film 59, a fifth contact hole He is formed for each sub-pixel SP. The fifth contact hole He extends to the relay line 40r. The planarization film 59 may include organic resin materials such as polyimide resin and acrylic resin, or polysiloxane-based SOG (Spin On Glass) materials.

[0062] <Light-emitting element layer> A light-emitting element layer 60 is disposed on the circuit board 5 (TFT layer 20). The light-emitting element layer 60 includes a plurality of organic EL elements 65 (organic electroluminescent elements) and an edge mask 66. The organic EL element 65 is an example of a light-emitting element. The organic EL element 65 is configured as a top-emitting type. The light emitted by the organic EL element 65 is extracted towards the sealing film 80 side.

[0063] Multiple organic EL elements 65 are disposed corresponding to multiple sub-pixels SP. Each organic EL element 65 constitutes a sub-pixel SP. The light emission of each organic EL element 65 is controlled by the operation of the corresponding pixel circuit PC. Each organic EL element 65 has a pixel electrode 61, an organic EL layer 62, and a common electrode 63.

[0064] Pixel electrodes 61 are disposed on planarization film 59. Pixel electrodes 61 are arranged in a matrix corresponding to each of the plurality of sub-pixels SP. Each pixel electrode 61 is connected to relay line 40r via the fifth contact hole He, and is connected to the third terminal electrode or the fourth terminal electrode (in...) via relay line 40r. Figure 4 The example shown is the fourth terminal electrode; pixel circuit PC). Pixel electrode 61 functions as an anode, injecting holes into the organic EL layer 62. Pixel electrode 61 is preferably made of a conductive material with a high work function.

[0065] Materials used for the pixel electrode 61 include, for example, metals such as silver (Ag), aluminum (Al), nickel (Ni), titanium (Ti), indium (In), and tin (Sn). The pixel electrode 61 can also be a metal compound or alloy. Furthermore, the pixel electrode 61 can be a conductive oxide such as indium tin oxide (ITO) or indium zinc oxide (IZO). The pixel electrode 61 can be composed of a single layer or a multilayer film.

[0066] An edge mask 66 is disposed on the planarization film 59. The edge mask 66 is located on top of the pixel electrode 61. The edge mask 66 is formed in a grid pattern to divide the multiple pixel electrodes 61. Specifically, the edge mask 66 extends between adjacent pixel electrodes 61 and around the display area DA, covering the outer edge (peripheral portion) of each pixel electrode 61.

[0067] The edge mask 66 has multiple openings 67 corresponding to the sub-pixels SP. Each opening 67 exposes the pixel electrode 61 partially from the edge mask 66. The edge mask 66 is made of the same material as the planarization film 59, such as organic resin materials like polyimide resin or acrylic resin, or SOG materials based on polysiloxane.

[0068] An organic EL layer 62 is disposed on each pixel electrode 61 within an opening 67 of an edge mask 66. The organic EL layer 62 comprises a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer. These layers are stacked on the pixel electrode 61 in this order and comprise known compounds suitable for their respective functions. The organic EL layer 62 emits light by applying a current between the pixel electrode 61 and a common electrode 63.

[0069] The common electrode 63 is arranged as a continuous common film in multiple sub-pixels SP, extending over the entire display area DA. The common electrode 63 covers the edge mask 66 and each organic EL layer 62, overlapping with each pixel electrode 61 across the organic EL layer 62. The common electrode 63 also extends to the bezel area FA, connecting to the second bezel line. The common electrode 63 functions as a cathode, injecting electrons into the organic EL layer 62. The common electrode 63 is preferably made of a conductive material with a low work function.

[0070] Materials used for the common electrode 63 include conductive oxides such as indium tin oxide (ITO) and indium zinc oxide (IZO). The common electrode 63 can also be made of metals such as silver (Ag), aluminum (Al), lithium (Li), magnesium (Mg), calcium (Ca), and ytterbium (Yb). Furthermore, the common electrode 63 can be a metal compound or an alloy. The common electrode 63 can be composed of a single-layer film or a multilayer film.

[0071] <Sealing film> A sealing film 80 is disposed on the light-emitting element layer 60. The sealing film 80 covers and seals multiple organic EL elements 65, protecting each organic EL element 65 (especially the organic EL layer 62) from the influence of moisture or oxygen. The sealing film 80 is disposed over the entire display area DA and extends to the bezel area FA. The sealing film 80 has a first inorganic barrier layer 81, an organic barrier layer 82, and a second inorganic barrier layer 83.

[0072] A first inorganic barrier layer 81 is disposed to cover a common electrode 63. An organic barrier layer 82 is disposed on the first inorganic barrier layer 81. A second inorganic barrier layer 83 is disposed on the organic barrier layer 82. The first inorganic barrier layer 81 and the second inorganic barrier layer 83 extend towards the outer periphery of the frame region FA than the organic barrier layer 82, and overlap each other at the outer portion of the frame region FA. The organic barrier layer 82 extends to the display region DA and its outer periphery, and is enclosed in the middle by the first inorganic barrier layer 81 and the second inorganic barrier layer 83.

[0073] The first inorganic barrier layer 81 and the second inorganic barrier layer 83 respectively comprise inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride. The organic barrier layer 82 comprises organic resin materials such as acrylic resin, epoxy resin, silicone resin, polyurea resin, parylene resin, polyimide resin, and polyamide resin. The organic barrier layer 82 is formed by coating a liquid material.

[0074] <Leader line> Multiple leads 40h extend beneath the sealing film 80 in a manner intersecting with the joint SZ and are led out to the terminal portion TP (see reference). Figure 5 The lead 40h has a stacked structure. In this example, the lead 40h is composed of two layers. Specifically, the lead 40h includes a first wiring layer 41 and a second wiring layer 42. The first wiring layer 41 is disposed on the first gate insulating film 23. The second wiring layer 42 is stacked on the first wiring layer 41 with a first interlayer insulating film 26 in between, and is covered by a second interlayer insulating film 34. The first interlayer insulating film 26 is an example of a first inorganic insulating film.

[0075] The first wiring layer 41 and the second wiring layer 42 are each formed into a conical shape with two sides facing each other towards the upper layer in the width direction of the lead-out line 40h. The two sides of the first wiring layer 41 and the second wiring layer 42 are staggered in the width direction of the lead-out line 40h. Specifically, the line width of the second wiring layer 42 is narrower than that of the first wiring layer 41. Furthermore, the two sides of the second wiring layer 42 correspond to the upper surface of the first wiring layer 41 in the stacking direction of the first wiring layer 41 and the second wiring layer 42.

[0076] When the angle formed by the side surface of the first wiring layer 41 in the width direction relative to the direction orthogonal to the thickness direction of the first wiring layer 41 within the inner side of the first wiring layer 41 is defined as the first tilt angle θ1, and the angle formed by the side surface of the second wiring layer 42 in the width direction relative to the direction orthogonal to the thickness direction of the second wiring layer 42 within the inner side of the second wiring layer 42 is defined as the second tilt angle θ2, the first tilt angle θ1 and the second tilt angle θ2 satisfy the relationship θ2≤θ1. The first tilt angle θ1 is, for example, 20° to 90°. The second tilt angle θ2 is, for example, 10° to 85°.

[0077] A plurality of first contact holes Ha are formed in the first interlayer insulating film 26. The first contact holes Ha are arranged in pairs for each lead 40h. The first wiring layer 41 and the second wiring layer 42 are connected via a pair of first contact holes Ha. When viewed from above, the pair of first contact holes Ha are positioned such that at least a portion (in this example, the entire width of the joint SZ) of the joint SZ is positioned relative to each other along the length of the lead 40h.

[0078] The first wiring layer 41 is formed in the same layer as the electrodes constituting the circuit elements or the wiring connected to the circuit elements, using the same material. In this example, the first wiring layer 41 is formed in the same layer as the first gate line 40ga, the light-emitting control line 40e, the initialization line 40i, and the first gate electrode 24, using the same material. The second wiring layer 42 is also formed in the same layer as the electrodes constituting the circuit elements or the wiring connected to the circuit elements, using the same material. In this example, the second wiring layer 42 is formed in the same layer as the third terminal electrode 28, the fourth terminal electrode 29, and the first capacitor electrode 25, using the same material.

[0079] -Manufacturing method of organic EL display device- To manufacture the organic EL display device 1, firstly, an organic resin material is coated onto the surface of a glass substrate and then baked. This forms a substrate layer 10 on the glass substrate.

[0080] Next, the TFT layer 20, the light-emitting element layer 60, and the sealing film 80 are sequentially formed on the substrate layer 10 using known film formation methods such as plasma CVD (Chemical Vapor Deposition), sputtering, vacuum evaporation, spin coating, slot coating, and photolithography.

[0081] Next, the glass substrate is peeled off from the substrate layer 10 by irradiating the back side of the substrate layer 10 with a laser or the like from the glass substrate side. Then, a protective film 11 is attached to the back side of the substrate layer 10. Additionally, a polarizing plate or a cover plate is attached to the surface of the sealing film 80. Then, the wiring board CB is connected to the terminal portion TP. Thus, a display control circuit (source driver) is installed on the panel constituting the organic EL display device 1.

[0082] As described above, an organic EL display device 1 can be manufactured.

[0083] <Processes involved in the formation of the lead wire> like Figure 8 (a) and Figure 8 As shown in (b), in the formation process of TFT layer 20, a silicon oxide film and a silicon nitride film are sequentially formed on substrate layer 10, for example, by plasma CVD. Thus, a base coating film 21 is formed.

[0084] Next, on the substrate where the undercoat film 21 has been formed, an amorphous silicon film is formed, for example, by plasma CVD. This amorphous silicon film is then crystallized by laser annealing or the like to form a first semiconductor film. Subsequently, the first semiconductor film is patterned by photolithography to form a first semiconductor layer 22. Furthermore, on the substrate where the first semiconductor layer 22 has been formed, a silicon oxide film is formed, for example, by plasma CVD. Thus, a first gate insulating film 23 is formed.

[0085] Next, on the substrate where the first gate insulating film 23 has been formed, a molybdenum film is formed to a thickness of 100 nm to 500 nm, for example, by sputtering. Then, on the substrate where the molybdenum film has been formed, a photoresist is formed into a predetermined pattern using a known photolithography process. Next, the molybdenum film is dry-etched using this photoresist as a mask, thereby patterning the molybdenum film to form the first gate line 40ga, the light-emitting control line 40e, the initialization line 40i, and the first gate electrode 24. At this time, a mixture of carbon tetrachloride (CF4) and oxygen (O2), for example, is used as the etching gas. Additionally, as... Figure 8 As shown in (c), the first wiring layer 41 is formed together with the first gate line 40ga and the like from the same film in a manner that forms a cone-shaped cross section.

[0086] Next, on the surface of the substrate where the first wiring layer 41 is formed, impurity ions such as phosphorus are doped using the first gate electrode 24 as a mask. As a result, a first channel region 22a and a pair of first conductor regions 22b are formed in the first semiconductor layer 22.

[0087] Furthermore, on a substrate doped with impurity ions, for example by plasma CVD, a silicon oxide film is formed to a thickness of 50 nm to 500 nm, covering the first gate line 40ga, the light-emitting control line 40e, the initialization line 40i, the first gate electrode 24, and the first wiring layer 41. Then, a silicon nitride film is formed to a thickness of 20 nm to 200 nm. This forms a first interlayer insulating film 26. Next, a plurality of first contact holes Ha are formed by photolithography accompanied by dry etching of the first interlayer insulating film 26. Thus, as... Figure 8 As shown in (d), the first wiring layer 41 is covered by the first interlayer insulating film 26.

[0088] Next, on the substrate where the first interlayer insulating film 26 has been formed, a molybdenum film is formed to a thickness of 100 nm to 500 nm, for example, by sputtering. Then, on the substrate where the molybdenum film has been formed, a photoresist is formed into a predetermined pattern using a known photolithography process. Next, the molybdenum film is dry-etched using this photoresist as a mask, thereby patterning the molybdenum film to form the third terminal electrode 28, the fourth terminal electrode 29, and the first capacitor electrode 25. At this time, a mixture of carbon tetrachloride (CF4) and oxygen (O2) is used as the etching gas, for example. Additionally, as... Figure 8 As shown in (e), the second wiring layer 42 is formed together with the third terminal electrode 28 and the like from the same film in a cone-shaped cross-section. Thus, multiple leads 40h are formed.

[0089] Next, on the substrate where the second wiring layer 42 has been formed, a second semiconductor film including an oxide semiconductor such as InGaZnO4 is formed, for example by plasma CVD. Then, the second semiconductor film is patterned by photolithography to form the second semiconductor layer 31.

[0090] Next, on the substrate where the second semiconductor layer 31 has been formed, a silicon oxide film is formed, for example by plasma CVD, and then a molybdenum film is formed. Next, these silicon oxide films and molybdenum films are patterned by photolithography, with the silicon oxide film forming the second gate insulating film 32, and the molybdenum film forming the second gate line 40gb, the second gate electrode 33, and the second capacitor electrode 30, respectively.

[0091] Next, hydrogen plasma treatment is performed on the surface of the substrate on which the second gate electrode 33 is formed, using the second gate electrode 33 as a mask. Through this hydrogen plasma treatment, the exposed portion of the second semiconductor layer 31 is exposed to the plasma. When the oxide semiconductor constituting the second semiconductor layer 31 is exposed to the plasma, oxygen defects occur, resulting in low resistance. Consequently, a second channel region 31a and a pair of second conductor regions 31b are formed in the second semiconductor layer 31.

[0092] Furthermore, on a substrate where the second semiconductor layer 31 has undergone such low-resistance treatment, for example by plasma CVD, a silicon oxide film is formed to a thickness of 100 nm to 1000 nm, and a silicon nitride film is formed to a thickness of 100 nm to 500 nm. Next, the stacked film including these silicon oxide and silicon nitride films is patterned by photolithography to form a second interlayer insulating film 34. Thus, as... Figure 8 As shown in (f), the second wiring layer 42 is covered by the second interlayer insulating film 34. Furthermore, a stacked insulating film 36 is formed on the substrate layer 10. Through patterning at this time, the third contact hole Hc and the fourth contact hole Hd are formed together on the stacked insulating film 36.

[0093] Next, on the substrate where the second interlayer insulating film 34 has been formed, a titanium film, an aluminum film, and another titanium film are sequentially formed, for example, by sputtering. Then, the stacked film including these titanium films, aluminum films, and titanium films is patterned by photolithography to form the first terminal electrode 37, the second terminal electrode 38, and the relay line 40r, etc.

[0094] Next, a photosensitive resin is coated onto the substrate on which the first terminal electrode 37, etc., is formed, using a known coating method. Then, the photosensitive resin coating film is pre-baked, exposed, developed, and post-baked to form a planarization film 59 having a third contact hole Hc. Then, on the substrate on which the planarization film 59 is formed, a pixel electrode 61, an edge mask 66, an organic EL layer 62, and a common electrode 63 are formed sequentially using a known method. Thus, a light-emitting element layer 60 is constituted.

[0095] After that, such as Figure 8 As shown in (g), a first inorganic barrier layer 81 is formed on a substrate on which the light-emitting element layer 60 is formed by plasma CVD. Next, an organic resin material is coated onto the substrate on which the first inorganic barrier layer 81 is formed, and the coating film of the organic resin material is cured to form an organic barrier layer 82. Then, a second inorganic barrier layer 83 is formed on the substrate on which the organic barrier layer 82 is formed by plasma CVD. Figure 8 (not shown in (g)). Thus, a sealing film 80 is formed, constituting a joint SZ that extends in a manner that intersects with each lead wire 40h.

[0096] -Features of Implementation Method 1- In the organic EL display device 1 of this embodiment 1, a laminated structure comprising a first wiring layer 41 and a second wiring layer 42 is adopted for the lead wire 40h. This enables low resistance in the lead wire 40h. The first wiring layer 41 and the second wiring layer 42 are connected via a pair of first contact holes Ha formed in a first interlayer insulating film 26 between them. Furthermore, a joint SZ is provided between the pair of first contact holes Ha when viewed from above. Therefore, even if the surface of the first wiring layer 41 exposed from the first contact holes Ha becomes roughened due to the etching process during the formation of the first contact holes Ha, a path for moisture to penetrate the joint SZ will not be formed. Thus, moisture intrusion into the display area DA along the lead wire 40h can be suppressed.

[0097] For example, in the comparative example organic EL display device 1 where the lead wire 40h employs a configuration similar to that in Patent Document 1, when moisture intrudes into the display area DA along the lead wire 40h, as... Figure 9B As shown, in the portion of the display area DA that has been infiltrated by moisture (the portion surrounded by the dashed circle), the brightness of the organic EL element 65 will decrease due to deterioration, resulting in uneven display. In contrast, in the organic EL display device 1 of this embodiment 1, as described above, it is possible to suppress the infiltration of moisture into the display area along the lead wire 40h, thus preventing deterioration of the organic EL element 65. Figure 9A As shown, it can suppress the generation of uneven display.

[0098] Furthermore, in the organic EL display device 1 according to this embodiment 1, a pair of first contact holes Ha are provided on the inner and outer sides of the junction SZ. Therefore, even if the connection portion between the first wiring layer 41 and the second wiring layer 42 within each first contact hole Ha becomes highly resistive for some reason, and heat is generated in this connection portion when the organic EL display device 1 operates, the impact of this heat on the junction SZ can be reduced. This also improves the reliability of the organic EL display device 1.

[0099] In the organic EL display device 1 of this embodiment 1, the first wiring layer 41 and the second wiring layer 42 are each formed in a conical cross-section. The two side surfaces of each of the conical first wiring layer 41 and the second wiring layer 42 in the width direction approach each other towards the upper layer. This improves the step coverage of the first inorganic barrier layer 81 over the lead wire 40h.

[0100] In the organic EL display device 1 of this embodiment 1, the two sides of the first wiring layer 41 and the two sides of the second wiring layer 42 are offset from each other in the width direction of the lead wire 40h. Figure 19AAs shown, when the side surface of the first wiring layer 41 and the side surface of the second wiring layer 42 correspond in their stacking direction, there is a tendency for the tilt angle formed by the side surface of the second wiring layer 42 to be steeper than that formed by the side surface of the first wiring layer 41. In contrast, this configuration can suppress the relatively steep tilt angle formed by the two side surfaces of the second wiring layer 42. This is advantageous for improving the stepped coverage of the first inorganic barrier layer 81 on the lead wire 40h.

[0101] In the organic EL display device 1 of this embodiment 1, the width of the second wiring layer 42 is smaller than the width of the first wiring layer 41. Furthermore, the two sides of the second wiring layer 42 are positioned offset from the two sides of the first wiring layer 41 in the width direction of the lead-out line 40h by corresponding to the upper surface of the first wiring layer 41 in the stacking direction of the first wiring layer 41 and the second wiring layer 42. This is advantageous for both increasing the stepped coverage of the first inorganic barrier layer 81 over the lead-out line 40h and simultaneously thinning the lead-out line 40h.

[0102] In the organic EL display device 1 of this embodiment 1, the second tilt angle θ2 formed by the side surface of the second wiring layer 42 is equal to or smaller than the first tilt angle θ1 formed by the side surface of the first wiring layer 41. This is advantageous for improving the stepped coverage of the first inorganic barrier layer 81 over the lead wire 40h.

[0103] In the organic EL display device 1 of this embodiment 1, the first wiring layer 41 and the electrodes or wirings of the circuit elements disposed in the display area DA are formed on the same layer using the same material. Therefore, in the manufacturing of the organic EL display device 1, it is not necessary to add a separate step for forming the first wiring layer 41 in addition to the step of forming the electrodes and wirings of the circuit elements. This reduces the need for additional steps in the manufacturing of the organic EL display device 1 and lowers its manufacturing cost.

[0104] In the OLED display device 1 of this embodiment 1, the second wiring layer 42 and the electrodes or wirings of the circuit elements disposed in the display area DA are formed on the same layer using the same material. Therefore, in the manufacturing of the OLED display device 1, it is not necessary to add a separate step for forming the second wiring layer 42 in addition to the step of forming the electrodes and wirings of the circuit elements. This reduces the need for additional steps in the manufacturing of the OLED display device 1 and lowers its manufacturing cost.

[0105] Implementation Method 2 The configuration of the lead wire 40h in this embodiment 2 of the organic EL display device 1 differs from that in embodiment 1. Furthermore, in subsequent embodiments, except for the configuration of the lead wire 40h, the organic EL display device 1 is configured in the same way as in embodiment 1.

[0106] like Figures 10-13 As shown, the lead wire 40h in the organic EL display device 1 of this embodiment 2 is composed of three layers. Specifically, in addition to the first wiring layer 41 and the second wiring layer 42, the lead wire 40h also includes a third wiring layer 43. The second wiring layer 42 is covered by a second gate insulating film 32. The third wiring layer 43 is stacked on the second wiring layer 42 with the second gate insulating film 32 in between. The second gate insulating film 32 is an example of a second inorganic insulating film. The third wiring layer 43 is stacked on the second wiring layer 42 with the second gate insulating film 32 in between. The third wiring layer 43 is covered by a second interlayer insulating film 34.

[0107] The third wiring layer 43 is formed as a cross-sectional cone with two sides facing each other towards the upper layer in the width direction of the lead-out line 40h. The two sides of the third wiring layer 43 are staggered from the two sides of the first wiring layer 41 and the second wiring layer 42 in the width direction of the lead-out line 40h. Specifically, the line width of the third wiring layer 43 is wider than the line width of the first wiring layer 41 and the line width of the second wiring layer 42. Furthermore, the two sides of the first wiring layer 41 and the two sides of the second wiring layer 42 correspond to the upper surface of the third wiring layer 43 in the stacking direction of the first wiring layer 41 to the third wiring layer 43, respectively.

[0108] When the angle formed by the side surface of the second wiring layer 42 in the width direction relative to the direction orthogonal to the thickness direction of the second wiring layer 42 on the inner side of the second wiring layer 42 is defined as the second tilt angle θ2, and the angle formed by the side surface of the third wiring layer 43 in the width direction relative to the direction orthogonal to the thickness direction of the third wiring layer 43 on the inner side of the third wiring layer 43 is defined as the third tilt angle θ3, the second tilt angle θ2 and the third tilt angle θ3 satisfy the relationship θ3≤θ2. The second tilt angle θ2 is, for example, 10° to 85°. The third tilt angle is, for example, 5° to 80°.

[0109] A plurality of second contact holes Hb are formed on the second gate insulating film 32. The second contact holes Hb are arranged in pairs for each lead 40h. The second wiring layer 42 and the third wiring layer 43 are connected via a pair of second contact holes Hb. This pair of second contact holes Hb, when viewed from above, is positioned such that at least a portion (in this example, the entire width of the junction SZ) of the junction SZ is located between them along the length of the lead 40h. The second contact holes Hb are formed at a position offset from the first contact hole Ha in the length of the lead 40h.

[0110] The third wiring layer 43 and the electrodes constituting the circuit elements or the wiring connected to the circuit elements are formed of the same material on the same layer. In this example, the third wiring layer 43, the second gate line 40gb, and the second gate electrode 33 are formed of the same material on the same layer.

[0111] To manufacture the organic EL display device 1 of this embodiment 2, after forming the second wiring layer 42, etc., in the same manner as in embodiment 1, as described above, Figure 14 As shown in (a), the second gate insulating film 32 is formed in a manner that covers a portion of the second semiconductor layer 31 (forming the portion of the second channel region 31a) and the first capacitor electrode 25, and also covers the second wiring layer 42. Then, on the substrate on which the second gate insulating film 32 is formed, the second gate line 40gb and the second gate electrode 33 are formed in the same manner as in Embodiment 1 described above. At this time, as Figure 14 As shown in (b), the third wiring layer 43 and the second gate line 40gb are formed together from the same film.

[0112] Next, on the substrate where the third wiring layer 43 has been formed, a second interlayer insulating film 34 is formed, for example, by plasma CVD, in a manner covering the second gate line 40gb and the second gate electrode 33. At this time, as... Figure 14 As shown in (c), a second interlayer insulating film 34 is formed to cover the third wiring layer 43. Then, on the substrate on which the second interlayer insulating film 34 is formed, a first terminal electrode 37, a second terminal electrode 38, and a relay line 40r are formed in the same manner as in Embodiment 1 described above.

[0113] Next, similarly to Embodiment 1 described above, a planarization film 59 and a light-emitting element layer 60 are formed on a substrate on which the first terminal electrode 37, etc., are formed. After this, a first inorganic barrier layer 81, an organic barrier layer 82, and a second inorganic barrier layer 83 are sequentially formed on the substrate on which the light-emitting element layer 60 is formed. Thus, as... Figure 14 As shown in (d), a sealing film 80 is formed to cover the lead wires 40h, constituting a joint SZ that extends in a manner that intersects with each lead wire 40h.

[0114] -Features of Implementation Method 2- In the organic EL display device 1 of this embodiment 2, a stacked structure is adopted in which the lead wire 40h includes a third wiring layer 43 in addition to the first wiring layer 41 and the second wiring layer 42. This allows for further reduction of the resistance of the lead wire 40h. The second wiring layer 42 and the third wiring layer 43 are connected via a pair of second contact holes Hb formed in the second interlayer insulating film 34. Furthermore, when viewed from above, at least a portion of the junction SZ is located between the pair of second contact holes Hb along the length direction of the lead wire 40h. Therefore, even if the surface of the second wiring layer 42 exposed from the second contact holes Hb becomes rough due to the etching process during the formation of the second contact holes Hb, a path for moisture to penetrate the junction SZ will not be formed. Thus, moisture intrusion into the display area DA along the lead wire 40h can be suppressed.

[0115] In this organic EL display device 1, the third wiring layer 43 is formed in a cone shape. The two sides of the cone-shaped third wiring layer 43 in the width direction approach each other towards the upper layer. As a result, the step coverage of the first inorganic barrier layer 81 on the lead wire 40h can be improved.

[0116] In the organic EL display device 1 of this embodiment 2, the two sides of the third wiring layer 43 are offset from the two sides of each of the first wiring layer and the second wiring layer 42 in the width direction of the lead wire 40h. Figure 19B As shown, when the side surface of the third wiring layer 43 corresponds to the side surfaces of the first wiring layer 41 and the second wiring layer 42 in their stacking direction, there is a tendency for the tilt angle formed by the side surface of the third wiring layer 43 to be steeper than the tilt angles formed by the side surfaces of the first wiring layer 41 and the second wiring layer 42. In contrast, according to this configuration, the relatively steep tilt angles formed by the two side surfaces of the second wiring layer 42 can be suppressed. This is advantageous for improving the stepped coverage of the first inorganic barrier layer 81 on the lead-out line 40h.

[0117] In the organic EL display device 1 of this embodiment 2, the third tilt angle θ3 formed by the side surface of the third wiring layer 43 is equal to or smaller than the second tilt angle θ2 formed by the side surface of the second wiring layer 42. This is advantageous for improving the stepped coverage of the inorganic barrier layer on the lead wire 40h.

[0118] Implementation Method 3 In this embodiment 3, the lead wire 40h in the organic EL display device 1 is composed of two layers. Specifically, as shown... Figures 15-17 As shown, lead wire 40h includes a first wiring layer 41 and a second wiring layer 42.

[0119] The first wiring layer 41 is only provided in the bezel area FA. Specifically, the first wiring layer 41 extends from the bezel area FA between the junction SZ and the display area DA through the junction SZ to the bezel area FA on the terminal portion TP side of the junction SZ. The first wiring layer 41 has a stacked structure in which multiple metal layers 44 are stacked. The multiple metal layers 44 include a first metal layer 44a, a second metal layer 44b, and a third metal layer 44c.

[0120] A first metal layer 44a is disposed on the surface of the first gate insulating film 23. A second metal layer 44b is disposed on the first metal layer 44a. A third metal layer 44c is disposed on the second metal layer 44b. The first metal layer 44a and the third metal layer 44c are respectively composed of titanium (Ti) or titanium alloy. The second metal layer 44b is composed of aluminum (Al) or aluminum alloy. The first interlayer insulating film 26 is disposed in such a way that it completely covers the first wiring layer 41.

[0121] When the first wiring layer 41 is configured as a three-layer structure as described above, during the manufacturing process of the organic EL display device 1, the second metal layer 44b is exposed to the alkaline developer used in etching or photolithography (resist patterning) during the patterning of the first wiring layer 41, thereby being side-etched in a manner that penetrates beneath the third metal layer 44c. As a result, the third metal layer 44c in the first wiring layer 41 protrudes laterally, forming an eave-like portion in the first wiring layer 41.

[0122] In this way, the first interlayer insulating film 26 cannot cover the side surface of the first wiring layer 41 in a tight fit, and a gap 45 will be formed between the second metal layer 44b and the first interlayer insulating film 26 on the side of the first wiring layer 41. However, this gap 45 of the first wiring layer 41 is covered and sealed by the first interlayer insulating film 26 over its entire circumference. Therefore, this gap 45 of the first wiring layer 41 will not become a path for external moisture to invade the display area DA.

[0123] The first wiring layer 41, like in Embodiment 1 described above, is formed of the same material as the first gate line 40ga, the light emission control line 40e, the initialization line 40i, and the first gate electrode 24, and is located on the same layer. That is, the first gate line 40ga, the light emission control line 40e, the initialization line 40i, and the first gate electrode 24, like the first wiring layer 41, have a three-layer structure including a first metal layer 44a, a second metal layer 44b, and a third metal layer 44c.

[0124] The second wiring layer 42 extends from the display area DA to the terminal portion TP, constituting the full length of the lead wire 40h. The second wiring layer 42 is configured to completely cover the first wiring layer 41 through the first interlayer insulating film 26. The two sides of the first wiring layer 41 and the second wiring layer 42 are staggered in the width direction of the lead wire 40h.

[0125] Specifically, the line width of the second wiring layer 42 is wider than that of the first wiring layer 41. Furthermore, the two sides of the first wiring layer 41 correspond to the upper surface of the second wiring layer 42 in the stacking direction of the first wiring layer 41 and the second wiring layer 42. The second wiring layer 42 is formed as a cross-section cone with its two sides in the width direction of the lead-out line 40h approaching each other from the upper layer. The second tilt angle θ2 is, for example, 10° to 85°.

[0126] The second wiring layer 42, like in Embodiment 1, is formed on the same layer as the third terminal electrode 28, using the same material. The second wiring layer 42 is stacked on top of the first wiring layer 41 across the first interlayer insulating film 26 and is covered by the second interlayer insulating film 34. Furthermore, the second wiring layer 42 is connected to the first wiring layer 41 via a pair of first contact holes Ha formed in the first interlayer insulating film 26.

[0127] To manufacture the organic EL display device 1 of this embodiment 3, after forming the first gate insulating film 23 in the same manner as in embodiment 1, a titanium film, an aluminum film, and a titanium film are sequentially formed, for example, by sputtering. Next, the stacked film including these titanium films, aluminum films, and titanium films is patterned by photolithography to form the first gate line 40ga, the light emission control line 40e, the initialization line 40i, and the first gate electrode 24. At this time, as... Figure 18 As shown in (a), the first wiring layer 41 and the first gate line 40ga are formed together from the same film.

[0128] Next, similarly to Embodiment 1 described above, the first semiconductor layer 22 is doped with impurity ions to form a first channel region 22a and a pair of first conductor regions 22b, as follows: Figure 18 As shown in (b), the first interlayer insulating film 26 is formed in a manner that covers the first wiring layer 41, etc. Furthermore, when the first contact hole Ha is formed in the first interlayer insulating film 26, as... Figure 18 As shown in (c), the first interlayer insulating film 26 is patterned into a shape that individually covers the first wiring layer 41.

[0129] Next, similarly to Embodiment 1 described above, a third terminal electrode 28, a fourth terminal electrode 29, and a first capacitor electrode 25 are formed on the substrate on which the first interlayer insulating film 26 is formed. At this time, as... Figure 18As shown in (d), the second wiring layer 42 is formed together with the third terminal electrode 28 and the like from the same film in a cone-shaped cross-section. Thus, multiple leads 40h are formed.

[0130] Next, similarly to Embodiment 1 described above, a second gate insulating film 32 and a second semiconductor layer 31 are formed on a substrate on which the second wiring layer 42, etc., are formed. A low-resistance treatment is performed on the second semiconductor layer 31 to form a second channel region 31a and a pair of second conductor regions 31b. Then, on the substrate on which the low-resistance treatment is performed on the second semiconductor layer 31, a second interlayer insulating film 34 is formed, and a third contact hole Hc and a fourth contact hole Hd are formed.

[0131] Next, on the substrate where the second wiring layer 42 has been formed, a second interlayer insulating film 34 is formed, for example, by plasma CVD, in a manner covering the second gate line 40gb and the second gate electrode 33. At this time, as... Figure 18 As shown in (e), a second interlayer insulating film 34 is formed to cover the second wiring layer 42. Then, on the substrate on which the second interlayer insulating film 34 is formed, a first terminal electrode 37, a second terminal electrode 38, and a relay line 40r are formed in the same manner as in Embodiment 1 described above.

[0132] Next, similarly to Embodiment 1 described above, a planarization film 59 and a light-emitting element layer 60 are formed on the substrate on which the first terminal electrode 37, etc., are formed. After this, a first inorganic barrier layer 81, an organic barrier layer 82, and a second inorganic barrier layer 83 are sequentially formed on the substrate on which the light-emitting element layer 60 is formed. Thus, as... Figure 18 As shown in (f), a sealing film 80 is formed in such a way as to cover the lead wires 40h, forming a joint SZ that extends in a manner that intersects with each lead wire 40h.

[0133] -Features of Implementation Method 3- In the organic EL display device 1 of this embodiment 3, the first wiring layer 41 has a stacked structure. By using a low-resistance metal material (aluminum or aluminum alloy in this example) for at least a portion of the plurality of metal layers 44 constituting the stacked structure, the resistance of the lead wire 40h can be further reduced. The first wiring layer 41 is entirely covered by the first interlayer insulating film 26. Thus, even if the middle or lower metal layer 44 (the second metal layer 44b in this example) in the stacking direction of the plurality of metal layers 44 constituting the first wiring layer 41 is side-etched by the etching process during the formation of the first wiring layer 41 in a manner that penetrates under the upper metal layer 44 (the third metal layer 44c in this example), forming a gap 45 on the side of the first wiring layer 41, the gap 45 can be surrounded and sealed by the first interlayer insulating film 26. Therefore, it is possible to prevent the gap 45 caused by the side etching of the first wiring layer 41 from becoming a path for moisture intrusion.

[0134] In the organic EL display device 1 of this embodiment 3, the first wiring layer 41 is configured to include a first metal layer 44a, a second metal layer 44b, and a third metal layer 44c. The second metal layer 44b comprises aluminum (Al) or an aluminum alloy. Aluminum (Al) or aluminum alloys have relatively low resistance and excellent conductivity. Therefore, the second metal layer 44b contributes to the low resistance of the first wiring layer 41. The first metal layer 44a and the third metal layer 44c comprise titanium (Ti) or a titanium alloy. Titanium or titanium alloys have relatively high corrosion resistance. Therefore, the first metal layer 44a and the third metal layer 44c appropriately function as protective layers for the second metal layer 44b, which includes materials such as aluminum (Al) that are prone to corrosion and deterioration.

[0135] In the organic EL display device 1 of this embodiment 3, the second wiring layer 42 is formed in a conical cross-section. The two side surfaces of the conical second wiring layer 42 in the width direction approach each other towards the upper layer. As a result, the step coverage of the first inorganic barrier layer 81 on the lead wire 40h can be improved.

[0136] In the organic EL display device 1 of this embodiment 3, the first wiring layer 41 is covered by the second wiring layer 42 through the second interlayer insulating film 34. Even if a gap 45 caused by side etching is formed on the side of the first wiring layer 41, the gap 45 can be surrounded and sealed by the laminate of the first interlayer insulating film 26 and the second wiring layer 42. This is advantageous for preventing the gap 45 caused by side etching of the first wiring layer 41 from becoming a path for moisture intrusion.

[0137] Other implementation methods In the above embodiment 1, the line width of the second wiring layer 42 is assumed to be narrower than the line width of the first wiring layer 41, and the two sides of the second wiring layer 42 correspond to the upper surface of the second wiring layer 42 in the stacking direction of the first wiring layer 41 and the second wiring layer 42, but this is not limited to this. Figure 20 As shown, the line width of the first wiring layer 41 may be narrower than the line width of the second wiring layer 42. Furthermore, the two sides of the first wiring layer 41 may correspond to the upper surface of the second wiring layer 42 in the stacking direction of the first wiring layer 41 and the second wiring layer 42.

[0138] In Embodiment 1 described above, the first wiring layer 41 and the gate line 40g are formed of the same material on the same layer, and the second wiring layer 42 and the third terminal electrode 28 are formed of the same material on the same layer. However, this is not a limitation; the first wiring layer 41 and the second wiring layer 42 may also be formed of the same material on the same layer as the electrodes constituting other circuit elements or the wiring connected to the circuit elements. Furthermore, the first wiring layer 41 and the second wiring layer 42 may be formed by different processes from the electrodes constituting the circuit elements or the wiring connected to the circuit elements. The same applies to the third wiring layer 43 in Embodiment 2 described above.

[0139] In Embodiment 1 described above, an example is shown where one first contact hole Ha is provided on both the inner and outer sides of the joint SZ for each lead-out wire 40h. However, this is not a limitation; multiple first contact holes Ha may be provided on the inner side of the joint SZ for each lead-out wire 40h, and multiple first contact holes Ha may also be provided on the outer side of the joint SZ for each lead-out wire 40h. The same applies to the second contact hole Hb in Embodiment 2 described above.

[0140] In the above embodiment, the organic EL layer 62 is provided separately for each sub-pixel SP, but it is not limited to this. The organic EL layer 62 may also be provided continuously in multiple sub-pixels SP. In this case, the organic EL display device 1 may also include a color filter or the like to represent the tone in each sub-pixel SP.

[0141] In the above embodiment, each pixel PX is assumed to be composed of 3-color sub-pixels SP, but this is not a limitation. The sub-pixels SP constituting each pixel PX may also be 4 colors or more. In addition, the 3-color sub-pixels SP constituting each pixel PX are arranged in a strip shape, but this is not a limitation. The arrangement of multiple sub-pixels SP may also be a pentile arrangement or other arrangements.

[0142] In the above embodiment, the pixel electrode 61 functions as the anode and the common electrode functions as the cathode, but it is not limited to this. The organic EL display device 1 may also be configured such that the pixel electrode 61 functions as the cathode and the common electrode 63 functions as the anode. In this case, the organic EL layer 62 is configured as a stacked structure with inversion.

[0143] In the above embodiment, the organic EL layer 62 is assumed to be a five-layer structure including a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer, but it is not limited to this. The organic EL layer 62 can also be a three-layer structure including a hole injection layer that also serves as a transport layer, a light-emitting layer, and an electron transport layer that also serves as an injection layer, and any other stacked structure can be adopted.

[0144] In the above embodiment, the substrate of the organic EL display device 1 is assumed to be substrate layer 10, but it is not limited thereto. As the substrate, any substrate made of materials such as polyethylene terephthalate (PET) plastic substrate or glass substrate can be used.

[0145] In the above embodiments, an organic EL display device 1 is exemplified as a display device according to this disclosure, but it is not limited thereto. The technology of this disclosure can be applied to display devices having multiple light-emitting elements. As such a display device, a quantum dot display device having a QLED (Quantum-dot Light Emitting Diode) as a light-emitting element using a quantum dot layer can be cited.

[0146] As illustrated above, preferred embodiments have been described as examples of the technology disclosed herein. However, the technology disclosed herein is not limited to these embodiments and can also be applied to embodiments with appropriate modifications, substitutions, additions, omissions, etc. Those skilled in the art will understand that various modifications can be made to the above embodiments without departing from the spirit of the disclosed technology, and such modifications also fall within the scope of the technology disclosed herein. Industrial availability

[0147] As explained above, this disclosure is useful for display devices. Explanation of reference numerals in the attached figures

[0148] DA display area FA border area Ha, first contact hole Hb second contact hole SZ joint TP terminal section 1 Organic EL display device (display device) 5. Circuit board 10. Substrate layer (base substrate) 26 First interlayer insulating film (first inorganic insulating film) 32 Second gate insulating film (second inorganic insulating film) 36-layer insulating film 40h lead wire 41 First wiring layer 42 Second wiring layer 43 Third wiring layer 44 Metal Layer 44a First metal layer 44b Second metal layer 44c Third metal layer 50 TFT (Circuit Components) 55. Capacitor (circuit element) 65 Organic EL elements (light-emitting elements) 80 sealing film 81 First Inorganic Barrier Layer 82 Organic Barrier Layer 83 Second inorganic barrier layer.

Claims

1. A display device comprising: Circuit board; Multiple light-emitting elements are disposed on the circuit board; and A sealing film is provided to cover the plurality of light-emitting elements. The plurality of light-emitting elements constitute the display area for displaying the image. Outside the display area, a border area is provided as a non-display area where no image is displayed. The circuit board includes: a substrate; and a laminated insulating film, which is made of laminated inorganic insulating materials and is disposed on the substrate in a manner that extends into the border region. The sealing membrane has an inorganic barrier layer comprising inorganic insulating material. The border region includes: a frame-shaped joint where the portion of the inorganic barrier layer along its periphery contacts the laminated insulating film; and a terminal portion located outside the joint. A lead wire is provided on the lower side of the sealing film in the frame area. The lead wire extends from the display area, intersecting the joint portion, and is led out to the terminal portion. The display device is characterized in that... The lead wire comprises: a first wiring layer; and a second wiring layer, which is laminated on the first wiring layer with a first inorganic insulating film in between. The first wiring layer and the second wiring layer are connected via a pair of first contact holes formed in the first inorganic insulating film. When viewed from above, the engagement portion is provided between the pair of first contact holes.

2. The display device according to claim 1, wherein, The first wiring layer and the second wiring layer are respectively formed as two side faces of the lead wire in the width direction that are close to each other in cross-section.

3. The display device according to claim 2, wherein, The two sides of the first wiring layer and the second wiring layer are staggered in the width direction of the lead wire.

4. The display device according to claim 3, wherein, The line width of the second wiring layer is narrower than that of the first wiring layer. The two sides of the second wiring layer correspond to the upper surface of the first wiring layer in the stacking direction of the first wiring layer and the second wiring layer.

5. The display device according to claim 3, wherein, The line width of the first wiring layer is narrower than the line width of the second wiring layer. The two sides of the first wiring layer correspond to the upper surface of the second wiring layer in the stacking direction of the first wiring layer and the second wiring layer.

6. The display device according to any one of claims 2 to 5, wherein, When the angle formed by the side surface of the first wiring layer in the width direction relative to the direction orthogonal to the thickness direction of the first wiring layer on the inner side of the first wiring layer is defined as the first tilt angle θ1, and the angle formed by the side surface of the second wiring layer in the width direction relative to the direction orthogonal to the thickness direction of the second wiring layer on the inner side of the second wiring layer is defined as the second tilt angle θ2, the following relationship is satisfied: θ2≤θ1.

7. The display device according to any one of claims 1 to 6, wherein, The lead wire also includes a third wiring layer that is stacked on the second wiring layer with a second inorganic insulating film in between. One or both of the first wiring layer and the second wiring layer are connected to the third wiring layer via a pair of second contact holes formed in a laminated film including the first inorganic insulating film and the second inorganic insulating film. The pair of second contact holes are configured such that, when viewed from above, at least a portion of the joint is positioned relative to each other along the length of the lead-out line.

8. The display device according to claim 7, wherein, The third wiring layer is formed as a cross-section cone with two sides facing each other towards the upper layer in the width direction of the lead wire.

9. The display device according to claim 8, wherein, The first wiring layer and the second wiring layer are respectively formed as two conical cross-sections with their sides facing each other towards the upper layer in the width direction of the lead wire. The two sides of each of the first wiring layer, the second wiring layer, and the third wiring layer are staggered in the width direction of the lead wire.

10. The display device according to claim 8 or 9, wherein, When the angle formed by the side surface of the second wiring layer in the width direction relative to the direction orthogonal to the thickness direction of the second wiring layer on the inner side of the second wiring layer is defined as the second tilt angle θ2, and the angle formed by the side surface of the third wiring layer in the width direction relative to the direction orthogonal to the thickness direction of the third wiring layer on the inner side of the third wiring layer is defined as the second tilt angle θ3, the following relationship is satisfied: θ3≤θ2.

11. The display device according to claim 1, wherein, The first wiring layer has a stacked structure with multiple metal layers. The first inorganic insulating film is configured to completely cover the first wiring layer.

12. The display device according to claim 11, wherein, The plurality of metal layers include a first metal layer, a second metal layer disposed on the first metal layer, and a third metal layer disposed on the second metal layer.

13. The display device according to claim 12, wherein, The first metal layer and the third metal layer respectively comprise titanium or a titanium alloy. The second metal layer comprises aluminum or an aluminum alloy.

14. The display device according to any one of claims 11 to 13, wherein, The second wiring layer is formed as a cross-section cone with two sides facing each other towards the upper layer in the width direction of the lead wire.

15. The display device according to any one of claims 11 to 14, wherein, The second wiring layer is configured to completely cover the first wiring layer through the first inorganic insulating film.

16. The display device according to any one of claims 1 to 15, wherein, The circuit board includes multiple circuit elements disposed in the display area. The first wiring layer and the electrodes constituting the circuit element or the wiring connected to the circuit element are formed of the same material in the same layer.

17. The display device according to any one of claims 1 to 16, wherein, The circuit board includes multiple circuit elements disposed in the display area. The second wiring layer and the electrodes constituting the circuit element or the wiring connected to the circuit element are formed of the same material in the same layer.

18. The display device according to any one of claims 1 to 17, wherein, The sealing membrane comprises: a first inorganic barrier layer as the inorganic barrier layer; an organic barrier layer disposed on the first inorganic barrier layer; and a second inorganic barrier layer disposed on the organic barrier layer.

19. The display device according to any one of claims 1 to 18, wherein, The light-emitting element is an organic electroluminescent element.

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