Display substrate and display device

Abstract

The invention provides a display substrate. The display substrate comprises a substrate; the first functional layer is located on the substrate; the insulating layer is located on the side, away from the substrate, of the first functional layer, and the insulating layer is provided with a via hole; the second functional layer is located on the side, away from the first functional layer, of the insulating layer, and the second functional layer is in lap joint with the first functional layer through a via hole; the first functional layer is located on the substrate, the at least one third functional layer is located between the first functional layer and the substrate, the orthographic projection of any third functional layer on the substrate is partially overlapped with the orthographic projection of the first functional layer on the substrate, the first functional layer is provided with a lap joint surface exposed by a via hole, and the third functional layer is located between the first functional layer and the substrate. And the lapping surface is a flat surface.

Description

Display substrate and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] Active-matrix organic light-emitting diodes (AMOLEDs) offer advantages such as self-luminescence, a wide color gamut, high contrast, flexibility, and high responsiveness, making them promising for broad application. With the rapid development of AMOLED display devices, the number of pixel circuit signals and the film layer stacking requirements have become increasingly complex. Optimizing pixel structure design to improve display quality has become a major concern for display product developers.

[0003] The above information disclosed in this section is only for understanding the background of the inventive concept of the present disclosure and therefore the above information may contain information that does not constitute prior art.

[0004] Summary of the Invention

[0005] In one aspect, a display substrate is provided, comprising:

[0006] substrate;

[0007] A first functional layer is located on the substrate;

[0008] an insulating layer, located on a side of the first functional layer away from the substrate, the insulating layer having a via hole;

[0009] a second functional layer, located on a side of the insulating layer away from the first functional layer, the second functional layer overlapping the first functional layer through the via hole; and

[0010] At least one third functional layer, wherein the at least one third functional layer is located between the first functional layer and the base substrate, and the orthographic projection of any third functional layer on the base substrate partially overlaps with the orthographic projection of the first functional layer on the base substrate,

[0011] The first functional layer has a lap joint surface exposed by the via hole, and the lap joint surface is a flat surface.

[0012] According to some exemplary embodiments, an orthographic projection of a bottom of the via hole close to the base substrate on the base substrate is located within an orthographic projection of any layer of the third functional layer on the base substrate.

[0013] According to some exemplary embodiments, the orthographic projection of the bottom of the via hole close to the base substrate on the base substrate does not overlap with the orthographic projection of each layer of the third functional layer on the base substrate.

[0014] According to some exemplary embodiments, the multilayer third functional layer includes at least one first sublayer and at least one second sublayer;

[0015] The orthographic projection of the bottom of the via hole close to the base substrate on the base substrate does not overlap with the orthographic projection of each first sub-layer on the base substrate; and

[0016] The orthographic projection of the bottom of the via hole close to the base substrate on the base substrate is located within the orthographic projection of any second sub-layer on the base substrate.

[0017] According to some exemplary embodiments, the third functional layer includes a functional portion, and an orthographic projection of a bottom of the via hole close to the base substrate on the base substrate partially overlaps or is flush with an orthographic projection of the functional portion on the base substrate; and

[0018] The third functional layer further includes a raised portion directly connected to the functional portion, and the orthographic projection of the bottom of the via hole close to the base substrate on the base substrate is located within the orthographic projections of the functional portion and the raised portion on the base substrate.

[0019] According to some exemplary embodiments, an edge of the raised portion extends beyond the bottom edge of the via hole by 0.4 μm-0.6 μm.

[0020] According to some exemplary embodiments, at least one layer of the third functional layer includes at least one metal functional layer, and the orthographic projection of the bottom of the via hole close to the base substrate on the base substrate is spaced apart from the orthographic projection of each layer of the metal functional layer on the base substrate.

[0021] According to some exemplary embodiments, at least one of the third functional layers includes at least one semiconductor functional layer;

[0022] The orthographic projection of the bottom of the via hole close to the substrate on the substrate is spaced apart from the orthographic projection of the semiconductor functional layer on the substrate, and / or

[0023] The orthographic projection of the bottom of the via hole close to the base substrate on the base substrate is flush with the orthographic projection of the semiconductor functional layer on the base substrate.

[0024] According to some exemplary embodiments, the first functional layer is a first semiconductor layer, the second functional layer is a first source-drain metal layer, the insulating layer has a first via hole, and the first source-drain metal layer is overlapped with the first semiconductor layer through the first via hole; and

[0025] The third functional layer is a light-shielding layer, and the orthographic projection of the bottom of the first via hole close to the base substrate on the base substrate is located within the orthographic projection of the light-shielding layer on the base substrate.

[0026] According to some exemplary embodiments, the light-shielding layer includes a light-shielding portion connecting trace and a first raised portion directly connected to the light-shielding portion connecting trace, the orthographic projection of the bottom of the first via hole close to the substrate on the substrate partially overlaps with the orthographic projection of the light-shielding portion connecting trace on the substrate, and the orthographic projection of the bottom of the first via hole close to the substrate on the substrate is located within the orthographic projection of the light-shielding portion connecting trace and the first raised portion on the substrate.

[0027] According to some exemplary embodiments, the first functional layer is a third gate metal layer, the second functional layer is a first source / drain metal layer, the insulating layer has a second via hole, and the first source / drain metal layer is overlapped with the third gate metal layer through the second via hole;

[0028] At least one of the third functional layers is a light shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, and a second semiconductor layer stacked between the base substrate and the third gate metal layer; and

[0029] The orthographic projection of the bottom of the second via hole close to the base substrate on the base substrate is spaced apart from the orthographic projections of the light shielding layer, the first semiconductor layer, the first gate metal layer, the second gate metal layer and the second semiconductor layer on the base substrate.

[0030] According to some exemplary embodiments, the first functional layer is a second semiconductor layer, the second functional layer is a first source-drain metal layer, the insulating layer has a third via hole, and the first source-drain metal layer is overlapped with the second semiconductor layer through the third via hole;

[0031] At least one of the third functional layers is a light shielding layer, a first semiconductor layer, a first gate metal layer, and a second gate metal layer stacked between the base substrate and the second semiconductor layer; and

[0032] The orthographic projection of the bottom of the third via hole close to the substrate on the substrate is flush with the orthographic projection of the first semiconductor layer on the substrate, and the orthographic projection of the bottom of the third via hole close to the substrate on the substrate is spaced apart from the orthographic projections of the light-shielding layer, the first gate metal layer and the second gate metal layer on the substrate.

[0033] According to some exemplary embodiments, the first functional layer is a second semiconductor layer, the second functional layer is a first source-drain metal layer, the insulating layer has a fourth via hole, and the first source-drain metal layer is overlapped with the second semiconductor layer through the fourth via hole;

[0034] At least one of the third functional layers is a light shielding layer, a first semiconductor layer, a first gate metal layer, and a second gate metal layer stacked between the base substrate and the second semiconductor layer; and

[0035] The orthographic projection of the bottom of the fourth via hole close to the base substrate on the base substrate is respectively located within the orthographic projection of the light-shielding layer and the first gate metal layer on the base substrate, and the orthographic projection of the bottom of the fourth via hole close to the base substrate on the base substrate is spaced from the orthographic projection of the first semiconductor layer and the second gate metal layer on the base substrate.

[0036] According to some exemplary embodiments, the light shielding layer includes a light shielding portion connecting wiring and a second padding portion directly connected to the light shielding portion connecting wiring, and the first gate metal layer includes a scan signal line and a third padding portion directly connected to the scan signal line;

[0037] The orthographic projection of the bottom of the fourth via hole close to the base substrate on the base substrate partially overlaps with the orthographic projection of the light-shielding portion connecting trace on the base substrate, and the orthographic projection of the bottom of the fourth via hole close to the base substrate on the base substrate is located within the orthographic projections of the light-shielding portion connecting trace and the second raised portion on the base substrate;

[0038] The orthographic projection of the bottom of the fourth via hole close to the base substrate on the base substrate partially overlaps with the orthographic projection of the scanning signal line on the base substrate, and the orthographic projection of the bottom of the fourth via hole close to the base substrate on the base substrate is located within the orthographic projections of the scanning signal line and the third raised portion on the base substrate; and

[0039] The first gate metal layer is located on a side of the light shielding layer away from the base substrate, and the orthographic projection of the third elevated portion on the base substrate is located within the orthographic projection of the light shielding portion connecting trace and the second elevated portion on the base substrate.

[0040] According to some exemplary embodiments, the first functional layer is a second semiconductor layer, the second functional layer is a first source-drain metal layer, the insulating layer has a third via hole, and the first source-drain metal layer is overlapped with the second semiconductor layer through the third via hole;

[0041] At least one of the third functional layers is a light shielding layer, a first semiconductor layer, a first gate metal layer, and a second gate metal layer stacked between the base substrate and the second semiconductor layer; and

[0042] The orthographic projection of the bottom of the third via hole close to the base substrate on the base substrate is located within the orthographic projection of the first semiconductor layer on the base substrate; the orthographic projection of the bottom of the third via hole close to the base substrate on the base substrate is spaced from the orthographic projections of the light-shielding layer, the first gate metal layer and the second gate metal layer on the base substrate respectively.

[0043] According to some exemplary embodiments, the first semiconductor layer has a first semiconductor portion and a fourth elevated portion directly connected to the first semiconductor portion, the orthographic projection of the bottom of the third via hole close to the base substrate on the base substrate is flush with the orthographic projection of the first semiconductor portion on the base substrate, and the orthographic projection of the bottom of the third via hole close to the base substrate on the base substrate is located within the fourth elevated portion.

[0044] According to some exemplary embodiments, the first functional layer is a third gate metal layer, the second functional layer is a first source / drain metal layer, the insulating layer has a fifth via hole, and the first source / drain metal layer is overlapped with the third gate metal layer through the fifth via hole;

[0045] At least one of the third functional layers is a light shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, and a second semiconductor layer stacked between the base substrate and the third gate metal layer; and

[0046] The orthographic projection of the bottom of the fifth via hole close to the base substrate on the base substrate is located within the orthographic projection of the first gate metal layer on the base substrate, and the orthographic projection of the bottom of the fifth via hole close to the base substrate on the base substrate is spaced from the orthographic projections of the light-shielding layer, the first semiconductor layer, the second gate metal layer, and the second semiconductor layer on the base substrate, respectively.

[0047] According to some exemplary embodiments, the third gate metal layer includes an initial signal line, the first source / drain metal layer is overlapped with the initial signal line through the fifth via hole, and the first gate metal layer includes a scan signal line and a fifth pad directly connected to the scan signal line; and

[0048] The orthographic projection of the bottom of the fifth via hole close to the base substrate on the base substrate partially overlaps with the orthographic projection of the scanning signal line on the base substrate, and the orthographic projection of the bottom of the fifth via hole close to the base substrate on the base substrate is located within the orthographic projection of the scanning signal line and the fifth raised portion on the base substrate.

[0049] According to some exemplary embodiments, the first functional layer is a second source-drain metal layer, the second functional layer is a third source-drain metal layer, the insulating layer has a sixth via hole, and the third source-drain metal layer is overlapped with the second source-drain metal layer through the sixth via hole; and

[0050] The third functional layer is a first source-drain metal layer, and the orthographic projection of the bottom of the sixth via hole close to the base substrate on the base substrate is spaced apart from the orthographic projection of the first source-drain metal layer on the base substrate.

[0051] In another aspect, a display substrate is provided, comprising:

[0052] substrate;

[0053] A first functional layer is located on the substrate;

[0054] an insulating layer, located on a side of the first functional layer away from the substrate, the insulating layer having a via hole;

[0055] a second functional layer, located on a side of the insulating layer away from the first functional layer, the second functional layer overlapping the first functional layer through the via hole;

[0056] At least one third functional layer, wherein the at least one third functional layer is located between the first functional layer and the base substrate, and the orthographic projection of any third functional layer on the base substrate partially overlaps with the orthographic projection of the first functional layer on the base substrate,

[0057] The first functional layer has an overlapping surface exposed by the via hole, and the difference between the maximum reflectivity and the minimum reflectivity of each area on the overlapping surface is less than or equal to 15%.

[0058] In another aspect, a display device is provided, comprising the above-mentioned display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Other objects and advantages of the present disclosure will become apparent from the following description of the present disclosure with reference to the accompanying drawings, which will help to provide a comprehensive understanding of the present disclosure.

[0060] FIG1A schematically shows a plan view of a partial area of ​​a display substrate in the related art.

[0061] FIG. 1B is a schematic cross-sectional view along the section line A1 - A2 in FIG. 1A .

[0062] FIG2A schematically shows a plan view of a partial area of ​​a display substrate in an embodiment of the present disclosure.

[0063] FIG. 2B illustrates a schematic cross-sectional view along the section line B1 - B2 in FIG. 2A .

[0064] FIG3 schematically shows a plan view of a partial film layer stack of a display substrate in an embodiment of the present disclosure.

[0065] FIG. 4 is a schematic diagram showing a partially enlarged structure of the P1 region in FIG. 3 .

[0066] FIG5 is a schematic diagram showing a partially enlarged structure of the P2 region in FIG3 .

[0067] FIG6 is a schematic diagram showing a partially enlarged structure of the P3 region in FIG3 .

[0068] FIG. 7 shows another partially enlarged structural schematic diagram of the P3 region in FIG. 3 .

[0069] FIG8 is a schematic diagram showing a partially enlarged structure of the P4 region in FIG3 .

[0070] FIG9 schematically shows a plan view of a partial film layer stack of another display substrate in an embodiment of the present disclosure.

[0071] FIG10 is a schematic diagram showing a partially enlarged structure of the P5 region in FIG9 .

[0072] FIG11 is a schematic diagram showing a partially enlarged structure of the P2 region in FIG9 .

[0073] FIG12 schematically shows an equivalent circuit diagram of a pixel driving circuit of a display substrate in an embodiment of the present disclosure.

[0074] 13A to 13W are plan views of some film layers in a display substrate located in a display area according to some exemplary embodiments of the present disclosure;

[0075] 13A schematically illustrates a light shielding layer, FIG13B schematically illustrates a first semiconductor layer, FIG13C schematically illustrates a first gate metal layer, FIG13D schematically illustrates a second gate metal layer, FIG13E schematically illustrates a second semiconductor layer, FIG13F schematically illustrates a third gate metal layer, FIG13G schematically illustrates a portion of vias in an interlayer insulating layer, FIG13H schematically illustrates another portion of vias in an interlayer insulating layer, FIG13I schematically illustrates a first source / drain metal layer, FIG13J schematically illustrates a combination of the first source / drain metal layer and a portion of vias in an interlayer insulating layer, FIG13K schematically illustrates a combination of the first source / drain metal layer and another portion of vias in an interlayer insulating layer, and FIG13L schematically illustrates a passivation layer. Figure 13M illustrates a first planarization layer, Figure 13N illustrates a second source-drain metal layer, Figure 13O illustrates a second planarization layer, Figure 13P illustrates a third source-drain metal layer, Figure 13Q illustrates a combination of the first source-drain metal layer, the second source-drain metal layer, the second planarization layer and the third source-drain metal layer, Figure 13R illustrates a third planarization layer, Figure 13S illustrates a fourth planarization layer, Figure 13T illustrates a combination of the second source-drain metal layer, the third source-drain metal layer, the third planarization layer and the fourth planarization layer, Figure 13U illustrates an anode layer, Figure 13V illustrates a pixel defining layer, and Figure 13W illustrates a combination of each film layer from the light-shielding layer to the pixel defining layer.

[0076] It should be noted that, for the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the sizes of layers, structures or regions may be enlarged or reduced, that is, these drawings are not drawn according to the actual scale. DETAILED DESCRIPTION

[0077] In the following description, for the purpose of explanation, many specific details are set forth to provide a comprehensive understanding of the various exemplary embodiments. However, it is apparent that the various exemplary embodiments can be implemented without these specific details or with one or more equivalent arrangements. In other cases, well-known structures and devices are shown in block diagram form to avoid unnecessarily obscuring the various exemplary embodiments. In addition, the various exemplary embodiments can be different, but not necessarily exclusive. For example, the specific shape, configuration, and characteristics of the exemplary embodiment can be used or implemented in another exemplary embodiment without departing from the inventive concept.

[0078] In the accompanying drawings, the sizes and relative sizes of the elements may be exaggerated for clarity and / or descriptive purposes. Thus, the sizes and relative sizes of the individual elements are not necessarily limited to those shown in the drawings. When the exemplary embodiments can be implemented differently, the specific process sequence can be performed differently from the described sequence. For example, two processes described in succession can be performed substantially simultaneously or in an order opposite to the described sequence. In addition, the same reference numerals represent the same elements.

[0079] When an element is described as being "on" another element, "connected to" another element, or "coupled to" another element, the element may be directly on, directly connected to, or directly coupled to another element, or there may be an intermediate element. However, when an element is described as being "directly on" another element, "directly connected to," or "directly coupled to," another element, there is no intermediate element. Other terms and / or expressions used to describe the relationship between elements should be interpreted in a similar manner, for example, "between" versus "directly between," "adjacent" versus "directly adjacent," or "on" versus "directly on," etc. In addition, the term "connected" may refer to a physical connection, an electrical connection, a communication connection, and / or a fluid connection. In addition, the X-axis, the Y-axis, and the Z-axis are not limited to the three axes of a rectangular coordinate system, and may be interpreted in a broader sense. For example, the X-axis, the Y-axis, and the Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XY, YZ, and XZ. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0080] It should be understood that although the terms first, second, etc. may be used herein to describe different elements, these elements should not be limited by these terms. These terms are merely used to distinguish one element from another. For example, a first element may be named a second element, and similarly, a second element may be named a first element without departing from the scope of the exemplary embodiments.

[0081] Fig. 1A schematically shows a plan view of a partial region of a display substrate in the related art. Fig. 1B schematically shows a cross-sectional view along the cutting line A1-A2 in Fig. 1A.

[0082] 1A and 1B , a substrate is shown including a base substrate 100, a first gate metal layer Gate1 located on the base substrate 100, a second insulating layer 300, a third gate metal layer Gate3, a first insulating layer 200, and a first source / drain metal layer SD1. The first insulating layer 200 has a via H, through which the first source / drain metal layer SD1 is electrically connected to the third gate metal layer Gate3. The orthographic projection of the via H on the base substrate 100 partially overlaps with the orthographic projection of the first gate metal layer Gate1 on the base substrate 100. Therefore, the cross-sectional structure of the portion of the third gate metal layer Gate3 exposed by the via H exhibits a stepped shape, wherein a first portion a is raised by the first gate metal layer Gate1, while a second portion b is not. Therefore, the height of the first portion a (which should be understood as the distance from the base substrate 100) is greater than the height of the second portion b.

[0083] The inventors have discovered through research that, in the display substrate, on the one hand, the overlapping area between the first source / drain metal layer SD1 and the third gate metal layer Gate3 at the via H will be reduced, thereby increasing the contact resistance between the first source / drain metal layer SD1 and the third gate metal layer Gate3; on the other hand, since, in the patterning process of the first insulating layer 200, there will be differences in exposure focus and exposure intensity between the upper portion of the first part a and the upper portion of the second part b during the exposure process, the aperture of the formed via H above the first part a is inconsistent with the aperture of the portion above the second part b, that is, the via H is gourd-shaped, which will further make the aperture of the via H more difficult to control during the exposure process, and the aperture deviation of the via H in different sub-pixels is large, which in turn leads to differences in the potential writing of the same node between different sub-pixels, and ultimately leads to poor display uniformity.

[0084] Figure 2A schematically shows a plan view of a partial area of ​​a display substrate in an embodiment of the present disclosure. Figure 2B schematically shows a cross-sectional view along the section line B1-B2 in Figure 2A.

[0085] 2A and 2B , the display substrate includes a base substrate 100, a first functional layer F1 located on the base substrate 100, a first insulating layer 200 located on a side of the first functional layer F1 away from the base substrate 100, and a second functional layer F2 located on a side of the first insulating layer 200 away from the base substrate 100. The insulating layer has a via H, through which the second functional layer F2 is electrically connected to the first functional layer F1 by overlapping.

[0086] The display substrate also includes at least one third functional layer F3 located between the first functional layer F1 and the base substrate 100. The figure shows an example of a third functional layer F3. A second insulating layer 300 is provided between the third functional layer F3 and the first functional layer F1. The orthographic projection of the third functional layer F3 on the base substrate 100 partially overlaps with the orthographic projection of the first functional layer F1 on the base substrate 100.

[0087] The first functional layer F1 has an overlapping surface F11 exposed by the via H. The relative position of the third functional layer F3 and the via H is configured to ensure that the overlapping surface F11 is a flat surface. This ensures that the overlapping area of ​​the second functional layer F2 and the first functional layer F1 at the via H is within the specification range, thereby ensuring that the contact resistance between the second functional layer F2 and the first functional layer F1 at the via H is within the specification range. Furthermore, because the overlapping surface F11 is a flat surface, during the patterning process of the first insulating layer 200, the exposure focus and exposure intensity over different areas of the overlapping surface F11 are approximately the same during the exposure process. Therefore, the aperture of the via H is easily controlled during the exposure process, and the aperture deviation of the via H in different sub-pixels is within the specification range, avoiding the problem of uneven display caused by large aperture deviation of the via H in different sub-pixels.

[0088] It should be noted that due to the influence of factors such as the surface flatness of the base substrate 100 and the uniformity of the film thickness, the overlapping surface F11 cannot be theoretically flat. In order to achieve the above technical effect, the flat surface defined should be understood as the height difference between the highest point (the part farthest from the base substrate 100) and the lowest point (the part closest to the base substrate 100) being less than For example, the height difference is wait.

[0089] It should be noted that the first functional layer F1, the second functional layer F2 and the third functional layer F3 should be understood as other film layers in the display substrate except the insulating film layer having an insulating function, such as a light shielding layer, a gate metal layer, a source / drain metal layer and a semiconductor layer.

[0090] According to some exemplary embodiments, referring to FIG. 2B , the first functional layer F1 has a lapped surface F11 exposed by the via H. The difference between the maximum and minimum reflectivity of various regions on the lapped surface F11 is less than or equal to 15%. For example, the difference between the maximum and minimum reflectivity is 1%, 2%, 3%, 4%, 5%, 6%, 7%, 8%, 9%, or 10%. This prevents problems such as excessive differences in surface reflectivity of the lapped surface F11 during the patterning process of the first insulating layer, which could lead to significant differences in exposure focus and intensity over different regions of the lapped surface F11 during the exposure process.

[0091] According to some exemplary embodiments, referring to Figures 2A and 2B, the orthographic projection of the bottom of the via hole H close to the base substrate 100 on the base substrate 100 is located within the orthographic projection of any third functional layer F3 on the base substrate 100, that is, each third functional layer F3 completely pads the first functional layer F1 at the via hole H, so that the overlapping surface F11 is a flat surface.

[0092] According to some exemplary embodiments, with continued reference to FIG. 2A , the third functional layer F3 includes a functional portion F31 and a raised portion F32 directly connected to the functional portion F31 . The functional portion F31 should be understood as a structure having specific functions such as transmitting specific display signals or optimizing display effects.

[0093] Among them, the orthographic projection of the bottom of the via hole H close to the base substrate 100 on the base substrate 100 overlaps or is flush with the orthographic projection of the functional part F31 on the base substrate 100, that is, the functional part F31 only partially raises the first functional layer F1 at the via hole H. In order to ensure the flatness of the overlapping surface F11, a raising part F32 is further connected to the functional part F31, so that the orthographic projection of the bottom of the via hole H close to the base substrate 100 on the base substrate 100 is located within the orthographic projections of the functional part F31 and the raising part F32 on the base substrate 100, that is, the functional part F31 and the raising part F32 jointly completely raise the first functional layer F1 at the via hole H, so that the overlapping surface F11 is a flat surface.

[0094] According to some exemplary embodiments, referring to FIG. 2A , the distance W extending from the bottom edge of the via hole H to the edge of the raised portion F32 is 0.4 μm-0.6 μm.

[0095] According to some exemplary embodiments, the orthographic projection of the bottom of the via hole near the base substrate on the base substrate does not overlap with the orthographic projection of each third functional layer on the base substrate. In other words, each third functional layer is arranged to avoid the via hole, thereby ensuring a flat overlapping surface.

[0096] According to some exemplary embodiments, the at least one third functional layer includes at least one metal functional layer, and the orthographic projection of the bottom of the via hole near the base substrate on the base substrate is spaced apart from the orthographic projections of each metal functional layer on the base substrate. Specifically, when the third functional layer is a metal functional layer, the film thickness is typically relatively thick. Therefore, to ensure the flatness of the overlapping surface, the orthographic projection of the bottom of the via hole near the base substrate on the base substrate and the orthographic projection of the metal functional layer on the base substrate need to be separated by a certain distance, for example, a distance greater than or equal to 0.4 μm.

[0097] According to some exemplary embodiments, the at least one third functional layer includes at least one semiconductor functional layer, and the orthographic projection of the bottom of the via hole near the substrate on the substrate is spaced apart from the orthographic projection of the semiconductor functional layer on the substrate, and / or the orthographic projection of the bottom of the via hole near the substrate on the substrate is flush with the orthographic projection of the semiconductor functional layer on the substrate. That is, when the third functional layer is a semiconductor functional layer, the film thickness is typically relatively thin. Based on specific process requirements, the orthographic projection of the bottom of the via hole near the substrate on the substrate and the orthographic projection of the semiconductor functional layer on the substrate can be spaced apart or flush with each other. When these projections are flush, this helps reduce the area occupied by sub-pixels, thereby improving display resolution.

[0098] It should be noted that, in the embodiments of the present disclosure, the orthographic projection of structure A on the substrate and the orthographic projection of structure B on the substrate are spaced apart, which should be understood as the orthographic projection of structure A on the substrate and the orthographic projection of structure B on the substrate do not overlap at all and there is a certain gap. The orthographic projection of structure A on the substrate and the orthographic projection of structure B on the substrate are flush, which should be understood as the orthographic projection of structure A on the substrate and the orthographic projection of structure B on the substrate do not overlap, and a portion of the edge of the orthographic projection of structure A on the substrate coincides with a portion of the edge of the orthographic projection of structure B on the substrate.

[0099] According to some exemplary embodiments, the multi-layer third functional layer includes at least one first sub-layer and at least one second sub-layer, wherein the orthographic projection of the bottom of the via hole near the substrate substrate on the substrate substrate does not overlap with the orthographic projection of each first sub-layer on the substrate substrate; and the orthographic projection of the bottom of the via hole near the substrate substrate on the substrate substrate is located within the orthographic projection of any second sub-layer on the substrate substrate. In other words, when there are multiple third functional layers, according to specific process requirements, a portion of the third functional layer can be arranged to avoid the via hole, while another portion of the third functional layer can be arranged to completely support the first functional layer at the via hole, thereby achieving a flat overlapping surface.

[0100] FIG3 schematically shows a plan view of a partial film layer stack of a display substrate in an embodiment of the present disclosure.

[0101] According to some exemplary embodiments, referring to FIG3 , a display substrate includes a base substrate, a light shielding layer (BSM) located on the base substrate, a buffer layer located on a side of the light shielding layer (BSM) away from the base substrate, a first semiconductor layer (Poly) located on a side of the buffer layer (Poly) away from the base substrate, a first gate insulating layer located on a side of the first semiconductor layer (Poly) away from the base substrate, a first gate metal layer (Gate1) located on a side of the first gate insulating layer (Gate1) away from the base substrate, a second gate insulating layer (Gate2) located on a side of the second gate insulating layer (Gate2) away from the base substrate, a third gate insulating layer (IGZO) located on a side of the third gate insulating layer (Gate2) away from the base substrate, a second semiconductor layer (IGZO) located on a side of the second semiconductor layer (IGZO) away from the base substrate, a third gate metal layer (Gate3) located on a side of the fourth gate insulating layer (Gate3) away from the base substrate, an interlayer insulating layer (Interlayer Insulator) located on a side of the third gate metal layer (Gate3) away from the base substrate, and a first source / drain metal layer (Source / Drain) located on a side of the interlayer insulating layer (Interlayer Insulator) away from the base substrate. FIG3 exemplarily illustrates some of the aforementioned film layers.

[0102] FIG. 4 is a schematic diagram showing a partially enlarged structure of the P1 region in FIG. 3 .

[0103] According to some exemplary embodiments, in combination with FIG3 and FIG4 , the first functional layer F1 is the second semiconductor layer IGZO, the second functional layer is the first source-drain metal layer, the insulating layer between the second semiconductor layer IGZO and the first source-drain metal layer is a fourth gate insulating layer and an interlayer insulating layer, the fourth gate insulating layer and the interlayer insulating layer have fourth vias H04, the first source-drain metal layer is overlapped with the second semiconductor layer IGZO through the fourth vias H04, and the first source-drain metal layer is omitted in the figure for the convenience of clearly showing the fourth vias H04.

[0104] When the first functional layer F1 is the second semiconductor layer IGZO, the at least one third functional layer F3 is a light shielding layer BSM, a first semiconductor layer Poly, a first gate metal layer Gate1, and a second gate metal layer Gate2, stacked between the base substrate 100 and the second semiconductor layer. The orthographic projection of the bottom of the fourth via hole H04 near the base substrate 100 on the base substrate 100 is located within the orthographic projections of the light shielding layer BSM and the first gate metal layer Gate1 on the base substrate 100, respectively. The orthographic projection of the bottom of the fourth via hole H04 near the base substrate 100 on the base substrate 100 is spaced apart from the orthographic projections of the first semiconductor layer Poly and the second gate metal layer Gate2 on the base substrate 100, respectively. In other words, the orthographic projection of the bottom of the fourth via hole H04 near the base substrate 100 on the base substrate 100 is spaced apart from the orthographic projection of a portion of the third functional layer F3 on the base substrate 100 and is located within the orthographic projection of the remaining portion of the third functional layer F3 on the base substrate 100.

[0105] According to some exemplary embodiments, referring to FIG4 , the light shielding layer BSM includes a light shielding portion connecting trace 11 and a second raised portion F312 directly connected to the light shielding portion connecting trace 11, and the first gate metal layer Gate1 includes a scan signal line S and a third raised portion F313 directly connected to the scan signal line S. The orthographic projection of the bottom of the fourth via hole H04 near the base substrate 100 on the base substrate 100 partially overlaps with the orthographic projection of the light shielding portion connecting trace 11 on the base substrate 100, and the orthographic projection of the bottom of the fourth via hole H04 near the base substrate 100 on the base substrate 100 is located within the orthographic projection of the light shielding portion connecting trace 11 and the second raised portion F312 on the base substrate 100.

[0106] The orthographic projection of the bottom of the fourth via hole H04 near the base substrate 100 on the base substrate 100 partially overlaps with the orthographic projection of the scan signal line S on the base substrate 100. The orthographic projection of the bottom of the fourth via hole H04 near the base substrate 100 on the base substrate 100 is located within the orthographic projection of the scan signal line S and the third raised portion F313 on the base substrate 100. Furthermore, the first gate metal layer Gate1 is located on the side of the light shielding layer BSM away from the base substrate 100. The orthographic projection of the third raised portion F313 on the base substrate 100 is located within the orthographic projection of the light shielding portion connecting trace 11 and the second raised portion F312 on the base substrate 100.

[0107] FIG5 is a schematic diagram showing a partially enlarged structure of the P2 region in FIG3 .

[0108] According to some exemplary embodiments, in combination with reference to FIG3 and FIG5 , the first functional layer F1 is the second semiconductor layer IGZO, the second functional layer is the first source-drain metal layer, the insulating layer between the second semiconductor layer IGZO and the first source-drain metal layer is the fourth gate insulating layer and the interlayer insulating layer, the fourth gate insulating layer and the interlayer insulating layer have a third via H03, the first source-drain metal layer is overlapped with the second semiconductor layer IGZO through the third via H03, and the first source-drain metal layer is omitted in the figure for the convenience of clearly showing the third via.

[0109] When the first functional layer F1 is the second semiconductor layer IGZO, the at least one third functional layer F3 is a light shielding layer BSM, a first semiconductor layer Poly, a first gate metal layer Gate1 and a second gate metal layer Gate2 stacked between the base substrate 100 and the second semiconductor layer IGZO.

[0110] The orthographic projection of the bottom of the third via hole H03 near the base substrate 100 on the base substrate 100 is flush with the orthographic projection of the first semiconductor layer Poly on the base substrate 100. The orthographic projection of the bottom of the third via hole H03 near the base substrate 100 on the base substrate 100 is spaced apart from the orthographic projections of the light shielding layer BSM, the first gate metal layer Gate1, and the second gate metal layer Gate2 on the base substrate 100. In other words, the orthographic projection of the bottom of the fourth via hole H04 near the base substrate 100 on the base substrate 100 is flush with the orthographic projection of a portion of the third functional layer F3 on the base substrate 100, and is spaced apart from the orthographic projection of the remaining portion of the third functional layer F3 on the base substrate 100.

[0111] FIG6 is a schematic diagram showing a partially enlarged structure of the P3 region in FIG3 .

[0112] According to some exemplary embodiments, with reference to FIG3 and FIG6 , the first functional layer F1 is the third gate metal layer Gate3, the second functional layer is the first source-drain metal layer, the insulating layer between the third gate metal layer Gate3 and the first source-drain metal layer is an interlayer insulating layer, the interlayer insulating layer has a second via H02, the first source-drain metal layer is overlapped with the third gate metal layer Gate3 through the second via H02, and the first source-drain metal layer is omitted in the figure for the convenience of clearly showing the second via H02.

[0113] When the first functional layer F1 is the third gate metal layer Gate3, at least one third functional layer F3 is a light shielding layer BSM, a first semiconductor layer Poly, a first gate metal layer Gate1, a second gate metal layer Gate2 and a second semiconductor layer IGZO stacked between the base substrate 100 and the third gate metal layer Gate3.

[0114] The orthographic projection of the bottom of the second via hole H02 near the base substrate 100 on the base substrate 100 is spaced apart from the orthographic projections of the light shielding layer BSM, the first semiconductor layer Poly, the first gate metal layer Gate1, the second gate metal layer Gate2, and the second semiconductor layer IGZO on the base substrate 100. That is, the orthographic projection of the bottom of the second via hole H02 near the base substrate 100 on the base substrate 100 is spaced apart from the orthographic projections of each third functional layer F3 on the base substrate 100.

[0115] FIG. 7 shows a schematic diagram of a partially enlarged structure of the P3 region in FIG. 3 .

[0116] According to some exemplary embodiments, with reference to FIG3 and FIG7 , the first functional layer F1 is the third gate metal layer Gate3, the second functional layer is the first source-drain metal layer, the insulating layer between the third gate metal layer Gate3 and the first source-drain metal layer is an interlayer insulating layer, the interlayer insulating layer has a second via H02, the first source-drain metal layer is overlapped with the third gate metal layer Gate3 through the second via H02, and the first source-drain metal layer is omitted in the figure for the convenience of clearly showing the second via H02.

[0117] When the first functional layer F1 is the third gate metal layer Gate3, at least one third functional layer F3 is a light shielding layer BSM, a first semiconductor layer Poly, a first gate metal layer Gate1, a second gate metal layer Gate2 and a second semiconductor layer IGZO stacked between the base substrate 100 and the third gate metal layer Gate3.

[0118] The orthographic projection of the bottom of the second via hole H02 near the base substrate 100 on the base substrate 100 is located within the orthographic projection of the first gate metal layer Gate1 on the base substrate 100. The orthographic projection of the bottom of the second via hole H02 near the base substrate 100 on the base substrate 100 is spaced apart from the orthographic projection of the light shielding layer BSM, the first semiconductor layer Poly, the second gate metal layer Gate2, and the second semiconductor layer IGZO on the base substrate 100. In other words, the orthographic projection of the bottom of the second via hole H02 near the base substrate 100 on the base substrate 100 is spaced apart from the orthographic projection of a portion of the third functional layer F3 on the base substrate 100 and is located within the orthographic projection of the remaining portion of the third functional layer F3 on the base substrate 100.

[0119] According to some exemplary embodiments, referring to FIG. 7 , the third gate metal layer Gate3 includes an initial signal grid line connection portion 51, the first source / drain metal layer overlaps the initial signal grid line connection portion 51 through a second via H02, and the first gate metal layer Gate1 includes a scan signal line S and a sixth raised portion F316 directly connected to the scan signal line S. The orthographic projection of the bottom of the second via H02 near the base substrate 100 on the base substrate 100 partially overlaps with the orthographic projection of the scan signal line on the base substrate 100, and the orthographic projection of the bottom of the second via H02 near the base substrate 100 on the base substrate 100 is located within the orthographic projection of the scan signal line S and the sixth raised portion F316 on the base substrate 100.

[0120] FIG8 is a schematic diagram showing a partially enlarged structure of the P4 region in FIG3 .

[0121] According to some exemplary embodiments, with reference to FIG3 and FIG8 , the first functional layer F1 is the third gate metal layer Gate3, the second functional layer is the first source-drain metal layer, the insulating layer between the third gate metal layer Gate3 and the first source-drain metal layer is an interlayer insulating layer, the interlayer insulating layer has a fifth via H05, the first source-drain metal layer is overlapped with the third gate metal layer Gate3 through the fifth via H05, and the first source-drain metal layer is omitted in the figure for the convenience of clearly showing the fifth via H05.

[0122] When the first functional layer F1 is the third gate metal layer Gate3, at least one third functional layer F3 is a light shielding layer BSM, a first semiconductor layer Poly, a first gate metal layer Gate1, a second gate metal layer Gate2 and a second semiconductor layer IGZO stacked between the base substrate 100 and the third gate metal layer Gate3.

[0123] The orthographic projection of the bottom of the fifth via hole H05 near the base substrate 100 on the base substrate 100 is located within the orthographic projection of the first gate metal layer Gate1 on the base substrate 100. The orthographic projection of the bottom of the fifth via hole H05 near the base substrate 100 on the base substrate 100 is spaced apart from the orthographic projections of the light shielding layer BSM, the first semiconductor layer Poly, the second gate metal layer Gate2, and the second semiconductor layer IGZO on the base substrate 100. In other words, the orthographic projection of the bottom of the fifth via hole H05 near the base substrate 100 on the base substrate 100 is spaced apart from the orthographic projection of a portion of the third functional layer F3 on the base substrate 100 and is located within the orthographic projection of the remaining portion of the third functional layer F3 on the base substrate 100.

[0124] According to some exemplary embodiments, referring to FIG8 , the third gate metal layer Gate3 includes an initial signal line INIT, the first source / drain metal layer overlaps the initial signal line INIT via a fifth via H05, and the first gate metal layer Gate1 includes a scan signal line and a fifth raised portion F315 directly connected to the scan signal line. The orthographic projection of the bottom of the fifth via H05 near the base substrate 100 on the base substrate 100 partially overlaps with the orthographic projection of the scan signal line on the base substrate 100, and the orthographic projection of the bottom of the fifth via H05 near the base substrate 100 on the base substrate 100 is located within the orthographic projection of the scan signal line and the fifth raised portion F315 on the base substrate 100.

[0125] FIG9 schematically shows a plan view of a partial film layer stack of another display substrate in an embodiment of the present disclosure.

[0126] According to some exemplary embodiments, referring to FIG9 , a display substrate includes a base substrate, a light shielding layer (BSM) located on the base substrate, a buffer layer located on a side of the light shielding layer (BSM) away from the base substrate, a first semiconductor layer (Poly) located on a side of the buffer layer (Poly) away from the base substrate, a first gate insulating layer located on a side of the first semiconductor layer (Poly) away from the base substrate, a first gate metal layer (Gate1) located on a side of the first gate insulating layer (Gate1) away from the base substrate, a second gate insulating layer (Gate2) located on a side of the second gate insulating layer (Gate2) away from the base substrate, a third gate insulating layer (IGZO) located on a side of the third gate insulating layer (Gate2) away from the base substrate, a second semiconductor layer (IGZO) located on a side of the second semiconductor layer (IGZO) away from the base substrate, a third gate metal layer (Gate3) located on a side of the fourth gate insulating layer (Gate3) away from the base substrate, an interlayer insulating layer (Interlayer Insulator) located on a side of the third gate metal layer (Gate3) away from the base substrate, and a first source / drain metal layer (Interlayer Insulator) located on a side of the interlayer insulating layer (Interlayer Insulator) away from the base substrate. FIG9 exemplarily illustrates some of the aforementioned film layers.

[0127] FIG10 is a schematic diagram showing a partially enlarged structure of the P5 region in FIG9 .

[0128] According to some exemplary embodiments, with reference to FIG10 in conjunction with FIG9 , the first functional layer F1 is a first semiconductor layer (Poly), the second functional layer is a first source / drain metal layer, the insulating layers between the first semiconductor layer (Poly) and the first source / drain metal layer are a first gate insulating layer, a second gate insulating layer, a third gate insulating layer, a fourth gate insulating layer, and an interlayer insulating layer, the first gate insulating layer, the second gate insulating layer, the third gate insulating layer, the fourth gate insulating layer, and the interlayer insulating layer having a first via H01, and the first source / drain metal layer overlaps the first semiconductor layer (Poly) through the first via H01. To clearly illustrate the first via H01, the first source / drain metal layer is omitted in the figure.

[0129] When the first functional layer F1 is the first semiconductor layer Poly, and the third functional layer F3 is merely the light-shielding layer BSM, the orthographic projection of the bottom of the first via hole H01 close to the base substrate 100 on the base substrate 100 is located within the orthographic projection of the light-shielding layer BSM on the base substrate 100. That is, the orthographic projection of the bottom of the first via hole H01 close to the base substrate 100 on the base substrate 100 is located within the orthographic projection of each third functional layer F3 on the base substrate 100.

[0130] According to some exemplary embodiments, referring to Figure 9, the light-shielding layer BSM includes a light-shielding portion connecting trace 11 and a first raised portion F311 directly connected to the light-shielding portion connecting trace, the orthographic projection of the bottom of the first via hole H01 close to the base substrate 100 on the base substrate 100 partially overlaps with the orthographic projection of the light-shielding portion connecting trace on the base substrate 100, and the orthographic projection of the bottom of the first via hole H01 close to the base substrate 100 on the base substrate 100 is located within the orthographic projection of the light-shielding portion connecting trace 11 and the first raised portion F311 on the base substrate 100.

[0131] FIG11 is a schematic diagram showing a partially enlarged structure of the P2 region in FIG9 .

[0132] According to some exemplary embodiments, in combination with reference to FIG11 and FIG9 , the first functional layer F1 is the second semiconductor layer IGZO, the second functional layer is the first source-drain metal layer, the insulating layer between the second semiconductor layer IGZO and the first source-drain metal layer is the fourth gate insulating layer and the interlayer insulating layer, the fourth gate insulating layer and the interlayer insulating layer have a third via H03, the first source-drain metal layer is overlapped with the second semiconductor layer IGZO through the third via H03, and the first source-drain metal layer is omitted in the figure for the convenience of clearly showing the third via H03.

[0133] When the first functional layer F1 is the second semiconductor layer IGZO, the at least one third functional layer F3 is a light shielding layer BSM, a first semiconductor layer Poly, a first gate metal layer Gate1 and a second gate metal layer Gate2 stacked between the base substrate 100 and the second semiconductor layer IGZO.

[0134] The orthographic projection of the bottom of the third via hole H03 near the base substrate 100 on the base substrate 100 is located within the orthographic projection of the first semiconductor layer Poly on the base substrate 100. The orthographic projection of the bottom of the third via hole H03 near the base substrate 100 on the base substrate 100 is spaced apart from the orthographic projection of the light shielding layer BSM, the first gate metal layer Gate1, and the second gate metal layer Gate2 on the base substrate 100. In other words, the orthographic projection of the bottom of the third via hole H03 near the base substrate 100 on the base substrate 100 is spaced apart from the orthographic projection of a portion of the third functional layer F3 on the base substrate 100 and is located within the orthographic projection of the remaining portion of the third functional layer F3 on the base substrate 100.

[0135] According to some exemplary embodiments, referring to FIG11 , the first semiconductor layer Poly has a first semiconductor portion and a fourth elevated portion F314 directly connected to the first semiconductor portion, the orthographic projection of the bottom of the third via hole H03 close to the base substrate 100 on the base substrate 100 is flush with the orthographic projection of the first semiconductor portion on the base substrate 100, and the orthographic projection of the bottom of the third via hole H03 close to the base substrate 100 on the base substrate 100 is located within the fourth elevated portion F314.

[0136] FIG12 schematically shows an equivalent circuit diagram of a pixel driving circuit of a display substrate in an embodiment of the present disclosure.

[0137] According to some exemplary embodiments, the pixel driving circuit may have a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. As shown in FIG12 , the pixel driving circuit may include eight transistors (a first transistor T1 to an eighth transistor T8) and a storage capacitor C. The pixel driving circuit is electrically connected to ten signal lines (a first scan signal line S1, a second scan signal line S2, a third scan signal line S3, a fourth scan signal line S4, a fifth scan signal line S5, a first initial signal line INIT1, a second initial signal line INIT2, a third initial signal line INIT3, a data signal line DATA, and a first power line VDD).

[0138] According to some exemplary embodiments, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is electrically connected to the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first plate of the storage capacitor C, respectively; the second node N2 is electrically connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5, and the second electrode of the eighth transistor T8, respectively; the third node N3 is electrically connected to the second electrode of the first transistor T1, the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6, respectively; the fourth node N4 is electrically connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, respectively; and the fourth node N4 is also electrically connected to the anode of the light emitting device EL.

[0139] According to some exemplary embodiments, a first plate of the storage capacitor C is electrically connected to the first node N1 , and a second plate of the storage capacitor C is electrically connected to the first power line VDD.

[0140] According to some exemplary embodiments, the first transistor T1 may be referred to as a first initialization transistor, wherein a gate electrode of the first transistor T1 is electrically connected to the fourth scan signal line S4, a first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1, and a second electrode of the first transistor T1 is electrically connected to the third node N3. The second transistor T2 may be referred to as a compensation transistor, wherein a gate electrode of the second transistor T2 is electrically connected to the fifth scan signal line S5, a first electrode of the second transistor T2 is electrically connected to the first node N1, and a second electrode of the second transistor T2 is electrically connected to the third node N3. The third transistor T3 may be referred to as a driving transistor, wherein a gate electrode of the third transistor T3 is electrically connected to the first node N1, that is, the gate electrode of the third transistor T3 is electrically connected to the first plate of the storage capacitor C, a first electrode of the third transistor T3 is electrically connected to the second node N2, and a second electrode of the third transistor T3 is electrically connected to the third node N3. The fourth transistor T4 may be referred to as a data write transistor, wherein a gate electrode of the fourth transistor T4 is electrically connected to the first scan signal line S1, a first electrode of the fourth transistor T4 is electrically connected to the data signal line DATA, and a second electrode of the fourth transistor T4 is electrically connected to the second node N2. The fifth transistor T5 can be referred to as a first emission control transistor. A gate electrode of the fifth transistor T5 is electrically connected to the second scan signal line S2, a first electrode of the fifth transistor T5 is electrically connected to the first power supply line VDD, and a second electrode of the fifth transistor T5 is electrically connected to the second node N2. The sixth transistor T6 can be referred to as a second emission control transistor. A gate electrode of the sixth transistor T6 is electrically connected to the second scan signal line S2, a first electrode of the sixth transistor T6 is electrically connected to the third node N3, and a second electrode of the sixth transistor T6 is electrically connected to the fourth node N4. The seventh transistor T7 can be referred to as a second initialization transistor. A gate electrode of the seventh transistor T7 is electrically connected to the third scan signal line S3, a first electrode of the seventh transistor T7 is electrically connected to the second initialization signal line INIT2, and a second electrode of the seventh transistor T7 is electrically connected to the fourth node N4. The eighth transistor T8 can be referred to as a third initialization transistor. A gate electrode of the eighth transistor T8 is electrically connected to the third scan signal line S3, a first electrode of the eighth transistor T8 is electrically connected to the third initialization signal line INIT3, and a second electrode of the eighth transistor T8 is electrically connected to the second node N2.

[0141] According to some exemplary embodiments, the light-emitting device EL can be an OLED, including a stacked anode layer (first pole), an organic light-emitting layer and a cathode layer (second pole), or can be a QLED, including a stacked anode layer (first pole), a quantum dot light-emitting layer and a cathode layer (second pole).

[0142] According to some exemplary embodiments, the first electrode of the light-emitting device EL is electrically connected to the fourth node N4, the second electrode of the light-emitting device EL is electrically connected to the second power line VSS, the signal of the second power line VSS is a continuously provided low-level signal, and the signal of the first power line VDD is a continuously provided high-level signal.

[0143] According to some exemplary embodiments, the first transistor T1 to the eighth transistor T8 may be a P-type transistor or an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the difficulty of the display substrate process, and improve the product yield. In some possible implementations, the first transistor T1 to the eighth transistor T8 may include a P-type transistor and an N-type transistor.

[0144] In an exemplary embodiment, the first transistor T1 to the eighth transistor T8 may be low-temperature polysilicon transistors, or oxide transistors, or both low-temperature polysilicon transistors and metal oxide transistors. The active layer of the low-temperature polysilicon transistor is made of low-temperature polysilicon (LTPS), while the active layer of the metal oxide transistor is made of metal oxide semiconductor (Oxide). Low-temperature polysilicon transistors have advantages such as high mobility and fast charging, while oxide transistors have advantages such as low leakage current. Integrating low-temperature polysilicon transistors and metal oxide transistors on a display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate can leverage the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0145] According to some exemplary embodiments, the second transistor T2 may be a metal oxide transistor, and the first transistor T1 and the third transistor T3 to the eighth transistor T8 may be low-temperature polysilicon transistors.

[0146] 13A to 13W are plan views of some film layers in a display substrate located in a display area according to some exemplary embodiments of the present disclosure;

[0147] 13A schematically illustrates a light shielding layer, FIG13B schematically illustrates a first semiconductor layer, FIG13C schematically illustrates a first gate metal layer, FIG13D schematically illustrates a second gate metal layer, FIG13E schematically illustrates a second semiconductor layer, FIG13F schematically illustrates a third gate metal layer, FIG13G schematically illustrates a portion of vias in an interlayer insulating layer, FIG13H schematically illustrates another portion of vias in an interlayer insulating layer, FIG13I schematically illustrates a first source / drain metal layer, FIG13J schematically illustrates a combination of the first source / drain metal layer and a portion of vias in an interlayer insulating layer, FIG13K schematically illustrates a combination of the first source / drain metal layer and another portion of vias in an interlayer insulating layer, and FIG13L schematically illustrates a passivation layer. Figure 13M illustrates a first planarization layer, Figure 13N illustrates a second source-drain metal layer, Figure 13O illustrates a second planarization layer, Figure 13P illustrates a third source-drain metal layer, Figure 13Q illustrates a combination of the first source-drain metal layer, the second source-drain metal layer, the second planarization layer and the third source-drain metal layer, Figure 13R illustrates a third planarization layer, Figure 13S illustrates a fourth planarization layer, Figure 13T illustrates a combination of the second source-drain metal layer, the third source-drain metal layer, the third planarization layer and the fourth planarization layer, Figure 13U illustrates an anode layer, Figure 13V illustrates a pixel defining layer, and Figure 13W illustrates a combination of each film layer from the light-shielding layer to the pixel defining layer.

[0148] According to some exemplary embodiments, referring to Figures 13A to 13W, the display substrate may include a base substrate, a light-shielding layer BSM located on the base substrate, a buffer layer located on a side of the light-shielding layer BSM away from the base substrate, a first semiconductor layer Poly located on a side of the buffer layer away from the base substrate, a first gate insulating layer located on a side of the first semiconductor layer Poly away from the base substrate, a first gate metal layer Gate1 located on a side of the first gate insulating layer away from the base substrate, a second gate insulating layer located on a side of the first gate metal layer Gate1 away from the base substrate, a second gate metal layer Gate2 located on a side of the second gate insulating layer away from the base substrate, a third gate insulating layer located on a side of the second gate metal layer Gate2 away from the base substrate, a second semiconductor layer IGZO located on a side of the third gate insulating layer away from the base substrate, a fourth gate insulating layer located on a side of the second semiconductor layer IGZO away from the base substrate, a third gate metal layer Gate3 located on a side of the fourth gate insulating layer away from the base substrate, and a Interlayer insulating layer ILD, first source-drain metal layer SD1 located on the side of the interlayer insulating layer ILD away from the substrate, passivation layer PVX located on the side of the first source-drain metal layer SD1 away from the substrate, first planarization layer PLN1 located on the side of the passivation layer PVX away from the substrate, second source-drain metal layer SD2 located on the side of the first planarization layer PLN1 away from the substrate, second planarization layer PLN2 located on the side of the second source-drain metal layer SD2 away from the substrate, third source-drain metal layer SD3 located on the side of the second planarization layer PLN2 away from the substrate, third planarization layer PLN3 located on the side of the third source-drain metal layer SD3 away from the substrate, fourth planarization layer PLN4 located on the side of the third planarization layer PLN3 away from the substrate, anode layer ANE located on the side of the fourth planarization layer PLN4 away from the substrate, pixel defining layer PDL located on the side of the anode layer ANE away from the substrate, light-emitting layer located on the side of the pixel defining layer PDL away from the substrate, cathode layer located on the side of the light-emitting layer away from the substrate.

[0149] In an exemplary embodiment, referring to Figure 13A, the light shielding layer BSM may include at least a light shielding portion 12 and a light shielding portion connecting trace 11, and the light shielding portion connecting trace 11 may include a first light shielding portion connecting trace 111, a second light shielding portion connecting trace 112 and a third light shielding portion connecting trace 113.

[0150] In an exemplary embodiment, the light shielding portion 12 may be rectangular in shape, and the corners of the rectangle may be chamfered. The first light shielding portion connecting trace 111 may be a straight line extending along the first direction X. The first light shielding portion connecting trace 111 may be arranged on one side of the light shielding portion 12 in the first direction X and connected to the light shielding portion 12. The second light shielding portion connecting trace 112 may be a zigzag line extending along the second direction Y. The second light shielding portion connecting trace 112 may be arranged on one side of the light shielding portion 12 in the second direction Y and connected to the light shielding portion 12. The third light shielding portion connecting trace 113 may be a zigzag line extending along the second direction Y. The third light shielding portion connecting trace 113 may be arranged on a side of the light shielding portion 12 opposite to the second direction Y and connected to the light shielding portion 12.

[0151] In an exemplary embodiment, the first shading portion connecting trace 111 of each circuit unit is connected to the shading portion 12 of the adjacent circuit unit in the first direction X, so that the shading layers in a unit row are connected as a whole to form an interconnected integrated structure.

[0152] In an exemplary embodiment, the second light-shielding portion connecting trace 112 of each circuit unit is connected to the third light-shielding portion connecting trace 113 of the circuit unit adjacent in the second direction Y, so that the second light-shielding portion connecting trace 112, the third light-shielding portion connecting trace 113 and the light-shielding portion 12 in a unit column are connected into one, forming an interconnected integrated structure.

[0153] In an exemplary embodiment, the light shielding layer BSM further includes a second raised portion F312 , and the second raised portion F312 is connected to the third light shielding portion connecting trace 113 .

[0154] In an exemplary embodiment, referring to Figure 13B, the first semiconductor layer Poly may include at least a first active portion of a first transistor T1, a third active portion of a third transistor T3, a fourth active portion of a fourth transistor T4, a fifth active portion of a fifth transistor T5, a sixth active portion of a sixth transistor T6, a seventh active portion of a seventh transistor T7, and an eighth active portion of an eighth transistor T8, and the third to seventh active portions are an integral structure connected to each other, and the first active portion and the eighth active portion are separately provided.

[0155] The active portion of each transistor includes a channel portion and first and second electrodes located on either side of the channel portion. The first semiconductor layer Poly includes a first channel portion 21, a first electrode 21S, and a second electrode 21D of the first transistor T1; a third channel portion 23, a first electrode 23S, and a second electrode 23D of the third transistor T3; a fourth channel portion 24, a first electrode 24S, and a second electrode 24D of the fourth transistor T4; a fifth channel portion 25, a first electrode 25S, and a second electrode 25D of the fifth transistor T5; a sixth channel portion 26, a first electrode 26S, and a second electrode 26D of the sixth transistor T6; a fifth channel portion 27, a first electrode 27S, and a second electrode 27D of the seventh transistor T7; and an eighth channel portion 28, a first electrode 28S, and a second electrode 28D of the eighth transistor T8.

[0156] In an exemplary embodiment, a first electrode 23S of the third transistor T3, a second electrode 24D of the fourth transistor T4, and a second electrode 25D of the fifth transistor T5 are all connected to the second node N2. A second electrode 23D of the third transistor T3 and a first electrode 26S of the sixth transistor T6 are all connected to the third node N3. A second electrode 26D of the sixth transistor T6 and a second electrode 27D of the seventh transistor T7 are all connected to the fourth node N4.

[0157] In an exemplary embodiment, referring to FIG. 13A and FIG. 13B , the orthographic projection of the third channel portion 23 of the third transistor T3 on the substrate is located within the orthographic projection of the light shielding portion 12 on the substrate, and the light shielding portion 12 can reduce the influence of light on the characteristics of the third transistor T3.

[0158] In an exemplary embodiment, the material of the first semiconductor layer Poly may be low-temperature polysilicon, that is, the first transistor and the third transistor to the eighth transistor are low-temperature polysilicon thin film transistors.

[0159] It should be noted that the first and second electrodes of each of the above-mentioned transistors can be symmetrical in structure, so the first electrode and the second electrode can be physically indistinguishable. In the embodiments of the present disclosure, in order to distinguish transistors, except for the gate electrode serving as the control electrode, one electrode is directly described as the first electrode and the other electrode is the second electrode. Therefore, the first and second electrodes of all or some of the transistors in the embodiments of the present disclosure can be interchanged as needed. For example, the first electrode is the source electrode and the second electrode is the drain electrode.

[0160] In an exemplary embodiment, referring to FIG. 13C , the first gate metal layer Gate1 includes at least a first scan signal line S1 , a second scan signal line S2 , a third scan signal line S3 , a fourth scan signal line S4 and a first conductive portion 31 .

[0161] In an exemplary embodiment, the first conductive portion 31 may be rectangular, with chamfered corners. The orthographic projection of the first conductive portion 31 on the substrate at least partially overlaps the orthographic projection of the third active layer of the third transistor T3 on the substrate. For example, the first conductive portion 31 may serve as both the first plate of the storage capacitor and the gate electrode of the third transistor T3.

[0162] In an exemplary embodiment, the shape of the first scan signal line S1 can be a zigzag shape with the main portion extending along the first direction X. Referring to Figure 13B, the area where the first scan signal line S1 overlaps with the fourth channel portion 24 of the fourth transistor T4 can serve as the gate electrode of the fourth transistor T4.

[0163] In an exemplary embodiment, the shape of the second scan signal line S2 can be a zigzag shape with the main portion extending along the first direction X. Referring to Figure 13B, the area where the second scan signal line S2 overlaps with the fifth channel portion 25 of the fifth transistor T5 can serve as the gate electrode of the fifth transistor T5, and the area where the second scan signal line S2 overlaps with the sixth channel portion 26 of the sixth transistor T6 can serve as the gate electrode of the sixth transistor T6.

[0164] In an exemplary embodiment, the shape of the third scan signal line S3 can be a zigzag shape with the main portion extending along the first direction X. Referring to Figure 13B, the area where the third scan signal line S3 overlaps with the seventh channel portion 27 of the seventh transistor T7 can serve as the gate electrode of the seventh transistor T7, and the area where the third scan signal line S3 overlaps with the eighth channel portion 28 of the eighth transistor T8 can serve as the gate electrode of the eighth transistor T8.

[0165] In an exemplary embodiment, the fourth scan signal line S4 may be shaped like a zigzag line with its main portion extending along the first direction X. The region where the fourth scan signal line S4 overlaps with the first channel portion 21 of the first transistor T1 may serve as the gate electrode of the first transistor T1.

[0166] In an exemplary embodiment, the first gate metal layer Gate1 may further include a third padding portion F313 and a fifth padding portion F315. The third padding portion F313 is connected to the first scan signal line S1. The fifth padding portion F315 includes a first fifth padding portion F3151 connected to the second scan signal line S2, a second fifth padding portion F3152 connected to the third scan signal line S3, and a third fifth padding portion F3153 connected to the fourth scan signal line S4.

[0167] In an exemplary embodiment, the first scanning signal line S1, the third scanning signal line S3, the fourth scanning signal line S4 and the second scanning signal line S2 can be designed with non-equal widths, and the width is the dimension in the second direction Y, which not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the signal lines. The present disclosure does not limit this.

[0168] In an exemplary embodiment, after forming the first gate metal layer Gate1, the first gate metal layer Gate1 can be used as a shield to perform conductorization on the first semiconductor layer. The portion of the first semiconductor layer in the area shielded by the first gate metal layer Gate1 forms the channel portion of the first transistor T1 and the third transistor T3 to the eighth transistor T8, and the portion of the first semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first electrode and the second electrode of the first transistor T1 and the third transistor T3 to the eighth transistor T8 are formed.

[0169] In an exemplary embodiment, referring to FIG. 13D , the second gate metal layer Gate2 includes at least a fifth scan signal line S5 , a second conductive portion 41 , a connecting trace 42 , and a connecting portion 43 .

[0170] In an exemplary embodiment, the fifth scan signal line S5 may be in the shape of a line with a main portion extending along the first direction X. The fifth scan signal line S5 may be designed with unequal widths, which not only facilitates the layout of the pixel structure but also reduces parasitic capacitance between signal lines.

[0171] In an exemplary embodiment, the outline of the second conductive portion 41 can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the second conductive portion 41 on the substrate at least partially overlaps with the orthographic projection of the first conductive portion 31 on the substrate. The second conductive portion 41 can serve as the second plate of the storage capacitor, and the first conductive portion 31 and the second conductive portion 41 together constitute the storage capacitor of the pixel driving circuit.

[0172] In an exemplary embodiment, the second conductive portion 41 is provided with an opening 411. The opening 411 may be rectangular and located in the middle of the second conductive portion 41, forming a ring-shaped structure. The orthographic projection of the opening 411 on the substrate is located within the orthographic projection of the first conductive portion 31 on the substrate.

[0173] In an exemplary embodiment, two second conductive portions 41 adjacent to each other along the first direction may be interconnected integral structures. For example, the second conductive portion 41 of the Nth column and the second conductive portion 41 of the N+1th column are interconnected via a connecting trace 42. For another example, the second conductive portion 41 of the N+1th column and the second conductive portion 41 of the N+2th column may be interconnected via a connecting portion 43. Since the second conductive portion 41 in each circuit unit is connected to the first power line formed subsequently, by forming the second conductive portions 41 of adjacent circuit units into an interconnected integral structure, it is possible to ensure that multiple second electrodes in a unit row have the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0174] In an exemplary embodiment, the lengths and widths of the connection traces 42 and the connection portions 43 may be different, and the connection traces 42 and the connection portions 43 may be staggered in the second direction.

[0175] In example embodiments, referring to FIG. 13E , the second semiconductor layer IGZO may include a second active portion of the second transistor T2 , that is, including the second channel portion 22 , the first electrode 22S, and the second electrode 22D of the second transistor T2 .

[0176] In an exemplary embodiment, referring to FIG13D , the region where the fifth scan signal line S5 overlaps with the second channel portion 22 of the second transistor T2 may serve as the bottom gate electrode of the second transistor T2. Furthermore, the fifth scan signal line S5 may serve as a shielding layer for the second transistor T2, shielding the second channel portion 22 of the second transistor T2 and ensuring the electrical performance of the oxide second transistor T2.

[0177] In an exemplary embodiment, the second semiconductor layer may be made of oxide, that is, the eighth transistor T8 is an oxide transistor. In an exemplary embodiment, the second semiconductor thin film may be made of indium gallium zinc oxide (IGZO), which has higher electron mobility than amorphous silicon.

[0178] In example embodiments, referring to FIG. 13F , the third gate metal layer Gate3 may include a sixth scan signal line S6 , a first initial signal line INIT1 , a second initial signal line INIT2 , and a third initial signal line INIT3 .

[0179] In an exemplary embodiment, the sixth scan signal line S6 may be in the shape of a line with a main portion extending along the first direction X. Referring to FIG13D , the region where the sixth scan signal line S6 overlaps with the second channel portion 22 of the second transistor T2 may serve as the top gate electrode of the second transistor T2. The sixth scan signal line S6 and the fifth scan signal line S5 are configured to receive the same voltage signal. For example, the sixth scan signal line S6 and the fifth scan signal line S5 may be electrically connected in a peripheral region of the display area.

[0180] In an exemplary embodiment, the shape of the first initial signal line INIT1 can be a broken line with the main portion extending along the first direction X, and a first initial connection block 53 is provided on the first initial signal line INIT1, and the first initial connection block 53 is configured to be electrically connected to the first electrode of the first transistor through a subsequently formed connection structure.

[0181] In an exemplary embodiment, the shape of the second initial signal line INIT2 can be a broken line with the main portion extending along the first direction X, and a second initial connection block 54 is provided on the second initial signal line INIT2, and the second initial connection block 54 is configured to be electrically connected to the first electrode of the seventh transistor through a subsequently formed connection structure.

[0182] In an exemplary embodiment, the shape of the third initial signal line INIT3 can be a broken line with the main portion extending along the first direction X, and a third initial connection block 52 is provided on the third initial signal line INIT3, and the third initial connection block 52 is configured to be connected to the first electrode of the eighth transistor through a subsequently formed connection structure.

[0183] In an exemplary embodiment, the third initial signal line INIT3 is provided with an initial signal grid line connection portion 51. The initial signal grid line connection portion 51 is configured to electrically connect to subsequently formed initial signal grid lines extending along the second direction Y, thereby forming a grid-like initial signal structure. Compared to conventional initial signal lines arranged only in a horizontal direction, this grid-like initial signal structure can reduce initialization signal loading, enabling faster initialization signal charging and better resetting of corresponding nodes. This beneficial effect is particularly significant for large-screen, high-frequency display substrates.

[0184] 13G , a plurality of vias are provided on the interlayer insulating layer ILD. For example, the plurality of vias include at least a first via H01, a sixth via H06, a seventh via H07, an eighth via H08, a ninth via H09, a tenth via H10, an eleventh via H11, a twelfth via H12, a thirteenth via H13, a fourteenth via H14, a fifteenth via H15, and a sixteenth via H16.

[0185] In an exemplary embodiment, the first via hole H01, the sixth via hole H06, the seventh via hole H07, the eighth via hole H08, the ninth via hole H09, the tenth via hole H10, the eleventh via hole H11, the twelfth via hole H12, the thirteenth via hole H13, and the fourteenth via hole H14 are all disposed through the interlayer insulating layer ILD, the fourth gate insulating layer, the third gate insulating layer, the second gate insulating layer, and the first gate insulating layer, thereby respectively exposing corresponding portions of the first semiconductor layer.

[0186] In an exemplary embodiment, the first via H01 exposes the first electrode of the seventh transistor, the sixth via H06 exposes the fourth node N4, the seventh via H07 exposes the second electrode of the eighth transistor, the eighth via H08 exposes the second electrode of the fifth transistor, the ninth via H09 exposes the first electrode of the first transistor, the tenth via H10 exposes the second electrode of the first transistor, the eleventh via H11 exposes the first electrode of the eighth transistor, the twelfth via H12 exposes the second node N2, the thirteenth via H13 exposes the first electrode of the fourth transistor, and the fourteenth via H14 exposes the third node N3.

[0187] In an exemplary embodiment, the fifteenth via hole H15 is arranged through the interlayer insulating layer ILD, the fourth gate insulating layer, the third gate insulating layer and the second gate insulating layer. With reference to FIG13D , the orthographic projection of the fifteenth via hole H15 on the base substrate is located within the orthographic projection of the opening 411 on the base substrate. With reference to FIG13C , the fifteenth via hole H15 exposes the first conductive portion 31 located in the first gate metal layer Gate1.

[0188] In an exemplary embodiment, the sixteenth via hole H16 penetrates the interlayer insulating layer ILD, the fourth gate insulating layer, and the third gate insulating layer. Referring to FIG. 13D , the sixteenth via hole H16 exposes the connection portion 43 in the second gate metal layer Gate2 .

[0189] In an exemplary embodiment, referring to FIG. 13H , a second via hole H02 , a third via hole H03 , a fourth via hole H04 , and a fifth via hole H05 are further provided on the interlayer insulating layer ILD.

[0190] In an exemplary embodiment, the third via hole H03 and the fourth via hole H04 are disposed through the interlayer insulating layer ILD and the fourth gate insulating layer. Referring to FIG. 13E , the third via hole H03 exposes the second electrode of the second transistor, and the fourth via hole H04 exposes the first electrode of the second transistor.

[0191] In an exemplary embodiment, the second via H02 and the fifth via H05 are disposed through the interlayer insulating layer ILD. Referring to FIG. 13F , the second via H02 exposes the initial signal grid line connection portion 51 in the third gate metal layer Gate3. The fifth via H05 includes a first fifth via H051, a second fifth via H052, and a third fifth via H053. The first fifth via H051 exposes the third initial connection block 52 in the third gate metal layer Gate3, the second fifth via H052 exposes the first initial connection block 53 in the third gate metal layer Gate3, and the third fifth via H053 exposes the second initial connection block 54 in the third gate metal layer Gate3.

[0192] In an exemplary embodiment, the plurality of via holes in adjacent cell columns may be mirror-symmetrical with respect to a column boundary line, and the shapes of the plurality of via holes in the plurality of cell rows may be substantially the same.

[0193] In an exemplary embodiment, referring to Figure 13I, the first source and drain metal layer SD1 may include a first connection structure 61, a second connection structure 62, a third connection structure 63, a fourth connection structure 64, a fifth connection structure 65, a sixth connection structure 66, a seventh connection structure 67, an eighth connection structure 68, a ninth connection structure 69 and an initial signal grid line 6M.

[0194] In an exemplary embodiment, with reference to Figures 13B, 13F, 13J and 13K, the first connection structure 61 is electrically connected to the first electrode of the eighth transistor through the eleventh via H11, and to the third initial connection block 52 through the first fifth via H051, thereby achieving electrical connection between the first electrode of the eighth transistor and the third initial signal line INIT3.

[0195] In an exemplary embodiment, with reference to Figures 13B, 13E, 13J and 13K, the second connection structure 62 is electrically connected to the second electrode of the first transistor through the tenth via H10, is electrically connected to the third node N3 through the fourteenth via H14, and is electrically connected to the second electrode of the second transistor through the third via H03, so that the second electrode of the first transistor and the second electrode of the second transistor are both electrically connected to the third node N3.

[0196] In an exemplary embodiment, with reference to Figures 13C, 13E, 13J and 13K, the third connection structure 63 is electrically connected to the first conductive portion 31 located in the first gate metal layer Gate1 through the fifteenth via H15, and is electrically connected to the first electrode of the second transistor through the fourth via H04, thereby achieving electrical connection between the first electrode of the second transistor and the gate electrode of the third transistor.

[0197] In this exemplary embodiment, referring to Figures 13B, 13D, 13J, and 13K, the fourth connection structure 64 is electrically connected to the second electrode of the fifth transistor through the eighth via H08 and to the connection portion 43 located in the second gate metal layer Gate2 through the sixteenth via H16. This electrically connects the second electrode of the fifth transistor to the second conductive portion 41, that is, the second electrode of the fifth transistor to the second plate of the storage capacitor. The fourth connection structure 64 is also used to electrically connect to a first power line formed subsequently, as described in detail below.

[0198] In an exemplary embodiment, referring to Figures 13B, 13J and 13K, the fifth connection structure 65 is electrically connected to the second electrode of the eighth transistor through the seventh via H07, and is electrically connected to the second node N2 through the twelfth via H12, thereby achieving electrical connection between the second electrode of the eighth transistor and the second node N2.

[0199] In an exemplary embodiment, with reference to Figures 13B, 13F, 13J and 13K, the sixth connection structure 66 is electrically connected to the first electrode of the first transistor through the ninth via H09, and is electrically connected to the first initial connection block 53 located in the third gate metal layer Gate3 through the second fifth via H052, thereby achieving electrical connection between the first electrode of the first transistor and the first initial signal line INIT1.

[0200] In an exemplary embodiment, referring to FIG. 13B , FIG. 13J and FIG. 13K , the seventh connection structure 67 is electrically connected to the fourth node N4 through the sixth via H06 . The seventh connection structure 67 is also used to be electrically connected to the anode portion, as will be described later.

[0201] In an exemplary embodiment, with reference to Figures 13B, 13F, 13J and 13K, the eighth connection structure 68 is electrically connected to the first electrode of the seventh transistor through the first via H01, and to the second initial connection block 54 located in the third gate metal layer Gate3 through the third fifth via H053, thereby achieving electrical connection between the first electrode of the seventh transistor and the second initial signal line INIT2.

[0202] In an exemplary embodiment, referring to FIG. 13B , FIG. 13J and FIG. 13K , the ninth connection structure 69 is electrically connected to the first electrode of the fourth transistor through the thirteenth via hole H13 . The ninth connection structure 69 is also used to be electrically connected to the data signal line, as described below.

[0203] In an exemplary embodiment, with reference to Figures 13F, 13J and 13K, the shape of the initial signal grid line 6M can be a straight line with the main portion extending along the second direction Y. The initial signal grid line 6M is electrically connected to the initial signal grid line connection portion 51 located in the third gate metal layer Gate3 through the second via H02, thereby achieving electrical connection between the initial signal grid line 6M and the third initial signal line INIT3.

[0204] In an exemplary embodiment, with reference to Figures 13A, 13C, 13E, 13H, and 13K, the second semiconductor layer IGZO has a first electrode 22S of the second transistor T2, and the first source-drain metal layer SD1 has a third connection structure 63, which is overlapped with the first electrode 22S of the second transistor T2 through a fourth via H04. To ensure a well-planar interface between the first electrode 22S of the second transistor T2 and the third connection structure 63, a second raised portion F312 is further provided on the third light-shielding portion connecting trace 113 in the light-shielding layer BSM, and a third raised portion F313 is provided on the first scan signal line S1 in the first gate metal layer Gate1. Furthermore, the orthographic projection of the fourth via H04 on the substrate is positioned within the orthographic projections of the third light-shielding portion connecting trace 113 and the second raised portion F312 on the substrate, and the orthographic projection of the fourth via H04 on the substrate is positioned within the orthographic projections of the first scan signal line S1 and the third raised portion F313 on the substrate. Furthermore, the orthographic projection of the fourth via H04 on the substrate is spaced apart from the orthographic projections of the second gate metal layer, the first semiconductor layer, and the light-shielding layer on the substrate.

[0205] In this exemplary embodiment, with reference to FIG13C , FIG13F , FIG13H , and FIG13K , the third gate metal layer Gate3 includes a third initial connection block 52, a first initial connection block 53, and a second initial connection block 54. The first source / drain metal layer SD1 includes a first connection structure 61, a sixth connection structure 66, and an eighth connection structure 68. The first connection structure 61 overlaps the third initial connection block 52 through the first fifth via H051, the sixth connection structure 66 overlaps the first initial connection block 53 through the second fifth via H052, and the eighth connection structure 68 overlaps the second initial connection block 54 through the third fifth via H053. In order to ensure that the overlapping surfaces between the third initial connection block 52, the first initial connection block 53, the second initial connection block 54 and the first source and drain metal layer SD1 have good flatness, in the first gate metal layer Gate1, the second scan signal line S2 is connected with a first fifth padding portion F3151, the third scan signal line S3 is connected with a second fifth padding portion F3152, and the fourth scan signal line S4 is connected with a third fifth padding portion F3153, and the orthographic projection of the first fifth via H051 on the substrate is located within the orthographic projection of the second scan signal line S2 and the first fifth padding portion F3151 on the substrate, the orthographic projection of the second fifth via H052 on the substrate is located within the orthographic projection of the third scan signal line S3 and the second fifth padding portion F3152 on the substrate, and the orthographic projection of the third fifth via H053 on the substrate is located within the orthographic projection of the fourth scan signal line S4 and the third fifth padding portion F3153 on the substrate. In addition, the orthographic projection of the fifth via hole H05 on the base substrate is spaced apart from the orthographic projections of the second semiconductor layer, the second gate metal layer, the first gate metal layer, the first semiconductor layer and the light shielding layer on the base substrate.

[0206] In an exemplary embodiment, with reference to Figures 13F, 13H, and 13K, the third gate metal layer Gate3 has an initial signal grid line connection portion 51, and the first source and drain metal layer SD1 has an initial signal grid line 6M. The initial signal grid line 6M is overlapped with the initial signal grid line connection portion 51 through the second via H02. In order to ensure that the overlapping surface between the initial signal grid line connection portion 51 and the initial signal grid line 6M has good flatness, the orthographic projection of the second via H02 on the base substrate is set to be spaced apart from the orthographic projections of the second semiconductor layer, the second gate metal layer, the first gate metal layer, the first semiconductor layer, and the light-shielding layer on the base substrate.

[0207] In an exemplary embodiment, with reference to Figures 13B, 13E, 13H, and 13K, the second semiconductor layer IGZO includes a second electrode 22D of the second transistor T2, and the first source-drain metal layer SD1 includes a second connection structure 62. The second connection structure 62 overlaps the second electrode 22D of the second transistor T2 via a third via H03. To ensure a smooth interface between the second electrode 22D of the second transistor T2 and the second connection structure 62, the orthographic projection of the third via H03 on the substrate is flush with the orthographic projection of the first semiconductor layer Poly on the substrate. Specifically, the orthographic projection of the third via H03 on the substrate is flush with the orthographic projection of the third node N3 on the substrate. Furthermore, the orthographic projection of the third via H03 on the substrate is spaced apart from the orthographic projections of the second gate metal layer, the first gate metal layer, and the light shielding layer on the substrate.

[0208] In an exemplary embodiment, referring to FIG13L , the passivation layer PVX is provided with a first via H21, a second via H22, and a third via H23. With reference to FIG13I , the first via H21 exposes the fourth connection structure 64 of the first source / drain metal layer SD1, the second via H22 exposes the seventh connection structure 67 of the first source / drain metal layer SD1, and the third via H23 exposes the ninth connection structure 69 of the first source / drain metal layer SD1.

[0209] In an exemplary embodiment, referring to FIG13M , the first planarization layer PLN1 is provided with a first via H31, a second via H32, and a third via H33. Referring to FIG13L , the first via H31 located in the first planarization layer PLN1 is connected to the first via H21 located in the passivation layer PVX, jointly exposing the fourth connection structure 64; the second via H32 located in the first planarization layer PLN1 is connected to the second via H22 located in the passivation layer PVX, jointly exposing the seventh connection structure 67; and the third via H33 located in the first planarization layer PLN1 is connected to the third via H23 located in the passivation layer PVX, jointly exposing the ninth connection structure 69.

[0210] In example embodiments, referring to FIG. 13N , the second source-drain metal layer SD2 may include a first power line VDD, a data signal line DATA, and a first anode transfer portion 71 .

[0211] In an exemplary embodiment, the first power line VDD may be shaped like a zigzag line with a main portion extending along the second direction Y. The first power line VDD is electrically connected to the fourth connection structure 64 through a first via H31 located in the first planarization layer PLN1 and a first via H21 located in the passivation layer PVX. Furthermore, because the fourth connection structure 64 is electrically connected to the second electrode of the fifth transistor and the second plate of the storage capacitor, the first power line VDD writes the first power signal to the second electrode of the fifth transistor and the second plate of the storage capacitor.

[0212] In an exemplary embodiment, the data signal line DATA may be in the shape of a line having a main portion extending along the second direction Y. The data signal line DATA is electrically connected to the ninth connection structure 69 through the third via hole H33 located in the first planarization layer PLN1 and the third via hole H23 located in the passivation layer PVX. Since the ninth connection structure 69 is electrically connected to the first electrode of the fourth transistor, the data signal line DATA writes the data signal to the first electrode of the fourth transistor.

[0213] In an exemplary embodiment, the first anode transition portion 71 is electrically connected to the seventh connection structure 67 through the second via H32 located in the first planarization layer PLN1 and the second via H22 located in the passivation layer PVX, and since the seventh connection structure 67 is electrically connected to the fourth node N4, the seventh connection structure 67 is electrically connected to the fourth node N4.

[0214] In an exemplary embodiment, referring to FIG. 130 , the second planarization layer has a first via hole H41 , and in combination with referring to FIG. 13N , the first via hole H41 exposes the first anode transfer portion 71 .

[0215] In example embodiments, referring to FIG. 13P , the third source-drain metal layer SD3 may include a second anode transfer portion 81 and a second power line 82 .

[0216] In an exemplary embodiment, referring to FIG. 13N and FIG. 130 , the second anode transition portion 81 is electrically connected to the first anode transition portion 71 , ie, the second anode transition portion 81 is electrically connected to the fourth node N4 , through the first via hole H41 .

[0217] In an exemplary embodiment, the second power lines 82 may be in a grid shape, distributed in the display area of ​​the display substrate, and electrically connected to the cathode layer in the peripheral area of ​​the display substrate, thereby writing the second power signal into the cathode layer.

[0218] According to some exemplary embodiments, the first functional layer is the second source-drain metal layer, the second functional layer is the third source-drain metal layer, the insulating layer has a sixth via, and the third source-drain metal layer is overlapped with the second source-drain metal layer through the sixth via; and the third functional layer is the first source-drain metal layer, and the orthographic projection of the bottom of the sixth via close to the substrate on the substrate is spaced from the orthographic projection of the first source-drain metal layer on the substrate.

[0219] In an exemplary embodiment, referring to Figures 13Q and 13N , the second anode transition 81 located in the third source / drain metal layer SD3 is electrically connected to the first anode transition 71 located in the second source / drain metal layer SD2 via a first via H41 located in the second planarization layer PLN2. The orthographic projection of the first via H41 on the substrate is spaced apart from the orthographic projection of the first source / drain metal layer SD1 on the substrate, ensuring that the overlapping surface of the first anode transition 71 exposed by the first via H41 has a high degree of flatness. Here, the second source / drain metal layer SD2 serves as the first functional layer, the third source / drain metal layer SD3 serves as the second functional layer, the first source / drain metal layer SD1 serves as the third functional layer, and the insulating layer between the second source / drain metal layer SD2 and the third source / drain metal layer SD3 is the second planarization layer PLN2.

[0220] It should be noted that when the first functional layer is the second source-drain metal layer SD2, in addition to the first source-drain metal layer SD1, the second source-drain metal layer SD2 close to the substrate also has a third gate metal layer, a second gate metal layer, and a first gate metal layer and other film layers, but only the first source-drain metal layer SD1 needs to be used as the third functional layer. The reason is that the first source-drain metal layer SD1 is provided with a first planarization layer close to the substrate, and the first planarization layer has filled the uneven structure of the underlying layer.

[0221] In an exemplary embodiment, referring to FIG13R , the third planarization layer PLN3 has a first via H51, and referring to FIG13S , the fourth planarization layer PLN4 has a first via H61. In conjunction with FIG13T , the orthographic projection of the first via H61 in the fourth planarization layer PLN4 on the base substrate overlaps the orthographic projection of the first via H51 in the third planarization layer PLN3 on the base substrate. The first via H61 in the fourth planarization layer PLN4 is connected to the first via H51 in the third planarization layer PLN3, and together they expose the second anode transition portion 81 in the third source / drain metal layer SD3.

[0222] In an exemplary embodiment, referring to Figures 13U and 13T, the anode layer ANE may include a plurality of anode portions 9, which are electrically connected to the second anode transition portion 81 located in the third source / drain metal layer through the first via H61 located in the fourth planarization layer PLN4, the first via H51 located in the third planarization layer PLN3, and the second anode transition portion 81 located in the third source / drain metal layer. Due to the electrical connection between the second anode transition portion 81 and the fourth node N4, the electrical connection between the anode portion 9 and the fourth node N4 is achieved.

[0223] 13U , in an exemplary embodiment, the anode portion 9 includes a first anode portion 91, a second anode portion 92, and a third anode portion 93. For example, the first anode portion 91 may be located in a red sub-pixel that emits red light, the second anode portion 92 may be located in a green sub-pixel that emits green light, and the third anode portion 93 may be located in a blue sub-pixel that emits blue light.

[0224] In an exemplary embodiment, at least one of the first anode portion 91, the second anode portion 92 and the third anode portion 93 may include an anode main portion and an anode connecting portion that are connected to each other. The shape of the anode main portion may be circular, elliptical, or diamond-shaped, and the corners may be rectangular with arc-shaped chamfers. The shape of the anode connecting portion may be a strip shape. The first end of the anode connecting portion is connected to the anode main portion, and the second end of the anode connecting portion extends in a direction away from the anode main portion and is electrically connected to the second anode transition portion through a via.

[0225] In an exemplary embodiment, with reference to FIG13T and FIG13U, the anode portion 9 located in the anode layer ANE is overlapped with the second anode transition portion 81 located in the third source-drain metal layer through the first via H61 located in the fourth planarization layer PLN4 and the first via H51 located in the third planarization layer PLN3, and the orthographic projection of the first via H61 located in the fourth planarization layer PLN4 on the substrate is spaced from the orthographic projection of the second source-drain metal layer on the substrate, and the orthographic projection of the first via H51 located in the third planarization layer PLN3 on the substrate is spaced from the orthographic projection of the second source-drain metal layer on the substrate. Here, the third source-drain metal layer serves as the first functional layer, the anode layer serves as the second functional layer, the second source-drain metal layer serves as the third functional layer, and the insulating layer between the third source-drain metal layer and the anode layer is the third planarization layer and the fourth planarization layer.

[0226] In an exemplary embodiment, referring to FIG13V , the pixel defining layer PDL includes a first opening K1, a second opening K2, and a third opening K3. Referring to FIG13W , the first opening K1 exposes a portion of the first anode portion 91, the second opening K2 exposes a portion of the second anode portion 92, and the third opening K3 exposes a portion of the third anode portion 93.

[0227] In an exemplary embodiment, the pixel definition layer (PDL) is made of a black organic material. The black pixel definition layer (PDL) can block the various metal traces located on the lower side of the pixel definition layer (PDL), thereby preventing the various metal traces on the lower side from reflecting ambient light, thereby eliminating the need for a polarizer on the light-emitting surface of the display substrate. Furthermore, in a display device including the display substrate, some optical sensing elements are usually provided on the back side of the display substrate. In order to allow ambient light to pass through the display substrate and be received by these optical sensing elements, referring to FIG13W , the pixel definition layer (PDL) further has a fourth opening K4, and the orthographic projection of the fourth opening K4 on the base substrate is spaced apart from the orthographic projections of the first gate metal layer, the second gate metal layer, the third gate metal layer, the first source and drain metal layer, the second source and drain metal layer, and the third source and drain metal layer on the base substrate. The area provided with the fourth opening K4 serves as the light-transmitting area of ​​the display substrate to meet the light-sensing requirements of the optical sensing elements located on the back side of the display substrate.

[0228] In an exemplary embodiment, the substrate substrate may be a flexible substrate or a rigid substrate. The rigid substrate may include, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an exemplary embodiment, the flexible substrate may include a stacked first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer. The materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the materials of the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The first and second inorganic material layers are also referred to as barrier layers, and the material of the semiconductor layer may be amorphous silicon (a-Si).

[0229] In an exemplary embodiment, the first gate metal layer, the second gate metal layer, the third gate metal layer, the first source-drain metal layer, the second source-drain metal layer, and the third source-drain metal layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), and titanium (Ti), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be a single layer structure or a multi-layer composite structure, such as Ti / Al / Ti. The buffer layer, the first gate insulating layer, the second gate insulating layer, the third gate insulating layer, the fourth gate insulating layer, the interlayer insulating layer, and the passivation layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be a single layer, a multi-layer, or a composite layer. The first planarization layer, the second planarization layer, the third planarization layer, the fourth planarization layer, and the pixel definition layer can be made of organic materials, such as resin.

[0230] In exemplary embodiments, the anode layer may have a single-layer structure, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or may have a multi-layer composite structure, such as ITO / Ag / ITO.

[0231] In an exemplary embodiment, an encapsulation structure layer is further provided on the side of the cathode layer away from the base substrate. The encapsulation structure layer may include a stacked first encapsulation layer, a second encapsulation layer and a third encapsulation layer. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to ensure that external water vapor cannot enter the light-emitting layer.

[0232] In another aspect, a display device is provided, comprising the display substrate described above. The display device may be a display device such as a liquid crystal display, electronic paper, or an OLED (Organic Light-Emitting Diode) display, as well as any product or component with touch and display functions, such as a television, digital camera, mobile phone, watch, tablet computer, laptop computer, or navigation system, that includes such a display device.

[0233] It should be understood that the display devices according to some exemplary embodiments of the present disclosure have all the features and advantages of the above-mentioned display substrate. These features and advantages can be referred to in the above description of the display substrate and will not be repeated here.

[0234] As used herein, the terms "substantially," "about," "approximately," and other similar terms are used as terms of approximation rather than as terms of degree, and are intended to account for the inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. To account for factors such as process fluctuations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), "about" or "approximately," as used herein, are inclusive of the stated value and mean within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, or within ±10% or ±5% of the stated value.

[0235] Although some embodiments according to the general inventive concept of the present disclosure have been illustrated and described, it will be appreciated by those skilled in the art that changes may be made to these embodiments without departing from the principles and spirit of the general inventive concept of the present disclosure, the scope of which is defined by the claims and their equivalents.

Claims

1. A display substrate, wherein: The display substrate comprises: substrate; A first functional layer is located on the substrate; an insulating layer, located on a side of the first functional layer away from the substrate, the insulating layer having a via hole; a second functional layer, located on a side of the insulating layer away from the first functional layer, the second functional layer overlapping the first functional layer through the via hole; and At least one third functional layer, the at least one third functional layer is located between the first functional layer and the base substrate, and the orthographic projection of any third functional layer on the base substrate partially overlaps with the orthographic projection of the first functional layer on the base substrate, The first functional layer has a lap joint surface exposed by the via hole, and the lap joint surface is a flat surface.

2. The display substrate according to claim 1, wherein The orthographic projection of the bottom of the via hole close to the base substrate on the base substrate is located within the orthographic projection of any layer of the third functional layer on the base substrate.

3. The display substrate according to claim 1, wherein The orthographic projection of the bottom of the via hole close to the base substrate on the base substrate does not overlap with the orthographic projection of each layer of the third functional layer on the base substrate.

4. The display substrate according to claim 1, wherein: The multilayer third functional layer includes at least one first sublayer and at least one second sublayer; The orthographic projection of the bottom of the via hole close to the base substrate on the base substrate does not overlap with the orthographic projection of each first sub-layer on the base substrate; and The orthographic projection of the bottom of the via hole close to the base substrate on the base substrate is located within the orthographic projection of any second sub-layer on the base substrate.

5. The display substrate according to claim 2, wherein: The third functional layer includes a functional portion, and the orthographic projection of the bottom of the via hole close to the base substrate on the base substrate partially overlaps or is flush with the orthographic projection of the functional portion on the base substrate; as well as The third functional layer further includes a raised portion directly connected to the functional portion, and the orthographic projection of the bottom of the via hole close to the base substrate on the base substrate is located within the orthographic projections of the functional portion and the raised portion on the base substrate. The display substrate according to claim 5 , wherein: The edge of the raised portion extends beyond the bottom edge of the via hole by 0.4 μm to 0.6 μm.

7. The display substrate according to claim 3, wherein: At least one third functional layer includes at least one metal functional layer, and the orthographic projection of the bottom of the via hole close to the base substrate on the base substrate is spaced apart from the orthographic projection of each metal functional layer on the base substrate.

8. The display substrate according to claim 3, wherein: At least one of the third functional layers comprises at least one semiconductor functional layer; The orthographic projection of the bottom of the via hole close to the substrate on the substrate is spaced apart from the orthographic projection of the semiconductor functional layer on the substrate, and / or The orthographic projection of the bottom of the via hole close to the base substrate on the base substrate is flush with the orthographic projection of the semiconductor functional layer on the base substrate.

9. The display substrate according to any one of claims 2, 5 and 6, wherein: The first functional layer is a first semiconductor layer, the second functional layer is a first source-drain metal layer, the insulating layer has a first via hole, and the first source-drain metal layer is overlapped with the first semiconductor layer through the first via hole; as well as The third functional layer is a light-shielding layer, and the orthographic projection of the bottom of the first via hole close to the base substrate on the base substrate is located within the orthographic projection of the light-shielding layer on the base substrate.

10. The display substrate according to claim 9, wherein: The light-shielding layer includes a light-shielding portion connecting trace and a first raised portion directly connected to the light-shielding portion connecting trace, the orthographic projection of the bottom of the first via hole close to the base substrate on the base substrate partially overlaps with the orthographic projection of the light-shielding portion connecting trace on the base substrate, and the orthographic projection of the bottom of the first via hole close to the base substrate on the base substrate is located within the orthographic projection of the light-shielding portion connecting trace and the first raised portion on the base substrate.

11. The display substrate according to claim 3 or 7, wherein: The first functional layer is a third gate metal layer, the second functional layer is a first source / drain metal layer, the insulating layer has a second via hole, and the first source / drain metal layer is overlapped with the third gate metal layer through the second via hole; At least one third functional layer is a light shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, and a second semiconductor layer stacked between the base substrate and the third gate metal layer; as well as The orthographic projection of the bottom of the second via hole close to the base substrate on the base substrate is spaced apart from the orthographic projections of the light shielding layer, the first semiconductor layer, the first gate metal layer, the second gate metal layer and the second semiconductor layer on the base substrate.

12. The display substrate according to claim 3 or 8, wherein: The first functional layer is a second semiconductor layer, the second functional layer is a first source-drain metal layer, the insulating layer has a third via hole, and the first source-drain metal layer is overlapped with the second semiconductor layer through the third via hole; At least one of the third functional layers is a light shielding layer, a first semiconductor layer, a first gate metal layer, and a second gate metal layer stacked between the base substrate and the second semiconductor layer; as well as The orthographic projection of the bottom of the third via hole close to the substrate on the substrate is flush with the orthographic projection of the first semiconductor layer on the substrate, and the orthographic projection of the bottom of the third via hole close to the substrate on the substrate is spaced apart from the orthographic projections of the light-shielding layer, the first gate metal layer and the second gate metal layer on the substrate.

13. The display substrate according to claim 4, wherein: The first functional layer is a second semiconductor layer, the second functional layer is a first source-drain metal layer, the insulating layer has a fourth via hole, and the first source-drain metal layer is overlapped with the second semiconductor layer through the fourth via hole; At least one of the third functional layers is a light shielding layer, a first semiconductor layer, a first gate metal layer, and a second gate metal layer stacked between the base substrate and the second semiconductor layer; and The orthographic projection of the bottom of the fourth via hole close to the substrate is located within the orthographic projection of the light shielding layer and the first gate metal layer on the substrate respectively. The orthographic projection of the hole bottom of the plate on the base substrate is spaced apart from the orthographic projections of the first semiconductor layer and the second gate metal layer on the base substrate.

14. The display substrate according to claim 13, wherein: The light shielding layer includes a light shielding portion connecting wiring and a second padding portion directly connected to the light shielding portion connecting wiring, and the first gate metal layer includes a scan signal line and a third padding portion directly connected to the scan signal line; The orthographic projection of the bottom of the fourth via hole close to the base substrate on the base substrate partially overlaps with the orthographic projection of the light-shielding portion connecting trace on the base substrate, and the orthographic projection of the bottom of the fourth via hole close to the base substrate on the base substrate is located within the orthographic projections of the light-shielding portion connecting trace and the second raised portion on the base substrate; The orthographic projection of the bottom of the fourth via hole close to the base substrate on the base substrate partially overlaps with the orthographic projection of the scanning signal line on the base substrate, and the orthographic projection of the bottom of the fourth via hole close to the base substrate on the base substrate is located within the orthographic projections of the scanning signal line and the third raised portion on the base substrate; as well as The first gate metal layer is located on a side of the light shielding layer away from the base substrate, and the orthographic projection of the third elevated portion on the base substrate is located within the orthographic projection of the light shielding portion connecting trace and the second elevated portion on the base substrate.

15. The display substrate according to claim 4, wherein The first functional layer is a second semiconductor layer, the second functional layer is a first source-drain metal layer, the insulating layer has a third via hole, and the first source-drain metal layer is overlapped with the second semiconductor layer through the third via hole; At least one of the third functional layers is a light shielding layer, a first semiconductor layer, a first gate metal layer, and a second gate metal layer stacked between the base substrate and the second semiconductor layer; as well as The orthographic projection of the bottom of the third via hole close to the base substrate on the base substrate is located within the orthographic projection of the first semiconductor layer on the base substrate; The orthographic projection of the bottom of the third via hole close to the base substrate on the base substrate is spaced apart from the orthographic projections of the light shielding layer, the first gate metal layer and the second gate metal layer on the base substrate.

16. The display substrate according to claim 15, wherein: The first semiconductor layer has a first semiconductor portion and a fourth elevated portion directly connected to the first semiconductor portion, the orthographic projection of the bottom of the third via hole close to the base substrate on the base substrate is flush with the orthographic projection of the first semiconductor portion on the base substrate, and the orthographic projection of the bottom of the third via hole close to the base substrate on the base substrate is located within the fourth elevated portion.

17. The display substrate according to claim 4, wherein: The first functional layer is a third gate metal layer, the second functional layer is a first source / drain metal layer, the insulating layer has a fifth via hole, and the first source / drain metal layer is overlapped with the third gate metal layer through the fifth via hole; At least one third functional layer is a light shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, and a second semiconductor layer stacked between the base substrate and the third gate metal layer; as well as The orthographic projection of the bottom of the fifth via hole close to the base substrate on the base substrate is located within the orthographic projection of the first gate metal layer on the base substrate, and the orthographic projection of the bottom of the fifth via hole close to the base substrate on the base substrate is spaced from the orthographic projections of the light-shielding layer, the first semiconductor layer, the second gate metal layer, and the second semiconductor layer on the base substrate, respectively.

18. The display substrate according to claim 17, wherein: The third gate metal layer includes an initial signal line, the first source / drain metal layer is overlapped with the initial signal line through the fifth via hole, and the first gate metal layer includes a scan signal line and a fifth pad directly connected to the scan signal line; as well as The orthographic projection of the bottom of the fifth via hole close to the base substrate on the base substrate partially overlaps with the orthographic projection of the scanning signal line on the base substrate, and the orthographic projection of the bottom of the fifth via hole close to the base substrate on the base substrate is located within the orthographic projection of the scanning signal line and the fifth raised portion on the base substrate.

19. The display substrate according to claim 3, wherein: The first functional layer is a second source-drain metal layer, the second functional layer is a third source-drain metal layer, the insulating layer has a sixth via hole, and the third source-drain metal layer is overlapped with the second source-drain metal layer through the sixth via hole; as well as The third functional layer is a first source-drain metal layer, and the orthographic projection of the bottom of the sixth via hole close to the base substrate on the base substrate is spaced apart from the orthographic projection of the first source-drain metal layer on the base substrate.

20. A display substrate, wherein: The display substrate comprises: substrate; A first functional layer is located on the substrate; an insulating layer, located on a side of the first functional layer away from the substrate, the insulating layer having a via hole; a second functional layer, located on a side of the insulating layer away from the first functional layer, the second functional layer overlapping the first functional layer through the via hole; At least one third functional layer, the at least one third functional layer is located between the first functional layer and the base substrate, and the orthographic projection of any third functional layer on the base substrate partially overlaps with the orthographic projection of the first functional layer on the base substrate, The first functional layer has an overlapping surface exposed by the via hole, and the difference between the maximum reflectivity and the minimum reflectivity of each area on the overlapping surface is less than or equal to 15%.

21. A display device, wherein: The display device comprises the display substrate according to any one of claims 1-20.

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