Silicon-based cavity structure and forming method thereof

Abstract

The invention discloses a silicon-based cavity structure and a forming method thereof. The manufacturing method of a semiconductor device comprises the following steps: providing a silicon substrate with an etching window; pretreating the silicon substrate to remove surface residues on the silicon substrate; the pretreated silicon substrate is placed in an etching cavity to be subjected to a main etching stage, in the main etching stage, only source power is applied to plasma, bias power is not applied, the flux of fluorine-containing etching gas is increased while the cavity pressure of the etching cavity is reduced, so that the transverse dispersive etching capacity of the plasma is enhanced, and the etching efficiency of the silicon substrate is improved. Therefore, a lateral cavity structure is formed at the specific depth of the silicon substrate, and the supporting structure is reserved. According to the embodiment of the invention, a controlled lateral cavity can be realized in a narrow and deeper groove.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a silicon-based cavity structure and a method for forming the same. Background Technology

[0002] As microelectronic devices and microelectromechanical systems (MEMS) evolve towards higher integration and more complex three-dimensional structures, the demand for forming controlled cavities (e.g., for releasing cantilever structures, forming air chambers, or optical resonant cavities) inside or beneath devices is increasing. Common methods for forming cavities in silicon substrates include sacrificial layer processes (depositing and subsequently removing sacrificial material before structure formation), wafer bonding / interlayer bonding (creating reserved spaces through the alignment and bonding of two or more wafers), and directly forming cavities in silicon using etching processes. Each method has its advantages: sacrificial layer processes offer superior morphology controllability; wafer bonding can produce regular cavity structures; and direct etching can generate cavities within a single-wafer process flow, facilitating process integration and cost control. However, existing direct etching methods mainly pursue high anisotropy, making it difficult to achieve controllable lateral etching in narrow and deep trenches to form predetermined lateral cavities. This limits the low-cost, repeatable fabrication of controlled cavity structures in a single-wafer process flow. Summary of the Invention

[0003] This application provides a silicon-based cavity structure and a method for forming the same, which can realize a controlled lateral cavity in a narrow and deep trench.

[0004] In a first aspect, this application provides a method for forming a silicon-based cavity structure, comprising: Provide a silicon substrate with an etching window; The silicon substrate is pretreated to remove surface residues on the silicon substrate; The pretreated silicon substrate is placed in an etching chamber for the main etching stage. In the main etching stage, only the source power is applied to the plasma, and no bias power is applied. The flow rate of fluorine-containing etching gas is increased while the chamber pressure of the etching chamber is reduced, so as to enhance the lateral dispersion etching capability of the plasma, thereby forming a lateral cavity structure at a specific depth of the silicon substrate and retaining the support structure.

[0005] In the silicon-based cavity structure formation method provided in this application embodiment, the pretreatment of the silicon substrate to remove surface residues on the silicon substrate includes: The silicon substrate is placed in an etching chamber and a preset bias power is applied to remove surface residues on the silicon substrate by ion bombardment.

[0006] In the silicon-based cavity structure formation method provided in the embodiments of this application, the preset bias power is 50V-800V and the application time is 0.5s-600s.

[0007] In the silicon-based cavity structure formation method provided in this application embodiment, reducing the cavity pressure of the etching cavity means adjusting the cavity pressure to a level lower than the high pressure / high passivation conditions commonly used in conventional deep reactive ion etching.

[0008] In the silicon-based cavity structure formation method provided in this application embodiment, reducing the cavity pressure of the etching cavity includes: The pressure in the cavity is adjusted to a range of 0.1 Pa to 50 Pa.

[0009] In the silicon-based cavity structure formation method provided in the embodiments of this application, the fluorine-containing etching gas is SF6 or a mixture containing SF6.

[0010] In the silicon-based cavity structure formation method provided in this application embodiment, increasing the flux of fluorine-containing etching gas includes: The flux of SF6 is adjusted to the range of 10 sccm-500 sccm, or the proportion of SF6 in the mixed gas is set to 10%-100%.

[0011] In the silicon-based cavity structure formation method provided in the embodiments of this application, the fluorine-containing etching gas does not contain polymerizable passivating gas, so as to reduce sidewall passivation and prevent etching from stopping.

[0012] In the silicon-based cavity structure formation method provided in the embodiments of this application, the source power is 200W-2000W.

[0013] Secondly, embodiments of this application provide a silicon-based cavity structure, which is fabricated using any of the silicon-based cavity structure forming methods described above.

[0014] In summary, the silicon-based cavity structure formation method provided in this application includes: providing a silicon substrate with an etching window; pre-treating the silicon substrate to remove surface residues; placing the pre-treated silicon substrate in an etching chamber for a main etching stage. In the main etching stage, only source power is applied to the plasma, without bias power, and the flux of fluorine-containing etching gas is increased while reducing the chamber pressure of the etching chamber to enhance the lateral dispersion etching capability of the plasma, thereby forming a lateral cavity structure at a specific depth on the silicon substrate while retaining the supporting structure. This application embodiment, by applying only source power without bias power in the main etching stage and increasing the flux of fluorine-containing etching gas while reducing the chamber pressure of the etching chamber, allows the plasma to primarily engage in weaker ion bombardment and enhanced neutral radical migration, thereby enhancing the lateral dispersion etching capability and facilitating controllable lateral etching at a predetermined depth on the silicon substrate. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic flowchart of the method for forming a silicon-based cavity structure provided in the embodiments of this application.

[0017] Figure 2 This is a schematic diagram of a silicon substrate with an etching window provided in an embodiment of this application.

[0018] Figure 3 This is a schematic diagram of the cavity structure provided in the embodiments of this application. Detailed Implementation

[0019] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0020] Unless otherwise defined, all technical and scientific terms used in this application have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this application and in its specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used in this application includes any and all combinations of one or more of the associated listed items.

[0021] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0022] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. Devices may be oriented otherwise (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly. Furthermore, terms such as “first,” “second,” etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0023] Existing deep silicon etching processes that directly etch to form cavities typically aim to achieve highly anisotropic profiles, which makes it significantly difficult to achieve controllable lateral etching within narrow and deep trenches.

[0024] Based on this, this application provides a silicon-based cavity structure and a method for forming the same. The technical solution shown in this application will be described in detail below through specific embodiments. It should be noted that the order of description of the following embodiments is not intended to limit the priority of the embodiments.

[0025] Please see Figure 1 , Figure 1 This is a schematic flowchart of the silicon-based cavity structure formation method provided in this application. The specific process of this silicon-based cavity structure formation method is as follows: 101. Provide a silicon substrate with an etched window.

[0026] The silicon substrate can be selected from single-crystal silicon substrates, epitaxial silicon substrates, and SOI (Silicon On Insulator) substrates. The preferred crystal orientation of the silicon substrate is <100>, as this orientation is mature in most microfabrication processes and its corresponding etching anisotropy facilitates subsequent lateral dispersion etching control. For specific requirements, <110> or other orientations can be selected to suit specific device performance. In the embodiments of this application, the resistivity of the silicon substrate is in the range of 1-20 Ω·cm, which avoids plasma instability or localized current concentration problems caused by excessively low resistance, while also meeting the electrical interconnection requirements of subsequent devices. If the device does not have strict requirements for electrical characteristics, the resistivity range can be appropriately widened; if high-frequency or low-noise characteristics are required, a more precise doping level should be selected based on the device design.

[0027] In some embodiments, after obtaining a suitable silicon substrate, it can be pretreated to ensure surface cleanliness. For example, a standard RCA cleaning process can be used. Specifically, RCA-1 can be performed first to remove organic contaminants and particles, followed by RCA-2 to remove metal ion contaminants; if necessary, a short immersion in a dilute HF solution can be used to remove the natural oxide layer on the surface and obtain a hydrogen-passivated silicon surface before subsequent processing. Pretreatment can significantly reduce the impact of organic residues and particles on photoresist adhesion and pattern transfer, improve window edge clarity, and reduce localized etching stops caused by oxide layers or residual photoresist during subsequent etching processes.

[0028] Understandably, the formation of the etching window can be accomplished by depositing a mask on the surface of a silicon substrate and then performing photolithography, development, and etching transfer. The mask material can be silicon dioxide, silicon nitride, low-stress photoresist, or a thin metal film.

[0029] Understandably, the choice and thickness of the mask should be determined based on the erosion intensity and required corrosion resistance of the subsequent deep silicon etching. For example, SiO2 masks are commonly used in the thickness range of 0.5-5 μm to provide sufficient corrosion resistance during long-term etching; if Si3N4 is used, the thickness can be reduced to 0.5-1 μm to reduce defects caused by stress and thermal expansion mismatch; metal masks are generally available in thicknesses of 100-300 nm, but the adhesion layer and stress control need to be considered.

[0030] Mask deposition can be achieved through methods such as thermal oxidation, PECVD, LPCVD, or PVD. After the mask layer is deposited, photoresist is spin-coated, exposed, and developed to obtain the etching window, forming a mask. Figure 2 The structure shown.

[0031] The geometric parameters (size, shape, and distribution) of the etching window significantly affect subsequent lateral dispersion etching. An excessively small window size restricts plasma entry and reduces the etching rate, while an excessively large window size may lead to premature cavity connectivity or localized structural instability. To balance manufacturing tolerances and functional requirements, this embodiment preferably uses a window size in the range of 2-20 μm (the specific size can be determined based on the target cavity size and mask offset correction). When forming a dense window array, the spacing between adjacent windows should not be less than 5 μm to avoid uncontrollable connectivity during lateral etching, which could affect structural integrity. The window shape can be circular, rectangular, or a rectangle with rounded corners, etc.

[0032] 102. Pre-treat the silicon substrate to remove surface residues.

[0033] Understandably, after the etching window is formed, the silicon substrate surface and the edges of the etching window may retain photoresist residue, organic contaminants from previous processes, and carbides and fluorocarbon polymers generated during mask exposure or etching transfer. If left untreated, these residues can become the source of etching stops during the main etching process, or cause uneven etching rates and morphologies, thus affecting the controllability and structural integrity of the cavity structure formation. Therefore, pretreatment of the silicon substrate is necessary before entering the main etching stage to remove surface residues.

[0034] Specifically, the pretreatment of the silicon substrate can be carried out by placing the silicon substrate in an etching chamber and applying a preset bias power to remove surface residues on the silicon substrate by ion bombardment.

[0035] Understandably, ions gain acceleration energy under an electric field. These accelerated ions collide with the silicon substrate surface at high energy, leading to physical sputtering, bond breaking, and localized surface heating. This causes the carbide layer and polymer film to decompose, sputter, or transform into volatile products. By increasing the bias power with an F-based gas, the surface-hardened polymer core is removed, while simultaneously defining the linewidth for the next lateral etching step. It is important to note that the biasing process should be completed within a vacuum etching chamber to utilize the directionality and energy distribution of ions in the plasma environment for efficient removal and to avoid recontamination or mechanical damage caused by external chemical treatments.

[0036] The preset bias power range is 50V-800V, and the application time is 0.5s-600s. These parameters are determined based on the physicochemical properties analysis and experimental verification of different residue types. Specifically, when the bias is below 50V, the ion energy is insufficient to break strong chemical bonds such as CC or CF, making it difficult to remove dense carbonized films; a bias above 800V may cause silicon surface roughening, mask damage, or the formation of micro-pits at the bottom of the window. Furthermore, too short a time leads to incomplete processing, while too long a time wastes processing resources and may cause unnecessary substrate erosion.

[0037] Therefore, within the parameter range of 50-800V and 0.5-600s, the residue can be further subdivided based on its severity and the mask's corrosion resistance. For example, for mild residue (such as only a small amount of photoresist residue or organic film), a bias of 50-200V for 0.5-30s can achieve significant results; for moderate residue (CF generated after conventional Bosch processes), the following approach can be used. x For polymers, the bias can be set at 200-500V and the time at 10-120s; for stubborn residues or multilayer cross-linked polymers, the bias can be set at 500-800V and the time at 30-600s.

[0038] 103. The pretreated silicon substrate is placed in the etching chamber for the main etching stage. During the main etching stage, only the source power is applied to the plasma, and no bias power is applied. While reducing the chamber pressure of the etching chamber, the flux of the fluorine-containing etching gas is increased to enhance the lateral dispersion etching capability of the plasma, thereby forming a lateral cavity structure at a specific depth of the silicon substrate and retaining the support structure.

[0039] In this embodiment, instead of relying on alternating etching / passivation cycles and high bias to achieve anisotropic engraving in traditional DRIE (such as Bosch process), a "diffuse etching" path is adopted to form the cavity structure.

[0040] Specifically, during the main etching stage, no bias power is applied; only source power is applied to the plasma. Simultaneously, while reducing the cavity pressure of the etching chamber, the flux of the fluorine-containing etching gas is increased. This results in controlled lateral etching at the target depth through chemical etching and the lateral diffusion of active species, forming a lateral cavity. At the same time, a low-energy chemical reaction is used to retain the necessary support structure, resulting in... Figure 3 The structure shown.

[0041] The reduction of the etching chamber pressure involves adjusting the chamber pressure to a level lower than the high-pressure / high-passivation conditions commonly used in conventional deep reactive ion etching. In this embodiment, lower than conventional high-pressure / high-passivation conditions means reducing the etching chamber pressure to a level significantly lower than the working pressure used for sidewall polymerization passivation, thereby suppressing the formation of the sidewall passivation layer and extending the mean free path of plasma active species. Specifically, in this embodiment, the chamber pressure is adjusted to a range of 0.1 Pa to 50 Pa. Conventional high-pressure / high-passivation conditions are typically in the range of several Pa to tens of Pa, accompanied by a high supply of polymerizable gas to deposit a protective layer on the sidewalls to achieve highly anisotropic etching.

[0042] In this embodiment, the source power is 200W-2000W, preferably 500W-1500W to balance plasma density and stability. The main function of the source power is to maintain plasma discharge, generate a sufficient number of active fluorine radicals (F·), and ensure that the overall plasma energy density meets the requirements of chemical etching. Below 200W, the plasma density is insufficient, the concentration of active species is low, the etching rate and lateral propagation ability are insufficient, and it is difficult to form obvious cavities. Above 2000W, although more active species can be generated, it will cause cavity overheating, local unstable discharge, and possible arcing, and will also bring thermal load and safety hazards to the equipment and substrate. Experimental results show that better lateral cavity size and morphology consistency can be obtained at about 1000W; in the range of 500-1500W, the cavity size can be further fine-tuned by adjusting other parameters. The increase or decrease of the source power directly affects the concentration of active fluorine radicals in the plasma, thereby affecting the lateral etching rate.

[0043] In traditional processes, bias power is used to give ions downward acceleration kinetic energy, thereby enhancing vertical ion bombardment and resulting in highly anisotropic etching. However, this strongly directional ion bombardment greatly suppresses lateral chemical etching, which is detrimental to the formation of lateral cavities in the depths of the trench. With the bias removed, ions in the plasma reach the substrate surface primarily through thermal motion or slight drift, reducing the physical bombardment component and allowing chemical etching to dominate. At this point, the etching behavior becomes more dependent on the diffusion of active materials and the rate of surface chemical reactions, making lateral dispersion possible.

[0044] In this embodiment, the fluorine-containing etching gas can be SF6 or a mixture containing SF6. Furthermore, the fluorine-containing etching gas does not contain polymerizable passivating gases to reduce sidewall passivation and prevent etching cessation.

[0045] Specifically, increasing the flux of fluorine-containing etching gas can be achieved by adjusting the flux of SF6 to the range of 10 sccm-500 sccm, or by setting the proportion of SF6 in the mixed gas to 10%-100%.

[0046] In this embodiment, by controlling the SF6 flux between 10 sccm and 500 sccm, or its proportion in the mixed gas between 10% and 100%, the lateral etching rate and morphology can be controlled by adjusting the F· concentration. When the flux is below 10 sccm, the amount of F· generated is insufficient to achieve significant lateral diffusion in deep trenches; when the flux is above 500 sccm, it may lead to over-etching and increase the gas handling load and equipment burden.

[0047] Polymerizing passivation gases form a protective polymer layer on the sidewalls. While this is beneficial for achieving vertical sidewalls using conventional DRIE (Dual Pathway Interrupter) methods, it severely inhibits lateral chemical etching, leading to the inability to form cavities or halting the etching process. Therefore, this embodiment directly ensures the opening of lateral diffusion channels through the selection of gas composition, guaranteeing the formability of cavities from a chemical mechanism perspective.

[0048] By jointly controlling the above parameters, controlled lateral cavity structures can be formed at specific depths in the silicon substrate. In fact, the formation process of the cavity structure is a competitive equilibrium: vertical chemical etching and lateral chemical etching compete for distribution under the constraints of active species concentration, free path, local reaction rate, and substrate geometry.

[0049] In this embodiment, by setting up no bias, low voltage, high SF6 flux, and moderate source power, the lateral chemical etching rate becomes dominant on lateral diffusion at a certain depth, thereby producing significant lateral etching at that depth and forming a cavity structure. Simultaneously, due to the lack of strong physical sputtering factors, the support pillars are not destroyed by high-energy ion bombardment, thus preserving the necessary mechanical support in the structure.

[0050] In summary, the silicon-based cavity structure formation method provided in this application includes providing a silicon substrate with an etching window; pre-treating the silicon substrate to remove surface residues; placing the pre-treated silicon substrate in an etching chamber for a main etching stage. During the main etching stage, only source power is applied to the plasma, without bias power. The flux of fluorinated etching gas is increased while reducing the chamber pressure of the etching chamber to enhance the lateral dispersion etching capability of the plasma, thereby forming a lateral cavity structure at a specific depth in the silicon substrate while retaining the supporting structure. This application, by applying only source power without bias power during the main etching stage and increasing the flux of fluorinated etching gas while reducing the chamber pressure, allows the plasma to primarily engage in weaker ion bombardment and enhanced neutral radical migration, thereby enhancing the lateral dispersion etching capability and facilitating the creation of a controlled lateral cavity within a narrow and deep trench.

[0051] In addition, this application embodiment also provides a silicon-based cavity structure, which is fabricated using the above-described silicon-based cavity structure forming method. The silicon-based cavity structure has a lateral cavity formed within its substrate and a support structure for support.

[0052] It should be noted that the meanings of the terms in this embodiment are the same as those in the above-described silicon-based cavity structure formation method embodiment. For specific implementation details, please refer to the description in the above-described silicon-based cavity structure formation method embodiment.

[0053] The silicon-based cavity structure and its formation method provided in this application have been described in detail above. Specific examples have been used in this application to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A method of forming a silicon-based cavity structure, comprising: The method comprises: providing a silicon substrate with an etching window; pre-treating the silicon substrate to remove surface residues on the silicon substrate; placing the pre-treated silicon substrate in an etching chamber for a main etching stage, in which only a source power is applied to plasma, no bias power is applied, and the cavity pressure of the etching chamber is reduced while the flux of fluorine-containing etching gas is increased to enhance the lateral dispersion etching capability of the plasma, so as to form a lateral cavity structure at a specific depth of the silicon substrate and retain a support structure.

2. The method of claim 1, wherein the step of forming the silicon-based cavity structure is performed by a method selected from the group consisting of: The pre-treating the silicon substrate to remove surface residues on the silicon substrate comprises: ​ placing the silicon substrate in an etching chamber and applying a preset bias power to remove surface residues on the silicon substrate by ion bombardment.

3. The method for forming a silicon-based cavity structure as described in claim 2, characterized in that, The preset bias power is 50V-800V, and the application time is 0.5s-600s.

4. The method for forming a silicon-based cavity structure as described in claim 1, characterized in that, The reducing the cavity pressure of the etching chamber is adjusting the cavity pressure to be lower than the high pressure / high passivation condition commonly used in conventional deep reactive ion etching.

5. The method for forming a silicon-based cavity structure as described in claim 4, characterized in that, The reducing the cavity pressure of the etching chamber comprises: adjusting the cavity pressure to be in the range of 0.1 Pa-50 Pa.

6. The method for forming a silicon-based cavity structure as described in claim 1, characterized in that, The fluorine-containing etching gas is SF6 or a mixed gas containing SF6.

7. The method for forming a silicon-based cavity structure as described in claim 6, characterized in that, The increasing the flux of fluorine-containing etching gas comprises: adjusting the flux of SF6 to be in the range of 10 sccm-500 sccm, or setting the proportion of SF6 in the mixed gas to be 10%-100%.

8. The method for forming a silicon-based cavity structure as described in claim 6, characterized in that, The fluorine-containing etching gas does not contain a polymerization passivation gas to reduce sidewall passivation and prevent etching from stopping.

9. The method of claim 1, wherein the silicon-based cavity structure is formed by a process selected from the group consisting of: The source power is 200W-2000W. ​ 10. A silicon-based cavity structure, characterized by, The silicon-based cavity structure is formed by the method according to any one of claims 1-9.

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