MOS tube parallel type electronic water gauge circuit

Abstract

The invention discloses an MOS tube parallel type electronic water gauge circuit. The circuit is composed of multiple levels of water level monitoring sub-circuit cascades which are arranged in series at equal intervals, a voltage division circuit, a power supply VCC and a bias power supply. The first-stage water level monitoring sub-circuit comprises an MOS (Metal Oxide Semiconductor) tube M1 serving as an electronic switch, a signal resistor S1 and a water submerging signal circuit; the n levels of water level monitoring sub-circuits which are arranged in series at equal intervals are cascaded, ngt; 1, each stage of sub-circuit has the same structure; one ends of the n stages of MOS tubes M1-Mn are connected in parallel to serve as a water level signal output end to output a water level monitoring signal Vo, and the voltage division circuit is formed by sequentially connecting signal resistors S1-Sn end to end and outputs a voltage division signal V1-V (n-1). A water body is utilized to contact with a monitoring electrode to determine the conduction of MOS (Metal Oxide Semiconductor) tubes, so that the MOS tubes M1-MN are conducted, a short-circuit signal resistor M2-MN (N is more than or equal to 2 and less than or equal to n) is further conducted, finally, a microprocessor MCU (Microprogrammed Control Unit) uses an ADC (Analog to Digital Converter) to carry out analog-to-digital conversion on Vo to obtain a voltage value, and water level information is obtained through calculation.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of water level measurement, in particular to a MOS transistor parallel type electronic water gauge circuit. BACKGROUND

[0002] The electronic water gauge (electrode type water level sensor) is a kind of water level measurement sensor, which uses the conductivity of water to collect water depth information through signal monitoring electrodes arranged in equal intervals in series. The signal monitoring electrodes of the collection circuit can determine whether the electrodes contact the water body according to the potential height, and determine the water depth according to the number of electrodes immersed in water. The electronic water gauges on the market are mainly composed of a circuit board, a common electrode, a monitoring electrode, an epoxy resin, a metal shell, etc. The common electrode is connected to the metal shell, the monitoring electrode is connected to the PCB circuit board, and the common electrode and the monitoring electrode are exposed to the water.

[0003] The electronic water gauge generally uses digital logic chips, resistors, capacitors and other components, and the chip power consumption is hundreds of microamperes, the cost is low, the patch area is large (belongs to integrated circuit), and it is easy to integrate on the PCB board. Like a voltage comparator, it also belongs to a kind of low-power water monitoring circuit, as follows: (1) Remote electronic water gauge, utility model patent, application number CN201520716037.4: the circuit part contains a digital logic circuit board, a wireless transmission module, a rechargeable battery and a voltage stabilizing circuit board, and a probe (electrode) electrically connected with the digital logic circuit board.

[0004] (2) A new type of electronic water gauge, utility model patent, application number CN201721276232.5: the sensing and measuring body uses mechanical method to position the water level change, and carries out digital coding processing through analog-digital conversion module, realizes digital division, digital sampling and digital transmission, and transmits the digital signal converted from the analog signal to the central controller.

[0005] (3) Integrated multi-segment search type intelligent electronic water gauge, utility model patent, publication (announcement) number CN201520468625.0: the data acquisition unit sensing acquisition module contains a plurality of contacts (electrodes), the contacts contain a contact power supply module, a contact level acquisition module and a signal return module. SUMMARY

[0006] The technical problem to be solved by the present application is to overcome the above technical defects and provide an electronic water gauge circuit with simple combination logic circuit and high-speed acquisition.

[0007] To solve the above technical problems, the technical scheme provided by the present application is as follows: a MOS transistor parallel type electronic water gauge circuit, the circuit is composed of a plurality of water level monitoring sub-circuit cascaded in equal intervals in series, a voltage dividing circuit, a power supply VCC and a bias power supply. The first-level water level monitoring sub-circuit includes a MOS transistor M1 as an electronic switch, a signal resistor S1, and a flooding signal circuit. The flooding signal circuit controls the conduction and cutoff of the MOS transistor M1. One end of the signal resistor S1 is connected to the MOS transistor M1, and the other end is connected to the negative terminal of the power supply. The n-level water level monitoring sub-circuits are cascaded in series with equal spacing, where n>1, and each sub-circuit has the same structure. One end of each of the MOS transistors M1~Mn is connected together as the water level signal output terminal, which outputs the water level monitoring signal Vo. The other end is connected to the voltage divider circuit, which outputs the voltage divider signals V1~V(n-1). The voltage divider circuit is formed by connecting signal resistors S1 to Sn sequentially end to end.

[0008] Preferably, the bias power supply is connected to a flooding signal circuit, which includes a resistor R1 and a monitoring electrode X1.

[0009] Preferably, the bias power supply is a negative bias power supply VEE, satisfying VEE - VCC < V TP V TP This is the turn-on threshold voltage of the PMOS transistor; The monitoring electrode X1 is connected to both resistor R1 and the gate of PMOS transistor M1. The other end of resistor R1 is connected to the positive terminal of power supply VCC. The source of PMOS transistor M1 is connected to one end of signal resistor S1, i.e., voltage divider signal V1. The drain of PMOS transistor M1 outputs water level monitoring signal Vo.

[0010] Preferably, the bias power supply is a positive bias power supply VBIAS, satisfying VBIAS > VCC + V TN V TN This is the NMOS transistor's turn-on threshold voltage; The monitoring electrode X1 is connected to both resistor R1 and the gate of NMOS transistor M1. The drain of NMOS transistor M1 is connected to one end of signal resistor S1, i.e., voltage divider signal V1. The source of NMOS transistor M1 outputs water level monitoring signal Vo.

[0011] Preferably, when the monitoring electrode XN of the Nth (1≤N≤n) level water level monitoring sub-circuit comes into contact with water, the NMOS transistors M1 to MN are turned on; The output water level monitoring signal Vo≈V1≈VN = VCC×S1 / (S1 + S(N + 1) + S(N + 2) + … +Sn).

[0012] Preferably, when the monitoring electrode XN of the Nth (1≤N≤n) level water level monitoring sub-circuit comes into contact with water, the PMOS transistors M1~MN are turned on; The output water level monitoring signal Vo≈V1≈VN=VCC×S1 / (S1+S(N + 1)+S(N + 2)+…+Sn).

[0013] Preferably, the signal resistors S1 to Sn are of equal value, i.e., S1 = S2 = S3 = … = Sn = R, and the value of R is set based on the current drawn by the ADC converter. When the Nth (1≤N≤n) level monitoring electrode XN comes into contact with water: The output water level monitoring signal Vo≈V1≈VN = VCC×S1 / (S1 + S(N + 1) + S(N + 2) + … +Sn) = VCC / (n - N + 1).

[0014] Preferably, the signal resistors S1 to Sn are proportional resistors with a common ratio q = 1.025, and the Nth (1≤N≤n) level resistor SN = S1×q. (N - 1) The total resistance of the n-stage resistors, Sum = S1 + S2 + S3 + ... + Sn = S1(1 - q) n ) / (1 - q); When the Nth (1≤N≤n) level monitoring electrode XN comes into contact with water, the output water level monitoring signal Vo≈V1≈VN; .

[0015] The advantages of this invention compared with the prior art are as follows: In this invention, the water contact monitoring electrode is used to determine the conduction of the MOS transistor, thereby short-circuiting the corresponding signal resistors of the two MOS transistors. Different voltage division signals are output according to the number of resistors short-circuited. Finally, the microprocessor MCU uses AD to perform analog-to-digital conversion to obtain the voltage value and calculates the water level information. Two circuit design schemes and theoretical analyses for PMOS and NMOS transistors are presented. MOS transistors are used as "mid-range switches" or "high-range switches," and simulation verification is performed, enriching the implementation methods of electronic water level gauge hardware circuits. Attached Figure Description

[0016] Figure 1 This is a block diagram illustrating the principle of the electronic water level gauge of the present invention. Figure 2 The schematic diagram of the parallel PMOS tube electronic water level gauge circuit of the present invention (n = 12); Figure 3 The schematic diagram of the parallel NMOS transistor electronic water level gauge circuit of the present invention (n = 12); Figure 4 for Figure 2 Simulation diagram of a 12-level electronic water level gauge circuit (Implementation method 1: Level 1 water level); Figure 5 for Figure 2 Simulation diagram of a 12-level electronic water level gauge circuit (Implementation method 1: four-level water level); Figure 6 for Figure 2 Simulation diagram of 12-level electronic water level gauge circuit (Implementation method 1: seven-level water level).

[0017] Figure 7 for Figure 3 Simulation diagram of a 12-level electronic water level gauge circuit (Implementation method 2: Level 1 water level); Figure 8 for Figure 3 Simulation diagram of a 12-level electronic water level gauge circuit (Implementation method 2: four-level water level); Figure 9 for Figure 3 Simulation diagram of 12-level electronic water level gauge circuit (Implementation method 2: seven-level water level). Detailed Implementation

[0018] The present invention will now be described in further detail with reference to the accompanying drawings.

[0019] The principle block diagram of the electronic water level gauge of this invention is as follows: Figure 1 As shown: Resistors S1, S2, ..., Sn are connected in series (end to end) to form a voltage divider circuit (potentiometer). One end of electronic switches M1, M2, ..., Mn is connected in parallel as the water level signal output terminal Vo. One end of S1 is connected to the negative terminal of the power supply. The other end of electronic switch M1 is connected to node V1, where S1 and S2 are connected. The other end of electronic switch M2 is connected to node V2, where S2 and S3 are connected. ... The other end of electronic switch M(n-1) is connected to node V(n-1), where S(n-1) and Sn are connected. The other end of electronic switch Mn is connected to node VCC (Vn), where Sn and the power supply VCC are connected. S1 is the low end of the potentiometer. All electronic switches M1, M2, ..., Mn (PMOS or NMOS transistors) are equivalent to being connected in parallel, which is equivalent to the middle (M1~M(n-1)) or high (Mn) electronic switches of the potentiometer (relative to S1).

[0020] When the first-stage monitoring electrode X1 is not in contact with water, the electronic switches (PMOS or NMOS transistors) M1, M2, ..., Mn are all off, and the output water level monitoring signal Vo is approximately 0V. If the first-stage monitoring electrode X1 is submerged in water, the MOS transistor M1 is turned on. The on-resistance of M1 is very small (tens of milliohms, much smaller than the resistance of resistor S1). The voltage divider signal V1 outputs the water level signal Vo through the low-impedance path (transistor M1). The on-resistance voltage drop of M1 is negligible, i.e., Vo≈V1. Resistors S1, S2, ..., Sn form a voltage divider circuit, and the output water level monitoring signal Vo≈V1 = VCC×S1 / (S1 + S2 + S3 + ... + Sn).

[0021] From the above analysis, we know that when M1 is turned on and the monitoring electrode X2 of the second-stage water level monitoring sub-circuit is not in contact with water, M2 is turned off, and the output water level monitoring signal Vo≈V1 remains unchanged. Conversely, when the second-stage monitoring electrode X2 is in contact with water, M2 is turned on, and node V2 returns to node V1 via the low-impedance path M2, node Vo, and M1. Resistor S2 is short-circuited by MOSFETs M1 and M2, and the on-state voltage drop of M1 and M2 is negligible. The current through resistor S2 of the voltage divider signal V2 is negligible, i.e., V1≈V2. Resistors S1, M1, M2, S3, ..., Sn constitute a voltage divider circuit, and the output water level monitoring signal Vo≈V1≈V2 = VCC×S1 / (S1+ S3 + S4 + ... + Sn).

[0022] From the above analysis, we know that M1 and M2 are already conducting. When the monitoring electrode X3 of the third-stage water level monitoring sub-circuit is not in contact with water, M3 is cut off, and the output water level monitoring signal Vo≈V2 remains unchanged. Conversely, when the third-stage monitoring electrode X3 is in contact with water, M3 is conducting. Node V3 flows through the low-impedance path M3, node Vo, and M2 to node V2. Resistors S2~S3 are short-circuited by MOSFETs M1 and M3. The conduction voltage drop of M1 and M3 is negligible, and the current of the voltage divider signal V3 through resistors S3~S2 is negligible, i.e., V1≈V3. Resistors S1, M1, M3, S4, ..., Sn constitute a voltage divider circuit, and the output water level monitoring signal Vo≈V1≈V3 = VCC×S1 / (S1 + S4 + S5 + ... + Sn).

[0023] As can be seen from the above analysis, M1, M2, ..., M(N-1) are already conducting. When the monitoring electrode XN of the Nth (natural number N: 3≤N≤n) level water level monitoring sub-circuit is not in contact with water, MN is cut off, and the output water level monitoring signal Vo≈V(N-1) remains unchanged. Conversely, when the Nth level monitoring electrode XN is in contact with water, MN is conducting, and node VN passes through the low-impedance path MN, node Vo, and M(N-1) to node V(N-1). Resistors S2~SN are short-circuited by MOS transistors M1 and MN. The conduction voltage drop of M1 and MN is negligible, and the current of the voltage divider signal VN through resistors SN~S2 is negligible, i.e., V1≈VN. Resistors S1, M1, MN, S(N+1), ..., Sn form a voltage divider circuit, outputting a water level monitoring signal Vo≈V1≈VN = VCC×S1 / (S1 + S(N+1) + S(N+2) + … + Sn).

[0024] The monitoring water level signals obtained by the other water level monitoring sub-circuits at each level are obtained in the same manner. Implementation Method 1

[0025] This invention discloses a parallel PMOS transistor electronic water level gauge circuit, which consists of cascaded water level monitoring sub-circuits arranged in series at equal intervals, a voltage divider circuit, a power supply VCC, a negative bias power supply VEE, etc., satisfying VEE - VCC < V TP V TP The turn-on threshold voltage of the PMOS transistor is shown in the schematic diagram. Figure 2 The diagram shows a water level monitoring circuit with n = 12 levels. The first-level water level monitoring sub-circuit is located at the lowest water level of the electronic water gauge and consists of a PMOS transistor M1, resistors S1 and R1, and a monitoring electrode X1. The negative bias power supply VEE, resistor RG, and common electrode G1 form a common part. In the circuit, the monitoring electrode X1 is connected to both resistor R1 and the gate (G) of PMOS transistor M1. The other end of R1 is connected to the positive terminal of the power supply VCC. The source (S) of PMOS transistor M1 is connected to one end of the signal resistor S1 (node ​​V1), and the other end of the signal resistor S1 is connected to the negative terminal of the power supply. The drain (D) of PMOS transistor M1 is the water level monitoring signal Vo, and W1 is the water resistance.

[0026] When the monitoring electrode X1 and the common electrode G1 (connected to the negative bias power supply VEE through resistor RG) are not in contact with water, the gate voltage of PMOS transistor M1 is approximately VCC, and the source voltage V1 is less than VCC. The voltage difference V between the gate and source of PMOS transistor M1 is V. GSWhen the voltage is greater than 0V, PMOS transistor M1 is cut off. Although resistors S1, S2, ..., Sn form a voltage divider circuit, the output water level monitoring signal Vo ≈ 0V. If monitoring electrodes X1 and G1 are submerged, analog switch D1 closes, and the voltage of monitoring electrode X1 changes from high level to negative level (the gate voltage of PMOS transistor M1: (VCC×W1 + VEE×R1) / (W1 + R1) is a negative voltage). The voltage difference V between the gate and source of PMOS transistor M1... GS Less than the turn-on threshold voltage V of PMOS transistor M1 TP V GS <V TP When PMOS transistor M1 is turned on, its on-resistance is very small (tens of milliohms, much smaller than the resistance of resistor S1). The voltage divider signal V1 passes through the low-impedance path (PMOS transistor M1) to obtain the voltage divider signal Vo. The on-voltage drop of PMOS transistor M1 is negligible. Resistors S1, S2, ..., Sn form a voltage divider circuit, and the output water level monitoring signal Vo ≈ V1 = VCC × S1 / (S1 + S2 + ... + Sn).

[0027] As can be seen from the above analysis, when the monitoring electrode X2 of the second-stage water level monitoring sub-circuit is not in contact with water, the M2 transistor is cut off; conversely, when the monitoring electrode X2 is in contact with water, the analog switches D1~D2 are closed (the other analog switches are open), the M1~M2 transistors are turned on, and V2 passes through the M2 transistor to obtain the water level monitoring signal Vo (almost no voltage drop). The resistor S2 is short-circuited by the PMOS transistors M1 and M2. The on-state voltage drop of the PMOS transistors M1 and M2 can be ignored. The current of the voltage divider signal V2 passing through S2 is negligible. The resistors S1, M1, M2, S3, S4, ..., Sn constitute a voltage divider circuit, and the output water level monitoring signal Vo≈V1≈V2 = VCC×S1 / (S1 + S3 + S4 + …+ Sn).

[0028] As can be seen from the above analysis, when the monitoring electrode X3 of the third-stage water level monitoring sub-circuit is not in contact with water, the M3 transistor is cut off; conversely, when the monitoring electrode X3 is in contact with water, the analog switches D1~D3 are closed (the other analog switches are open), the M1~M3 transistors are turned on, and V3 passes through the M3 transistor to obtain the water level monitoring signal Vo (with almost no voltage drop). The resistors S2~S3 are short-circuited by the PMOS transistors M1 and M3. The on-state voltage drop of the PMOS transistors M1 and M3 can be ignored. The current of the voltage divider signal V3 through S3~S2 is negligible. The resistors S1, M1, M3, S4, S5, ..., Sn form a voltage divider circuit. The output water level monitoring signal Vo≈V1≈V3 = VCC×S1 / (S1 + S4 + S5 + ... + Sn).

[0029] As can be seen from the above analysis, when the monitoring electrode XN of the Nth (natural number N: 4≤N≤n) level water level monitoring sub-circuit is not in contact with water, the MN tube is cut off; conversely, when the monitoring electrode XN is in contact with water, the analog switches D1~DN are closed (the other analog switches are open), the M1~MN tubes are turned on, and VN passes through the MN tube to obtain the water level monitoring signal Vo (almost no voltage drop). The resistors S2~SN are short-circuited by the PMOS tubes M1 and MN. The on-state voltage drop of the PMOS tubes M1 and MN can be ignored. The current of the voltage divider signal VN through SN~S2 is negligible. The resistors S1, M1, MN, and S(N + 1)~Sn constitute a voltage divider circuit. The output water level monitoring signal Vo≈V1≈VN = VCC×S1 / (S1 + S(N + 1) + S(N + 2) + … + Sn).

[0030] The monitoring water level signals obtained by the other water level monitoring sub-circuits at each level are obtained in the same manner.

[0031] Signal resistance values: Considering the ease of data processing by the MCU microprocessor after ADC conversion, it is preferable to select equal signal resistance values ​​for each stage of the water level monitoring sub-circuit, i.e., S1 = S2 = S3 = … = Sn = R. Since ADC converters generally require a certain current draw to operate normally, the total signal resistance value is n×R, where the range of R depends on the magnitude of the current drawn by the ADC converter. PMOS transistor on-resistance R DS(ON) The resistance is tens of milliohms (much smaller than the resistance R), since the signal only passes through two PMOS transistors, M1 and MN, i.e., 2 × R. DS(ON) With a strength on the order of tens of milliohms, R is much greater than 2 × R. DS(ON) If the total signal resistance is too large, the ADC conversion voltage error will increase; if the signal resistance is too small, the power consumption will be high. Therefore, the value of R must be appropriately balanced to meet the usage requirements, and high-precision resistors should be preferred.

[0032] The calculation and analysis process is as follows: When the monitoring electrodes X1~Xn are not in contact with water (equivalent to level 0 water level), tubes M1, M2, ..., Mn are all cut off, and the power supply VCC forms a voltage divider circuit through the signal resistors S1~Sn. At this time, Vo≈0V.

[0033] When the first-stage monitoring electrode X1 comes into contact with water, analog switch D1 is closed (the other analog switches are open), tube M1 is turned on, and tubes M2, ..., Mn are turned off. The power supply VCC passes through Sn~S1 to the negative terminal of the power supply in sequence. The voltage drop of tube M1 is negligible. The output water level monitoring signal Vo≈V1=VCC×S1 / (S1+S2+...+Sn)=VCC / n.

[0034] When the second-stage monitoring electrode X2 comes into contact with water, analog switches D1~D2 are closed (the rest of the analog switches are open), M1~M2 are turned on, M3, ..., Mn are turned off, S2 is short-circuited by M1 and M2, and the power supply VCC passes through Sn, S(n-1), ..., S3, M2, M1, S1 to the negative terminal of the power supply in sequence. The voltage drop of M1~M2 when they are turned on is negligible. The output water level monitoring signal Vo≈V1≈V2=VCC×S1 / (S1+S3+S4+...+Sn)=VCC / (n-1).

[0035] When the third-level monitoring electrode X3 comes into contact with water, analog switches D1~D3 are closed (the rest of the analog switches are open), M1~M3 are turned on, M4, ..., Mn are turned off, and S2~S3 are short-circuited by M1 and M3. The power supply VCC passes through Sn, S(n-1), ..., S4, M3, M1, S1 to the negative terminal of the power supply in sequence. The voltage drop of M1 and M3 is negligible. The output water level monitoring signal Vo≈V1≈V3=VCC×S1 / (S1+S4+...+Sn)=VCC / (n-2).

[0036] When the Nth (4≤N≤n) level monitoring electrode XN comes into contact with water, the analog switches D1~DN are closed (the rest of the analog switches are open), the M1~MN tubes are turned on, the M(N+1) tubes, ..., Mn tubes are turned off, and the S2~SN tubes are short-circuited by the M1 tubes and the MN tubes. The power supply VCC passes through Sn, S(n-1), ..., S(N+1), MN, M1, S1 to the negative terminal of the power supply in sequence. The voltage drop of the M1 tubes and the MN tubes is negligible. The output water level monitoring signal Vo≈V1≈VN=VCC×S1 / (S1+S(N+1)+S(N+2)+...+Sn)=VCC / (n-N+1).

[0037] ADC Converter: Currently, microcontrollers have multiple built-in ADCs (M = 12 / 14 / 16 bits). To ensure resolution, the voltage difference between the voltage in the absence of water and the first-stage quantization stage must satisfy: VCC / n - VCC / (n + 1) ≥ VCC / 2 M n(n + 1)≤2 M When M = 12, n ≤ 63; when M = 14, n ≤ 127; when M = 16, n ≤ 255. The quantization levels are 63, 127, and 255 respectively. If the spacing between the signal monitoring electrodes is 1 cm, and the measurement ranges are 63 cm, 127 cm, and 255 cm respectively, then approximately n = 100 cascade levels of the electronic water level gauge will meet the requirements.

[0038] Therefore, we can determine the level of the monitoring electrodes based on the voltage signal acquired by the MCU, and thus obtain the water level information. Furthermore, S1~Sn can also be selected as either a geometric series resistor or an arithmetic series resistor, as detailed below.

[0039] Currently, the resistors used in electronic products, namely the E48, E96, and E192 series, are proportional resistors with common ratios q of 1.052, 1.025, and 1.012, respectively. Their accuracy errors are ±2%, ±1%, and ±0.5% / 0.2% / 0.1%, respectively. E192 resistors have high accuracy but are more expensive. We prioritize the use of E96 resistors, which offer better cost performance.

[0040] According to the formula for a geometric series, the common ratio q = 1.025, and the resistance of the Nth (1≤N≤n) stage is SN = S1×q. (N - 1) The total resistance of the n-stage resistors, Sum = S1 + S2 + S3 + ... + Sn = S1(1 - q) n ) / (1 - q).

[0041] according to Figure 1 , Figure 2 The calculation and analysis process is as follows: When the monitoring electrodes X1~Xn are not in contact with water, tubes M1, M2, ..., Mn are cut off, and the power supply VCC passes through Sn, S(n-1), ..., S3, S2, S1 to the negative terminal of the power supply, and the output water level monitoring signal Vo≈0V is generated.

[0042] When the first-stage monitoring electrode X1 comes into contact with water, analog switch D1 is closed (the other analog switches are open), tube M1 is turned on, and tubes M2, ..., Mn are turned off. The power supply VCC passes through Sn~S1 to the negative terminal of the power supply in sequence. The voltage drop of tube M1 is negligible. The output water level monitoring signal Vo≈V1 is as shown in equation (1):

[0043] When the second-stage monitoring electrode X2 comes into contact with water, analog switches D1~D2 are closed (the rest of the analog switches are open), tubes M1 and M2 are turned on, and tubes M3, ..., Mn are turned off. The power supply VCC passes through Sn, S(n-1), ..., S3, M2, M1, S1 to the negative terminal of the power supply in sequence. The voltage drop of tubes M1 and M2 is negligible. The output water level monitoring signal Vo≈V1≈V2, as shown in equation (2):

[0044] When the Nth (4≤N≤n) level monitoring electrode XN comes into contact with water, the analog switches D1~DN are closed (the rest of the analog switches are open), tubes M1, M2, ..., MN are turned on, and tubes M(N + 1), ..., Mn are turned off. The power supply VCC passes through Sn, S(n - 1), ..., S(N + 1), MN, M1, S1 to the negative terminal of the power supply in sequence. The voltage drop of tubes M1, M2, ..., MN is negligible. The output water level monitoring signal Vo≈V1≈VN is shown in equation (3):

[0045] ADC converter: Currently, microcontrollers have multiple built-in ADCs (M = 12 / 14 / 16 / 18 / 20 bits). In order to ensure resolution, the quantization voltage difference between the first-level and second-level water levels must meet the condition, as shown in equation (4):

[0046] Let X=q n -1, as shown in equation (5):

[0047] The rearranged formula (5) is shown in formula (6):

[0048] Solving the quadratic equation in one variable, when equation (6) takes the equality sign, we get equation (7):

[0049] Since 4q(2 M -1)>>q 2 Simplifying the calculation of equation (7), 4q(2 M -1)+q 2 ≈4q(2 M -1)≈4q2 M Equation (8) is obtained:

[0050] If M=12 and q=1.025, the range of values ​​for n is shown in equation (9):

[0051] The range of values ​​for the cascade series n in other cases is shown in Table 1 below.

[0052]

[0053] If the spacing between the signal monitoring electrodes is 1 cm, then M = 16, q = 1.012, and n = 119 are selected. A cascade number of n = 100 for the electronic water level gauge can meet the requirements. However, the drawback is that over 100 types of resistors need to be soldered. The number of cascaded stages obtained with the same ADC bit depth is less than that of the same signal resistors in Implementation Method 1. Therefore, Implementation Method 1 is preferred.

[0054] This circuit consists of a power supply VCC, a water level signal Vo, a negative power supply terminal, and a negative bias power supply. The output water level monitoring signal Vo is an analog signal that needs to be processed by an ADC. Compared to digital signals, this analog signal has the advantages of ultra-low power consumption and strong anti-interference capability. Implementation Method 2

[0055] The difference between Implementation Method 2 and Implementation Method 1 lies in the selection of MOS transistor type: Implementation Method 1 uses PMOS transistor, while Implementation Method 2 uses NMOS transistor.

[0056] This invention discloses another NMOS transistor parallel electronic water level gauge circuit. The circuit consists of cascaded water level monitoring sub-circuits arranged in series at equal intervals, a voltage divider circuit, a power supply VCC, and a positive bias power supply VBIAS, etc., which must satisfy VBIAS > VCC + V TN V TN The NMOS transistor's turn-on threshold voltage is shown in the schematic diagram. Figure 3 The diagram shows a water level monitoring circuit with n = 12 levels. The first-level water level monitoring sub-circuit is located at the lowest water level of the electronic water gauge and consists of an NMOS transistor M1, resistors S1 and R1, and a monitoring electrode X1. The positive bias power supply VBIAS, resistor RG, and common terminal G1 are common components. In the circuit, the monitoring electrode X1 is connected to both R1 and the gate (G) of the NMOS transistor M1. The drain (D) of the NMOS transistor M1 is connected to one end of the signal resistor S1 (node ​​V1). The other end of the signal resistor S1 and R1 is connected to the negative terminal of the power supply. The source (S) of the NMOS transistor M1 is the water level monitoring signal Vo, and W1 is the water resistance.

[0057] When the monitoring electrode X1 and the common electrode G1 (connected to the positive bias power supply VBIAS through resistor RG) are not in contact with water, the gate voltage of NMOS transistor M1 is approximately 0V and the source voltage Vo is approximately 0V. The voltage difference V between the gate and source of NMOS transistor M1 is... GS The voltage is approximately 0V, so NMOS transistor M1 is cut off. Although resistors S1, S2, ..., Sn form a voltage divider circuit, the output water level monitoring signal Vo ≈ 0V. If monitoring electrodes X1 and G1 are submerged, analog switch D1 closes, and the voltage of monitoring electrode X1 changes from low to high (R1 is much larger than W1, VBIAS × R1 / (W1 + R1) ≈ VBIAS is high). The voltage difference V between the gate and source of NMOS transistor M1... GS Greater than the NMOS transistor M1's turn-on threshold voltage V TN V GS ≈VBIAS - VCC>V TN When NMOS transistor M1 is turned on, its on-resistance is very small (tens of milliohms, much smaller than the resistance of resistor S1). The voltage divider signal V1 passes through the low-impedance path (NMOS transistor M1) to obtain the voltage divider signal Vo. Its on-resistance drop is negligible. Resistors S1, S2, ..., Sn form a voltage divider circuit. The output water level monitoring signal Vo≈V1 =VCC×S1 / (S1 + S2 + … + Sn).

[0058] As can be seen from the above analysis, when the monitoring electrode X2 of the second-stage water level monitoring sub-circuit is not in contact with water, the M2 transistor is cut off; conversely, when the monitoring electrode X2 is in contact with water, the analog switches D1~D2 are closed (the other analog switches are open), the M1~M2 transistors are turned on, and V2 passes through the M2 transistor to obtain the water level monitoring signal Vo (with almost no voltage drop). S2 is short-circuited by the NMOS transistors M1 and M2, and the current of the voltage divider signal V2 passing through S2 is negligible. Resistors S1, M1 transistor, M2 transistor, and S3~Sn form a voltage divider circuit, and the output water level monitoring signal Vo≈V1≈V2 = VCC×S1 / (S1 + S3 + S4 + … + Sn).

[0059] As can be seen from the above analysis, when the monitoring electrode X3 of the third-stage water level monitoring sub-circuit is not in contact with water, the M3 transistor is cut off; conversely, when the monitoring electrode X3 is in contact with water, the analog switches D1~D3 are closed (the other analog switches are open), the M1~M3 transistors are turned on, and V3 passes through the M3 transistor to obtain the water level monitoring signal Vo (with almost no voltage drop). S2~S3 are short-circuited by the NMOS transistors M1 and M3. The current of the voltage divider signal V3 passing through S3~S2 is negligible. Resistors S1, M1 transistor, M3 transistor, and S4~Sn form a voltage divider circuit, and the output water level monitoring signal Vo≈V1≈V2≈V3 = VCC×S1 / (S1 + S4 + S5 + … + Sn).

[0060] As can be seen from the above analysis, when the monitoring electrode XN of the Nth (natural number N: 4≤N≤n) level water level monitoring sub-circuit is not in contact with water, the MN tube is cut off; conversely, when the monitoring electrode XN is in contact with water, the analog switches D1~DN are closed (the other analog switches are open), the M1~MN tubes are turned on, and VN passes through the MN tube to obtain the water level monitoring signal Vo (almost no voltage drop). S2~SN are short-circuited by the NMOS tubes M1 and MN. The current of the voltage divider signal VN through SN~S2 is negligible. The resistors S1, M1, MN, and S(N + 1)~Sn form a voltage divider circuit, and the output water level monitoring signal Vo≈V1≈VN = VCC×S1 / (S1 + S(N + 1) + S(N + 2) + … +Sn).

[0061] The monitoring water level signals obtained by the other water level monitoring sub-circuits at each level are obtained in the same manner.

[0062] Signal resistance value S1: Considering the ease of data processing by the MCU microprocessor after ADC conversion, it is preferable to select signal resistances of equal magnitude for each stage of the water level monitoring sub-circuit, i.e., S1 = S2 = S3 = … = Sn = R. Since ADC converters generally require a certain current draw to operate normally, the total signal resistance is n×R, where R's value depends on the current draw of the ADC converter and the NMOS transistor's on-resistance R.DS(ON) The resistance is tens of milliohms (much smaller than the resistance R). Since the signal only passes through two NMOS transistors, M1 and MN, that is, 2 × R. DS(ON) With a value on the order of milliohms, R is much greater than 2×R. DS(ON) If the total signal resistance is too large, the ADC conversion voltage error will increase; if the signal resistance is too small, the power consumption will be large. Therefore, the value of R must be appropriately balanced to meet the usage requirements, and high-precision resistors should be selected first.

[0063] The calculation and analysis process is as follows: When the monitoring electrodes X1~Xn are not in contact with water (equivalent to level 0 water level), tubes M1, M2, ..., Mn are all cut off. Although the power supply VCC forms a voltage divider circuit through the signal resistors S1~Sn, Vo≈0V.

[0064] When the first-stage monitoring electrode X1 comes into contact with water, analog switch D1 is closed (the other analog switches are open), tube M1 is turned on, and tubes M2, ..., Mn are turned off. The power supply VCC passes through Sn~S1 to the negative terminal of the power supply in sequence. The voltage drop of tube M1 is negligible. The output water level monitoring signal Vo≈V1 = VCC×S1 / (S1 + S2 + … + Sn) = VCC / n.

[0065] When the second-stage monitoring electrode X2 comes into contact with water, analog switches D1~D2 are closed (the rest of the analog switches are open), M1 and M2 are turned on, M3, ..., Mn are turned off, and S2 is short-circuited by M1 and M2. The power supply VCC passes through Sn, S(n - 1), ..., S3, M2, M1, and S1 to the negative terminal of the power supply in sequence. The voltage drop of M1 and M2 when they are turned on is negligible. The output water level monitoring signal Vo≈V1≈V2 = VCC×S1 / (S1 + S3 + S4 + … + Sn) = VCC / (n - 1).

[0066] When the third-level monitoring electrode X3 comes into contact with water, analog switches D1~D3 are closed (the rest of the analog switches are open), M1, M2, and M3 are turned on, and M4, ..., Mn are turned off. S2~S3 are short-circuited by M1 and M3. The power supply VCC passes through Sn, S(n-1), ..., S4, M3, M1, and S1 to the negative terminal of the power supply in sequence. The voltage drop of M1 and M3 when they are turned on is negligible. The output water level monitoring signal Vo≈V1≈V2≈V3 = VCC×S1 / (S1 + S4 + … + Sn) = VCC / (n-2).

[0067] When the Nth (4≤N≤n) level monitoring electrode XN comes into contact with water, the analog switches D1~DN are closed (the rest of the analog switches are open), M1, M2, ..., MN are turned on, M(N + 1), ..., Mn are turned off, and S2~SN are short-circuited by M1 and MN. The power supply VCC passes through Sn, S(n - 1), ..., S(N + 1), MN, M1, S1 to the negative terminal of the power supply in sequence. The voltage drop of M1 and MN is negligible. The output water level monitoring signal Vo≈V1≈VN = VCC×S1 / (S1 + S(N + 1) + S(N + 2) + … + Sn) = VCC / (n - N + 1).

[0068] The monitoring water level signals obtained by the other water level monitoring sub-circuits at each level are obtained in the same manner.

[0069] ADC Converter: Currently, microcontrollers have multiple built-in ADCs (M = 12 / 14 / 16 bits). To ensure resolution, the voltage difference between the voltage in the absence of water and the first-stage quantization stage must satisfy: VCC / n - VCC / (n + 1) ≥ VCC / 2 M That is, n(n + 1)≤2 M When M = 12, n ≤ 63; when M = 14, n ≤ 127; when M = 16, n ≤ 255. The number of quantization levels are 63, 127, and 255 respectively. If the spacing between the signal monitoring electrodes is 1 cm, the measurement ranges are 63 cm, 127 cm, and 255 cm respectively. The number of cascaded electronic water level gauges is approximately n = 100, which meets the requirements.

[0070] Therefore, we can determine the level of the monitoring electrodes based on the voltage signal acquired by the MCU, and thus obtain the water level information. Furthermore, S1~Sn can also be selected as geometric series resistors or arithmetic series resistors; please refer to Implementation Method 1 for details, which will not be elaborated further. Implementation Simulation

[0071] according to Figure 2 , Figure 3 The circuit was simulated and tested using Multisim (version V14.0) software from National Instruments. The PMOS transistor selected was from ON Semiconductor, model NVTFS5124PLTAG, with a minimum turn-on threshold voltage of V. TP(MIN) = -1.5V, maximum value V TP(MAX) = -2.5V, typical value V not given. TP The conduction current can reach -6A, and the conduction impedance R DS(ON) = 260mΩ (V GS = -10V), R DS(ON)= 380mΩ (V GS = -4.5V), let's take the turn-on threshold voltage V TP = -2.5V. The NMOS transistor used is from NXP, model BSP030, with a minimum turn-on threshold voltage of V. TN(MIN) = 1V, maximum value V TN(MAX) = 2.8V, typical value V not given TN The conduction current reaches 10A, and the conduction impedance R DS(ON) =30mΩ (V) GS = 10V), R DS(ON) = 50mΩ (V GS = 4.5V), let's take the turn-on threshold voltage V. TN = 2.8V.

[0072] When n = 12, for ease of calculation, the series resistance of each water level monitoring sub-circuit is chosen to be equal to that of S1, i.e., S1 = S2 = S3 = … = S12 = R = 1kΩ, power supply VCC = 3.3V, negative bias power supply VEE = -10V, positive bias power supply VBIAS = 10V, and the water resistance WN = 100kΩ (1≤N≤12, generally ranging from a few kΩ to several hundred kΩ, the specific resistance value depends on the contact area and distance between the monitoring electrode and the common electrode, and the conductivity of the liquid); when the monitoring electrode XN is exposed to water, the simulated switch DN is closed and the MOS transistor MN is turned on; when the monitoring electrode XN is dry, the simulated switch DN is open and the MOS transistor MN is turned off. The simulation results are shown below. Implementation Method 1: Simulation

[0073] (1) When the first-stage monitoring electrode X1 contacts water (N = 1): Analog switch D1 is closed (the rest of the analog switches are open), PMOS transistor M1 is turned on (the rest M2~M12 are turned off), and the power supply VCC passes through S12, S11, ..., S3, S2, S1 to the negative terminal of the power supply in sequence, and outputs a water level monitoring signal Vo = 0.275196V (measured with a multimeter). The specific simulation is as follows: Figure 4 As shown, it is consistent with the theoretical voltage Vo = VCC / n = VCC / 12 = 0.275V, with a relative error of approximately 0.07%.

[0074] (2) When the fourth-stage monitoring electrode X4 contacts water (N = 4): Analog switches D1~D4 are closed (the rest of the analog switches are open), PMOS transistors M1~M4 are turned on (the rest M5~M12 are turned off), and the power supply VCC passes through S12, S11, ..., S5, M4, M1, S1 to the negative terminal of the power supply in sequence, outputting a water level monitoring signal Vo = 0.366882V (measured with a multimeter). The specific simulation is as follows: Figure 5As shown, it is consistent with the theoretical voltage Vo = VCC / (n - N + 1) = VCC / 9 = 0.3667V, with a relative error of approximately 0.05%.

[0075] (3) When the seventh-level monitoring electrode X7 contacts water (N = 7): Analog switches D1~D7 are closed (the rest of the analog switches are open), PMOS transistors M1~M7 are turned on (the rest M8~M12 are turned off), and the power supply VCC passes through S12, S11, ..., S8, M7, M1, S1 to the negative terminal of the power supply in sequence, outputting a water level monitoring signal Vo = 0.550181V (measured with a multimeter). The specific simulation is as follows: Figure 6 As shown, it is consistent with the theoretical voltage Vo = VCC / (n - N + 1) = VCC / 6 = 0.55V, with a relative error of approximately 0.03%.

[0076] Therefore, we can determine the level of the monitoring electrode based on the voltage signal acquired by the MCU, and thus obtain the water level information. The simulation test data from no water contact to level 12 is shown in Table 2.

[0077]

[0078] Implementation Method Two: Simulation (1) When the first-stage monitoring electrode X1 contacts water (N = 1): Analog switch D1 is closed (the rest of the analog switches are open), NMOS transistor M1 is turned on (the rest M2~M12 are turned off), and the power supply VCC passes through S12, S11, ..., S3, S2, S1 to the negative terminal of the power supply in sequence, and outputs a water level monitoring signal Vo = 0.275007V (measured with a multimeter). The specific simulation is as follows: Figure 7 As shown, it is consistent with the theoretical voltage Vo = VCC / n = VCC / 12 = 0.275V, with a relative error of approximately 0.00%.

[0079] (2) When the fourth-stage monitoring electrode X4 contacts water (N = 4): Analog switches D1~D4 are closed (the rest of the analog switches are open), NMOS transistors M1~M4 are turned on (the rest M5~M12 are turned off), and the power supply VCC passes through S12, S11, ..., S5, M4, M1, S1 to the negative terminal of the power supply in sequence, outputting a water level monitoring signal Vo = 0.366690V (measured with a multimeter). The specific simulation is as follows: Figure 8 As shown, it is consistent with the theoretical voltage Vo = VCC / (n - N + 1) = VCC / 9 = 0.3667V, with a relative error of approximately 0.00%.

[0080] (3) When the seventh-level monitoring electrode X7 contacts water (N = 7): Analog switches D1~D7 are closed (the rest of the analog switches are open), NMOS transistors M1~M7 are turned on (the rest M8~M12 are turned off), and the power supply VCC passes through S12, S11, ..., S8, M7, M1, S1 to the negative terminal of the power supply in sequence, outputting a water level monitoring signal Vo = 0.550033V (measured with a multimeter). The specific simulation is as follows: Figure 9 As shown, it is consistent with the theoretical voltage Vo = VCC / (n - N + 1) = VCC / 6 = 0.55V, with a relative error of approximately 0.01%.

[0081] Therefore, we can determine the level of the monitoring electrode based on the voltage signal acquired by the MCU, and thus obtain the water level information. Simulation test data from no water contact to level 12 are shown in Table 3.

[0082]

[0083] Comparing the simulation test data in Tables 2 and 3, the NMOS electronic switch has superior performance and smaller relative error compared to the PMOS electronic switch due to its lower on-resistance.

[0084] The present invention and its embodiments have been described above. This description is not restrictive, and the accompanying drawings are only one embodiment of the present invention; the actual structure is not limited thereto. In conclusion, if those skilled in the art are inspired by this description and design similar structures and embodiments without departing from the spirit of the invention, such designs should fall within the protection scope of the present invention.

Claims

1. A parallel MOS transistor electronic water level gauge circuit, characterized in that: The circuit consists of a cascaded multi-stage water level monitoring sub-circuits arranged in series at equal intervals, a voltage divider circuit, a power supply VCC, and a bias power supply. The first-level water level monitoring sub-circuit includes a MOS transistor M1 as an electronic switch, a signal resistor S1, and a flooding signal circuit. The flooding signal circuit controls the conduction and cutoff of the MOS transistor M1. One end of the signal resistor S1 is connected to the MOS transistor M1, and the other end is connected to the negative terminal of the power supply. The n-level water level monitoring sub-circuits, which are arranged in series at equal intervals, are cascaded, where n>1, and each sub-circuit has the same structure. One end of each of the MOS transistors M1~Mn is connected together as the water level signal output terminal, which outputs the water level monitoring signal Vo. The other end is connected to the voltage divider circuit, which outputs the voltage divider signals V1~V(n-1). The voltage divider circuit is formed by connecting signal resistors S1 to Sn sequentially end to end.

2. The parallel MOS transistor electronic water level gauge circuit according to claim 1, characterized in that: The bias power supply is connected to the flooding signal circuit, which includes a resistor R1 and a monitoring electrode X1.

3. The parallel MOS transistor electronic water level gauge circuit according to claim 2, characterized in that: The bias power supply is a negative bias power supply VEE, satisfying VEE - VCC < V. TP V TP This is the turn-on threshold voltage of the PMOS transistor; The MOS transistor M1 is a PMOS transistor M1; The monitoring electrode X1 is connected to both resistor R1 and the gate of PMOS transistor M1. The other end of resistor R1 is connected to the positive terminal of power supply VCC. The source of PMOS transistor M1 is connected to one end of signal resistor S1, i.e., voltage divider signal V1. The drain of PMOS transistor M1 outputs water level monitoring signal Vo.

4. The parallel MOS transistor electronic water level gauge circuit according to claim 2, characterized in that: The bias power supply is a positive bias power supply VBIAS, satisfying VBIAS > VCC + V. TN V TN This is the NMOS transistor's turn-on threshold voltage; The MOS transistor M1 is an NMOS transistor M1; The monitoring electrode X1 is connected to both resistor R1 and the gate of NMOS transistor M1. The drain of NMOS transistor M1 is connected to one end of signal resistor S1, which is the voltage divider signal V1. The source of NMOS transistor M1 outputs the water level monitoring signal Vo.

5. The parallel MOS transistor electronic water level gauge circuit according to claim 4, characterized in that: When the monitoring electrode XN of the Nth (1≤N≤n) level water level monitoring sub-circuit comes into contact with water, the NMOS transistors M1~MN are turned on. Output water level monitoring signal Vo≈V1≈VN=VCC×S1 / (S1+ S(N+1) +S(N+2) +…+ Sn).

6. The parallel MOS transistor electronic water level gauge circuit according to claim 3, characterized in that: When the monitoring electrode XN of the Nth (1≤N≤n) level water level monitoring sub-circuit comes into contact with water, the PMOS transistors M1~MN are turned on. The output water level monitoring signal Vo≈V1≈VN=VCC×S1 / (S1+S(N + 1)+S(N + 2)+…+Sn).

7. The parallel MOS transistor electronic water level gauge circuit according to claim 5, characterized in that: The signal resistors S1 to Sn are of equal value, i.e., S1 = S2 = S3 = … = Sn = R, and the value of R is set based on the current drawn by the ADC converter. When the Nth (1≤N≤n) level monitoring electrode XN comes into contact with water: The output water level monitoring signal Vo≈V1≈VN = VCC×S1 / (S1 + S(N + 1) + S(N + 2) + … + Sn)= VCC / (n - N + 1).

8. A parallel MOS transistor electronic water level gauge circuit according to claim 6, characterized in that: The signal resistors S1 to Sn are proportional resistors with a common ratio q = 1.

025. The Nth (1≤N≤n) level resistor SN = S1×q (N - 1) The total resistance of the n-stage resistors, Sum = S1 + S2 + S3 + ... + Sn = S1(1 - q) n ) / (1 - q); When the Nth (1≤N≤n) level monitoring electrode XN comes into contact with water, the output water level monitoring signal Vo≈V1≈VN, that is...

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