Serial electronic water gauge circuit based on NMOS (N-channel Metal Oxide Semiconductor) tube

Abstract

The invention discloses a series electronic water gauge circuit based on NMOS (N-channel Metal Oxide Semiconductor) transistors, a first-stage water level monitoring sub-circuit comprises an NMOS transistor M1 serving as an electronic switch and a signal resistor S1, a drain electrode of the NMOS transistor M1 is connected to a power supply VCC through the signal resistor S1, the power supply VCC outputs a water level monitoring signal V1 through the signal resistor S1, and a source electrode of the NMOS transistor M1 is connected with a voltage division circuit to output a water level monitoring signal Vo; the signal resistor S1 is also connected to the source electrode of the next-stage electronic switch NMOS tube M2; the water level monitoring sub-circuits which are arranged in series and in cascade at equal intervals comprise n stages of sub-circuits, n is greater than 1, and each stage of sub-circuit has the same structure; in the n levels of water level monitoring sub-circuits, signal resistors S1-Sn and a power supply VCC are arranged in parallel, and electronic switch NMOS tubes M1-Mn are arranged in series. Compared with the prior art, the serial electronic water gauge circuit based on the NMOS tubes has the advantages that the serial electronic water gauge circuit based on the NMOS tubes is simple in combinational logic circuit and high in acquisition speed.

Description

Technical Field

[0001] This invention relates to the field of water level measurement, specifically to an electronic water level gauge circuit based on NMOS transistors in series. Background Technology

[0002] An electronic water level gauge (electrode-type water level sensor) is a water level (or conductive liquid) measurement sensor widely used in smart agriculture, industry, urban roads, lakes, and other liquid level monitoring applications. It utilizes the conductivity of water, collecting water depth information through signal monitoring electrodes (usually stainless steel screws) arranged in series at equal intervals. The signal monitoring electrodes in the acquisition circuit determine whether they are in contact with the water based on their potential. The water depth is determined by the number of electrodes submerged in the water. Commercially available electronic water level gauges typically consist of a circuit board, a common electrode, monitoring electrodes, epoxy resin, and a metal casing. The common electrode is connected to the metal casing, and the monitoring electrodes are connected to the PCB circuit board. The common electrode and monitoring electrodes are exposed (with impedances ranging from tens to hundreds of kΩ when in contact with water, and very high impedance otherwise) to ensure good contact with the water.

[0003] Electronic water level gauges typically use digital logic chips, resistors, capacitors, and other components. The chips consume hundreds of microamps of power, are low-cost, have a large surface-mount area (belonging to integrated circuits), and are easy to integrate onto a PCB board. Like voltage comparators, it is also a type of low-power water detection circuit, as detailed below.

[0004] (1) Telemetry electronic water level gauge (Utility Model Patent No.: ZL201520716037.4): The circuit part includes a digital logic circuit board, a wireless transmission module, a rechargeable battery and a voltage regulator circuit board, as well as probes (electrodes) electrically connected to the digital logic circuit board.

[0005] (2) A new type of electronic water level gauge (utility model patent number: ZL201721276232.5): The sensor uses mechanical methods to locate and sense changes in water level. After digital encoding processing by the analog-to-digital conversion module, it realizes digital indexing, digital sampling and digital transmission. The analog signal is converted into a digital signal and then transmitted to the central controller.

[0006] (3) Integrated multi-segment search-type intelligent electronic water level gauge (utility model patent number: ZL201520468625.0), the data acquisition unit sensor acquisition module includes multiple contacts (electrodes), the contacts include contact power supply module, contact level high and low acquisition module, and signal feedback module.

[0007] Since the above scheme uses digital logic chips, it requires relatively complex timing circuits and multiple interface pins of a microprocessor (MCU). Too many cascaded monitoring electrodes will reduce the water level acquisition speed, reduce anti-interference performance, and make it difficult to adapt to occasions with high data update frequency.

[0008] The relevant patents related to the electronic water level gauge based on simple combinational logic circuits are as follows.

[0009] (1) A two-wire series-connected electronic water level gauge circuit (Invention Patent Application No.: CN202010115994.7): The circuit consists of multi-stage water level monitoring sub-circuits, voltage divider circuits, microprocessors, etc., arranged in parallel at equal intervals, such as Figure 1 As shown, the water level monitoring sub-circuit consists of an NMOS transistor, resistors, monitoring electrodes, and a common electrode. The conduction and cutoff of the NMOS transistor are determined by whether the water is in contact with the monitoring electrodes, thus determining whether a low-impedance path is provided for the monitoring signal transmission. The signal is transmitted through multiple parallel stages, converging at the sampling resistor. Finally, the microprocessor (MCU) uses an ADC to perform analog-to-digital conversion to obtain the voltage value, which is compared with a reference voltage to obtain the water level information. Essentially, a resistor Sn and an electronic switch Mn (NMOS transistor, low-side switch, low-end switch, or low-side-edge switch) connected in series form a single-stage water level monitoring circuit. Multiple stages of the water level monitoring circuit are then connected in parallel and combined with the sampling resistor to form a series electronic water level gauge circuit.

[0010] (2) A three-wire series electronic water level gauge circuit (Invention Patent Application No.: CN202010116367.5): The design concept is similar to that of the applied invention patent (Application No.: CN202010115994.7), such as Figure 2 As shown, the difference is that a PMOS transistor is used instead of an NMOS transistor. The resistor Sn and the electronic switch Mn (PMOS transistor, high-side switch, high-side switch, or high-reverse switch) are connected in series to form a single-stage water level monitoring circuit. The multi-stage water level monitoring circuits are connected in parallel to form a series electronic water level gauge circuit.

[0011] (3) A three-wire series-connected electronic water level gauge circuit (authorized invention patent, patent number: ZL202010116357.1): The circuit consists of a multi-stage water level monitoring sub-circuit cascaded at equal intervals, a voltage divider circuit, a microprocessor, etc., such as Figure 3 As shown, the water level monitoring sub-circuit consists of a PMOS transistor, resistors, monitoring electrodes, and a common electrode. The conduction and cutoff of the PMOS transistor are determined by whether the water is in contact with the monitoring electrodes, thus determining whether a low-impedance path is provided for the monitoring signal transmission. Multiple water level signals are transmitted in series, and finally, the microprocessor (MCU) uses an ADC to perform analog-to-digital conversion to obtain the voltage value, which is compared with a reference voltage to obtain the water level information. Essentially, resistor Sn and electronic switch Mn (PMOS transistor) are connected in parallel to form a single-stage water level monitoring circuit. The multiple water level monitoring circuits are then connected in series and combined with the sampling resistor to form a series electronic water level gauge circuit.

[0012] (4) A three-wire series electronic water level gauge circuit (authorized utility model patent, application number: CN202020206268.1): The design concept is similar to that of the authorized invention patent (patent number: ZL202010116357.1), such as Figure 3 As shown, the difference is that an NMOS transistor is used instead of a PMOS transistor, and a high-voltage bias power supply is added to turn on the NMOS transistor. The bias power supply is V higher than the operating power supply. TN The above (V) TN (This is the NMOS transistor's turn-on threshold voltage). Resistor Sn and electronic switch Mn (NMOS transistor) are connected in parallel to form a first-stage water level monitoring circuit. The multi-stage water level monitoring circuits are connected in series and then combined with the sampling resistor to form a series electronic water level gauge circuit.

[0013] NMOS transistors treat electrons as the "majority carriers," and compared to holes, the "majority carriers" in PMOS transistors, electrons have a higher mobility. This means that under the same conditions (physical density), NMOS transistors have higher transconductance than PMOS transistors. In the on-state, the on-resistance R of an NMOS transistor is... DS(ON) Smaller, R of PMOS transistor DS(ON) The on-resistance R of the NMOS transistor is relatively large. DS(ON) The on-resistance R of a PMOS transistor of the same size is generally... DS(ON) Theoretically, the drain current I is 1 / 3 to 1 / 2 of the drain current. D It is also higher than the corresponding multiple (not considering other factors). For the same R DS(ON) and I D NMOS transistors generally require a smaller silicon wafer area, and their gate capacitance and threshold voltage are lower than those of PMOS transistors. NMOS transistors are preferred when a high bias power supply is required.

[0014] Characteristics of NMOS transistors: Voltage difference V between gate and source GS Greater than V TN (NMOS transistor turn-on threshold voltage V) TN It will conduct when the voltage is greater than 0V, making it suitable for low-side driving. It only requires a certain voltage difference between the gate and source, such as V. TN =2V. For NMOS transistors driven from the low end, the source (S) is directly connected to the negative terminal of the power supply, and the source voltage is fixed at 0V. The NMOS transistor can be turned on and off by controlling the gate (G) voltage to reach the switching threshold voltage. If the NMOS transistor is driven from the high end, the source voltage is uncertain, making it difficult to determine the gate voltage. When a high-side driven NMOS transistor is turned on, the source voltage and drain voltage (VCC) are the same. Therefore, the gate voltage must be at least V higher than VCC. TN (The gate voltage must be greater than VCC + V) TNIf a voltage higher than VCC is needed within the same system, a dedicated boost circuit is required. Many chip drivers integrate charge pump circuits; when connecting an external capacitor, a suitable capacitor should be selected to obtain sufficient instantaneous current to drive the NMOS transistor.

[0015] Charge pump circuit: This increases chip design complexity and silicon area, thereby reducing the size of the NMOS transistor due to its low on-resistance R. DS(ON) This leads to an advantage in reducing silicon wafer area. When the load current is relatively large, NMOS transistors are a better choice, especially for high-power power switches that require extremely low RO. DS(ON) The system is either a low-operating-voltage system or a system that delivers power to the load. NMOS switching solutions are more expensive and have a higher design complexity than PMOS switching solutions.

[0016] DC bias VBIAS: Bias from low to high level, does not require a charge pump, and does not increase silicon area. However, it requires an additional high voltage from the power supply system to drive the NMOS transistor to turn on and off.

[0017] The aforementioned four patent applications for electronic water level gauges based on simple combinational logic circuits all employ a circuit structure where the resistors and electronic switches (MOS transistors) are connected in series and then reconnected, or in parallel and then reconnected. Combining the characteristics of these patents, this invention takes a different approach, designing an electronic water level gauge circuit based on NMOS transistors in series. This circuit uses whether the water body is in contact with the monitoring electrodes to determine the conduction and cutoff of the NMOS transistors, thereby determining whether to provide a low-impedance path for water level signal transmission. After multiple parallel stages are combined, the microprocessor (MCU) uses an ADC to perform analog-to-digital conversion to obtain the voltage value, thus obtaining the water level information, enriching the hardware circuit implementation methods of electronic water level gauges. Summary of the Invention

[0018] The technical problem to be solved by the present invention is to overcome the above-mentioned technical defects and provide a high-speed acquisition NMOS transistor series electronic water level gauge circuit based on a simple combinational logic circuit.

[0019] To solve the above-mentioned technical problems, the technical solution provided by the present invention is: an electronic water level gauge circuit based on NMOS transistor series connection, the circuit including a water level monitoring sub-circuit arranged in series with equal spacing, a voltage divider circuit, a power supply VCC and a bias power supply VBIAS; The first-level water level monitoring sub-circuit includes an NMOS transistor M1 as an electronic switch and a signal resistor S1. The drain of the NMOS transistor M1 is connected to the power supply VCC through the signal resistor S1. The power supply VCC outputs a water level monitoring signal V1 through the signal resistor S1. The source of the NMOS transistor M1 is connected to a voltage divider circuit to output a water level monitoring signal Vo. The signal resistor S1 is also connected to the source of the next-stage electronic switch NMOS transistor M2; The water level monitoring sub-circuit arranged in series at equal intervals includes n levels of sub-circuits, where n>1, and each level of sub-circuit has the same structure. In the water level monitoring sub-circuit of level n, the signal resistors S1~Sn are connected in parallel with the power supply VCC, and the electronic switches NMOS transistors M1~Mn are connected in series.

[0020] Preferably, the voltage divider circuit includes a signal resistor S0 and a voltage divider resistor R0 connected in series, and the voltage divider resistor R0 outputs a water level monitoring signal Vo to the signal resistor S0.

[0021] Preferably, the first-stage water level monitoring sub-circuit further includes a water body resistor W1, a monitoring electrode X1, and a bias resistor R1; The monitoring electrode X1 is connected to the gate of the NMOS transistor M1 and the bias resistor R1 through the analog switch D1, and is also connected to the water body resistor W1. The water body resistor W1 is connected to the bias power supply VBIAS through the resistor RG.

[0022] Preferably, when the monitoring electrode X1 is submerged in water: When analog switch D1 is closed and NMOS transistor M1 is turned on, the power supply VCC outputs water level monitoring signal V1 through resistor S1 and NMOS transistor M1, and outputs water level monitoring signal Vo through voltage divider circuit. When the monitoring electrode XN of the Nth level water level monitoring sub-circuit comes into contact with water, the NMOS transistors M1~Mn are turned on, the VCC current is divided into N branches, and the output water level monitoring signal Vo≈S0 / (S0 + R0 + (S1 / / S2 / / S3 / / … / / SN))×VCC; The output water level monitoring signal Vo in other water level monitoring sub-circuits follows the same principle.

[0023] Preferably, the bias power supply VBIAS satisfies VBIAS > VCC + V TN V TN This is the turn-on threshold voltage of the NMOS transistor.

[0024] Preferably, the resistance values ​​of the signal resistors S1 to Sn are equal, i.e., S0 = R, S1 = S2 = S3 = … = Sn = h×R (h≥1), R0 = m×R; The value of m is determined based on the power supply VCC and the operating voltage VDD of the microprocessor MCU.

[0025] Preferably, it also includes an operational amplifier U1, and the water level monitoring signal Vo is connected to the operational amplifier U1.

[0026] The advantages of this invention compared with the prior art are as follows: The circuit of this invention uses a series of multi-level water level monitoring sub-circuits arranged at equal intervals to form an electronic water level gauge circuit. It uses whether the water body is in contact with the monitoring electrode to determine the conduction and cutoff of the NMOS transistor, and then determines whether to provide a lower conduction path for the water level signal transmission. After multi-level cascade transmission, the microprocessor MCU uses the ADC to perform analog-to-digital conversion to obtain the voltage value and compares it with the reference voltage to obtain the water level information. Two design schemes, voltage divider and operational amplifier, are presented and verified by simulation: the conduction and cutoff of the NMOS transistor are determined by whether the water body is in contact with the monitoring electrode, thereby determining whether to provide a low impedance path for the water level signal transmission. After multiple parallel stages are combined, the microprocessor MCU uses the ADC to perform analog-to-digital conversion to obtain the voltage value, thereby obtaining the water level information, and enriching the hardware circuit implementation of the electronic water level gauge. Attached Figure Description

[0027] Figure 1 For existing patent applications: a block diagram of the principle of a two-line parallel electronic water level gauge; Figure 2 The following is a block diagram of the principle of a three-wire parallel electronic water level gauge circuit, for an existing patent application. Figure 3 The following is a block diagram of a three-wire series electronic water level gauge circuit (PMOS or NMOS transistor) that is currently authorized as an invention patent. Figure 4 This is a block diagram of the series-connected electronic water level gauge circuit of the present invention; Figure 5 This is a schematic diagram of the series-connected electronic water level gauge circuit based on the voltage divider method and equivalent resistors of the present invention. Figure 6 This is a schematic diagram of the series-type electronic water level gauge circuit based on the operational amplifier method of the present invention. Figure 7 for Figure 5 Simulation diagram of a 12-level equivalent resistor series electronic water level gauge circuit (first level encountering water); Figure 8 for Figure 5 Simulation diagram of a 12-level equivalent resistor series electronic water level gauge circuit (levels 1-4 encountering water); Figure 9 for Figure 5 Simulation diagram of a 12-level equivalent resistor series electronic water level gauge circuit (levels 1 to 7 when encountering water); Figure 10 for Figure 5 Simulation diagram of a 12-level equivalent resistor series electronic water level gauge circuit (levels 1-12 when encountering water); Figure 11 for Figure 6Simulation diagram of a 12-level equivalent resistor series electronic water level gauge circuit (first level encountering water); Figure 12 for Figure 6 Simulation diagram of a 12-level equivalent resistor series electronic water level gauge circuit (levels 1-4 encountering water); Figure 13 for Figure 6 Simulation diagram of a 12-level equivalent resistor series electronic water level gauge circuit (levels 1 to 7 when encountering water); Figure 14 for Figure 6 Simulation diagram of a 12-level equivalent resistor series electronic water level gauge circuit (levels 1 to 12 when encountering water). Detailed Implementation

[0028] The present invention will now be described in further detail with reference to the accompanying drawings.

[0029] This invention discloses an electronic water level gauge based on NMOS transistor series connection, the circuit block diagram of which is shown below. Figure 4 As shown, n electronic switches are connected in series. One end of each electronic switch (M1, Mn) or between two adjacent electronic switches (M1~Mn) is connected to one end of a resistor. The other ends of all resistors S1~Sn are connected in parallel to the power supply VCC, forming a series-connected electronic water level gauge circuit based on NMOS transistors. The circuit consists of a water level monitoring sub-circuit arranged in series at equal intervals, a voltage divider circuit, a power supply VCC, a bias power supply VBIAS, etc. The specific circuit is shown in the figure. Figure 5 As shown: The bias power supply is composed of a charge pump circuit or a high-voltage DC power supply, where VBIAS > VCC + V. TN .

[0030] The first-stage water level monitoring sub-circuit consists of an NMOS transistor M1, a resistor S1, a water body resistor W1, and a monitoring electrode X1. The power supply VCC, the bias power supply VBIAS, and the resistor RG (with a small resistance value) are common components. In the circuit, the monitoring electrode X1 is connected to the gate (G) of transistor M1 and the bias resistor R1 through an analog switch D1. X1 is also connected to the water body resistor W1. One end of S0 is connected to the source (S) of NMOS transistor M1 through R0, and the other end of S0 is connected to the negative terminal of the power supply. The output water level monitoring signal Vo is located between R0 and S0. The drain (D) of NMOS transistor M1 is the water level monitoring signal V1. The other end of the water body resistor W1 is connected to the bias power supply VBIAS through the resistor RG.

[0031] When the monitoring electrode X1 is not in contact with water (equivalent to analog switch D1 being open), the gate-source voltage difference V of NMOS transistor M1 is... GS The voltage is approximately 0V, so NMOS transistor M1 is cut off, and Vo≈0V.

[0032] When the monitoring electrode X1 is flooded with water (equivalent to the analog switch D1 being closed), the voltage of the gate (G) of the M1 transistor changes from a low voltage to a high voltage, approximately VBIAS. The voltage difference V between the gate and source of the NMOS transistor M1 GS is greater than the conduction threshold voltage V of the NMOS transistor M1 TN , the NMOS transistor M1 conducts, and the conduction impedance R DS(ON) is very small and can be ignored (much smaller than the resistance values of S1 = S2 = … = Sn). The conduction voltage drop of the NMOS transistor M1 can be ignored. The power supply VCC passes through the resistor S1, the low-impedance path of the NMOS transistor M1, R0, S0 to the negative terminal of the power supply, and the output water level monitoring signal Vo≈V1≈S0 / (S0 + R0 + S1)×VCC.

[0033] From the above analysis, it can be seen that when the monitoring electrode X2 of the second-level water level monitoring sub-circuit does not come into contact with water, the M2 transistor is cut off; conversely, when X2 comes into contact with water, the M1~M2 transistors conduct, and the VCC current is divided into two branches: the first branch current passes through S1, and the second branch current passes through S2 and the M2 transistor, and finally converges into one path at the M1 transistor, passes through R0, S0 to the negative terminal of the power supply. Since the drain-source conduction impedance M2R of the M2 transistor DS(ON) <<S2, the conduction voltage drops of the NMOS transistors M1 and M2 can be ignored, and the resistor S1 / / (S2 + M2R DS(ON) )≈S1 / / S2, and the output water level monitoring signal Vo≈V1≈V2≈S0 / (S0 + R0 + (S1 / / S2))×VCC.

[0034] When the monitoring electrode X3 of the third-level water level monitoring sub-circuit does not come into contact with water, the M3 transistor is cut off; conversely, when X3 comes into contact with water, the M1~M3 transistors conduct, and the VCC current is divided into three branches: the first branch current passes through S1, the second branch current passes through S2 and the M2 transistor, and the third branch current passes through S3, the M3 transistor, and the M2 transistor, and finally converges into one path at the M1 transistor, passes through R0, S0 to the negative terminal of the power supply. Since the drain-source conduction impedance M3R of the M3 transistor DS(ON) <<S3, the conduction voltage drops of the NMOS transistors M1, M2, and M3 can be ignored, and the resistor S1 / / (S2 / / (S3 + M3R DS(ON) ) + M2R DS(ON) )≈S1 / / S2 / / S3, and the output water level monitoring signal Vo≈V1≈V2≈V3≈S0 / (S0 + R0 + (S1 / / S2 / / S3))×VCC.

[0035] When the monitoring electrode XN of the Nth (4 ≤ N ≤ n) level water level monitoring sub - circuit does not contact water, the MN tube is cut off; conversely, when XN contacts water, the M1 - MN tubes are turned on, and the VCC current is divided into N branches: the first - branch current passes through S1, the second - branch current passes through S2 and the M2 tube, the third - branch current passes through S3, the M3 tube, and the M2 tube, …, the Nth - branch current passes through SN, the MN - M2 tubes, and finally converges into one path at the M1 tube, and then passes through R0, S0 to the negative power supply terminal. Since the on - resistance of the drain - source channel of the MN tube is MNR DS(ON) <<SN, the on - voltage drops of the NMOS tubes M1, M2, M3, …, MN can be ignored, and the N - path parallel impedance is equivalent to S1 / / S2 / / S3 / / … / / SN, and the output water - level monitoring signal Vo≈S0 / (S0 + R0 + (S1 / / S2 / / S3 / / … / / SN))×VCC.

[0036] The output water - level monitoring signal Vo of other levels of water - level monitoring sub - circuits can be deduced by analogy.

[0037] In the specific implementation of the present invention: The specific implementation method is as Figures 4 to 14 shown. Embodiment

[0038] The present invention discloses a series - type electronic water gauge circuit based on NMOS tubes. The circuit consists of water - level monitoring sub - circuits arranged in series at equal intervals, a voltage - dividing circuit, a bias power supply VBIAS, etc., as Figure 5 shown. The bias power supply is composed of a charge - pump circuit or a high - voltage DC power supply, satisfying VBIAS>VCC + V TN .

[0039] Parallel - resistance value selection: Considering the convenience of data processing by the MCU micro - processor after the ADC converter conversion, it is preferred that the parallel resistances of each level of water - level monitoring sub - circuits are equal, that is, S0 = R, S1 = S2 = S3 = … = Sn = h×R (h≥1), R0 = m×R. The value of m depends on the power supply VCC and the working voltage VDD of the micro - processor MCU, so as to prevent the voltage VCC from directly entering the MCU and causing damage. m = VCC / VDD and is rounded down (for example, if VCC = 12V, VDD = 3.3V, then m = 3). Generally, VCC = VDD, that is, m = 0, R0 = 0. Since a general ADC converter needs to draw a certain amount of current to work properly, the value range of the parallel - resistance value is (h / n + m + 1)×R ~ (h + m + 1)×R, and the on - resistance R DS(ON) is dozens of milliohms (much smaller than the resistance value R). If n = 100, n×R DS(ON)The number of ohms is negligible relative to (h + m + 1) × R, but for (h / n + m + 1) × R, it needs to be analyzed on a case-by-case basis (if R >> n × R). DS(ON) (It can be ignored). If the total parallel resistance is too small, the ADC conversion voltage error will increase and the power consumption will be greater. Therefore, the value of R must be appropriately compromised to meet the usage requirements. High-precision resistors should be selected first.

[0040] The calculation and analysis process is as follows: When no water is detected by the monitoring electrodes X1 ~ Xn, the NMOS transistors M1 ~ Mn are all cut off, the power supply VCC cannot pass through the NMOS transistors M1, M2, M3, ..., Mn, and the output water level monitoring signal Vo is 0V.

[0041] When the first-stage monitoring electrode X1 comes into contact with water, if monitoring electrode X1 is submerged (equivalent to analog switch D1 being closed), the gate (G) voltage of transistor M1 changes from low to high, by approximately VBIAS. The gate-source voltage difference V of NMOS transistor M1... GS Greater than the NMOS transistor M1's turn-on threshold voltage V TN NMOS transistor M1 is turned on, and its on-resistance R is... DS(ON) The voltage drop across the NMOS transistor M1 is negligible (far smaller than the resistance values ​​of S1 = S2 = … = Sn). The on-state voltage drop of the NMOS transistor M1 is negligible. The power supply VCC passes through resistor S1, the low-impedance path of the NMOS transistor M1, R0, and S0 to the negative terminal of the power supply. The output water level monitoring signal Vo≈V1≈S0 / (S0+R0+S1)×VCC=VCC×R / (R+h×R)=VCC / (1+h).

[0042] From the above analysis, it can be seen that when the monitoring electrode X2 of the second-stage water level monitoring sub-circuit is not in contact with water, transistor M2 is cut off; conversely, when X2 is in contact with water, transistors M1 and M2 are turned on, and the VCC current splits into two branches: the first branch current passes through S1, and the second branch current passes through S2 and transistor M2, finally converging at transistor M1 and flowing through R0 and S0 to the negative terminal of the power supply. Due to the drain-source impedance M2R of transistor M2... DS(ON) << S2, the on-state voltage drop of NMOS transistors M1 and M2 can be ignored, and the resistance S1 / / (S2 + M2R) DS(ON) )≈S1 / / S2 = h×R / 2, output water level monitoring signal Vo≈V1≈V2≈S0 / (S0+R0+(S1 / / S2))×VCC=VCC×R / (R+h×R / 2)=2×VCC / (2+h).

[0043] When the monitoring electrode X3 of the third-stage water level monitoring subcircuit is not in contact with water, transistor M3 is cut off; conversely, when X3 is in contact with water, transistors M1 to M3 are turned on, and the VCC current is divided into three branches: the first branch current passes through S1, the second branch current passes through S2 and transistor M2, and the third branch current passes through S3, transistor M3, and transistor M2, finally converging at transistor M1 and flowing through R0 and S0 to the negative terminal of the power supply. Due to the drain-source on-resistance M3R... DS(ON) << S3, the on-state voltage drop of NMOS transistors M1, M2, and M3 can be ignored, and the resistance S1 / / (S2 / / (S3 + M3R) DS(ON) ) + M2R DS(ON) )≈S1 / / S2 / / S3 = h×R / 3, output water level monitoring signal Vo≈V1≈V2≈V3≈S0 / (S0+R0+(S1 / / S2 / / S3))×VCC=VCC×R / (R+h×R / 3)=3×VCC / (3+h).

[0044] When the monitoring electrode XN of the Nth (4≤N≤n) level water level monitoring subcircuit is not in contact with water, transistor MN is cut off; conversely, when XN is in contact with water, transistors M1 to MN are turned on, and the VCC current is divided into N branches: the first branch current passes through S1, the second branch current passes through S2 and M2, the third branch current passes through S3, M3, M2, ..., the Nth branch current passes through SN, MN to M2, and finally converges into one line at transistor M1, flowing through R0 and S0 to the negative terminal of the power supply. Due to the drain-source impedance MNR of transistor MN... DS(ON) << SN, the on-state voltage drop of NMOS transistors M1, M2, M3, ..., MN can be ignored. The N parallel impedance is equivalent to S1 / / S2 / / S3 / / ... / / SN = h×R / N, Vo≈S0 / (S0+R0+(S1 / / S2 / / S3 / / ... / / SN))×VCC=VCC×R / (R+h×R / N)=N×VCC / (N+h).

[0045] The output water level monitoring signal Vo in other water level monitoring sub-circuits at each level follows the same pattern.

[0046] Figure 4 The electronic switches in the middle are theoretically random and independent, and there are a total of 2 ⁿ There are several possible combinations of states, but the electronic water level gauge is installed vertically, and the conduction of the electronic switches is subject to certain constraints: the electronic switches have priorities, with higher priorities for switches installed at lower positions (highest priority being M1) and lower priorities for switches installed at higher positions (lowest priority being Mn), similar to a priority encoder. As the water level rises, the number of electronic switches that are closed (conducting) increases. Figure 4The switch states corresponding to different water level values ​​are shown in Table 1. There are a total of n + 1 possible combinations, where all resistors have the same resistance value: S1 = S2 = … = Sn =, R0 = 0.

[0047]

[0048] The relationship between the voltage value Vo of the voltage divider signal and the water level of level N (1≤N≤n) is: Vo = VCC×N×S0 / (N×S0 + S1).

[0049] ADC converter: Currently, microcontrollers have multiple built-in ADCs (M = 12 / 14 / 16 / 20 bits). As n increases, Vo is an increasing function. In order to ensure resolution, the voltage difference between the last two quantization stages must meet the condition, as shown in equation (1):

[0050] Equation (1) is simplified as shown in equation (2):

[0051] Equation (2) can be rearranged as shown in Equation (3):

[0052] Equation (3) can be rearranged as shown in equation (4):

[0053] Equation (4) can be rearranged as shown in Equation (5):

[0054] Finally, when equation (5) is equal, the result is as shown in equation (6):

[0055] Due to 4 h 2 M Much greater than |1 - 4 h |, approximate the result as (1 - 4h) + 4h² M ≈ 4h2 M Equation (6) can be rearranged as shown in equation (7):

[0056] If M=12 and h=121, substituting into equation (7) yields the range of n values: -824 to 583. Theoretically, a maximum of 583 monitoring sub-circuits can be connected in parallel. The range of n values ​​for cascade levels obtained when M = 12, 14, 16, 18, and 20 are shown in Table 2.

[0057]

[0058] With M = 12, 14, 16, 18, and 20, the quantization levels are 583, 1287, 2695, 5511, and 11143, respectively. If the spacing between the signal monitoring electrodes is 1 cm, the measurement ranges are 583 cm, 1287 cm, 2695 cm, 5511 cm, and 11143 cm, providing a very wide measurement length range. Currently, a cascade number of electronic water level gauges of approximately n = 100 is sufficient to meet the requirements. Implementation

[0059] Implementation method one is a resistor voltage divider monitoring method. Based on implementation method one, the circuit is slightly modified by using an operational amplifier, such as... Figure 6 As shown, the value of the parallel resistor is the same as in Implementation Method 1.

[0060] The calculation and analysis process is as follows: When no water is detected in X1~Xn, NMOS transistors M1~Mn are all cut off, and the power supply VCC cannot pass through NMOS transistors M1, M2, M3, ..., Mn, so the output water level monitoring signal Vo = 0V.

[0061] When the first-stage monitoring electrode X1 comes into contact with water, if monitoring electrode X1 is submerged (equivalent to analog switch D1 being closed), the gate (G) voltage of transistor M1 changes from low to high, by approximately VBIAS. The gate-source voltage difference V of NMOS transistor M1... GS Greater than the NMOS transistor M1's turn-on threshold voltage V TN NMOS transistor M1 is turned on, and its on-resistance R is... DS(ON) The voltage drop is very small and negligible (much smaller than the resistance values ​​of S1 = S2 = … = Sn). The power supply VCC passes through resistor S1, the low-impedance path of NMOS transistor M1, and S0 to the inverting input VN of operational amplifier U1. The on-state voltage drop of NMOS transistor M1 is negligible. The output voltage signal Vo of operational amplifier U1 is approximately -S0 / (S0 + S1)×VCC = -VCC / (1 + h).

[0062] When the monitoring electrode X2 of the second-stage water level monitoring subcircuit is not in contact with water, transistor M2 is cut off; conversely, when X2 is in contact with water, transistors M1 and M2 are turned on, and the VCC current splits into two branches: the first branch current flows through S1, and the second branch current flows through S2 and transistor M2, finally converging at transistor M1 and flowing through S0 to the inverting input VN of operational amplifier U1. This is because the drain-source path on-resistance of transistor M2 is M2R. DS(ON) << S2, resistor S1 / / (S2 + M2R) DS(ON)) ≈ S1 / / S2, the on-state voltage drop of NMOS transistors M1 and M2 can be ignored, and the output voltage signal Vo of operational amplifier U1 is approximately -S0 / (S0 + (S1 / / S2))×VCC = -2VCC / (2 + h).

[0063] When the monitoring electrode X3 of the third-stage water level monitoring subcircuit is not in contact with water, transistor M3 is cut off; conversely, when X3 is in contact with water, transistors M1 to M3 are turned on, and the VCC current is divided into three branches: the first branch current passes through S1, the second branch current passes through S2 and transistor M2, and the third branch current passes through S3, transistor M3, and transistor M2, finally converging at transistor M1 and flowing through S0 to the inverting input VN of operational amplifier U1. Due to the drain-source impedance M3R of transistor M3... DS(ON) << S3, resistor S1 / / (S2 / / (S3 + M3R) DS(ON) +M2R DS(ON) ) ≈ S1 / / S2 / / S3, the on-state voltage drop of NMOS transistors M1, M2, and M3 can be ignored, and the output voltage signal Vo of operational amplifier U1 is approximately -S0 / (S0 + (S1 / / S2 / / S3))×VCC = -3VCC / (3 + h).

[0064] When the monitoring electrode XN of the Nth (4 ≤ N ≤ n) level water level monitoring subcircuit is not in contact with water, transistor MN is cut off; conversely, when XN is in contact with water, transistors M1~MN are turned on, and the VCC current is divided into N branches: the first branch current passes through S1, the second branch current passes through S2 and M2, the third branch current passes through S3, M3, M2, ..., the Nth branch current passes through SN, MN, ..., M2, and finally converges into one path at transistor M1, flowing through S0 to the inverting input VN of operational amplifier U1. Due to the drain-source impedance MNR of transistor MN... DS(ON) << SN, the equivalent resistance of N parallel circuits is S1 / / S2 / / S3 / / … / / SN, the on-state voltage drop of NMOS transistors M1, M2, M3, …, MN can be ignored, the output voltage signal Vo of operational amplifier U1 is approximately -S0 / (S0 + (S1 / / S2 / / S3 / / … / / SN))×VCC = -N×VCC / (N + h).

[0065] ADC Converter: Currently, microcontrollers have multiple built-in ADCs (M = 12, 14, 16 bits). As n increases, Vo is an increasing function. To ensure resolution, the specific calculation process is described in Implementation Method 1 and will not be detailed here. The range of values ​​for the cascade number n is the same, as shown in Table 2.

[0066] There are only two types of resistors that need to be welded, which are easy to procure, so high-precision resistors are preferred. Therefore, we can determine the level of the monitoring electrodes based on the voltage signal acquired by the MCU, and thus obtain the water level information.

[0067] This circuit is connected to the following external connections: power supply VCC, negative power supply, bias power supply VBIAS, and water level signal Vo. The water level signal Vo is an analog signal that needs to be processed by an ADC. Therefore, the analog signal replaces the digital signal, which has the characteristics of ultra-low power consumption and strong anti-interference.

[0068] Implementation Method 1: Simulation according to Figure 5 The circuit was simulated and tested using National Instruments' Multisim simulation software (version V14.0). The NMOS transistor selected was NXP's BSP030 model, and the minimum turn-on threshold voltage was V. TN(MIN) = 1V, maximum value V TN(MAX) = 2.8V, typical value V not given TN The conduction current reaches 10A, and the conduction impedance R DS(ON) =30mΩ (V) GS = 10V), R DS(ON) = 50mΩ (V GS = 4.5V), let's take the turn-on threshold voltage V. TN = 2.8V.

[0069] When n = 12, the parallel resistors of each water level monitoring sub-circuit are equal: S0 = R = 1kΩ, S1 = S2 = S3 = … = Sn = h×R = 121kΩ, m = 0, R0 = m×R = 0, RG = 1kΩ, power supply voltage VCC = 3.3V, bias power supply voltage VBIAS = 10V, assuming the water resistance WN = 100kΩ (N = 1, 2, …, n, generally a few kΩ to several hundred kΩ, the specific resistance value depends on the contact area and distance between the monitoring electrode and the common electrode, and the conductivity of the liquid); when the monitoring electrode XN is in contact with water, the simulated switch DN is closed and the NMOS transistor MN is turned on; when there is no water, the simulated switch DN is open and the NMOS transistor MN is turned off, as shown in the simulation below.

[0070] (1) When the first-stage monitoring electrode X1 contacts water (N = 1): analog switch D1 is closed (the rest of the analog switches are open), NMOS transistor M1 is turned on (the rest M2~M12 are turned off), and the power supply VCC passes through S1, NMOS transistor M1, and S0 to the negative terminal of the power supply in sequence, outputting a water level monitoring signal Vo = 27.1mV. The specific simulation is as follows: Figure 7As shown: This is consistent with the theoretical voltage Vo = VCC / (1 + h) = 3.3V / (1 +121) ≈ 27.05mV, with a relative error of approximately 0.18%.

[0071] (2) When the fourth-stage monitoring electrode X4 comes into contact with water (N = 4), analog switches D1~D4 are closed (the rest of the analog switches are open), NMOS transistors M1~M4 are turned on (the rest M5~M12 are turned off), and the four currents of the power supply VCC pass through S4~S1, NMOS transistors M4~M1, and S0 to the negative terminal of the power supply in sequence, outputting a water level monitoring signal Vo = 106mV. The specific simulation is as follows: Figure 8 As shown: It is consistent with the theoretical voltage Vo = 4×VCC / (4 + 121) = 4×3.3V / (4 + 121) ≈ 106.45mV, with a relative error of about 0.43%.

[0072] (3) When the seventh-level monitoring electrode X7 contacts water (N = 7), analog switches D1~D7 are closed (the rest of the analog switches are open), NMOS transistors M1~M7 are turned on (the rest M8~M12 are turned off), and the seven currents of the power supply VCC pass through S7~S1, NMOS transistors M7~M1, and S0 to the negative terminal of the power supply in sequence, outputting a water level monitoring signal Vo = 181mV. The specific simulation is as follows: Figure 9 As shown: This is consistent with the theoretical voltage Vo = 7×VCC / (7 + 121) = 7×3.3V / (7 + 121) ≈ 180.47mV, with a relative error of approximately 0.29%.

[0073] (4) When the 12th monitoring electrode X12 comes into contact with water (N = 12), analog switches D1~D12 are closed (the rest of the analog switches are open), and the 12 currents of the power supply VCC pass through S12~S1, NMOS transistors M12~M1, and S0 to the negative terminal of the power supply in sequence, outputting a water level monitoring signal Vo = 298mV. The specific simulation is as follows. Figure 10 As shown: It is consistent with the theoretical voltage Vo = 12×VCC / (12 + 121) = 12×3.3V / (12 + 121) ≈ 297.74mV, with a relative error of about 0.08%.

[0074] Implementation Method Two: Simulation according to Figure 6The circuit was simulated and tested under the same conditions as in Implementation Method 1. The operational amplifier used was a TI 3554BM, powered by a single VCC supply. When n = 12, the parallel resistors of each water level monitoring sub-circuit were equal: S0 = R = 1kΩ, S1 = S2 = S3 = … = Sn = h×R = 121kΩ, m = 0, R0 = m×R = 0. The power supply VCC = 3.3V, the negative power supply VCCN = -3.3V, and the bias power supply VBIAS = 10V. The simulation results are shown below.

[0075] (1) When the first-stage monitoring electrode X1 contacts water (N = 1): analog switch D1 is closed (the rest of the analog switches are open), NMOS transistor M1 is turned on (the rest M2~M12 are turned off), and the power supply VCC passes through S1, NMOS transistor M1, and S0 to the negative terminal of the power supply in sequence, outputting a water level monitoring signal Vo = -26.9mV. The specific simulation is as follows. Figure 11 As shown: This is consistent with the theoretical voltage Vo = -VCC / (1 + h) = -VCC / 122 = -27.05mV, with a relative error of approximately 1.39%.

[0076] (2) When the fourth-stage monitoring electrode X4 contacts water (N = 4), analog switches D1~D4 are closed (the rest of the analog switches are open), NMOS transistors M1~M4 are turned on (the rest M5~M12 are turned off), and the four currents of the power supply VCC pass through S4~S1, NMOS transistors M4~M1, and S0 to the negative terminal of the power supply in sequence, outputting a water level monitoring signal Vo = -105mV. The specific simulation is as follows. Figure 12 As shown: This is consistent with the theoretical voltage Vo = -4×VCC / (4 + 121) = -106.45mV, with a relative error of approximately 1.36%.

[0077] (3) When the seventh-level monitoring electrode X7 contacts water (N = 7), analog switches D1~D7 are closed (the rest of the analog switches are open), NMOS transistors M1~M7 are turned on (the rest M8~M12 are turned off), and the seven currents of the power supply VCC pass through S7~S1, NMOS transistors M7~M1, and S0 to the negative terminal of the power supply in sequence, outputting a water level monitoring signal Vo = -180mV. The specific simulation is as follows: Figure 13 As shown: This is consistent with the theoretical voltage Vo = -7×VCC / (7 + 121) = -180.47mV, with a relative error of approximately 0.26%.

[0078] (4) When the eleventh-level monitoring electrode X12 comes into contact with water (N = 12), analog switches D1~D12 are closed (the rest of the analog switches are open), NMOS transistors M1~M12 are turned on, and the 12 currents of the power supply VCC pass through S12~S1, NMOS transistors M12~M1, and S0 to the negative terminal of the power supply in sequence, outputting a water level monitoring signal Vo = -298mV. The specific simulation is as follows. Figure 14 As shown: This is consistent with the theoretical voltage Vo = -12×VCC / (12 + 121) = -297.74mV, with a relative error of approximately 0.08%.

[0079] The circuit is designed based on an NMOS transistor series-connected electronic water level gauge, and its feasibility is verified through simulation, demonstrating its good application value.

[0080] The present invention and its embodiments have been described above. This description is not restrictive, and the accompanying drawings are only one embodiment of the present invention; the actual structure is not limited thereto. In conclusion, if those skilled in the art are inspired by this description and design similar structures and embodiments without departing from the spirit of the invention, such designs should fall within the protection scope of the present invention.

Claims

1. A NMOS transistor series-based electronic water gauge circuit, characterized in that: The circuit comprises water level monitoring sub-circuits arranged in equal interval series connection, a voltage dividing circuit, a power supply VCC and a bias power supply VBIAS; the first water level monitoring sub-circuit comprises an NMOS transistor M1 as an electronic switch and a signal resistor S1, the drain of the NMOS transistor M1 is connected to the power supply VCC through the signal resistor S1, the power supply VCC outputs a water level monitoring signal V1 through the signal resistor S1, and the source of the NMOS transistor M1 is connected to the voltage dividing circuit to output a water level monitoring signal Vo; The signal resistor S1 is also connected to the source of the next electronic switch NMOS transistor M2; The water level monitoring sub-circuits arranged in equal interval series connection comprise n sub-circuits, n>1, and each sub-circuit has the same structure; The signal resistors S1-Sn in the n water level monitoring sub-circuits are connected in parallel to the power supply VCC, and the electronic switches NMOS transistors M1-Mn are connected in series.

2. The electronic water gauge circuit based on series connection of NMOS transistors according to claim 1, characterized in that: The voltage dividing circuit comprises a signal resistor S0 and a voltage dividing resistor R0 connected in series, and the voltage dividing resistor R0 outputs the water level monitoring signal Vo to the signal resistor S0.

3. The electronic water gauge circuit based on NMOS transistor series according to claim 1 or 2, characterized in that: The first water level monitoring sub-circuit further comprises a water body resistor W1, a monitoring electrode X1 and a bias resistor R1; The monitoring electrode X1 is connected to the gate of the NMOS transistor M1 and the bias resistor R1 through an analog switch D1, and is also connected to the water body resistor W1, and the water body resistor W1 is connected to the bias power supply VBIAS through a resistor RG.

4. The electronic water gauge circuit based on series connection of NMOS transistors according to claim 3, characterized in that: When the monitoring electrode X1 is submerged by water: The analog switch D1 is closed, the NMOS transistor M1 is turned on, the power supply VCC outputs the water level monitoring signal V1 through the resistor S1 and the NMOS transistor M1, and outputs the water level monitoring signal Vo through the voltage dividing circuit; When the monitoring electrode XN of the Nth water level monitoring sub-circuit contacts water, the NMOS transistors M1-MN are turned on, the VCC current is divided into N branches, and the output water level monitoring signal Vo≈S0 / (S0+R0+(S1 / / S2 / / S3 / / … / / SN))×VCC; The output water level monitoring signal Vo of each other water level monitoring sub-circuit is the same.

5. The electronic water gauge circuit based on series connection of NMOS transistors as claimed in claim 4, wherein: The bias power supply VBIAS satisfies VBIAS > VCC + V TN where V TN is the turn-on threshold voltage of the electronic switch NMOS transistor.

6. The electronic water gauge circuit based on series connection of NMOS transistors according to claim 1, characterized in that: The signal resistors S1-Sn have the same resistance value, i.e. S0=R, S1=S2=S3=…=Sn=h×R (h≥1), and R0=m×R; The value of m is set according to the working voltage VDD of the power supply VCC and the microprocessor MCU.

7. The electronic water gauge circuit based on series connection of NMOS transistors as claimed in claim 4, wherein: The circuit further comprises an operational amplifier U1, and the water level monitoring signal Vo is connected to the operational amplifier U1.

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