Test system and test method for chip aging test

Abstract

The invention provides a test system and a test method for a chip aging test, belongs to the technical field of chip testing, adopts single-board single-area independent control, supports gigabit Ethernet communication, is compatible with a serial / parallel test mode, and remarkably improves the test efficiency. FPGA online dynamic configuration is supported, and the system is adaptive to various chip types (such as a memory, a DSP and an FPGA). The power supply module provides a high-precision programmable power supply, a digital channel supports 3072 I / O, the temperature control precision of the high-temperature test box reaches + / -2 DEG C, and the test environment is ensured to be stable. Over-current, over-voltage, under-voltage and over-temperature protection is integrated, a UPS (Uninterrupted Power Supply) and a three-color light alarm are arranged, the power supply is automatically cut off in case of abnormity, and the test safety is ensured. The software module based on Windows supports program library management, real-time monitoring, report generation and historical data tracing, an automatic testing process is achieved, and manual intervention is reduced. Various waveform formats (such as RL, RH and NR) and mainstream test platform file conversion are supported, the complex test scene requirements are met, and the test coverage rate and reliability are remarkably improved.

Description

Technical Field

[0001] This invention relates to the field of chip testing technology, and in particular to a testing system and method for chip aging testing. Background Technology

[0002] In the field of chip manufacturing, aging testing is a crucial step in ensuring chip reliability and stability. However, existing chip aging testing technologies still have many problems in practical applications and urgently need improvement. The following are some of the main problems existing in the current technology: 1. Existing aging test systems typically only support testing of a single type of chip (such as digital or analog chips), lacking compatibility with multiple chips (such as memory, DSP, FPGA, etc.). Furthermore, their testing algorithms are often limited (e.g., only supporting all-1 or all-0 modes), making it difficult to meet the testing needs of complex chips and resulting in insufficient test coverage.

[0003] 2. Traditional testing systems often employ a centralized control model, which cannot achieve independent control of individual boards and zones, resulting in poor testing flexibility. Furthermore, their communication speeds are relatively low (e.g., 100Mbps Ethernet), leading to insufficient data transmission efficiency and impacting testing efficiency, especially during large-scale parallel testing.

[0004] 3. Existing power modules have low output accuracy (e.g., excessive ripple, inadequate load change rate) and lack real-time monitoring and protection functions (e.g., overcurrent, overvoltage, and undervoltage protection). These problems may lead to chip damage or inaccurate test data during testing.

[0005] 4. Existing systems have a limited number of I / O channels, which cannot be independently configured as input, output, or bidirectional modes, and the signal speed is also low (usually below 50MHz). In addition, the lack of support for various waveform formats (such as RL, RH, NR, etc.) limits the implementation of complex test scenarios.

[0006] 5. Traditional high-temperature test chambers have large temperature control errors (e.g., ±5℃ or more), substandard temperature uniformity and fluctuation, and lack independent over-temperature protection mechanisms. These problems may lead to unstable testing environments and affect the reliability of aging test results.

[0007] 6. Existing testing software typically does not support functions such as aging program library management, real-time data monitoring, and report generation. Its user interface is complex and lacks user-friendliness. Furthermore, its exception handling capabilities during testing are weak, failing to allow for pausing, resuming, or safely terminating the test.

[0008] 7. Existing testing methods require significant manual intervention, such as manually configuring test parameters and downloading test programs, lacking automated processes. The recording and analysis of test data also rely on manual operation, which is inefficient and prone to errors.

[0009] 8. Traditional systems require manual hardware replacement or FPGA reprogramming when testing chips with different functions, which cannot achieve online dynamic configuration, resulting in low testing efficiency and insufficient flexibility.

[0010] 9. When encountering abnormal situations such as overcurrent, overvoltage, or overtemperature, the existing system often only provides simple alarm functions and lacks safety measures such as automatic power cut-off and UPS power supply protection, which may cause secondary damage to equipment or chips.

[0011] 10. The storage, query and comparison functions of test data are incomplete, and there is a lack of support for automatic generation of electronic reports and retrieval of historical data, which makes it difficult to meet the high requirements of modern chip testing for data traceability and analysis.

[0012] Existing chip aging test systems and methods have significant shortcomings in terms of test range, control efficiency, power management, environmental control, software functionality, and automation level, and there is an urgent need for a more efficient, flexible, and safe solution.

[0013] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0014] The purpose of this invention is to provide a more efficient, flexible and safe chip aging test system and test method.

[0015] To achieve the above objectives, the present invention provides the following solution: A test system for chip aging testing, comprising: The control module adopts a single-board, single-zone control method, with each driver test board independently controlling a high-temperature aging zone. It communicates with the host computer via gigabit Ethernet at a speed of 1Gb / s. This will not affect the aging tests of other aging zones. This control method makes the system operation more convenient and safer.

[0016] The power module provides four programmable power channels per slot, with each power supply outputting a voltage range of 0~5V and a maximum output current of 25A. It supports real-time voltage and current monitoring and overcurrent, overvoltage, and undervoltage protection. Each slot's drive detection board provides four programmable secondary power supplies, and the power-on and power-off sequence of each secondary power supply can be controlled. Each secondary power supply independently controls its power-on and power-off sequence. The type of secondary power supply can be selected and configured in any slot, supporting up to four secondary power supply outputs.

[0017] The digital channel module supports 16 slots, with 192 I / O channels per slot, for a total of 3072 I / O channels. Each channel can be independently configured as input, output, or bidirectional mode. The maximum signal speed is 100MHz, and the minimum can reach 10KHz. In actual use, the speed of each I / O can be flexibly selected according to the type and model of the memory being aged, which is convenient to use and can maximize the aging of the memory being aged.

[0018] Each slot channel is independently programmable and can be used as I / O, independently configured as input or output; Drive capability: IOL≤40mA, IOH≤40mA; Signal voltage VIL range: 0V~5V programmable; Signal voltage VIH range: 0V~5V programmable; Signal comparison voltage VOL range: 0~5V programmable; Signal comparison voltage VOH range: 0V~5V programmable.

[0019] The high-temperature aging test equipment adopts a dual-position control mode, and all operations can be completed through a control computer. It can provide control signals to the aging equipment, and during the experiment, it can monitor the four secondary power supply voltages and currents of each tank, as well as the shell temperature of the aging equipment in real time. The voltage and current have upper and lower limit protection; in the event of a malfunction in the aging equipment, the power supply to that circuit will be promptly cut off. All test records of the high-temperature aging equipment are stored by the control computer and can be viewed later.

[0020] The communication method between the high-temperature aging test equipment and the host computer is Gigabit Ethernet. Ethernet interfaces are commonly used, and any computer is equipped with an Ethernet interface, so it is relatively simple and convenient to upgrade the equipment or system. In addition, the use of Gigabit Ethernet, i.e. 1Gb / s, is faster than traditional serial communication or USB communication interfaces, saving the time for downloading parameters and the communication time between the host computer and the slave computer, making the aging test more efficient and thorough.

[0021] The output signal format of the I / O channel is the same as that of mainstream test machines. The maximum number of edges per cycle is four, and each edge can output waveforms of arbitrary high and low levels. When editing waveforms, the waveforms required by the aged memory can be flexibly written, making it convenient to use.

[0022] The algorithm module supports all 1s, all 0s, checkerboard, column jump, and user-defined algorithms for generating test vectors. This test system is a general-purpose algorithm system that can select and write different memory algorithms according to different memory types and failure modes. That is, write X / Y / Z address lines and find the correspondence between data and address lines, so that memory vectors with different algorithms can be written.

[0023] The signal format module supports multiple waveform formats for output, including RL, RH, NR, SBL, SBH, and SBC. The protection module includes a three-color indicator light unit, a buzzer alarm unit, a watchdog protection unit, and a UPS power supply unit, which are used to ensure test safety under abnormal conditions. The high-temperature test chamber provides an aging environment from room temperature to 150℃, with a temperature control error of ≤±3℃, and supports simultaneous aging in 16 tanks. The software module, developed based on the Windows platform, supports aging program library management, real-time monitoring, data logging, and report generation. It operates on AgingOI (a powerful analytical tool for aging equipment testing and data acquisition). The module also supports single-board testing using AgingPro (a powerful analytical tool for single-board testing of aging equipment), including loading test programs, verifying programs, running tests, and capturing test data.

[0024] It also includes an adaptive learning module, which analyzes historical test data through machine learning algorithms to dynamically optimize test parameters and algorithms, thereby improving test efficiency and coverage; The wireless monitoring module supports remote real-time monitoring of the test status via 5G or Wi-Fi and can receive alarm information via mobile terminals; The self-calibration module has a built-in high-precision reference source that automatically calibrates the voltage, current, and signal timing of the power supply and digital channels on a regular basis to ensure long-term stability of test accuracy. The AgingOI operating software is user-friendly with a simple interface, making it easy to use in production. It features a device library management function, allowing users to call up or edit previous aging programs; it has aging board in-situ detection and channel self-test functions; it has aging test start, pause, continue, and termination control functions; it has a timing function for each aging test channel; it can age different chips in different slots; it can save all test information and generate test results reports for easy statistics and analysis; it supports online debugging; and it can display the aging process, status, history, and results.

[0025] The system supports high-temperature dynamic and static aging tests and dynamic aging tests on digital and analog chips, and supports aging tests on memory, DSP, and FPGA integrated circuits.

[0026] Different configuration files are required for different internal structures of FPGAs to fully cover all functions of the internal structure, allowing the FPGA to fully age. This system can re-download the configuration file to the FPGA before testing, reconfiguring the FPGA with different circuits and functions.

[0027] The software-programmable driver module can output commonly used general-purpose interfaces such as SPI, UART, and IIC, as well as standard memory interfaces such as SRAM, covering common interface function tests.

[0028] The entire testing system is powered by 380V / 50Hz (three-phase four-wire system). The power supply of the system and its various units is controlled by a main power switch. The front control panel of the whole machine mainly includes an over-temperature protection device, a main power switch, an emergency stop button, indicator lights, etc.

[0029] The aging test chamber and drive module are connected back-to-back. The drive module and aging board are interconnected via slots in the rear wall of the high-temperature chamber. The aging rack inside the chamber provides 14 slots for inserting 14 aging boards. These boards connect to the drive module via connectors and receive power and excitation waveforms from it. The chamber has a maximum of 16 zones, each capable of independent operation.

[0030] Optionally, the control module supports serial testing and parallel testing modes. Serial testing is suitable for chips with high pin density. Serial testing can save on burn-in boards and save costs while monitoring the function of the memory. The disadvantage is that it is less efficient than parallel testing. Parallel testing is suitable for chips with fewer pins. All chips on the same burn-in board can perform read and write operations simultaneously, which is more efficient, but it can only be used for memory chips with fewer pins.

[0031] This system supports online download of FPGA configuration programs, enabling aging tests with different functions by reconfiguring the internal circuitry of the FPGA. The FPGA configuration program utilizes the InsInterface dynamic library (used for upgrading the test board, with functions including device upgrade, DDR data reading, register reading, and register writing) to implement upgrade functions, including device upgrade, register read / write, and DDR data reading. Different configuration files are required for different internal structures of the FPGA to fully cover all functions and ensure sufficient FPGA aging. This system allows for re-downloading the configuration file to the FPGA before testing, reconfiguring the FPGA with different circuits and functions.

[0032] Optionally, the ripple of each power supply of the power module is ≤10mV, and the load change rate is ≤10mV; it supports current clamping protection and power-on / off sequence control; wherein, the voltage and current parameters of the power module are configured through the Level table of AgingPro software, including VIH, VIL, VOH, and VOL parameters.

[0033] Optionally, each channel of the digital channel module supports waveform output with four edges, with a minimum edge time resolution of 39.0625 ps. It supports ATE vector conversion tools and is compatible with 750 platform, 93K platform, VCD, and VEC format files (in the semiconductor testing field, the 750 platform and 93K platform are two mainstream ATE (Automatic Test Equipment) platforms, developed by different manufacturers for mass production testing and verification of chips (ICs)). The waveform format is configured via a Time Set table, supporting six formats: NR, RH, RL, SBL, SBH, and SBC. A maximum of four edges are supported per cycle, and each edge can output waveforms of arbitrary high and low frequencies. When editing waveforms, the waveforms required by the aged memory can be flexibly written, facilitating use.

[0034] Optionally, the high-temperature test chamber includes: an independent over-temperature protection device and a leakage protection device, which automatically shuts off the heating and maintains the operation of the circulating air duct when the temperature exceeds the limit; temperature uniformity ≤ ±2℃, temperature fluctuation ≤ ±0.5℃, temperature monitoring is displayed in real time through AgingOI software, and over-temperature alarm function is supported.

[0035] Optionally, the software module supports component library management, can call or edit historical aging programs; it also supports real-time display of power supply voltage, current, and temperature parameters for each slot, and generates temperature-time curves; it also supports pause, resume, and terminate operations during the aging process; wherein, component library management is implemented through the Test Flow table of the AgingPro software, and the execution order and activation status of test items can be configured.

[0036] A chip aging test method includes the following steps: Step 1: Install the chip under test onto the burn-in board, ensuring good contact; Step 2: Turn on the main power supply and control computer, start the AgingOI software, and automatically detect the power-on status of each slot; Step 3: Select the test program and download it to the driver board, and set the aging parameters, including power supply voltage, current, temperature and aging time; Step 4: Begin aging test, monitor power supply voltage, current and case temperature in real time, and record test data; Step 5: When overcurrent, overvoltage, undervoltage, or overtemperature is detected, the power supply will be automatically cut off and an alarm will be triggered; Step Six: The test will automatically terminate after aging is complete, save the data, and generate a test report; Optional, also includes: Step 7: Analyze the test data using the adaptive learning module, generate optimization suggestions, and automatically adjust subsequent test parameters; Step 8: Utilize the self-calibration module to automatically execute the calibration procedure during test intervals to ensure system accuracy; Step 9: Upload the test report and key data to the cloud via the wireless monitoring module, supporting access and sharing from multiple terminals.

[0037] Optionally, step three further includes: Select either serial or parallel test mode based on the chip type; Configure the FPGA internal circuitry and download the corresponding configuration file to achieve full functional coverage; The FPGA configuration file is generated and sent using BurnInTester software (BurnInTester is a test assistant specifically developed for aging test equipment).

[0038] Optionally, step four further includes: The status of the three-color indicator lights is displayed in real time: green indicates normal operation, yellow indicates idle operation, and flashing red indicates a fault. The test is safely shut down in the event of an abnormal power outage using a UPS power supply. The tri-color lights are monitored in real time by the alarm detection module of the AgingOI software.

[0039] Optionally, step six further includes: Generate electronic reports containing temperature, voltage, and current data; Supports historical data query, retrieval, and printing; The test data is captured and displayed using Hram software (Hram is a tool used in conjunction with AgingPro to capture AgingPro test information and can display errors in the Pattern program). It also supports comparison with expected values.

[0040] Compared with the prior art, the present invention has the following beneficial effects: This invention provides an efficient, flexible, and secure test system and method for chip aging testing. It adopts independent control of a single board and a single area, supports gigabit Ethernet communication (1Gb / s), is compatible with serial / parallel test modes, and significantly improves test efficiency. It also supports online dynamic configuration of FPGA and is compatible with various chip types (such as memory, DSP, and FPGA).

[0041] The power module provides a high-precision programmable power supply (ripple ≤10mV), the digital channel supports 3072 I / Os (100MHz signal speed), and the temperature control accuracy of the high-temperature test chamber reaches ±2℃, ensuring a stable test environment.

[0042] It integrates overcurrent, overvoltage, undervoltage and overtemperature protection, and is equipped with UPS power supply and three-color alarm. It automatically cuts off the power supply in case of abnormality to ensure test safety.

[0043] The Windows-based software modules (AgingOI / AgingPro) support library management, real-time monitoring, report generation, and historical data tracing, enabling automated testing processes and reducing manual intervention.

[0044] It supports conversion of various waveform formats (such as RL, RH, NR) and mainstream test platform files, meeting the needs of complex test scenarios and significantly improving test coverage and reliability. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0046] Figure 1 This is a schematic diagram of the chip aging test system provided in an embodiment of the present invention.

[0047] Figure 2 This is a schematic diagram of the main interface of the AgingOI software provided in an embodiment of the present invention.

[0048] Figure 3 This is a schematic diagram of the aging control menu provided in an embodiment of the present invention.

[0049] Figure 4 This is a schematic diagram of the workstation viewing interface provided in an embodiment of the present invention.

[0050] Figure 5 This is a schematic diagram of the BurnInTester main interface provided in an embodiment of the present invention.

[0051] Figure 6 A schematic diagram of the measured output waveform at 100MHz provided in an embodiment of the present invention. Detailed Implementation

[0052] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0053] The purpose of this invention is to provide a more efficient, flexible and safe chip aging test system and test method.

[0054] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0055] Example 1: This embodiment provides a test system for chip aging testing, such as... Figure 1 As shown, it includes: The control module adopts a single-board, single-zone control method. Each driver test board independently controls a high-temperature aging zone and communicates with the host computer via gigabit Ethernet at a communication speed of 1Gb / s. The power module provides 4 programmable power channels in each slot driver board. Each power output voltage range is 0~5V and the maximum output current is 25A. It supports real-time voltage and current monitoring and overcurrent, overvoltage and undervoltage protection. The digital channel module supports 16 slots, with 192 I / O channels per slot, for a total of 3072 I / O channels. Each channel can be independently configured as input, output, or bidirectional mode, with a maximum signal speed of 100MHz. The algorithm module supports all 1s, all 0s, checkerboard, column jump, and user-defined algorithms for generating test vectors. The signal format module supports multiple waveform formats for output, including RL, RH, NR, SBL, SBH, and SBC. The protection module includes a three-color indicator light unit, a buzzer alarm unit, a watchdog protection unit, and a power supply unit, which are used to ensure test safety under abnormal conditions. The high-temperature test chamber provides an aging environment from room temperature to 150℃, with a temperature control error of ≤±3℃, and supports simultaneous aging in 16 tanks. The software module, developed based on the Windows platform, supports aging program library management, real-time monitoring, data recording and report generation, and operates on AgingOI. The software module supports single-board testing through AgingPro software, including loading test programs, verifying programs, running tests and capturing test data.

[0056] A chip aging test method includes the following steps: Step 1: Install the chip under test onto the burn-in board, ensuring good contact; Step 2: Turn on the main power supply and control computer, start the AgingOI software, and automatically detect the power-on status of each slot; Step 3: Select the test program and download it to the driver board, and set the aging parameters, including power supply voltage, current, temperature and aging time; Step 4: Begin aging test, monitor power supply voltage, current and case temperature in real time, and record test data; Step 5: When overcurrent, overvoltage, undervoltage, or overtemperature is detected, the power supply will be automatically cut off and an alarm will be triggered; Step Six: The test will automatically terminate after aging is complete, save the data, and generate a test report; Step three also includes: Select either serial or parallel test mode based on the chip type; Configure the FPGA internal circuitry and download the corresponding configuration file to achieve full functional coverage; The FPGA configuration file is generated and sent using BurnInTester software (BurnInTester is a test assistant specifically developed for aging test equipment). The BurnInTester software main interface is shown below. Figure 5 As shown.

[0057] The working process of the high-temperature aging equipment is as follows: (1) Ensure that the relevant parameters and conditions of the aging board meet the test conditions; the aging control menu is as follows: Figure 3 As shown.

[0058] (2) Install the aging board correctly in each slot, ensuring full contact and securing it firmly.

[0059] (3) If no abnormalities are found, turn on the power switch of the whole machine and turn on the control computer.

[0060] (4) Start the operating software AgingOI (such as...) for the control computer Figure 2 As shown in the figure, the power-on status of each slot card is automatically detected.

[0061] (5) Select the test program, download the test program to the driver board, and start the aging process.

[0062] (6) During the test, monitor the secondary power supply voltage, secondary power supply current and case temperature in real time. During the aging process, observe whether the parameters displayed by the software are normal. After the sampling time is reached, there should be corresponding data records.

[0063] (7) The aging process can be automatically ended after the aging time is reached, the aging process is turned off, and the power supply of the whole machine is turned off after the aging board is removed.

[0064] The integrated user software package is developed based on the Windows platform. It is fully functional and has good scalability. It supports mouse operation, provides network interface and data exchange capabilities, including AgingOI. The system also provides debugging software and tools, which can facilitate users to debug in the initial stage of product development, providing great convenience to users.

[0065] The overall testing process is as follows: Configure the vector parameters of the device under test using an Excel spreadsheet, including: slot channel management, digital channel output drive voltage range, DPS parameters, and drive signal rate.

[0066] The test vector can be freely edited using the pattern; Set the test parameters in the AgingOI software; Real-time display of vector comparison results; such as Figure 6 The diagram shows the measured waveform of the 100MHz output.

[0067] The operating procedures are as follows: (1) Check whether the aging boards at each workstation can move up and down to ensure good contact between the aging boards and the drive boards. The workstation viewing interface is as follows: Figure 4 As shown.

[0068] (2) When a batch of aging boards is aged for the first time, only one board is installed on the aging board. After debugging and inspection, it can be used in a formal manner.

[0069] (3) For the whole machine aging test, first turn on the main power switch of the system and power on, and then observe whether there are any abnormal voltage and current values ​​on the power meter of the aging equipment.

[0070] (4) When using AgingOI software to test on the control computer, check that there are no input errors in the corresponding items in the corresponding program library before downloading the corresponding program parameters to the test board.

[0071] (5) Special attention should be paid to parameters such as power supply voltage, power supply current and plate temperature during the testing of the re-aging equipment.

[0072] (6) After the aging test is completed, the aging state of each zone is ended in the system-specific software so that each aging zone returns to the idle state.

[0073] (7) Turn off the power supply for each stage of aging.

[0074] (8) Turn off the main power switch of the equipment.

[0075] The software system has a complete program library management function, with functions such as editing, creating, and deleting. For various types of test devices and different test conditions, independent device parameters can be compiled to form a program library. The corresponding device program library can be directly called up for each test, without the need for complicated parameter settings, process editing, and protection parameter settings.

[0076] The control operation is simple. As long as the program library parameters are downloaded to the corresponding aging tank, the user does not need to perform any other operations. Just click "Start Test" and the system will automatically enter the detection, monitoring and recording state until the test ends and a test report is generated. Test reports can save all data information electronically. During or after each test, the system can automatically generate a corresponding test report based on the test data. Current and historical test data can be queried, accessed, and printed at any time.

[0077] The aging zone can be paused, continued, or terminated during the test.

[0078] It can dynamically display the electrical parameters of each device and the test voltage and current value of each aging board channel in real time.

[0079] The aging time can be set arbitrarily, the test process is automatically controlled, and the system will automatically terminate the test or provide intermittent alarm prompts when the test time is up.

[0080] Device operating power supply information settings (protection voltage, current information, power-on timing control, etc.).

[0081] The aging test system provided in this embodiment uses an FPGA chip to control the heating device of each slot in real time, and uses a high-precision AD to monitor the case temperature of the chip under test in real time; the FPGA collects the voltage and current of each slot through the high-precision ADC; it supports temperature measurement and display of up to 32 slots; the FPGA summarizes and transmits back the real-time data.

[0082] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the systems disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple; relevant parts can be referred to the method section.

[0083] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. Furthermore, those skilled in the art will recognize that, based on the ideas of the present invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A test system for chip burn-in testing, the test system comprising: Comprise: Control module, using single-board single-area control mode, each drive test board independently controls a high-temperature aging area, and communicates with the upper computer through gigabit Ethernet; Power module, each slot drive board provides 4 programmable power supply channels, each power output voltage range is 0~5V, supports real-time monitoring of voltage and current and overcurrent, overvoltage and undervoltage protection; Digital channel module, supporting 16 slots, each slot has 192 I / O channels, a total of 3072 I / O channels, each channel can be independently configured as input, output or bidirectional mode; Algorithm module, supporting all 1, all 0, checkerboard, column step and user-defined algorithm, for generating test vectors; Signal format module, supporting RL, RH, NR, SBL, SBH, SBC waveform format output; Protection module, including three-color light state indication unit, buzzer alarm unit, watchdog protection unit and power supply unit, for ensuring test safety in abnormal conditions; High-temperature test chamber, providing aging environment from room temperature to 150℃, temperature control error ≤±3℃, supporting 16 slots aging at the same time; Software module, supporting aging program library management, real-time monitoring, data recording and report generation, supporting single-board testing through software, including loading test program, verifying program, running test and capturing test data functions.

2. The test system for chip burn-in testing of claim 1, wherein, The control module supports serial and parallel test modes; Supporting FPGA configuration program online download, different functions of aging test are realized by reconfiguring FPGA internal circuit; wherein, the FPGA configuration program realizes upgrade function through dynamic library, including device upgrade, register read and write and DDR data reading.

3. The test system for chip burn-in testing of claim 1, wherein, The ripple of each power supply of the power module is ≤10mV, and the load change rate is ≤10mV; Supporting current clamping protection and power-on and power-off timing control.

4. The test system for chip burn-in testing of claim 1, wherein, Each channel of the digital channel module supports 4 edge waveform outputs; supporting ATE vector conversion tool.

5. The test system for chip burn-in testing of claim 1, wherein, The high-temperature test chamber comprises: independent over-temperature protection device and leakage protection device, which automatically closes the heating and keeps the circulating air duct running when over-temperature; temperature uniformity ≤±2℃, temperature fluctuation ≤±0.5℃, supporting over-temperature alarm function.

6. The test system for chip burn-in testing of claim 1, wherein, The software module supports device library management, can call or edit historical aging programs; also supports real-time display of power voltage, current and temperature parameters of each slot, and generates temperature-time curve; also supports pause, continue and terminate operations during aging process.

7. A method of chip burn-in testing, the method comprising: Comprise the following steps: Step one: install the chip to be tested to the aging board and ensure good contact; Step two: turn on the system power supply and control computer, start the software, and automatically detect the power-on state of each slot; Step three: select the test program and download it to the drive board, set the aging parameters, including power voltage, current, temperature and aging time; Step four: start the aging test, real-time monitor the power voltage, current and shell temperature, and record the test data; Step five: when overcurrent, overvoltage, undervoltage or over-temperature is detected, automatically cut off the power and alarm; Step six: automatically terminate the test after the aging is completed, save the data and generate the test report.

8. The chip burn-in test method of claim 7, wherein, The step three further comprises: Selecting serial or parallel test mode according to chip type; Configure the FPGA internal circuit, download the corresponding configuration file to achieve full coverage of functions.

9. The chip burn-in test method of claim 7, wherein, The fourth step further comprises: Real-time display of three-color light status, green for normal, yellow for idle, and red for fault; Through the UPS power supply, the test is safely closed in the event of abnormal power failure; Among them, the three-color light is monitored in real time through the alarm detection module.

10. The chip burn-in test method of claim 7, wherein, The sixth step further comprises: Generate an electronic report containing temperature, voltage, and current data; Support historical data query, review, and printing; Among them, the test data is captured and error information is displayed through the software, and the comparison function with the expected value is supported.

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