Data processing device, data processing method, chip and electronic equipment

Abstract

The application discloses a data processing device, a data processing method, a chip and an electronic equipment, and relates to the technical field of data processing. The data processing device comprises a storage module configured to store data; and a calculation module coupled to the storage module and configured to: access an original data vector stored by the storage module, wherein the original data vector comprises m data elements; split the original data vector based on a target k value to obtain a plurality of first data vectors; perform odd-even merge sort on data elements in each of the first data vectors to obtain a plurality of first ordered data vectors; and perform merge sort on data elements in the first ordered data vectors to obtain top-k data elements in the m data elements. The data processing device, the data processing method, the chip and the electronic equipment provided by the application can obtain the top-k data elements without a special hardware sorting network.

Description

Technical Field

[0001] This application relates to the field of data processing technology, specifically to a data processing device, a data processing method, a chip, and an electronic device. Background Technology

[0002] In the technical framework of Large Language Models (LLM), the top-k operator is a core component balancing model efficiency and performance. Its core value lies in helping the model achieve efficient decision-making in complex natural language processing tasks by dynamically filtering key information. LLMs, represented by GPT, LLaMA, and BERT, need to complete core tasks such as text generation, semantic understanding, and logical reasoning. These tasks require the model to quickly locate key content from massive amounts of candidate information (such as words and knowledge fragments), and the top-k operator's characteristic of "taking the top k optimal solutions" precisely matches this high-frequency requirement.

[0003] Especially in Hybrid Expert Model (MoE) architectures, the top-k operator, as the core hub for achieving sparse activation and efficient computation, directly determines the model's resource allocation logic. Large MoE models refer to models that are split into multiple expert networks, using gating networks to dynamically select activated expert combinations for each input sample. The top-k operator is the "core engine" of this sparse activation technique, efficiently determining the subset of experts participating in the current computation by ranking expert matching scores, thus fundamentally breaking through the computational bottleneck of traditional dense models (such as Transformer). Because each layer of a traditional dense large model requires computation of all parameters of that layer, the computational load increases exponentially with model size (for example, the 175-parameter GPT-3 faces high inference costs). In contrast, the MoE large model achieves dynamic sparse activation through top-k routing and selects a small number of activation experts to participate in the computation, thereby significantly reducing the computational cost of the model. Therefore, while the model parameter scale expands to hundreds of billions or even trillions, the actual computational cost of the model can be controlled at a level comparable to that of small and medium-sized dense large models, thus significantly improving the scalability and economy of the model.

[0004] Given the crucial role of the top-k operator in large language models, researching and optimizing the computational efficiency of the top-k operator on hardware devices such as GPUs (Graphics Processing Units) / TPUs (Tensor Processing Units) (e.g., quickly extracting the indices and scores of the top k experts) will directly affect the training and inference speed of the MoE large model and become a key technical point connecting algorithm design and engineering implementation.

[0005] Existing technical solutions typically utilize dedicated hardware sorting networks to sort data in parallel, and then select the top-k data from the sorted results. While this approach, which relies on dedicated hardware, offers high execution efficiency, it requires software compilers to be customized to suit the characteristics of the dedicated hardware. This results in poor programming flexibility and versatility, and is not conducive to the expansion and migration of large models across different hardware platforms.

[0006] This section is intended to provide background or context for the embodiments of this application set forth in the claims. The description herein is not an admission that it is prior art simply because it is included in this section. Summary of the Invention

[0007] In order to solve at least one of the above-mentioned problems in the prior art, embodiments of this application provide a data processing apparatus, a data processing method, a chip, and an electronic device.

[0008] This application provides a data processing apparatus, including: a storage module configured to store data; and a computing module including a single instruction multiple data (SIMD) unit and a vector register group, wherein the SIMD unit is coupled to the vector register group, and the vector register group is coupled to the storage module. The computing module is configured to: access an original data vector stored in the storage module, wherein the original data vector contains m data elements, where m is a positive integer; split the original data vector based on a target value k to obtain multiple first data vectors, where k is a positive integer; map the data elements in each of the first data vectors to the vector register group, and use the SIMD unit to perform parallel comparison-swapping operations on the data elements in the vector register group to perform parity merge sort on the data elements in each of the first data vectors to obtain multiple first ordered data vectors; and merge sort the data elements in the multiple first ordered data vectors to obtain the top-k data elements among the m data elements.

[0009] In some embodiments, the calculation module splits the original data vector based on a target k value to obtain multiple first data vectors, including: calculating an integer greater than or equal to a power of 2 based on the target k value; and splitting the original data vector using the integer greater than or equal to a power of 2 as the grouping granularity to obtain multiple first data vectors.

[0010] In some embodiments, the computation module maps one data element from the first data vector to the vector register group each time, and uses the single instruction multiple data execution unit to perform parallel comparison-swapping operations on the data elements in the vector register group, thereby performing parity merge sort on the data elements in the first data vector to obtain a first ordered data vector; or, the computation module maps at least two data elements from the first data vector to the vector register group each time, and uses the single instruction multiple data execution unit to perform parallel comparison-swapping operations on the data elements in the vector register group, thereby performing parallel parity merge sort on the data elements in the at least two first data vectors to obtain a first ordered data vector corresponding to each of the at least two first data vectors.

[0011] In some embodiments, the computing module performs parity merge sort on the data elements in each of the first data vectors, including: mapping the data elements in the first data vector to the vector register group according to a first mapping rule; using the single instruction multiple data execution unit to perform parallel comparison-swapping operations on the data elements at the same position in the vector register group to obtain two first sub-data vectors; then, reversibly mapping the data elements in the two first sub-data vectors back to the address space where the storage module stores the first data vector according to the first mapping rule, so that the first data vector stored in the storage module is updated to the second data vector; and then processing the data elements in the second data vector... Data elements are mapped into the vector register group according to the second mapping rule. The single instruction multiple data execution unit (SID) performs parallel comparison-swapping operations on the data elements at the same position in the vector register group to obtain two second sub-data vectors. Then, the data elements in the two second sub-data vectors are reverse-mapped back to the address space of the storage module that stores the second data vector according to the second mapping rule, so that the second data vector stored in the storage module is updated to the third data vector. This process is repeated until the comparison-swapping operations required for one round of parity merge sort are completed, that is, the parity merge sort of the first data vector is completed, resulting in a first ordered data vector.

[0012] In some embodiments, mapping the data elements in the i-th data vector to the vector register group according to the i-th mapping rule includes: determining the pairs of data elements in the i-th data vector that need to be compared and swapped based on the odd-even merge sort algorithm, where i=1,2; mapping the two data elements in each pair of data elements to the same position in two different vector registers, wherein the data elements in each pair of data elements are mapped to the two different vector registers.

[0013] In some embodiments, the step of reverse mapping the data elements in the two i-th sub-data vectors back to the address space where the storage module stores the i-th data vector according to the i-th mapping rule, so that the i-th data vector stored in the storage module is updated to the (i+1)-th data vector, includes: determining the index value of each data element according to the position of each data element in the two vector registers, writing each data element in the two i-th sub-data vectors back to the storage module according to the index value, overwriting the data element with the corresponding index value of the i-th data vector stored in the storage module, so that the i-th data vector stored in the storage module is updated to the (i+1)-th data vector.

[0014] In some embodiments, when the computing module processes at least two of the first data vectors in parallel, the single instruction multiple data execution unit uses a single instruction multiple data operation instruction to execute in parallel the comparison-swap operation that can be executed in parallel during the parity merge sorting process of the at least two first data vectors.

[0015] In some embodiments, the calculation module performs merge sorting on the data elements in the plurality of first ordered data vectors to obtain the top-k data elements among the m data elements, including: grouping the plurality of first ordered data vectors into pairs, and merging and sorting the data elements in the two first ordered data vectors in each group to obtain a plurality of first target data vectors; extracting the top-b data elements of each first target data vector to generate a plurality of second ordered data vectors, where b is an integer greater than or equal to a power of 2 of the value of k; grouping the plurality of second ordered data vectors into pairs, and merging and sorting the data elements in the two second ordered data vectors in each group to obtain a plurality of second target data vectors; extracting the top-b data elements of each second target data vector to generate a plurality of third ordered data vectors; and so on, until an nth ordered data vector is generated; extracting the top-k data elements in the nth ordered data vector, where the top-k data elements in the nth ordered data vector are the top-k data elements among the m data elements.

[0016] In some embodiments, the calculation module groups the plurality of i-th ordered data vectors into pairs, and performs merge sorting on the data elements in the two i-th ordered data vectors within each group to obtain a plurality of i-th target data vectors. This includes: grouping the plurality of i-th ordered data vectors into pairs, processing one group of i-th ordered data vectors at a time, sequentially completing the merge sorting of the two i-th ordered data vectors within each group, and finally obtaining a plurality of i-th target data vectors; or, grouping the plurality of i-th ordered data vectors into pairs, processing at least two groups of i-th ordered data vectors in parallel each time, until the merge sorting of the two i-th ordered data vectors within each group is completed, and finally obtaining a plurality of i-th target data vectors; where i = 1, 2, 3, ..., n-1.

[0017] In some embodiments, the computing module merges and sorts the data elements of the two i-th ordered data vectors within each group, including: mapping the data elements of the two i-th ordered data vectors within the group to the vector register group according to a third mapping rule; using the single instruction multiple data execution unit to perform parallel comparison-swapping operations on the data elements at the same position in the vector register group to obtain two first intermediate data vectors; then, reversibly mapping the data elements of the two first intermediate data vectors back to the storage module according to the third mapping rule to obtain two second intermediate data vectors; and finally, sorting the data elements of the two second intermediate data vectors... The data elements are mapped to the vector register group according to the fourth mapping rule. The single instruction multiple data execution unit performs parallel comparison-swapping operations on the data elements at the same position in the vector register group to obtain two third intermediate data vectors. Then, the data elements in the two third intermediate data vectors are reverse-mapped back to the storage module according to the fourth mapping rule to obtain two fourth intermediate vectors. This process is repeated until the comparison-swapping operations required for one round of merge sort are completed, that is, the merge sort of the two i-th ordered data vectors is completed to obtain an i-th target data vector, where i=1,2,3,…,n-1.

[0018] In some embodiments, mapping the data elements of the two i-th ordered data vectors within the group to the vector register group according to a third mapping rule includes: determining, based on a set merge sort algorithm, that there are first valid data element pairs in the two i-th ordered data vectors within the group that need to be compared and swapped; mapping the two data elements in each of the first valid data element pairs to the same position in two different vector registers, wherein the data elements in each of the first valid data element pairs are mapped to the two different vector registers; mapping the data elements of the two second intermediate data vectors to the vector register group according to a fourth mapping rule includes: determining, based on the set merge sort algorithm, that there are second valid data element pairs in the two second intermediate data vectors that need to be compared and swapped; mapping the two data elements in each of the second valid data element pairs to the same position in two different vector registers, wherein the data elements in each of the second valid data element pairs are mapped to the two different vector registers.

[0019] In some embodiments, the step of reverse mapping the data elements of the two first intermediate data vectors back to the storage module according to the third mapping rule to obtain two second intermediate data vectors includes: determining the index value of each data element according to the position of each data element in the two first intermediate data vectors in the two vector registers, writing each data element in the two first intermediate data vectors back to the storage module according to the index value, overwriting the data elements corresponding to the index values ​​of the two i-th ordered data vectors stored in the storage module, so that the two i-th ordered data vectors stored in the storage module are updated to two second intermediate data vectors; the step of reverse mapping the two third intermediate data vectors back to the storage module according to the fourth mapping rule to obtain two fourth intermediate vectors includes: determining the index value of each data element according to the position of each data element in the two third intermediate data vectors in the two vector registers, writing each data element in the two third intermediate data vectors back to the storage module according to the index value, overwriting the data elements corresponding to the index values ​​of the two second intermediate data vectors stored in the storage module, so that the two second intermediate data vectors stored in the storage module are updated to two fourth intermediate data vectors.

[0020] In some embodiments, when the computing module processes at least two sets of the i-th ordered data vectors in parallel each time, the single instruction multiple data execution unit uses a single instruction multiple data operation instruction to execute the comparison-swap operation that can be executed in parallel during the merge sorting process of the two sets of i-th ordered data vectors.

[0021] In some embodiments, the comparison-swapping operation performed on the data elements in the first valid data element pair is a comparison-swapping operation that contributes to the identification of the top-k data elements; the comparison-swapping operation performed on the data elements in the second valid data element pair is a comparison-swapping operation that contributes to the identification of the top-k data elements.

[0022] In some embodiments, the system further includes: an instruction decoding unit coupled to the storage module and configured to parse RISC-V instructions extracted from the storage module; and a scheduler coupled to the instruction decoding unit and the computing module and configured to determine the execution order of each RISC-V instruction based on the instruction characteristics of the RISC-V instructions and the resource status of the computing module, such that the single instruction multiple data execution unit executes the RISC-V instructions in the execution order of each RISC-V instruction.

[0023] In some embodiments, the storage module includes a static random access memory coupled to the computing module and configured to store data and RISC-V instructions.

[0024] In some embodiments, the system further includes: an instruction cache unit coupled to the static random access memory (SRAM) and configured to retrieve and store RISC-V instructions from the SRAM; and an instruction fetch cache unit coupled to the instruction cache unit and the instruction decoding unit and configured to store RISC-V instructions retrieved from the instruction cache unit in an ordered manner, such that the instruction decoding unit retrieves RISC-V instructions from the instruction fetch cache unit.

[0025] This application embodiment also provides a data processing method, including: accessing an original data vector stored in a storage module, wherein the original data vector contains m data elements, where m is a positive integer; splitting the original data vector based on a target k value to obtain multiple first data vectors, where k is a positive integer; mapping the data elements in each of the first data vectors to the vector register group respectively, and using the single instruction multiple data execution unit to perform parallel comparison-swapping operations on the data elements in the vector register group to achieve parity merge sorting of the data elements in each of the first data vectors respectively, to obtain multiple first ordered data vectors; and merging sorting the data elements in the multiple first ordered data vectors to obtain the top-k data elements among the m data elements.

[0026] This application also provides a chip, which includes the data processing device described in any of the above embodiments.

[0027] This application also provides an electronic device, which includes the chip described in any of the above embodiments.

[0028] The data processing apparatus, data processing method, chip, and electronic device proposed in this application split the original data vector to obtain multiple first data vectors. Then, the data elements in each of the first data vectors are mapped to the vector register group. The single instruction multiple data execution unit (SMI) performs parallel comparison-swapping operations on the data elements in the vector register group, thereby performing parity merge sort on the data elements in each of the first data vectors to obtain multiple first ordered data vectors. Next, the data elements in the multiple first ordered data vectors are merge sorted to obtain the top-k data elements among the m data elements. Thus, based on the parity merge sort algorithm and the merge sort algorithm, the top-k data elements among the m data elements can be obtained without a dedicated hardware sorting network, avoiding dependence on dedicated hardware and improving programming flexibility and versatility. This is beneficial for the expansion and migration of large models across different hardware platforms. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings:

[0030] Figure 1 This is a schematic diagram of the structure of a data processing device provided in an embodiment of this application.

[0031] Figure 2 This is a schematic diagram of the algorithm flow for selecting the largest or smallest k data points from m data points, provided in an embodiment of this application.

[0032] Figure 3 This is a comparison diagram of the data bit width and data precision processed by a single instruction in a vector processor using a SIMD architecture, provided in an embodiment of this application.

[0033] Figure 4 This is a schematic diagram of an 8-element odd-even merge sort network provided in an embodiment of this application.

[0034] Figure 5 This is a schematic diagram of a process for performing parity-even merge sort on data elements in a first data vector, provided in an embodiment of this application.

[0035] Figure 6 This is a schematic diagram illustrating how operands in a parallel block of an odd-even merge sort network are mapped to a vector register, as provided in an embodiment of this application.

[0036] Figure 7 This is a schematic diagram illustrating the execution steps of a single compare-swap operation based on the RISC-V vector extension instruction architecture, as provided in an embodiment of this application.

[0037] Figure 8 This is a schematic diagram of a process provided in this application embodiment to map data elements in the i-th data vector to the vector register group according to the i-th mapping rule.

[0038] Figure 9 This is a flowchart illustrating a process of merging and sorting data elements in multiple first ordered data vectors to obtain the top-k data elements, as provided in an embodiment of this application.

[0039] Figure 10 This is a schematic diagram of a process for merging and sorting data elements of two i-th ordered data vectors within each group, provided by an embodiment of this application.

[0040] Figure 11 This is a comparative diagram of a trimmed merge sort method provided in an embodiment of this application and a conventional merge sort method.

[0041] Figure 12 This is a schematic diagram of a process provided in this application embodiment to map data elements in two i-th ordered data vectors within a group to the vector register group according to a third mapping rule.

[0042] Figure 13 This is a schematic diagram of a process provided in this application embodiment to map data elements in two second intermediate data vectors to the vector register group according to the fourth mapping rule.

[0043] Figure 14 This is a schematic diagram of the structure of a data processing device provided in an embodiment of this application.

[0044] Figure 15 This is a schematic diagram comparing the bit width and data precision of SIMD processing according to an embodiment of this application.

[0045] Figure 16 This is a schematic diagram illustrating how a comparison-exchange operation of four ordered sequences is mapped to ten SIMD operations, as provided in an embodiment of this application.

[0046] Figure 17 This is a schematic diagram of the execution flow of each SIMD operation provided in an embodiment of this application.

[0047] Figure 18 This is a schematic diagram illustrating how the comparison-swapping operations of four ordered sequences can be integrated into five SIMD operations in one embodiment of this application.

[0048] Figure 19 This is a schematic diagram illustrating how the comparison-exchange operation of two sets of ordered 8-element sequences can be integrated into 4 SIMD operations in one embodiment of this application.

[0049] Figure 20 This is a flowchart illustrating a data processing method provided in an embodiment of this application.

[0050] Figure 21 This is a block diagram of an electronic device provided in an embodiment of this application. Detailed Implementation

[0051] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component reference numerals are used in the drawings and description to denote the same or similar parts.

[0052] The term "coupled (or connected)" as used throughout this specification (including the claims) may refer to any direct or indirect means of connection. For example, if the text describes a first device coupled (or connected) to a second device, it should be interpreted as the first device being directly connected to the second device, or the first device being indirectly connected to the second device through other devices or some means of connection. The terms "first," "second," etc., used throughout this specification (including the claims) are used to name components and are not intended to limit the upper or lower limit of the number of components, nor to limit the order of components. Furthermore, wherever possible, components / components / steps using the same reference numerals in the drawings and embodiments represent the same or similar parts. Components / components / steps using the same reference numerals or the same terms in different embodiments may be referred to mutually in the relevant descriptions.

[0053] Figure 1 This application provides a schematic diagram of the structure of a data processing device, as shown below. Figure 1 As shown, this application provides a data processing apparatus 100, including:

[0054] Storage module 1 is configured to store data;

[0055] The computation module 2 includes a single instruction multiple data (SIMD) execution unit 21 and a vector register group 22. The SIMD 21 is coupled to the vector register group 22, and the vector register group 22 is coupled to the storage module 1. The computation module 2 is configured to: access an original data vector stored in the storage module, wherein the original data vector contains m data elements, where m is a positive integer; split the original data vector based on a target value k to obtain multiple first data vectors, where k is a positive integer; map the data elements in each of the first data vectors to the vector register group 22, and use the SIMD 21 to perform parallel comparison-swapping operations on the data elements in the vector register group 22 to perform parity merge sort on the data elements in each of the first data vectors, thereby obtaining multiple first ordered data vectors; and merge sort the data elements in the multiple first ordered data vectors to obtain the top-k data elements among the m data elements.

[0056] The data processing apparatus provided in this application splits the original data vector into multiple first data vectors. Then, the data elements in each of the first data vectors are mapped to the vector register group. The single instruction multiple data execution unit (SMI) performs parallel comparison-swapping operations on the data elements in the vector register group, thereby performing odd-even merge sort on the data elements in each of the first data vectors to obtain multiple first ordered data vectors. Next, the data elements in the multiple first ordered data vectors are merge sorted to obtain the top-k data elements among the m data elements. Thus, based on the odd-even merge sort algorithm and the merge sort algorithm, the top-k data elements among the m data elements can be obtained without a dedicated hardware sorting network, avoiding dependence on dedicated hardware and improving programming flexibility and versatility. This is beneficial for the expansion and migration of large models across different hardware platforms.

[0057] In some embodiments, the calculation module splits the original data vector based on a target k value to obtain multiple first data vectors, including: calculating an integer greater than or equal to a power of 2 based on the target k value; and splitting the original data vector using the integer greater than or equal to a power of 2 as the grouping granularity to obtain multiple first data vectors.

[0058] For example, Figure 2 This demonstrates the process of selecting the k largest or smallest data points from m data points. The specific steps are as follows:

[0059] The first step is to determine the grouping granularity: Based on the value of k, determine an integer b that is a power of 2 greater than or equal to k. For example, if k=5, then b=8 (2 to the power of 3).

[0060] The second step is data grouping: the m data points are divided into m / b groups with a grouping granularity of b.

[0061] The third step is to sort the data within each group: use the odd-even merge sort algorithm to sort the data within each group, resulting in m / b ordered groups of data.

[0062] The fourth step is the merge sort loop: group the multiple sets of ordered data into pairs and perform merge sort; then extract the first b data from each merge sorted data set to obtain a new set of ordered data; check if the number of ordered data sets is equal to 1. If it is not equal to 1, repeat the merge sort steps.

[0063] Step 5, extract the results: When the number of ordered data groups is equal to 1, extract the first k data from the b ordered data in that group, which are the k largest or smallest data selected in the end.

[0064] In some embodiments, the calculation module 2 maps a data element from one of the first data vectors to the vector register group 22 each time, and uses the single instruction multiple data execution unit 21 to perform parallel comparison-swapping operations on the data elements in the vector register group 22, thereby performing parity merge sort on the data elements in the first data vector to obtain a first ordered data vector; or, the calculation module 2 maps at least two data elements from the first data vectors to the vector register group 22 each time, and uses the single instruction multiple data execution unit 21 to perform parallel comparison-swapping operations on the data elements in the vector register group 22, thereby performing parallel parity merge sort on the data elements in the at least two first data vectors to obtain a first ordered data vector corresponding to each of the at least two first data vectors.

[0065] Specifically, the calculation module 2 can sequentially perform parity merge sort on the data elements in each of the first data vectors, or it can perform parity merge sort on the data elements in multiple first data vectors in parallel. The number of first data vectors processed in parallel each time can be determined according to the SIMD (Single Instruction Multiple Data) width of the calculation module.

[0066] like Figure 1 As shown, in some embodiments, in tasks requiring extensive parallel data processing, the data bit width of a single vector register can be equal to the data bit width of the SIMD, using vector register set 22 to store multiple data elements and cooperating with the SIMD execution unit to achieve parallel computation. The SIMD execution unit can perform the same operation on multiple data in vector register set 22 simultaneously under the control of a single instruction, accelerating data processing.

[0067] When it is necessary to select the largest or smallest k data points (top-k) from m data points, where 1 = < k < m, for scalar processor architectures, sorting algorithms such as bubble sort are usually used to compare and swap the m elements in turn, and finally select the required top-k data points from the original m data points. However, this scalar processor is a serial data processing architecture with low data processing efficiency. As m increases, the processing time will increase sharply.

[0068] like Figure 3 As shown, for vector processors using the SIMD architecture, the data bit width processed by a single instruction is very large (e.g., 128 bits). When the precision of each data is 8 bits, 16 bits, or 32 bits, a single instruction of the processor can process 16, 8, or 4 data simultaneously, significantly improving data processing efficiency.

[0069] Although a single instruction in a SIMD architecture can process multiple data points in parallel, these data points must be independent of each other. If dependencies exist, these data points cannot be executed in parallel within a single instruction. Furthermore, while SIMD architecture provides a large data processing bit width, offering the hardware foundation for parallel execution of multiple data points, the actual number of data points that can be executed in parallel may be less than the maximum number of parallel data points in a SIMD architecture due to data dependencies. This leads to reduced utilization of the SIMD execution unit; for example, in practice, only four data points (precision = 16 bits) can be processed in parallel, resulting in low hardware utilization. If this happens, the parallel computing performance of the SIMD execution unit will decrease by 50%. Therefore, to ensure the efficiency of top-k operator execution, it is crucial to study the parallel execution strategy of data on the SIMD architecture.

[0070] Batcher's Odd-Even Network is a parallel sorting algorithm based on a comparison network. Its core idea is to recursively merge elements at odd and even positions to construct a data-independent sorting network. This algorithm offers significant advantages in hardware implementation, making it particularly suitable for applications requiring high parallelism. Figure 4 This is a schematic diagram of an 8-element parity merge sort network provided in an embodiment of this application. Wherein,

[0071] 0~7: Represents data 0~7, with each horizontal line corresponding to a data element.

[0072] Dashed box (parallelizable block): Independent operation units are divided according to the dashed box. The operations within each block can be executed simultaneously, which reflects the parallelism of the algorithm.

[0073] The arrows within the dashed box indicate comparison-swap operations, with the arrow direction reflecting the direction of the data comparison. For example, up and down arrows indicate comparison of adjacent or specific data positions; if the order is incorrect, the data is swapped.

[0074] In odd-even merge sort, the sorting process is divided into multiple parallel blocks. The comparison-swap operations within each block can be executed simultaneously, which facilitates the parallel use of hardware resources. Different parallel blocks need to be executed from left to right. The data sorting is completed after all the operations in the parallel blocks have been executed.

[0075] Based on this feature of the odd-even merge sort network, such as Figure 5 As shown, the calculation module performs parity merge sort on each data element in the first data vector, which may include:

[0076] S11. Map the data elements in the first data vector to the vector register group according to the first mapping rule. Use the single instruction multiple data execution unit to perform parallel comparison-exchange operations on the data elements at the same position in the vector register group to obtain two first sub-data vectors. Then, reverse map the data elements in the two first sub-data vectors back to the address space where the storage module stores the first data vector according to the first mapping rule, so that the first data vector stored in the storage module is updated to the second data vector.

[0077] In step S11, the odd-even merge sort algorithm is used to sort the data elements in each first data vector, see [link to step S11]. Figure 4 For each first data vector, the comparison-swap operations within each parallel block of the corresponding odd-even merge sort network can be executed in parallel. To further explore the data parallelism capability of the top-k operator, the comparison-swap operations within the same parallel block can be mapped to a SIMD operation. For example... Figure 6 As shown, the two operands of the comparison-swap operation within the same parallel block of an even-odd merge sort network are mapped to two different vector registers, which makes it easier for the SIMD execution unit to perform parallel processing on the vector registers using a single instruction.

[0078] Based on the above data mapping scheme, the complete execution steps of a single comparison-swap operation are explained in detail below.

[0079] Figure 7 This demonstrates the execution steps of a single compare-swap operation based on the RISC-V vector extension instruction architecture. For example... Figure 7 As shown, the execution steps of a single compare-swap operation based on the RISC-V vector extension instruction architecture are as follows:

[0080] Step 1 (Data Reading): Read the two sets of vectors vs1 and vs2 to be compared from the storage module (e.g., SRAM, static random access memory), as well as the index vectors vs3 and vs4 that record the positions of the data elements in the vectors, and store vs1, vs2, vs3 and vs4 in the vector register to prepare data for subsequent operations.

[0081] In step 1, data elements in the first data vector stored in the storage module can be read based on the above data mapping rules. The required data elements are extracted and formed into two sets of vectors vs1 and vs2, which are then stored in two vector registers respectively.

[0082] Step 2 (Element Comparison): Use the compare instruction in the RISC-V vector extension instruction set, such as vmfne (to determine if they are equal), vmflt (to determine if they are less than), vmfle (to determine if they are less than or equal to), vmfgt (to determine if they are greater than), and vmfge (to determine if they are greater than or equal to), to compare the elements at the same position in vectors vs1 and vs2, and obtain a bit-mask value (represented by v0) that indicates the size relationship between the elements in the two sets of vectors. This value is used to identify the comparison result of each pair of elements (such as greater than, less than, or equal to).

[0083] Step 3 (Selection and Merging): Using the merge instruction in the vector extension instruction set, such as vmerge, vectors vs1 and vs2 are selected and merged based on the bit-mask value v0, generating two new vectors vd1 and vd2; simultaneously, vectors vs3 and vs4 are selected and merged based on v0, resulting in two new vectors vd3 and vd4. This step achieves the selection and recombination of vector element values ​​and indices based on the comparison results.

[0084]

[0085]

[0086]

[0087]

[0088] Step 4 (Result Write-back): Assign the new vectors vd1 and vd2 to vs1 and vs2 respectively, or write them back to the storage module directly; similarly, assign the new vectors vd3 and vd4 to vs3 and vs4 respectively, or write them back to the storage module, thereby completing a comparison-exchange operation on the data elements in the first data vector.

[0089] S12. Map the data elements in the second data vector to the vector register group according to the second mapping rule. Use the single instruction multiple data execution unit to perform parallel comparison-swapping operations on the data elements at the same position in the vector register group to obtain two second sub-data vectors. Then, reverse map the data elements in the two second sub-data vectors back to the address space of the storage module storing the second data vector according to the second mapping rule, so that the second data vector stored in the storage module is updated to the third data vector.

[0090] The execution process of step S12 is similar to that of step S11, the difference being that in step S12, data elements are mapped and inversely mapped according to the second mapping rule. Figure 6 Taking the odd-even merge sort network in the upper left corner as an example, such as Figure 6 As shown, for a first data vector, during the first comparison and swap operation on the data elements in the first data vector, the data elements to be compared and swapped in parallel block 0 are mapped to two vector registers respectively. During the second comparison and swap operation, the data elements to be compared and swapped in parallel block 1 are mapped to two vector registers respectively. In other words, the difference between steps S12 and S11 lies only in the different data elements to be operated on, hence the corresponding data mapping rules are also different. Their execution processes are similar, therefore the execution process of step S12 will not be elaborated upon here; please refer to the detailed description of the execution process of step S11 above.

[0091] S13. Continue in this manner until the comparison-exchange operation required for one round of parity merge sort is completed, that is, the parity merge sort of the first data vector is completed, and a first ordered data vector is obtained.

[0092] Step S13: When sorting the data elements in a data vector, the execution process of each comparison-swap operation is similar, only the mapping rule used each time is different. After completing the comparison-swap operations required for one round of parity merge sort, the parity merge sort of the first data vector is completed, resulting in a first ordered data vector.

[0093] like Figure 8 As shown, in some embodiments, mapping the data elements in the i-th data vector to the vector register group according to the i-th mapping rule includes:

[0094] S21. Based on the odd-even merge sort algorithm, determine the data element pairs in the i-th data vector that need to be compared and swapped, where i=1,2;

[0095] S22. Map the two data elements in each data element pair to the same position in two different vector registers, wherein the data elements in each data element pair are mapped to the two different vector registers.

[0096] For example, Figure 6 The parity merge sorting network in the upper left corner illustrates the parity merge sorting process of a first data vector. First, based on the parity merge sorting algorithm, the pairs of data elements in the original first data vector that need to be compared and swapped (see parallel block 0) are determined to be (d0, d1), (d2, d3), (d4, d5), and (d6, d7). At this time, d0, d1, d2, d3, d4, d5, d6, and d7 represent the data elements with indices 0, 1, 2, 3, 4, 5, 6, and 7 in the first data vector, respectively. Next, the two data elements in each pair are mapped to two different vector registers. Figure 6 The upper right corner corresponds to the two vector registers of SIMD0. Then, based on the SIMD0 operation, a comparison-swapping operation is performed on the data elements at the same position in the two vector registers. After completing the comparison-swapping operation, two first sub-data vectors are obtained. After the data elements in these two first sub-data vectors are reverse-mapped back to the memory module, the second data vector is obtained.

[0097] Next, based on the odd-even merge sort algorithm, the data element pairs in the second data vector that need to be compared and swapped (see parallel block 1) are determined to be (d0, d2), (d1, d3), (d4, d6), and (d5, d7). At this time, d0, d1, d2, d3, d4, d5, d6, and d7 represent the data elements with indices 0, 1, 2, 3, 4, 5, 6, and 7 in the second data vector, respectively. Then, the two data elements in each data element pair are mapped to two different vector registers. Figure 6 The top right corner corresponds to the two vector registers of SIMD1. Then, based on SIMD1 operations, a comparison-swapping operation is performed on the data elements at the same position in the two vector registers. After completing the comparison-swapping operation, two second sub-data vectors are obtained. After the data elements in these two second sub-data vectors are reverse-mapped back to the memory module, a third data vector is obtained.

[0098] And so on.

[0099] In some embodiments, the step of reverse mapping the data elements in the two i-th sub-data vectors back to the address space where the storage module stores the i-th data vector according to the i-th mapping rule, so that the i-th data vector stored in the storage module is updated to the (i+1)-th data vector, includes: determining the index value of each data element according to the position of each data element in the two vector registers, writing each data element in the two i-th sub-data vectors back to the storage module according to the index value, overwriting the data element with the corresponding index value of the i-th data vector stored in the storage module, so that the i-th data vector stored in the storage module is updated to the (i+1)-th data vector.

[0100] Continue with Figure 6 For example, suppose the original first data vector is (1,3,5,2,4,8,6,7), and the goal is to obtain the k largest data elements. After the SIMD0 operation, the two first sub-data vectors obtained are (3,5,8,7) and (1,2,4,6). Next, determine the index of data element 3 in the first sub-data vector (3,5,8,7) as 0, the index of data element 5 as 1, the index of data element 8 as 2, and the index of data element 7 as 3. In the first sub-data vector (1,2,4,6), determine the index of data element 1 as 4, the index of data element 2 as 5, the index of data element 4 as 6, and the index of data element 6 as 7. Write each data element in the two first sub-data vectors back to the storage module according to the index value, overwriting the data element with the corresponding index value of the first data vector stored in the storage module, so that the first data vector stored in the storage module is updated to the second data vector (3,5,8,7,1,2,4,6).

[0101] Next, the data elements in the second data vector (3,5,8,7,1,2,4,6) are mapped to two vector registers and a SIMD1 operation is performed to obtain two second sub-data vectors (8,7,3,5) and (4,6,1,2). Then, the indices of data element 8 in the second sub-data vector (8,7,3,5) are determined to be 0, 7 to be 1, 3 to be 2, and 5 to be 3. The indices of data element 4 in the second sub-data vector (4,6,1,2) are determined to be 4, 6 to be 5, 1 to be 6, and 2 to be 7. Each data element in the two second sub-data vectors is written back to the storage module according to its index value, overwriting the data element with the corresponding index value of the second data vector stored in the storage module, so that the second data vector stored in the storage module is updated to the third data vector (8,7,3,5,4,6,1,2).

[0102] Then, the data elements in the third data vector (8,7,3,5,4,6,1,2) that need to be compared and swapped (see parallel block 2) are mapped to two vector registers, one storing vector (7,6) and the other storing (3,1). Then, a SIMD2 operation is performed to obtain two second sub-data vectors (7,6) and (3,1). Next, the index of data element 7 in the third sub-data vector (7,6) is determined to be 1, the index of data element 6 to be 5, the index of data element 3 in the third sub-data vector (3,1) to be 2, and the index of data element 1 to be 6. Each data element in the two third sub-data vectors is written back to the storage module according to its index value, overwriting the data element with the corresponding index value of the third data vector stored in the storage module, so that the third data vector stored in the storage module is updated to the fourth data vector (8,7,3,5,4,6,1,2).

[0103] And so on, eventually we get an ordered vector (8,7,6,5,4,3,2,1).

[0104] In some embodiments, when the computing module processes at least two of the first data vectors in parallel, the single instruction multiple data execution unit uses a single instruction multiple data operation instruction to execute in parallel the comparison-swap operation that can be executed in parallel during the parity merge sorting process of the at least two first data vectors.

[0105] For details, see Figure 6 If the SIMD width of the computation module (e.g., a vector processor) allows, data from the first parallel block of two different parity merge sort networks (corresponding to two first data vectors) can be mapped to a single SIMD operation, data from the second parallel block of the same two parity merge sort networks can be mapped to another SIMD operation, and so on. It is understood that, if the SIMD width of the computation module allows, data from the first parallel block of three or more parity merge sort networks can also be mapped to a single SIMD operation, data from the second parallel block can be mapped to another SIMD operation, and so on. The data mapping scheme proposed in this embodiment facilitates the efficient implementation of top-k operators based on a SIMD parallel processing architecture.

[0106] like Figure 9 As shown, in some embodiments, the calculation module performs merge sorting on the data elements in the plurality of first ordered data vectors to obtain the top-k data elements among the m data elements, including:

[0107] S21. The plurality of first ordered data vectors are grouped into pairs, and the data elements in the two first ordered data vectors in each group are merged and sorted to obtain a plurality of first target data vectors.

[0108] In step S21, after merging and sorting two ordered data vectors in a set, a target data vector is obtained, in which at least the first b data elements are ordered, or all data elements in the target data vector are ordered.

[0109] S22. Extract the top-b data elements of each of the first target data vectors to generate multiple second ordered data vectors, where b is an integer greater than or equal to the value of k, which is a power of 2.

[0110] In step S22, the integer b can be the same as the grouping granularity of the original data vector, or it can be different.

[0111] S23. The plurality of second ordered data vectors are grouped into pairs, and the data elements of the two second ordered data vectors in each group are merged and sorted to obtain a plurality of second target data vectors.

[0112] S24. Extract the top-b data elements of each of the second target data vectors to generate multiple third ordered data vectors;

[0113] S25. Continue in this manner until an nth ordered data vector is generated;

[0114] S26. Extract the top-k data elements from the nth ordered data vector, wherein the top-k data elements in the nth ordered data vector are the top-k data elements among the m data elements.

[0115] Specifically, in each merge sort loop, multiple ordered data vectors are first grouped into pairs, and then the two ordered data vectors in each group are merge sorted to obtain the target data vector. Then, the top-b data elements of each target data vector are extracted to obtain a new ordered data vector. This loop is executed until the number of ordered data vectors obtained is equal to 1. The first k data are extracted from the ordered data vector, which are the final selected largest or smallest k data.

[0116] In some embodiments, the calculation module groups the plurality of i-th ordered data vectors into pairs, and merges and sorts the data elements in the two i-th ordered data vectors within each group to obtain a plurality of i-th target data vectors, including:

[0117] The plurality of i-th ordered data vectors are grouped pairwise, and each time a group of i-th ordered data vectors is processed, the merge sort of the two i-th ordered data vectors in each group is completed sequentially, and finally a plurality of i-th target data vectors are obtained; or,

[0118] The plurality of i-th ordered data vectors are grouped in pairs, and at least two groups of i-th ordered data vectors are processed in parallel each time until the merging and sorting of the two i-th ordered data vectors in each group is completed, and finally a plurality of i-th target data vectors are obtained, where i=1,2,3,…,n-1.

[0119] Specifically, in each merge sort loop, multiple ordered data vectors need to be grouped into pairs. Then, the data elements in the two ordered data vectors within each group are merge sorted. When merging sorting the data elements in the two ordered data vectors within each group, one group of ordered data vectors can be processed at a time to complete the merge sorting of the two ordered data vectors within each group sequentially. Alternatively, at least two groups of ordered data vectors can be processed in parallel each time until the merge sorting of the two ordered data vectors within each group is completed.

[0120] like Figure 10 As shown, in some embodiments, the calculation module performs merge sorting on the data elements of the two i-th ordered data vectors within each group, including:

[0121] S31. Map the data elements of the two i-th ordered data vectors in the group to the vector register group according to the third mapping rule. Use the single instruction multiple data execution unit to perform parallel comparison-exchange operations on the data elements at the same position in the vector register group to obtain two first intermediate data vectors. Then, reverse map the data elements of the two first intermediate data vectors back to the storage module according to the third mapping rule to obtain two second intermediate data vectors.

[0122] Step S31 involves using a conventional merge sort algorithm to map the data elements of the two i-th ordered data vectors within a group to two vector registers, with one i-th ordered data vector mapped to one vector register and the other to the other. Then, the single instruction multiple data execution unit (SIM) performs parallel comparison-swapping operations on the data elements at the same positions in the two vector registers to obtain two first intermediate data vectors. Next, the data elements of these two first intermediate data vectors are written back to the storage module to obtain two second intermediate data vectors. The data elements of the two first intermediate data vectors can be written back to the address space in the storage module where the two i-th ordered data vectors are stored. At this point, the storage module updates the two i-th ordered data vectors to the two second intermediate data vectors, which can be identical to the two first intermediate data vectors.

[0123] Taking the merge sort of two sets of 8-element data as an example, when k=7, the conventional merge sort algorithm merges and sorts the ordered sequences of the two sets of 8-element data. The goal is to output a complete ordered sequence of 16 elements. By performing a complete comparison-exchange operation on all elements, the overall orderliness of the sequence is ensured (regardless of whether these comparison-exchange operations are related to the top-7 output sequence), so that all 16 elements in the final output are ordered.

[0124] However, in the top-k problem, it is usually only necessary to ensure that the first k data in the output result are ordered sequences, while the conventional merge sort aims to make the entire output result ordered. Therefore, the efficiency of the top-k operator can be improved by pruning some comparison-swap operations that do not contribute to the top-k output, reducing redundant processing logic. Figure 11 This is a comparison diagram of regular merge sort and optimized merge sort. In the scenario of k=7, since it is only necessary to ensure that the first k elements in the output are ordered, the regular merge sort is eliminated by identifying and retaining the comparison-exchange operations related to the first 7 elements. Figure 11 The comparison-swap operations on the left that do not contribute to the top-7, such as... Figure 11 Nine comparison-swap operations are pruned, namely (7,15), (7,11), (7,9), (7,8), (10,12), (11,13), (9,10), (11,12), and (13,14), to avoid invalid processing of invalid elements and thus improve the efficiency of operator execution.

[0125] Therefore, in step S31, the data elements in the two i-th ordered data vectors within a group can be mapped to the two vector registers according to the mapping rules of the optimized merge sort algorithm. The subsequent comparison-swap operation, reverse mapping, and write-back operation are similar to the conventional merge sort operation.

[0126] S32. Map the data elements in the two second intermediate data vectors to the vector register group according to the fourth mapping rule. Use the single instruction multiple data execution unit to perform parallel comparison-exchange operations on the data elements at the same position in the vector register group to obtain two third intermediate data vectors. Then, reverse map the data elements in the two third intermediate data vectors back to the storage module according to the fourth mapping rule to obtain two fourth intermediate vectors.

[0127] The execution process of step S32 is similar to that of step S31, and will not be described again here.

[0128] S33. Continue in this manner until the comparison-exchange operation required for one round of merge sort is completed, that is, the merge sort of the two i-th ordered data vectors is completed to obtain an i-th target data vector, where i=1,2,3,…,n-1.

[0129] Specifically, after completing the comparison-swap operations required for one round of merge sort, two data vectors are obtained. These two data vectors are then concatenated to obtain the i-th target data vector. For example, if the desired top-k data elements are the k largest data elements among m data elements, then during concatenation, the data vector with the larger data element is placed first, and the data vector with the smaller data element is placed last. If the desired top-k data elements are the k smallest data elements among m data elements, then during concatenation, the data vector with the smaller data element is placed first, and the data vector with the larger data element is placed last.

[0130] It should be understood that if the conventional merge sort algorithm is used to merge and sort the data elements of the two i-th ordered data vectors in each group, then the data elements in the i-th target data vector obtained in step S33 above are an ordered sequence; if the optimized merge sort algorithm is used to merge and sort the data elements of the two i-th ordered data vectors in each group, then at least the first b data elements in the i-th target data vector obtained in step S33 above are ordered.

[0131] like Figure 12As shown, in some embodiments, mapping the data elements of the two i-th ordered data vectors within the group to the vector register group according to the third mapping rule includes:

[0132] S41. Based on the set merge sort algorithm, determine the first effective data element pair that needs to be compared and swapped between the two i-th ordered data vectors in the group.

[0133] S41. Map the two data elements in each of the first valid data element pairs to the same position in two different vector registers, wherein the data elements in each of the first valid data element pairs are mapped to the two different vector registers.

[0134] Specifically, the set merge sort algorithm can be a conventional (or classic) merge sort algorithm, or the optimized merge sort algorithm described above. For each round of merge sorting, after grouping the ordered data vectors, the data elements in the two ordered data vectors within each group are mapped to two vector registers according to the set merge sort algorithm. The third mapping rule is described in detail below through an example. Assume that the two i-th ordered data vectors in a group are (18,15,13,11,9,7,8,3) and (20,16,13,9,8,7,6,0), the goal is to obtain the top-7 data, and the set merge sort algorithm is the optimized merge sort algorithm. Then, see... Figure 11 The first valid data element pairs that need to be compared and swapped in the two i-th ordered data vectors are (18,20), (15,16), (13,13), (11,9), (9,8), (7,7), and (8,6). The data elements 3 and 0, which are in the 8th position in the two ordered data vectors, do not contribute substantially to the filtering of the top-7 data, so no comparison and swap operation is required for them. After determining the first valid data element pairs that need to be compared and swapped, the two data elements in each first valid data element pair are mapped to the same position in two different vector registers. Then, a SIMD operation is used to perform a parallel comparison and swap operation on the two data elements in each first valid data element pair. The two first intermediate data vectors are (20,16,13,11,9,7,8) and (18,15,13,9,8,7,6).

[0135] In some embodiments, the step of reverse mapping the data elements in the two first intermediate data vectors back to the storage module according to the third mapping rule to obtain two second intermediate data vectors includes: determining the index value of each data element according to the position of each data element in the two vector registers, writing each data element in the two first intermediate data vectors back to the storage module according to the index value, overwriting the data elements corresponding to the index values ​​of the two i-th ordered data vectors stored in the storage module, so that the two i-th ordered data vectors stored in the storage module are updated to two second intermediate data vectors.

[0136] Specifically, taking the two first intermediate data vectors (20,16,13,11,9,7,8) and (18,15,13,9,8,7,6) as examples, based on the storage location of each data element, the indices of each data element in the first intermediate data vector (20,16,13,11,9,7,8) from left to right are 0, 1, 2, 3, 4, 5, 6, and the indices of each data element in the first intermediate data vector (18,15,13,9,8,7,6) from left to right are 8, 9, 10, 11, 12, 13, 14. Then, the data elements in the first intermediate data vector (20,16,13,11,9,7,8) are arranged according to their indices. Write back to the storage module, overwriting the first 7 data elements of the i-th ordered data vector (18,15,13,11,9,7,8,3) in the storage module. At this time, the i-th ordered data vector (18,15,13,11,9,7,8,3) in the storage module is updated to the second intermediate data vector (20,16,13,11,9,7,8,3). Similarly, after the first intermediate data vector (18,15,13,9,8,7,6) is written back to the storage module, the i-th ordered data vector (20,16,13,9,8,7,6,0) in the storage module is updated to the second intermediate data vector (18,15,13,9,8,7,6,0).

[0137] Then, the data elements in the two second intermediate data vectors are mapped to the vector register group according to the fourth mapping rule, such as... Figure 13 As shown, in some embodiments, mapping the data elements in the two second intermediate data vectors to the vector register group according to the fourth mapping rule includes:

[0138] S51. Based on the set merge sort algorithm, determine the second effective data element pair that needs to be compared and swapped in the two second intermediate data vectors;

[0139] S52. Map the two data elements in each of the second valid data element pairs to the same position in two different vector registers, wherein the data elements in each of the second valid data element pairs are mapped to the two different vector registers.

[0140] Specifically, taking the two second intermediate data vectors (20,16,13,11,9,7,8,3) and (18,15,13,9,8,7,6,0) as examples, see [link to relevant documentation]. Figure 11 Based on the optimized merge sort algorithm, the second valid data element pairs that need to be compared and swapped in the two second intermediate data vectors are determined to be (9, 18), (7, 15), and (8, 13). Then, the two data elements in each data element pair are mapped to the same position in two different vector registers. Next, a SIMD operation is used to compare and swap the data elements at the same position in the vector registers to obtain two third intermediate data vectors (18, 15, 13) and (9, 7, 8).

[0141] Next, the two third intermediate data vectors are reverse-mapped back to the storage module according to the fourth mapping rule to obtain two fourth intermediate vectors. In some embodiments, the step of reverse-mapping the two third intermediate data vectors back to the storage module according to the fourth mapping rule to obtain two fourth intermediate vectors includes: determining the index value of each data element in the two third intermediate data vectors according to the position of each data element in the two vector registers, writing each data element in the two third intermediate data vectors back to the storage module according to the index value, overwriting the data elements of the two second intermediate data vectors stored in the storage module corresponding to the index values, so that the two second intermediate data vectors stored in the storage module are updated to two fourth intermediate data vectors.

[0142] Specifically, continuing with the two third intermediate data vectors (18,15,13) and (9,7,8) mentioned above, the indices of each data element in the third intermediate data vector (18,15,13) from left to right are (4,5,6), and the indices of each data element in the third intermediate data vector (9,7,8) from left to right are (8,9,10). The third intermediate data vector (18,15,13) is written back to the storage module according to the indices of each data element, overwriting the data elements of the second intermediate data vector (20,16,13,11,9,7,8,3) stored in the storage module with the corresponding index values, so that the second intermediate data vector (20,16,13,11,9,7,8,3) stored in the storage module is updated to the fourth data vector (20,16,13,11,9,7,8,3). 18,15,13,3); Similarly, the third intermediate data vector (9,7,8) is written back to the storage module, and the second intermediate data vector (18,15,13,9,8,7,6,0) stored in the storage module is updated to the fourth data vector (9,7,8,9,8,7,6,0).

[0143] This process continues until the comparison-swap operations required for one round of merge sort are completed, resulting in two data vectors: (20,18,16,15,13,13,11,3) and (9,7,8,9,8,7,6,0). These two data vectors are then concatenated to obtain a target data vector of the i-th order: (20,18,16,15,13,13,11,3,9,7,8,9,8,7,6,0). It can be seen that the first 8 elements in this target data vector of the i-th order are ordered, and the 7 largest elements are at the beginning.

[0144] In some embodiments, when the computing module processes at least two sets of the i-th ordered data vectors in parallel each time, the single instruction multiple data execution unit uses a single instruction multiple data operation instruction to execute the comparison-swap operation that can be executed in parallel during the merge sorting process of the two sets of i-th ordered data vectors.

[0145] For example, the process of merging and sorting four pairs of ordered numerical sequences and position index sequences of 8 elements is as follows:

[0146] In the first round of merge sort, a large number of comparison-swap operations need to be performed on the four ordered sequences. These comparison-swap operations within the same parallel block can be executed in parallel. Therefore, according to the granularity of the parallel block, these comparison-swap operations are integrated into a set of SIMD operations, such as... Figure 18As shown, the comparison-swapping operations of the four ordered sequences can be integrated into five SIMD operations. For each SIMD operation, the source operands (the data vector to be compared and the position index vector) are read from the storage module, and the data (data vector and position index vector) after the comparison-swapping operation is completed are written back to the storage module. The five SIMD operations are executed sequentially, resulting in two sets of 16-element sequences. The first eight elements of each sequence are extracted, namely d0~d7 and d16~d23, resulting in two sets of 8-element ordered numerical sequences and position index sequences.

[0147] The second round of merge sort performs merge sort on the two previously obtained ordered sequences of 8 elements, such as... Figure 19 As shown, these comparison-swap operations are integrated according to the parallel block granularity to obtain 4 SIMD operations. The 4 SIMD operations are executed sequentially, and after completion, a set of 16-element data sequence and index sequence are obtained. The first 8 values ​​of the sequence are extracted, and the top-8 numerical results and position indices are output.

[0148] The RISC-V instruction set architecture, as an open-source, scalable, and completely free ISA (Instruction Set Architecture), provides a new path that balances flexibility and performance for the efficient implementation of top-k operators. Its core advantage lies in achieving hardware-level acceleration of the data top-k filtering process by avoiding reliance on dedicated hardware through modular instruction extensions and standardized toolchains. The data processing device provided in this application embodiment can implement a top-k operator implementation scheme based on the RISC-V vector extension architecture. This scheme can integrate various standard RISC-V vector extension instructions based on the RISC-V instruction set architecture to achieve parallel execution of top-k operators. With the popularization of standardized acceleration instructions such as vector extension (RVV) and the continuous maturation of open-source toolchains and ecosystems, this scheme is expected to become a core technology for future intelligent computing (from real-time filtering at the edge to large-scale sparse activation in the cloud).

[0149] Figure 14 This is a schematic diagram of the structure of a data processing device provided in an embodiment of this application. Figure 14 It demonstrates the complete process of a data processing device, from instruction fetching, decoding, and scheduling to achieving efficient parallel computing using SIMD execution units.

[0150] like Figure 14 As shown, in some embodiments, the data processing device 100 further includes:

[0151] The instruction decoding unit 3 is coupled to the storage module 1 and is configured to parse the RISC-V instructions extracted from the storage module 1. The instruction decoding unit 3 can quickly parse these instructions, rapidly identify the type of operation to be performed by the instruction and the source of operands, and prepare for subsequent computation and processing.

[0152] Scheduler 4, coupled to the instruction decoding unit 3 and the computing module 2, is configured to determine the execution order of each RISC-V instruction based on the instruction characteristics of the RISC-V instructions and the resource status of the computing module 2, so that the single instruction multiple data execution unit 21 executes the RISC-V instructions in the order they are executed. Scheduler 4 rationally arranges the instruction execution order according to the resource status (such as register resources, execution unit status, etc.) and instruction characteristics under different application scenarios.

[0153] In some embodiments, the storage module 1 includes a static random access memory (SRAM) coupled to the computing module 2 and configured to store data and RISC-V instructions. Static random access memory (SRAM) has extremely high data access speed and, in RISC-V architecture systems, is used to store program instructions and data to meet the architecture system's requirements for data access speed.

[0154] like Figure 14 As shown, in some embodiments, the data processing apparatus 100 further includes:

[0155] Instruction cache unit (instruction cache) 5 is coupled to the static random access memory and is configured to retrieve and store RISC-V instructions from the static random access memory. The instruction cache is a high-speed cache space. The RISC-V architecture emphasizes the efficiency of memory access. It usually retrieves frequently used instructions from SRAM quickly and stores them in the instruction cache to reduce the time the processor waits for instructions.

[0156] The instruction fetch cache unit 6, coupled to the instruction cache unit 5 and the instruction decoding unit 3, is configured to store RISC-V instructions fetched from the instruction cache unit 5 in an orderly manner, enabling the instruction decoding unit 3 to fetch RISC-V instructions from the instruction fetch cache unit 5. The instruction fetch cache unit 6 further temporarily stores instructions fetched from the instruction cache. During the instruction fetch phase, the RISC-V architecture processor uses the instruction fetch cache unit 6 to store instructions in an orderly manner, preparing for subsequent decoding and execution.

[0157] In addition, the RISC-V architecture uses vector register sets to store data vectors. In tasks requiring a large amount of parallel data processing, the data bit width of a single vector register can be equal to the data bit width of SIMD, using vector register sets to store multiple data elements and working in conjunction with the SIMD execution unit 21 to achieve parallel computation.

[0158] The RISC-V Vector Extensions instruction set supports SIMD operations. The SIMD execution unit 21 can perform the same operation on multiple data elements in a vector register set simultaneously under the control of a single instruction, accelerating data processing. RVV supports Single Instruction Multiple Data (SIMD) mode, allowing comparison-swap operations to be performed on multiple data elements in parallel within a single instruction cycle. For example, traditional scalar instructions process vector elements one by one, while RVV's compare and merge instructions can process multiple element pairs simultaneously, significantly reducing the number of instruction executions and greatly improving data processing speed, making it particularly suitable for large-scale data sorting and filtering scenarios.

[0159] To better understand this application, the following detailed description of the method performed by the data processing apparatus provided in this application is provided through a specific embodiment.

[0160] In scenarios involving small batches of data, where only one or a few sets of vectors need to be selected at a time, such as the inference and decoding phase of a large MOE model (low batch size scenario), the batches of data requiring top-k processing are too small. Therefore, it's necessary to deeply analyze the parallelism within the merge sort algorithm to ensure the utilization rate of SIMD. Figure 15 As shown, assuming the SIMD execution unit has a processing bit width of 128 bits and a data precision of 16 bits, a single SIMD execution unit can process 8 data items in parallel. Taking the selection of the top-8 elements from a batch of 32 elements as an example:

[0161] Step 1: Divide the 32 elements into 4 groups with a granularity of 8;

[0162] Step 2: Use odd-even merge sort to sort the 4 groups of 8-element sequences within each group;

[0163] Since a single SIMD operation can process 8 data points simultaneously, and the data batch size is 1, to ensure the utilization rate of SIMD, it is necessary to analyze the parallelizability of each comparison-swap operation based on the granularity of the comparison-swap operation. For example... Figure 15 As shown, the odd-even merge sort network for an 8-element sequence contains 6 parallel blocks. The comparison-swap operations within the parallel blocks are independent and can be integrated into a single SIMD operation. However, there are dependencies between the 6 parallel blocks, which need to be executed from left to right.

[0164] Merge sorting four ordered numerical sequences requires numerous comparison-swap operations. These operations, which are within the same parallel block, can be executed in parallel. Therefore, based on the parallel block granularity, these comparison-swap operations are integrated into a set of SIMD operations, such as... Figure 16As shown, the comparison-swapping operation of 4 ordered sequences can be mapped to 10 SIMD operations. The 10 SIMD operations are executed sequentially, and after execution, 4 sequences of 8 elements are obtained. Each sequence contains a numerical sequence and a position index sequence of 8 elements.

[0165] See Figure 17 Each SIMD operation first reads the source operands (the value vector and the position index vector to be compared) of the compare-swap operation from SRAM. Then, the RISC-V instruction controls the SIMD unit to complete the compare-swap operation and save the processing result to the free register in the vector register group. Since the number of vector register groups is usually relatively small, it is usually necessary to write the output result (value vector and position index vector) after the compare-swap operation is completed back to SRAM to release the occupancy of the vector register.

[0166] Step 3: Group the four sets of 8-element ordered numerical sequences and position index sequences pairwise, and perform merge sort (execute in a loop):

[0167] In the first round of merge sort, a large number of comparison-swap operations need to be performed on the four ordered sequences. These comparison-swap operations within the same parallel block can be executed in parallel. Therefore, according to the granularity of the parallel block, these comparison-swap operations are integrated into a set of SIMD operations, such as... Figure 18 As shown, the comparison-swapping operations of the four ordered sequences can be integrated into five SIMD operations. In each SIMD operation, the source operands (the value vector and position index vector to be compared) are read from SRAM, and the data (value vector and position index vector) after the comparison-swapping operation is completed are written back to SRAM. The five SIMD operations are executed sequentially, resulting in two sequences of 16 elements each. The first eight elements of each sequence are extracted, namely d0~d7 and d... 16 ~d 23 Then, we obtain two sets of ordered numerical sequences and position index sequences of 8 elements each.

[0168] The second round of merge sort performs merge sort on the two previously obtained ordered sequences of 8 elements, such as... Figure 19 As shown, these comparison-swap operations are integrated according to the parallel block granularity to obtain 4 SIMD operations. The 4 SIMD operations are executed sequentially, and after completion, a set of 16-element numerical sequence and index sequence is obtained. The first 8 values ​​of the sequence are extracted, and the top-8 numerical results and position indices are output.

[0169] Step 4: Extract the first 8 values ​​from the obtained 16-element numerical sequence and index sequence, and output the top-8 numerical results and position index results of a batch of data.

[0170] Based on the same inventive concept, embodiments of this application also provide a data processing method. Figure 20 This is a flowchart illustrating a data processing method provided in an embodiment of this application, as shown below. Figure 20 As shown in the embodiment of this application, a data processing method includes:

[0171] S10. Access the original data vector stored in the storage module, wherein the original data vector contains m data elements, where m is a positive integer;

[0172] S20. The original data vector is split based on the target k value to obtain multiple first data vectors, where k is a positive integer;

[0173] S30. Map the data elements in each of the first data vectors to the vector register group respectively, and use the single instruction multiple data execution unit to perform parallel comparison-exchange operations on the data elements in the vector register group, so as to realize the parity merge sort of the data elements in each of the first data vectors respectively, and obtain multiple first ordered data vectors.

[0174] S40. Merge and sort the data elements in the plurality of first ordered data vectors to obtain the top-k data elements among the m data elements.

[0175] The data processing method provided in this application splits the original data vector into multiple first data vectors. Then, the data elements in each first data vector are mapped to a vector register group. A single instruction multiple data execution unit (SMI) performs parallel comparison-swapping operations on the data elements in the vector register group, achieving parity merge sorting of the data elements in each first data vector to obtain multiple first ordered data vectors. Next, the data elements in the multiple first ordered data vectors are merge sorted to obtain the top-k data elements from the m data elements. Thus, based on the parity merge sort algorithm and the merge sort algorithm, the top-k data elements from the m data elements can be obtained without a dedicated hardware sorting network, avoiding dependence on dedicated hardware and improving programming flexibility and versatility. This is beneficial for the expansion and migration of large models across different hardware platforms, and the method can effectively improve the execution efficiency of hardware processing of top-k tasks.

[0176] The embodiments of the method provided in this application are specifically the data processing flow of the data processing device in the above-described device embodiments. The specific implementation method will not be repeated here, but can be referred to the detailed description of the above-described device embodiments.

[0177] This application also provides a chip that includes the data processing device described in any of the above embodiments. For example, the chip may be a many-core artificial intelligence (AI) chip based on the RISC-V vector extended instruction architecture.

[0178] The chip provided in this application embodiment includes the data processing device, and therefore can achieve the same technical effect as the data processing device, which will not be described in detail here.

[0179] This application also provides an electronic device, which includes the chip described in any of the above embodiments.

[0180] The electronic device provided in this application embodiment includes the data processing device, and therefore can achieve the same technical effect as the data processing device, which will not be described in detail here.

[0181] Figure 21 This is a block diagram of an electronic device provided in an embodiment of this application. For example, the electronic device 200 may be an AI server, an artificial intelligence server cluster, a training and promotion integrated machine, etc.

[0182] Reference Figure 21 The electronic device 200 may include one or more of the following components: an AI-accelerated computing module, a CPU module, a power supply module, a hard drive module, and a fan module. Each module works in conjunction with the bus system through a standardized hardware interface, with the specific architecture as follows:

[0183] The AI-accelerated computing module comprises multiple AI accelerator cards deployed in parallel. Each AI accelerator card integrates at least one AI accelerator chip (such as an RPU chip, GPU chip, or CGRA chip). Data communication between the AI ​​accelerator cards is achieved through a high-speed card-to-card (C2C) interconnect structure, supporting low-latency, high-bandwidth horizontal scaling. The AI ​​accelerator chip is dedicated to performing AI computing tasks such as high-density matrix operations, neural network model training, and / or inference, providing the main computing power support.

[0184] The CPU module includes at least one CPU board, which houses a central processing unit (CPU) chip and associated CPU memory (such as DDR4 / DDR5, RAM). The CPU chip serves as the system control center, responsible for task scheduling, resource allocation, I / O management, and coordinating the parallel computing of the AI ​​acceleration computing module, while also handling non-accelerated general-purpose computing tasks.

[0185] The power module is equipped with redundant power supply units to provide stable power distribution and management for the AI ​​acceleration computing module, CPU module and other modules.

[0186] The hard drive module integrates a high-speed solid-state drive (SSD) and / or a large-capacity hard disk drive (HDD), connected to the system bus via a backplane. The hard drive stores the operating system, AI training datasets, model parameters, and computation results, providing high-throughput data read / write channels and supporting data preprocessing and persistence.

[0187] The fan module uses a multi-zone independent speed-controlled fan array, which is configured in key heat source areas (such as AI accelerator cards and CPU heat dissipation areas) to achieve system heat dissipation through forced air cooling and ensure the stable operation of high-efficiency computing components.

[0188] The CPU module is connected to the AI ​​acceleration computing module via the PCIe bus to enable task distribution, result collection, and memory coordination.

[0189] The CPU module manages the data access of the hard drive module through SATA / SAS / NVMe interfaces.

[0190] The power module provides tiered power to all functional modules through the power distribution backplane.

[0191] The fan module adjusts the fan speed based on temperature monitoring signals from the CPU board and AI accelerator card.

[0192] This embodiment of the application provides a computer program product, which includes a computer program stored on a non-transitory computer-readable storage medium. The computer program includes program instructions, and when the program instructions are executed by a computer, the computer is able to execute the methods provided in the above-described method embodiments.

[0193] This embodiment provides a computer-readable storage medium storing a computer program that causes the computer to execute the methods provided in the above-described method embodiments.

[0194] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0195] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0196] In the description of this specification, the references to terms such as "an embodiment," "a specific embodiment," "some embodiments," "for example," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0197] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of this application. It should be understood that the above descriptions are merely specific embodiments of this application and are not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A data processing apparatus, characterized in that, include: The storage module is configured to store data; The computing module includes a single instruction multiple data (SMI) unit and a vector register set, wherein the SMI is coupled to the vector register set, and the vector register set is coupled to the memory module. The computing module is configured as follows: Access the original data vector stored in the storage module, wherein the original data vector contains m data elements, where m is a positive integer; The original data vector is split based on the target k value to obtain multiple first data vectors, where k is a positive integer; The data elements in each of the first data vectors are mapped to the vector register group, and the single instruction multiple data execution unit is used to perform parallel comparison-exchange operations on the data elements in the vector register group, thereby performing parity merge sort on the data elements in each of the first data vectors to obtain multiple first ordered data vectors. Merge sort the data elements in the plurality of first ordered data vectors to obtain the top-k data elements among the m data elements; Specifically, performing parity merge sort on each data element in the first data vector includes: The data elements in the first data vector are mapped to the vector register group according to the first mapping rule. The single instruction multiple data execution unit performs parallel comparison-swapping operations on the data elements at the same position in the vector register group to obtain two first sub-data vectors. Then, the data elements in the two first sub-data vectors are reverse mapped back to the address space of the storage module storing the first data vector according to the first mapping rule, so that the first data vector stored in the storage module is updated to the second data vector. The data elements in the second data vector are mapped to the vector register group according to the second mapping rule. The single instruction multiple data execution unit is used to perform parallel comparison-swapping operations on the data elements at the same position in the vector register group to obtain two second sub-data vectors. Then, the data elements in the two second sub-data vectors are reverse mapped back to the address space of the storage module that stores the second data vector according to the second mapping rule, so that the second data vector stored in the storage module is updated to the third data vector. This process continues until the comparison-swap operations required for one round of parity merge sort are completed, thus completing the parity merge sort of the first data vector and obtaining a first ordered data vector.

2. The data processing apparatus according to claim 1, characterized in that, The calculation module splits the original data vector based on the target k value to obtain multiple first data vectors, including: Based on the target value k, calculate an integer that is a power of 2 greater than or equal to the value k; The original data vector is split using integers greater than or equal to the power of 2 of the k value as the grouping granularity to obtain multiple first data vectors.

3. The data processing apparatus according to claim 1, characterized in that, The calculation module maps a data element from the first data vector to the vector register group each time, and uses the single instruction multiple data execution unit to perform parallel comparison-swapping operations on the data elements in the vector register group, thereby performing parity merge sort on the data elements in the first data vector to obtain a first ordered data vector. or, The calculation module maps data elements from at least two of the first data vectors to the vector register group each time, and uses the single instruction multiple data execution unit to perform parallel comparison-swapping operations on the data elements in the vector register group, thereby realizing parallel parity merge sorting of the data elements in the at least two first data vectors and obtaining the first ordered data vectors corresponding to each of the at least two first data vectors.

4. The data processing apparatus according to claim 1, characterized in that, The step of mapping the data elements in the first data vector to the vector register group according to the first mapping rule includes: determining the data element pairs in the first data vector that need to be compared and swapped based on the odd-even merge sort algorithm; mapping the two data elements in each data element pair to the same position in two different vector registers, wherein the data elements in each data element pair are mapped to the two different vector registers; The step of mapping the data elements in the second data vector to the vector register group according to the second mapping rule includes: determining the pairs of data elements in the second data vector that need to be compared and swapped based on the odd-even merge sort algorithm; mapping the two data elements in each pair of data elements to the same position in two different vector registers, wherein the data elements in each pair of data elements are mapped to the two different vector registers.

5. The data processing apparatus according to claim 4, characterized in that, The step of reverse mapping the data elements in the two first sub-data vectors back to the address space of the storage module storing the first data vector according to the first mapping rule, so that the first data vector stored in the storage module is updated to the second data vector, includes: determining the index value of each data element according to the position of each data element in the two first sub-data vectors in the two vector registers, writing each data element in the two first sub-data vectors back to the storage module according to the index value, overwriting the data element of the first data vector stored in the storage module corresponding to the index value, so that the first data vector stored in the storage module is updated to the second data vector; The step of reverse mapping the data elements in the two second sub-data vectors back to the address space of the storage module storing the second data vector according to the second mapping rule, so that the second data vector stored in the storage module is updated to the third data vector, includes: determining the index value of each data element according to the position of each data element in the two vector registers, writing each data element in the two second sub-data vectors back to the storage module according to the index value, overwriting the data element of the second data vector stored in the storage module corresponding to the index value, so that the second data vector stored in the storage module is updated to the third data vector.

6. The data processing apparatus according to claim 1, characterized in that, When the computing module processes at least two of the first data vectors in parallel, the single instruction multiple data execution unit uses a single instruction multiple data operation instruction to execute the comparison-swap operation that can be executed in parallel during the parity merge sorting process of the at least two first data vectors.

7. The data processing apparatus according to claim 1, characterized in that, The calculation module performs merge sorting on the data elements in the plurality of first ordered data vectors to obtain the top-k data elements among the m data elements, including: The plurality of first ordered data vectors are grouped into pairs, and the data elements in the two first ordered data vectors in each group are merged and sorted to obtain a plurality of first target data vectors. Extract the top-b data elements of each of the first target data vectors to generate multiple second ordered data vectors, where b is an integer greater than or equal to the value of k, which is a power of 2. The plurality of second ordered data vectors are grouped in pairs, and the data elements of the two second ordered data vectors in each group are merged and sorted to obtain a plurality of second target data vectors. Extract the top-b data elements of each of the second target data vectors to generate multiple third ordered data vectors; This process continues until an nth ordered data vector is generated; Extract the top-k data elements from the nth ordered data vector, where the top-k data elements in the nth ordered data vector are the top-k data elements among the m data elements.

8. The data processing apparatus according to claim 7, characterized in that, The calculation module groups the plurality of first ordered data vectors into pairs, and merges and sorts the data elements in the two first ordered data vectors within each group to obtain a plurality of first target data vectors. This includes: grouping the plurality of first ordered data vectors into pairs, processing one group of first ordered data vectors at a time, sequentially completing the merge and sorting of the two first ordered data vectors within each group, and finally obtaining a plurality of first target data vectors; or, grouping the plurality of first ordered data vectors into pairs, processing at least two groups of first ordered data vectors in parallel each time, until the merge and sorting of the two first ordered data vectors within each group is completed, and finally obtaining a plurality of first target data vectors. The calculation module groups the plurality of second ordered data vectors into pairs, and merges and sorts the data elements of the two second ordered data vectors in each group to obtain a plurality of second target data vectors. This includes: grouping the plurality of second ordered data vectors into pairs, processing one group of second ordered data vectors at a time, and sequentially completing the merge and sorting of the two second ordered data vectors in each group to finally obtain a plurality of second target data vectors; or, grouping the plurality of second ordered data vectors into pairs, processing at least two groups of second ordered data vectors in parallel each time, until the merge and sorting of the two second ordered data vectors in each group is completed to finally obtain a plurality of second target data vectors.

9. The data processing apparatus according to claim 8, characterized in that, The calculation module performs a merge sort on the data elements of the two first ordered data vectors within each group, including: The data elements in the two first ordered data vectors in the group are mapped to the vector register group according to the third mapping rule. The single instruction multiple data execution unit is used to perform parallel comparison-exchange operations on the data elements at the same position in the vector register group to obtain two first intermediate data vectors. Then, the data elements in the two first intermediate data vectors are reverse mapped back to the storage module according to the third mapping rule to obtain two second intermediate data vectors. The data elements in the two second intermediate data vectors are mapped to the vector register group according to the fourth mapping rule. The single instruction multiple data execution unit is used to perform parallel comparison-exchange operations on the data elements at the same position in the vector register group to obtain two third intermediate data vectors. Then, the data elements in the two third intermediate data vectors are reverse mapped back to the storage module according to the fourth mapping rule to obtain two fourth intermediate vectors. This process continues until the comparison-swap operations required for one round of merge sort are completed, that is, the merge sort of the two first ordered data vectors is completed, resulting in a first target data vector.

10. The data processing apparatus according to claim 9, characterized in that, The calculation module performs a merge sort on the data elements of the two second ordered data vectors within each group, including: The data elements in the two second ordered data vectors in the group are mapped to the vector register group according to the third mapping rule. The single instruction multiple data execution unit is used to perform parallel comparison-exchange operations on the data elements at the same position in the vector register group to obtain two first intermediate data vectors. Then, the data elements in the two first intermediate data vectors are reverse mapped back to the storage module according to the third mapping rule to obtain two second intermediate data vectors. The data elements in the two second intermediate data vectors are mapped to the vector register group according to the fourth mapping rule. The single instruction multiple data execution unit is used to perform parallel comparison-exchange operations on the data elements at the same position in the vector register group to obtain two third intermediate data vectors. Then, the data elements in the two third intermediate data vectors are reverse mapped back to the storage module according to the fourth mapping rule to obtain two fourth intermediate vectors. This process continues until the comparison-swap operations required for one round of merge sort are completed, that is, the merge sort of the two second ordered data vectors is completed, resulting in a second target data vector.

11. The data processing apparatus according to claim 10, characterized in that, The step of mapping the data elements in the two first / second ordered data vectors within the group to the vector register group according to the third mapping rule includes: Based on the set merge sort algorithm, it is determined that the first valid data element pair needs to be compared and swapped among the two ordered data vectors in the group; Each pair of first valid data elements maps two data elements to the same location in two different vector registers, wherein each data element in each pair of first valid data elements is mapped to the two different vector registers; The step of mapping the data elements in the two second intermediate data vectors to the vector register group according to the fourth mapping rule includes: Based on the set merge sort algorithm, determine the second effective data element pairs that need to be compared and swapped in the two second intermediate data vectors; The two data elements in each second valid data element pair are respectively mapped to the same position in two different vector registers, wherein the data elements in each second valid data element pair are mapped to the two different vector registers.

12. The data processing apparatus according to claim 11, characterized in that, The step of reversing the mapping of data elements from the two first intermediate data vectors back into the storage module according to the third mapping rule to obtain two second intermediate data vectors includes: Based on the position of each data element in the two first intermediate data vectors in the two vector registers, the index value of each data element is determined, and each data element in the two first intermediate data vectors is written back to the storage module according to the index value, overwriting the data elements corresponding to the index values ​​of the two ordered data vectors stored in the storage module, so that the two ordered data vectors stored in the storage module are updated to two second intermediate data vectors. The step of reversing the mapping of the two third intermediate data vectors back into the storage module according to the fourth mapping rule to obtain two fourth intermediate vectors includes: Based on the position of each data element in the two third intermediate data vectors in the two vector registers, the index value of each data element is determined. Each data element in the two third intermediate data vectors is written back to the storage module according to the index value, overwriting the data elements with corresponding index values ​​of the two second intermediate data vectors stored in the storage module, so that the two second intermediate data vectors stored in the storage module are updated to two fourth intermediate data vectors.

13. The data processing apparatus according to claim 10, characterized in that, When the computing module processes at least two sets of the first / second ordered data vectors in parallel each time, the single instruction multiple data execution unit uses a single instruction multiple data operation instruction to execute the comparison-swap operation that can be executed in parallel during the merge sorting process of the at least two sets of ordered data vectors.

14. The data processing apparatus according to claim 11, characterized in that, The comparison-swapping operation performed on the data elements in the first valid data element pair is a comparison-swapping operation that contributes to the identification of the top-k data elements; The comparison-swapping operation performed on the data elements in the second valid data element pair is a comparison-swapping operation that contributes to the identification of the top-k data elements.

15. The data processing apparatus according to claim 1, characterized in that, Also includes: An instruction decoding unit, coupled to the storage module, is configured to parse RISC-V instructions extracted from the storage module; The scheduler, coupled to the instruction decoding unit and the computing module, is configured to determine the execution order of each RISC-V instruction based on the instruction characteristics of the RISC-V instructions and the resource status of the computing module, so that the single instruction multiple data execution unit executes the RISC-V instructions in the execution order of each RISC-V instruction.

16. The data processing apparatus according to claim 15, characterized in that, The storage module includes: A static random access memory, coupled to the computing module, is configured to store data and RISC-V instructions.

17. The data processing apparatus according to claim 16, characterized in that, Also includes: An instruction cache unit, coupled to the static random access memory, is configured to retrieve and store RISC-V instructions from the static random access memory. The instruction fetch cache unit, coupled to the instruction cache unit and the instruction decode unit, is configured to store RISC-V instructions fetched from the instruction cache unit in an ordered manner, so that the instruction decode unit fetches RISC-V instructions from the instruction fetch cache unit.

18. A data processing method, characterized in that, include: Access the original data vector stored in the storage module, wherein the original data vector contains m data elements, where m is a positive integer; The original data vector is split based on the target k value to obtain multiple first data vectors, where k is a positive integer; The data elements in each of the first data vectors are mapped to vector register groups, and the data elements in the vector register groups are compared and swapped in parallel using a single instruction multiple data execution unit, so as to perform parity merge sorting on the data elements in each of the first data vectors and obtain multiple first ordered data vectors. Merge sort the data elements in the plurality of first ordered data vectors to obtain the top-k data elements among the m data elements; Specifically, performing parity merge sort on each data element in the first data vector includes: The data elements in the first data vector are mapped to the vector register group according to the first mapping rule. The single instruction multiple data execution unit performs parallel comparison-swapping operations on the data elements at the same position in the vector register group to obtain two first sub-data vectors. Then, the data elements in the two first sub-data vectors are reverse mapped back to the address space of the storage module storing the first data vector according to the first mapping rule, so that the first data vector stored in the storage module is updated to the second data vector. The data elements in the second data vector are mapped to the vector register group according to the second mapping rule. The single instruction multiple data execution unit is used to perform parallel comparison-swapping operations on the data elements at the same position in the vector register group to obtain two second sub-data vectors. Then, the data elements in the two second sub-data vectors are reverse mapped back to the address space of the storage module that stores the second data vector according to the second mapping rule, so that the second data vector stored in the storage module is updated to the third data vector. This process continues until the comparison-swap operations required for one round of parity merge sort are completed, thus completing the parity merge sort of the first data vector and obtaining a first ordered data vector.

19. A chip, characterized in that, Includes the data processing apparatus according to any one of claims 1 to 17.

20. An electronic device, characterized in that, Includes the chip described in claim 19 above.

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