Out-of-order instruction transmitting module passive inspection method and device

Abstract

The invention relates to a passive checking method and device for an out-of-order instruction transmitting module. The method is applied to an instruction transmitting model and comprises the steps that an instruction distributed to a to-be-tested out-of-order instruction transmitting module by an instruction distribution module is monitored, a transmitting queue of the instruction transmitting model is filled with the instruction, and the instruction carries unique identification information; monitoring a first target instruction transmitted to an instruction execution module by an out-of-order instruction transmitting module; obtaining a second target instruction which is the same as the unique identification information of the first target instruction from an emission queue of an instruction emission model; transmitting the second target instruction in an instruction transmitting model; and checking the out-of-order instruction transmitting module according to the transmitting result of the second target instruction. Through the method provided by the embodiment of the invention, the workload and difficulty of model development are reduced, and when the instruction transmitted by the out-of-order instruction transmitting module has an error, the error instruction and the error occurrence time can be reported immediately, so that the convenience of error debugging is improved.

Description

Technical Field

[0001] The embodiments in this specification relate to the field of computer technology, and in particular to a passive inspection method and apparatus for out-of-order instruction issuance modules. Background Technology

[0002] As the computational performance demands of modern microprocessors continue to rise, out-of-order execution technology has become the core of high-performance CPU design. By allowing instructions to be issued to the execution unit as soon as operands are ready, rather than being executed strictly in program order, it effectively unlocks instruction-level parallelism (ILP), masks pauses caused by data dependencies between instructions and long-latency operations (such as cache access), and significantly improves pipeline throughput.

[0003] However, the extremely high hardware complexity of out-of-order deployment pipelines also brings unprecedented verification challenges, making it one of the most critical and difficult stages in the entire chip design process. These challenges mainly stem from the following aspects: State Space Explosion: The core components of an out-of-order pipeline, such as the Reorder Buffer (ROB), Issue Queue, and Load-Store Queue (LSQ), together constitute a massive and highly interconnected state machine. The ordering, scheduling, and contention of instructions within these structures generate an astronomical number of possible states. Traditional directed tests or simple random stimuli cannot effectively cover these complex interactions and extreme scenarios.

[0004] Non-deterministic behavior: Out-of-order issuance is inherently dynamic. The order in which instructions are issued and executed is influenced by various factors such as timing, resource contention, external interrupts, and cache hit status, exhibiting non-determinism. This makes defect reproduction and debugging extremely difficult, as the same test input may produce different results due to minute differences in initial state or timing.

[0005] The reference model in the existing verification environment is usually a sequential execution model, which makes it difficult to accurately simulate and predict all intermediate and non-architectural states during out-of-order execution. As a result, the result comparison can only rely on the final architectural state, and it is impossible to detect transient errors inside the pipeline in real time.

[0006] Chinese patent application CN117667216A discloses an instruction verification method. First, a target instruction stream is acquired. Then, one of the reference model and the device under test is controlled to execute the target instruction stream, obtaining the first execution result of each instruction in the target instruction stream, and storing the first execution result in a preset instruction result queue. Next, another target instruction stream in the reference model and the device under test is controlled to execute, obtaining the second execution result of each instruction. Finally, based on the completion time of each instruction's execution in the device under test, the second execution result is compared with the corresponding first execution result in the preset instruction result queue. However, this method is very difficult to reproduce and debug, making it difficult to accurately locate the instruction that actually erroneous and the time of error. Furthermore, the result comparison can only rely on the final architecture state and cannot detect instantaneous errors within the design under test in real time.

[0007] In existing technologies, the out-of-order instruction issuance module under test (i.e., the out-of-order instruction issuance module under test) is modeled and the same out-of-order instruction issuance function as the pre-out-of-order instruction issuance module is performed. Although it is possible to check each signal every clock cycle, the model development is difficult and time-consuming, the model has poor robustness, and cannot adapt to the changes of the out-of-order instruction issuance module under test. In addition, the model is at risk of having the same errors as the out-of-order instruction issuance module under test, which makes it impossible to accurately check for errors.

[0008] Therefore, how to accurately check for transient errors inside the out-of-order instruction issuance module under test is a technical problem that urgently needs to be solved. Summary of the Invention

[0009] To address the problems existing in the prior art, this specification provides a passive inspection method and apparatus for out-of-order instruction issuance modules. The method involves designing an instruction issuance model, monitoring the instructions issued by the out-of-order instruction issuance module under test, issuing the same instructions within the instruction issuance model, and inspecting the out-of-order instruction issuance module based on the same instructions issued within the instruction issuance model.

[0010] The specific technical solutions of the embodiments in this specification are as follows: On the one hand, this specification provides a passive checking method for out-of-order instruction issuance modules, applied to an instruction issuance model, the method comprising: The monitoring instruction distribution module distributes instructions to the out-of-order instruction issuing module under test, and fills the instructions into the issuing queue of the instruction issuing model. The instructions carry unique identification information. Monitor the first target instruction issued by the out-of-order instruction issuing module to the instruction execution module; Obtain a second target instruction from the launch queue that has the same unique identifier as the first target instruction; The second target command is transmitted in the command transmission model; The out-of-order command transmission module is checked based on the transmission result of the second target command.

[0011] Furthermore, in the command issuance model, issuing the second target command further includes: Obtain the launch conditions of the second target command in the command launch model; Determine whether the second target command can be launched based on the launch conditions.

[0012] Furthermore, checking the out-of-order command transmission module based on the transmission result of the second target command further includes: If the second target instruction cannot be transmitted based on the transmission conditions, then the first target instruction transmitted by the out-of-order instruction transmission module is erroneous.

[0013] Furthermore, checking the out-of-order command transmission module based on the transmission result of the second target command also includes: If it is determined that the second target command can be launched based on the launch conditions, then the first launch element of the second target command is calculated; Extract the second launch element of the first target command; If the first transmission element is different from the second transmission element, then the first target instruction transmitted by the out-of-order instruction transmission module is erroneous.

[0014] Furthermore, obtaining the launch conditions of the second target command in the command launch model further includes: Obtain the valid identifier of the first register corresponding to the second target instruction in the instruction issuance model; Determining whether the second target command can be launched based on the launch conditions further includes: Determine whether the validity flag of the first register is valid; If so, then the second target command can be launched; If not, the second target command cannot be issued.

[0015] Furthermore, if the first target instruction emitted by the out-of-order instruction emission module is error-free, the method further includes: After detecting the write-back valid signal after the instruction execution module executes the first target instruction, the valid flag of the second register corresponding to the first target instruction in the instruction issuance model is set to valid.

[0016] Furthermore, if the first target instruction issued by the out-of-order instruction issuing module contains an error, the method further includes: The transmission clock cycle and unique identifier information of the first target instruction are provided to the user so that the user can debug the out-of-order instruction transmission module according to the transmission clock cycle and unique identifier information of the first target instruction.

[0017] Furthermore, the method also includes: Extract the instruction execution delay of the second target instruction; The write-back clock cycle of the first target instruction is calculated based on the instruction execution delay of the second target instruction and the transmit clock cycle of the first target instruction. The system determines whether there is an error in the first target instruction issued by the out-of-order instruction issuing module based on the write-back clock cycle of the first target instruction.

[0018] Furthermore, determining whether the first target instruction issued by the out-of-order instruction issuing module has an error based on the write-back clock cycle of the first target instruction further includes: Determine whether there is a conflict between the write-back clock cycle of the first target instruction and the write-back clock cycles of other target instructions preceding the first target instruction; If a conflict exists, the first target instruction issued by the out-of-order instruction issuing module is incorrect.

[0019] On the other hand, embodiments of this specification also provide a passive inspection device for an out-of-order command issuance module, comprising: The instruction filling unit is used to monitor the instructions distributed by the instruction distribution module to the out-of-order instruction issuing module under test, and fill the instructions into the issuing queue of the instruction issuing model. The instructions carry unique identification information. The instruction issuing unit is configured to monitor the first target instruction issued by the out-of-order instruction issuing module to the instruction execution module; obtain a second target instruction with the same unique identifier information as the first target instruction from the issuing queue; and issue the second target instruction in the instruction issuing model. The processing unit is used to check the out-of-order instruction transmission module based on the transmission result of the second target instruction.

[0020] Using the embodiments of this specification, an instruction issuance model is designed. This model does not perform the out-of-order instruction issuance logic of the out-of-order instruction issuance module, thereby reducing the workload and difficulty of model development. The instruction issuance model in this embodiment can monitor instructions distributed by the instruction distribution module to the out-of-order instruction issuance module and fill the issuance queue of the instruction issuance model. The out-of-order instruction issuance module issues instructions distributed by the instruction distribution module out of order to the instruction execution module. To check for errors in the instructions issued by the out-of-order instruction issuance module, this embodiment directly listens to the instructions issued by the out-of-order instruction issuance module to the instruction execution module. After detecting the first target instruction issued by the out-of-order instruction issuance module, a second target instruction identical to the first target instruction is retrieved from the issuance queue of the instruction issuance model. The second target instruction is then issued within the instruction issuance model. Finally, the issuance result of the second target instruction is used to check for errors in the first target instruction issued by the out-of-order instruction issuance module. This specification's embodiments check each instruction issued by the out-of-order instruction dispatch module in real time, rather than checking the final execution result after all instructions in the instruction stream have been executed. Therefore, the method in this specification's embodiments can immediately report the erroneous instruction and the time of error when an instruction issued by the out-of-order instruction dispatch module is erroneous, thereby improving the convenience of error debugging. Furthermore, because the instruction dispatch model in this specification's embodiments does not perform the out-of-order instruction dispatch logic within the out-of-order instruction dispatch module, even if the out-of-order instruction dispatch module changes, the instruction dispatch model in this specification's embodiments can still check the out-of-order instruction dispatch module, improving the model's robustness. In addition, it avoids the instruction dispatch model and the out-of-order instruction dispatch module from encountering the same errors, improving the accuracy of error checking. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this specification or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the embodiments of this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 The diagram shown is a flowchart illustrating a passive checking method for an out-of-order instruction issuing module in an embodiment of this specification. Figure 2 The diagram shown is a flowchart illustrating the process of transmitting the second target command in the command transmission model described in this embodiment of the specification. Figure 3 The diagram shown is a flowchart illustrating the process of checking the transmission elements of the first target command in an embodiment of this specification. Figure 4 The diagram shown is a flowchart illustrating the process of checking for write-back conflicts of instructions in an embodiment of this specification. Figure 5 The diagram shown is a structural schematic of a passive inspection device for an out-of-order command issuance module in an embodiment of this specification. Figure 6 The diagram shown is a structural schematic of the computer device in an embodiment of this specification.

[0023] [Explanation of Figure Markers]: 501, Instruction Filling Unit; 502. Command Transmission Unit; 503. Processing Unit; 602. Computer equipment; 604. Processing equipment; 606. Storage resources; 608. Drive mechanism; 610. Input / output module; 612. Input devices; 614. Output devices; 616. Presentation equipment; 618. Graphical User Interface; 620. Network interface; 622. Communication link; 624. Communication bus. Detailed Implementation

[0024] The technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the embodiments of this specification, and not all embodiments. Based on the embodiments of this specification, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the embodiments of this specification.

[0025] It should be noted that the terms "first," "second," etc., in the description, claims, and accompanying drawings of the embodiments herein are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the embodiments described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, apparatus, product, or device that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0026] It should be noted that the acquisition, storage, use, and processing of data in the technical solutions of the embodiments of this specification all comply with the relevant provisions of national laws and regulations.

[0027] It should be noted that in the embodiments of this specification, certain software, components, models and other existing solutions in the industry may be mentioned. These should be regarded as exemplary and are only intended to illustrate the feasibility of implementing the technical solution of this application. However, they do not mean that the applicant has used or necessarily used the solution.

[0028] To address the problems existing in the prior art, this specification provides a passive inspection method for out-of-order instruction issuance modules. The method involves designing an instruction issuance model, monitoring the instructions issued by the out-of-order instruction issuance module under test, issuing the same instructions within the instruction issuance model, and inspecting the out-of-order instruction issuance module based on the same instructions issued within the instruction issuance model. Figure 1 The diagram shown is a flowchart illustrating a passive error checking method for an out-of-order instruction issuance module according to an embodiment of this specification. The diagram depicts the process of error checking for instructions issued by the out-of-order instruction issuance module. The order of steps listed in the embodiment is merely one possible execution order among many and does not represent the only possible execution order. In actual system or device products, the methods shown in the embodiment or the accompanying drawings can be executed sequentially or in parallel. Specifically, as shown... Figure 1 As shown, the method is executed by an instruction issuance model, and the method may include: Step 101: Monitor the instructions distributed by the instruction distribution module to the out-of-order instruction issuing module under test, and fill the instructions into the issuing queue of the instruction issuing model. The instructions carry unique identification information. Step 102: Monitor the first target instruction sent by the out-of-order instruction issuing module to the instruction execution module; Step 103: Obtain a second target instruction from the launch queue that has the same unique identifier information as the first target instruction; Step 104: Receive the second target command in the command delivery model; Step 105: Check the out-of-order command transmission module based on the transmission result of the second target command.

[0029] Using the embodiments of this specification, an instruction issuance model is designed. This model does not perform the out-of-order instruction issuance logic of the out-of-order instruction issuance module, thereby reducing the workload and difficulty of model development. The instruction issuance model in this embodiment can monitor instructions distributed by the instruction distribution module to the out-of-order instruction issuance module and fill the issuance queue of the instruction issuance model. The out-of-order instruction issuance module issues instructions distributed by the instruction distribution module out of order to the instruction execution module. To check for errors in the instructions issued by the out-of-order instruction issuance module, this embodiment directly listens to the instructions issued by the out-of-order instruction issuance module to the instruction execution module. After detecting the first target instruction issued by the out-of-order instruction issuance module, a second target instruction identical to the first target instruction is retrieved from the issuance queue of the instruction issuance model. The second target instruction is then issued within the instruction issuance model. Finally, the issuance result of the second target instruction is used to check for errors in the first target instruction issued by the out-of-order instruction issuance module. This specification's embodiments check each instruction issued by the out-of-order instruction dispatch module in real time, rather than checking the final execution result after all instructions in the instruction stream have been executed. Therefore, the method in this specification's embodiments can immediately report the erroneous instruction and the time of error when an instruction issued by the out-of-order instruction dispatch module is erroneous, thereby improving the convenience of error debugging. Furthermore, because the instruction dispatch model in this specification's embodiments does not perform the out-of-order instruction dispatch logic within the out-of-order instruction dispatch module, even if the out-of-order instruction dispatch module changes, the instruction dispatch model in this specification's embodiments can still check the out-of-order instruction dispatch module, improving the model's robustness. In addition, it avoids the instruction dispatch model and the out-of-order instruction dispatch module from encountering the same errors, improving the accuracy of error checking.

[0030] In the embodiments of this specification, the instruction distribution module distributes instructions to the out-of-order instruction issuing module under test. The out-of-order instruction issuing module issues the instructions out of order to the instruction execution module. The instruction execution module obtains the execution result of the instructions and writes the execution result back. The method in the embodiments of this specification checks the out-of-order instruction issuing module to see if there are any errors in the instructions issued by the out-of-order instruction issuing module, but does not check the functionality of the instruction execution module.

[0031] The embodiments in this specification design an instruction issuance model. The instruction issuance model can realize other functions in the out-of-order instruction issuance module besides instruction out-of-order processing and calculation of the issuance clock period. For example, the instruction issuance model can perform functions such as instruction issuance condition judgment and issuance element judgment.

[0032] In the embodiments of this specification, the instruction issuance model monitors the instructions issued by the instruction distribution module to the out-of-order instruction issuance module under test. If the instructions are valid, they are filled into the issuance queue of the instruction issuance model, and each instruction carries unique identification information for subsequent retrieval of instructions from the issuance queue.

[0033] The instruction issuance model has the capability to obtain the values ​​of each register in the register file. In addition, each register file can be simulated in the instruction issuance model. This specification does not limit the implementation of the embodiments.

[0034] The out-of-order instruction issuance module checks the issuance conditions, generates issuance elements, and performs out-of-order issuance processing on the instructions distributed by the instruction distribution module. Then, it issues the instructions to the instruction execution module. The instruction issuance model in this embodiment monitors the instructions issued by the out-of-order instruction issuance module and uses them as the first target instruction. It then determines a second target instruction identical to the first target instruction in the instruction issuance model's issuance queue and issues the second target instruction. If the second target instruction is not found, the first target instruction is considered to have an error.

[0035] Then, the out-of-order instruction issuing module is checked based on the result of the second target instruction issuance. For example, if the instruction issuing model successfully issues the second target instruction, it means that the first target instruction issued by the out-of-order instruction issuing module is without error. If the instruction issuing model fails to issue the second target instruction, it means that the first target instruction issued by the out-of-order instruction issuing module is without error.

[0036] In some other embodiments of this specification, if the first target instruction emitted by the out-of-order instruction emission module is erroneous, the method further includes: The transmission clock cycle and unique identifier information of the first target instruction are provided to the user so that the user can debug the out-of-order instruction transmission module according to the transmission clock cycle and unique identifier information of the first target instruction.

[0037] In the embodiments of this specification, the transmission clock cycle of the first target instruction is monitored by the instruction transmission model. For example, if the out-of-order instruction transmission module transmits an instruction with unique identification information (ID) of 002 in the third clock cycle, and the instruction transmission model fails to transmit the same instruction, an alarm is generated. The alarm information may include: the instruction with ID 002 transmitted by the out-of-order instruction transmission module in the third clock cycle has an error, so that personnel can analyze the cause of the error and repair the problem of the out-of-order instruction transmission module.

[0038] In the embodiments described in this specification, the command issuance model issues a second target command that is identical to the first target command. Specifically, as shown below... Figure 2As shown, transmitting the second target command in the command transmission model further includes: Step 201: Obtain the launch conditions of the second target command in the command launch model; Step 202: Determine whether the second target command can be launched based on the launch conditions.

[0039] In the embodiments of this specification, the launch conditions of the second target instruction in the instruction launch model are first obtained, and then it is determined whether the second target instruction can be launched based on the launch conditions. Since the first target instruction has already been launched to the instruction execution module by the out-of-order instruction launch module, it can be assumed that the out-of-order instruction launch module's determination of the launch conditions of the first target instruction is that the launch conditions are met. Therefore, if the determination of the launch conditions of the second target instruction in the instruction launch model is that the launch conditions are not met, it indicates that the out-of-order instruction launch module has made an error in launching the first target instruction.

[0040] In this embodiment of the specification, obtaining the launch conditions for the second target command in the command launch model further includes: Obtain the valid identifier of the first register corresponding to the second target instruction in the instruction issuance model; Determining whether the second target command can be launched based on the launch conditions further includes: Determine whether the validity flag of the first register is valid; If so, then the second target command can be launched; If not, the second target command cannot be issued.

[0041] In the embodiments of this specification, the instruction information of the second target instruction includes the ID of the source register, the ID of the target register, the ID of the mask register, etc. The first register can be the source register, the target register, or the mask register, etc. The first register is the register that needs to be checked in the issue conditions. If the valid identifier of the first register is valid, the instruction execution module can obtain the corresponding register data when executing the instruction. If the valid identifier of the register is invalid, the instruction execution module cannot execute the instruction, and the instruction should not be issued by the out-of-order instruction issue module.

[0042] After the register's valid flag is determined to be valid, other issuance conditions of the second target instruction are then determined, such as instruction operand preparation information.

[0043] In the embodiments of this specification, if the transmission condition is determined to be met, it means that the out-of-order instruction transmission module's action of transmitting this instruction is correct. However, there is a possibility that the transmission elements of the instruction calculated by the out-of-order instruction transmission module may be incorrect. Therefore, according to one embodiment of this specification, such as Figure 3 As shown, the out-of-order command transmission module is checked based on the transmission result of the second target command, and the process further includes: Step 301: If it is determined that the second target command can be launched based on the launch conditions, then calculate the first launch element of the second target command; Step 302: Extract the second launch element of the first target command; Step 303: If the first transmission element is different from the second transmission element, then the first target instruction transmitted by the out-of-order instruction transmission module is erroneous.

[0044] In the embodiments of this specification, the transmission element represents the information required to execute the instruction, such as the instruction encoding, write-back address, etc. When determining that the second target instruction can be transmitted based on the transmission conditions of the second target instruction, this specification calculates the first transmission element of the second target instruction, then extracts the second transmission element of the first target instruction, and compares whether the first and second transmission elements are consistent. If they are inconsistent, it indicates that the out-of-order instruction transmission module may have made an error in calculating the second transmission element of the first target instruction.

[0045] It should be noted that the method in the embodiments of this specification does not check the execution process of instructions, but rather checks for out-of-order issuance of instructions. Therefore, it is not necessary to ensure that the values ​​of the source register, destination register, mask register, etc., corresponding to the instructions are correct. However, the validity of the registers needs to be checked. Therefore, the embodiments of this specification also include an instruction write-back process, the purpose of which is to set the validity flag of the corresponding registers after the instruction execution is completed, so as to facilitate the instruction issuance model's checking of subsequent instructions.

[0046] Therefore, according to one embodiment of this specification, if the first target instruction emitted by the out-of-order instruction emission module does not contain an error, the method further includes: After detecting the write-back valid signal after the instruction execution module executes the first target instruction, the valid flag of the second register corresponding to the first target instruction in the instruction issuance model is set to valid.

[0047] In the embodiments described in this specification, the second register may be the target register corresponding to the second target instruction in the instruction issuance model, used to store the result after the execution of the first target instruction, so as to facilitate the normal issuance of subsequent instructions.

[0048] It should be noted that, since the method in the embodiments of this specification does not check the execution process of the instruction, the data written back can be predetermined data. The embodiments of this specification do not require the data written back to be the actual execution result obtained by the instruction execution module after executing the instruction.

[0049] According to one embodiment of this specification, in addition to checking the instruction issue conditions and issue elements, it is also necessary to check for instruction write-back conflicts. An instruction write-back conflict refers to two or more instruction write-backs within the same clock cycle. The instruction write-back clock cycle is calculated by the instruction execution unit based on the instruction issue clock cycle and instruction execution delay. The instruction execution unit will write the execution result of the instruction back to the corresponding register according to the instruction write-back clock cycle.

[0050] In the embodiments described in this specification, such as Figure 4 As shown, the steps for checking for write-back conflicts of instructions include: Step 401: Extract the instruction execution delay of the second target instruction; Step 402: Calculate the write-back clock cycle of the first target instruction based on the instruction execution delay of the second target instruction and the transmit clock cycle of the first target instruction; Step 403: Determine whether there is an error in the first target instruction issued by the out-of-order instruction issuing module based on the write-back clock cycle of the first target instruction.

[0051] In the embodiments of this specification, the instruction execution delay can be extracted from the instruction information of the second target instruction, and then the write-back clock cycle can be calculated based on the transmission clock cycle of the first target instruction and the instruction execution delay. For example, if the instruction is transmitted in the third clock cycle and the instruction execution delay is 2 clock cycles, the instruction execution unit will write back the execution result of the instruction in the fifth clock cycle.

[0052] Then, it is determined whether there is a conflict between the write-back clock cycle of the first target instruction and the write-back clock cycles of other target instructions preceding the first target instruction. If a conflict exists, the first target instruction issued by the out-of-order instruction issuing module is incorrect.

[0053] Specifically, if the write-back clock cycle of the first target instruction is the same as the write-back clock cycle of the target instruction preceding the first target instruction, it indicates that the out-of-order instruction issuing module has calculated an error in the issuing clock cycle of the first target instruction. That is, the out-of-order instruction issuing module should not have issued the first target instruction in the calculated clock cycle, resulting in a write-back conflict. Therefore, it can be determined that the first target instruction issued by the out-of-order instruction issuing module is erroneous.

[0054] After detecting an error in the first target instruction transmitted by the out-of-order instruction transmission module, the transmission clock cycle and unique identification information of the first target instruction can be provided to the user so that the user can debug the out-of-order instruction transmission module based on the transmission clock cycle and unique identification information of the first target instruction.

[0055] It should be noted that the method in the embodiments of this specification can be applied to out-of-order instruction issuing modules with a single issuing queue, that is, the out-of-order instruction issuing module can only issue instructions serially. In this case, only one issuing queue needs to be deployed in the instruction issuing model.

[0056] If the out-of-order instruction issuing module is a multi-issue queue issuing module, that is, the out-of-order instruction issuing module can issue instructions in parallel, then multiple issue queues can be deployed in the instruction issuing model. The number of issue queues in the instruction issuing model is the same as the number of issue queues in the out-of-order instruction issuing module. The instruction dispatching module and the instruction execution module need to support multiple issue queues working at the same time.

[0057] Based on the same inventive concept, embodiments of this specification also provide a passive inspection device for out-of-order instruction issuance modules, such as... Figure 5 As shown, it includes: The instruction filling unit 501 is used to monitor the instructions distributed by the instruction distribution module to the out-of-order instruction issuing module under test, and fill the instructions into the issuing queue of the instruction issuing model. The instructions carry unique identification information. Command issuing unit 502 is used to monitor the first target command issued by the out-of-order command issuing module to the command execution module; obtain a second target command with the same unique identification information as the first target command from the issuing queue; and issue the second target command in the command issuing model. The processing unit 503 is used to check the out-of-order instruction transmission module according to the transmission result of the second target instruction.

[0058] The beneficial effects obtained by the above-described device are the same as those obtained by the above-described method, and will not be described in detail in the embodiments of this specification.

[0059] like Figure 6The diagram illustrates the structure of a computer device according to an embodiment of this specification. The instruction issuance model described in this embodiment can be applied to the computer device in this embodiment to execute the methods described in the embodiments of this specification. The computer device 602 may include one or more processing devices 604, such as one or more central processing units (CPUs), each of which may implement one or more hardware threads. The computer device 602 may also include any storage resource 606 for storing information of any kind, such as code, settings, data, etc. Without limitation, for example, the storage resource 606 may include any one or more combinations of the following: any type of RAM, any type of ROM, flash memory, hard disk, optical disk, etc. More generally, any storage resource can use any technology to store information. Furthermore, any storage resource may provide volatile or non-volatile retention of information. Furthermore, any storage resource may represent a fixed or removable component of the computer device 602. In one case, when the processing device 604 executes associated instructions stored in any storage resource or combination of storage resources, the computer device 602 may perform any operation of the associated instructions. The computer device 602 also includes one or more drive mechanisms 608 for interacting with any storage resource, such as a hard disk drive mechanism, an optical disk drive mechanism, etc.

[0060] Computer device 602 may also include an input / output module 610 (I / O) for receiving various inputs (via input device 612) and providing various outputs (via output device 614). A specific output mechanism may include a presentation device 616 and an associated graphical user interface (GUI) 618. In other embodiments, the input / output module 610 (I / O), input device 612, and output device 614 may be omitted, and the device may function solely as a computer device within a network. Computer device 602 may also include one or more network interfaces 620 for exchanging data with other devices via one or more communication links 622. One or more communication buses 624 couple the components described above together.

[0061] Communication link 622 can be implemented in any way, such as via a local area network, a wide area network (e.g., the Internet), a point-to-point connection, or any combination thereof. Communication link 622 may include any combination of hardwired links, wireless links, routers, gateway functions, name servers, etc., governed by any protocol or combination of protocols.

[0062] This specification also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described method.

[0063] This specification also provides computer-readable instructions, wherein when a processor executes the instructions, the program therein causes the processor to perform the above-described method.

[0064] It should be understood that in the various embodiments of this specification, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this specification.

[0065] It should also be understood that, in the embodiments of this specification, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Furthermore, in the embodiments of this specification, the character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0066] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed in this specification can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of the embodiments in this specification.

[0067] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0068] In the embodiments provided in this specification, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the couplings or direct couplings or communication connections shown or discussed may be indirect couplings or communication connections through some interfaces, devices, or units, or they may be electrical, mechanical, or other forms of connection.

[0069] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of the embodiments described in this specification, depending on actual needs.

[0070] Furthermore, the functional units in the various embodiments of this specification can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0071] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the embodiments of this specification, in essence, or the parts that contribute to the prior art, or all or part of the technical solutions, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this specification. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0072] This specification describes the principles and implementation methods of the embodiments using specific examples. The above descriptions of the embodiments are only for the purpose of helping to understand the methods and core ideas of the embodiments in this specification. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the embodiments in this specification. Therefore, the content of this specification should not be construed as a limitation on the embodiments in this specification.

Claims

1. A passive inspection method for an out-of-order instruction issuing module, characterized in that, The method is applied to an instruction emission model, and the method comprises: monitoring instructions distributed by an instruction distribution module to a to-be-tested out-of-order instruction emission module, and filling the instructions into an emission queue of the instruction emission model, the instructions carrying unique identification information; monitoring a first target instruction emitted by the out-of-order instruction emission module to an instruction execution module; acquiring a second target instruction identical to the unique identification information of the first target instruction from the emission queue; emitting the second target instruction in the instruction emission model; checking the out-of-order instruction emission module according to an emission result of the second target instruction.

2. The method of claim 1, wherein, The method further comprises: acquiring an emission condition of the second target instruction in the instruction emission model; judging whether the second target instruction can be emitted according to the emission condition.

3. The method of claim 2, wherein, The method further comprises: if the second target instruction is judged to be unable to be emitted according to the emission condition, the first target instruction emitted by the out-of-order instruction emission module has an error.

4. The method of claim 3, wherein, The method further comprises: if the second target instruction is judged to be able to be emitted according to the emission condition, calculating a first emission element of the second target instruction; extracting a second emission element of the first target instruction; if the first emission element is different from the second emission element, the first target instruction emitted by the out-of-order instruction emission module has an error.

5. The method of claim 3, wherein, The method further comprises: acquiring a valid identification of a first register corresponding to the second target instruction in the instruction emission model; The method further comprises: judging whether the valid identification of the first register is valid; if yes, the second target instruction can be emitted; if no, the second target instruction cannot be emitted.

6. The method of claim 5, wherein, The method further comprises: after monitoring a write-back valid signal after the instruction execution module executes the first target instruction, setting a valid identification of a second register corresponding to the first target instruction in the instruction emission model as valid.

7. The method of claim 3, wherein, The method further comprises: providing an emission clock period and unique identification information of the first target instruction to a user, so that the user debugs the out-of-order instruction emission module according to the emission clock period and the unique identification information of the first target instruction.

8. The method of claim 1, wherein, The method further comprises: extracting an instruction execution delay of the second target instruction; calculating a write-back clock period of the first target instruction according to the instruction execution delay of the second target instruction and the emission clock period of the first target instruction; judging whether the first target instruction emitted by the out-of-order instruction emission module has an error according to the write-back clock period of the first target instruction.

9. The method of claim 8, wherein, The determining whether the first target instruction emitted by the out-of-order instruction emitting module has an error according to a write-back clock cycle of the first target instruction further comprises: determining whether a write-back clock cycle of the first target instruction and a write-back clock cycle of another target instruction before the first target instruction have a conflict; if there is a conflict, the first target instruction emitted by the out-of-order instruction emitting module has an error.

10. An out-of-order instruction issue module passive checking apparatus, characterized in that, comprise: an instruction filling unit, configured to monitor instructions distributed by an instruction distribution module to a to-be-tested out-of-order instruction emitting module, and fill the instructions into an emitting queue of an instruction emitting model, the instructions carrying unique identification information; an instruction emitting unit, configured to monitor a first target instruction emitted by the out-of-order instruction emitting module to an instruction execution module, acquire a second target instruction with same unique identification information as the first target instruction from the emitting queue, and emit the second target instruction in the instruction emitting model; a processing unit, configured to check the out-of-order instruction emitting module according to an emitting result of the second target instruction.

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