Control flow integrity protection method and program product

Abstract

The invention discloses a control flow integrity protection method and a program product, and the method comprises the steps: in a process that an embedded system executes a target program, identifying a jump type of a current execution instruction in an instruction flow of the target program, and verifying the current execution instruction according to the jump type; under the condition that the current execution instruction successfully passes the check, backing up the current execution instruction and execution data thereof at a hardware backup point in a register in the embedded system chip; under the condition that the current execution instruction does not pass the inspection, obtaining target backup data from a hardware backup point in a register in the embedded system chip, adopting the target backup data to cover a current register value, and re-executing the target program from an instruction position corresponding to the target backup data; therefore, the integrity of the program control flow is guaranteed.

Description

Technical Field

[0001] This invention relates to the field of secure embedded processor chip technology, and more particularly to a method and program product for protecting control flow integrity. Background Technology

[0002] With the continuous evolution of control flow attack methods, the security threats faced by embedded systems continue to intensify, and the protection of control flow integrity has become a critical issue that urgently needs to be addressed.

[0003] Existing software-based control flow integrity protection methods primarily rely on static analysis before program execution, scanning source code or intermediate representations to identify potential control flow vulnerabilities or attack code. These methods typically require large-scale rewriting of the source code or compiled intermediate representation, inserting numerous additional runtime checking instructions. Since these instructions are directly embedded in the program body, this not only significantly increases code size but also introduces frequent conditional checks and jump operations, significantly increasing processor load and memory access latency, leading to high runtime performance overhead. Furthermore, due to reliance on static analysis, control flow modeling is often based on approximate or conservative assumptions, making it difficult to accurately depict the actual path during dynamic program execution. When faced with complex control flow semantics such as indirect calls and polymorphic jumps, problems such as overgeneralization or missing key constraints can easily occur, allowing attackers to construct legitimate jump chains and tamper with the control flow. Therefore, a control flow integrity protection method is needed to achieve more accurate and reliable protection of control flow integrity. Summary of the Invention

[0004] This invention provides a method and program product for protecting control flow integrity, aiming to achieve more accurate and reliable protection of control flow integrity while ensuring high real-time performance and low resource consumption.

[0005] According to one aspect of the present invention, a method for protecting control flow integrity is provided, the method comprising:

[0006] During the execution of a target program in an embedded system, the jump type of the currently executed instruction in the instruction stream of the target program is identified, and the currently executed instruction is verified based on the jump type.

[0007] If the currently executed instruction successfully passes the verification, the currently executed instruction and its execution data are backed up at the hardware backup point in the register within the embedded system chip;

[0008] If the currently executed instruction fails the verification, target backup data is obtained from the hardware backup point in the register of the embedded system chip, the target backup data is used to overwrite the current register value, and the target program is re-executed from the instruction corresponding to the target backup data.

[0009] According to another aspect of the present invention, a control flow integrity protection device is provided, the device comprising:

[0010] A jump type determination module is used to identify the jump type of the currently executing instruction in the instruction stream of the target program during the execution of the target program in the embedded system, and to verify the currently executing instruction based on the jump type;

[0011] The first verification module is used to back up the currently executed instruction and its execution data at a hardware backup point in the register within the embedded system chip, provided that the currently executed instruction has successfully passed the verification.

[0012] The second verification module is used to obtain target backup data from the hardware backup point in the register of the embedded system chip when the current execution instruction fails the verification, overwrite the current register value with the target backup data, and re-execute the target program from the instruction corresponding to the target backup data.

[0013] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising:

[0014] At least one processor; and

[0015] A memory communicatively connected to the at least one processor; wherein,

[0016] The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the control flow integrity protection method according to any embodiment of the present invention.

[0017] According to another aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing computer instructions for causing a processor to execute and implement the control flow integrity protection method according to any embodiment of the present invention.

[0018] According to another aspect of the present invention, embodiments of this disclosure also provide a computer program product, including a computer program that, when executed by a processor, implements a method for protecting control flow integrity as described in any of the embodiments of this disclosure.

[0019] The technical solution of this invention firstly identifies the jump type of the currently executing instruction in the instruction stream of the target program during the execution of the target program in the embedded system, and verifies the currently executing instruction based on the jump type; targeted verification of the currently executing instruction based on the jump type improves the efficiency and accuracy of security verification; nextly, if the currently executing instruction successfully passes the verification, the currently executing instruction and its execution data are backed up at a hardware backup point in the register within the embedded system chip; successful data backup ensures the traceability of the legal execution state and provides a reliable foundation for subsequent recovery from possible anomalies; finally, if the currently executing instruction fails the verification, the data is backed up from the... The method obtains target backup data from the hardware backup point in the register of the embedded system chip, overwrites the current register value with the target backup data, and re-executes the target program from the instruction corresponding to the target backup data. If verification fails, it accurately rolls back from the hardware backup point and re-executes, avoiding the performance overhead and real-time loss caused by restarting the entire program. This greatly enhances the fault tolerance, robustness, and anti-attack resilience of the embedded system. It can achieve fast and accurate control flow integrity monitoring for different types of jump instructions, and realize rapid control flow recovery after detecting attacks against the control flow. It significantly enhances the fault tolerance, robustness, and anti-attack capabilities of the embedded system, and can achieve comprehensive protection of control flow integrity while ensuring high real-time performance and low resource consumption.

[0020] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a flowchart of a control flow integrity protection method provided according to Embodiment 1 of the present invention;

[0023] Figure 2 This is a flowchart of a control flow integrity protection method provided according to Embodiment 2 of the present invention;

[0024] Figure 3 This is a flowchart of a control flow integrity protection method provided according to Embodiment 3 of the present invention;

[0025] Figure 4a This is a flowchart of a control flow integrity protection method provided in Embodiment 4 of the present invention;

[0026] Figure 4b This is a flowchart of a control flow integrity protection method provided in Embodiment 4 of the present invention;

[0027] Figure 4c This is a flowchart illustrating the design of a control flow integrity tag for a control flow integrity protection method according to Embodiment 4 of the present invention.

[0028] Figure 4d This is a flowchart of bitmap construction for a control flow integrity protection method according to Embodiment 4 of the present invention.

[0029] Figure 4e This is a flowchart illustrating the storage of control flow integrity parameters in a control flow integrity protection method according to Embodiment 4 of the present invention.

[0030] Figure 4f This is a flowchart of a control flow integrity verification method for a control flow integrity protection method according to Embodiment 4 of the present invention.

[0031] Figure 5 This is a schematic diagram of a control flow integrity protection device provided according to Embodiment 5 of the present invention;

[0032] Figure 6 This is a schematic diagram of the structure of an electronic device that implements the control flow integrity protection method of the present invention. Detailed Implementation

[0033] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0034] It should be noted that the terms "first," "second," "target," etc., used in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0035] It should be noted that the terms "a" and "a plurality of" used in this disclosure are illustrative rather than restrictive, and those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more".

[0036] The names of messages or information exchanged between multiple devices in the embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of such messages or information.

[0037] It is understood that before using the technical solutions disclosed in the various embodiments of this disclosure, users should be informed of the types, scope of use, and usage scenarios of the personal information involved in this disclosure in an appropriate manner in accordance with relevant laws and regulations, and user authorization should be obtained.

[0038] For example, upon receiving a user's active request, a prompt message is sent to the user to explicitly inform them that the requested operation will require the acquisition and use of the user's personal information. This allows the user to independently choose whether to provide personal information to the software or hardware, such as the electronic device, application, server, or storage medium performing the operations of this disclosed technical solution, based on the prompt message.

[0039] As an optional but non-limiting implementation, in response to a user's active request, sending a prompt message to the user can be done via a pop-up window, where the prompt message can be presented in text format. Furthermore, the pop-up window can also include a selection control allowing the user to choose "agree" or "disagree" to provide personal information to the electronic device.

[0040] It is understood that the above notification and user authorization process are merely illustrative and do not constitute a limitation on the implementation of this disclosure. Other methods that comply with relevant laws and regulations may also be applied to the implementation of this disclosure.

[0041] It is understood that the data involved in this technical solution (including but not limited to the data itself, the acquisition or use of the data) shall comply with the requirements of relevant laws, regulations and related provisions.

[0042] Example 1

[0043] Figure 1 This is a flowchart illustrating a control flow integrity protection method provided in Embodiment 1 of the present invention. This embodiment is applicable to protecting the integrity of program control flow. The method can be executed by a control flow integrity protection device, which can be implemented in hardware and / or software, optionally through an electronic device, such as a mobile terminal, PC, or server. Figure 1 As shown, the method may specifically include:

[0044] S110. During the execution of the target program in the embedded system, the jump type of the currently executed instruction in the instruction stream of the target program is identified, and the currently executed instruction is verified according to the jump type.

[0045] In this embodiment of the invention, an embedded system can be understood as a small computer system designed for a specific device or scenario, which can be embedded in various hardware devices to control the specific functions of the device. The target program refers to a specific application program being executed in the embedded system. The instruction stream can be understood as a continuous sequence of instructions formed in a certain order during the execution of the target program, which can be used to reflect the steps and flow of program execution.

[0046] Jump types can be understood as the types of instructions in the instruction stream that change the normal execution order of the program. For example, jump types can include, but are not limited to, direct jumps, branch jumps, and indirect jumps. Different jump types correspond to different ways of changing the program's execution path.

[0047] To determine the integrity of the instruction stream of the target program, optionally, during the execution of the target program by the embedded system, the jump type of the currently executed instruction in the instruction stream of the target program can be identified, and the currently executed instruction can be verified based on the jump type to confirm whether it conforms to the normal program execution logic.

[0048] Specifically, the type of the currently executing instruction can be identified based on the opcode of the currently executing instruction decoding signal in the instruction stream of the target program.

[0049] S120. If the currently executed instruction successfully passes the verification, the currently executed instruction and its execution data are backed up at the hardware backup point in the register of the embedded system chip.

[0050] Optionally, if the currently executed instruction successfully passes the verification, meaning that the target program control flow has not been tampered with, the currently executed instruction and its execution data can be backed up to the internal register of the embedded system chip, thus preserving the legal execution state of the currently executed instruction.

[0051] Specifically, if the current execution instruction successfully passes the verification, backups can be performed based on the differences in jump types. For branch jump instructions, the following three types of data need to be backed up: jump direction, jump address, and the binary code corresponding to the execution instruction. The jump direction indicates whether a jump has occurred, and the jump address includes jump addresses that meet and do not meet preset conditions. All three types of data are protected by encryption or integrity tags. For indirect jump instructions, due to their unconditional jump nature, there is no need to back up the jump direction. Instead, the jump address and the execution instruction code need to be backed up. The execution instruction code is the binary code of the indirect jump instruction, and its jump address consists of multiple dynamically changing potential jump addresses. These potential jump addresses can be stored using bitmap compression technology to ensure the simplicity and security of the backup data. For direct jump instructions, due to their unconditional jump nature, there is no need to back up the jump direction. Instead, the corresponding static fixed jump address and the execution instruction code need to be backed up. Data integrity can be quickly verified using Hamming distance tags.

[0052] Registers are high-speed storage units within an embedded system-on-a-chip (SoC) used to temporarily store data and instructions. They can be quickly accessed by the processor, improving the efficiency of subsequent data recovery. Hardware backup points can be specific storage locations within the SoC's registers specifically designated for storing backup data.

[0053] Optionally, execution data refers to data related to the currently executed instruction. For example, execution data may include, but is not limited to, intermediate results during program execution, system status parameters, and other types of data.

[0054] S130. If the currently executed instruction fails the verification, obtain the target backup data from the hardware backup point in the register of the embedded system chip, use the target backup data to overwrite the current register value, and re-execute the target program from the instruction corresponding to the target backup data.

[0055] The target backup data refers to the corresponding backup data selected from the hardware backup point when the currently executed instruction fails the verification, which can be used to restore the embedded system state. Optionally, the target backup data can be the data backed up when the verification was most recently successfully passed, to ensure the timeliness of the backup data.

[0056] Optionally, when the currently executed instruction fails the verification, i.e. the current program control flow has been tampered with, the operation of the embedded system chip is stopped and a control flow fast recovery mechanism is started. The target backup data corresponding to the currently executed instruction is read from the hardware backup point in the register of the embedded system chip, and the target backup data is used to replace the data stored in the current register that may contain errors or abnormalities, so that the register is restored to a valid state.

[0057] After the register value is overwritten by the target backup data, the target program can be executed again from the instruction location corresponding to the target backup data to quickly restore the embedded system.

[0058] By embedding hardware systems within hardware devices, hardware-assisted mechanisms can effectively alleviate the performance and accuracy bottlenecks caused by code bloat and static approximation analysis in traditional software solutions. These hardware-assisted mechanisms can implement critical verification and backup logic at the processor microarchitecture level, without modifying the target program source code or intermediate representation. Jump target verification and state backup can be completed directly during instruction execution, significantly reducing interference with the embedded system's main execution path and decreasing the number of executed instructions and memory accesses. Simultaneously, hardware-based address verification and data recovery can be performed at line speed, significantly improving the real-time performance of control flow integrity detection and system throughput. Furthermore, hardware isolation mechanisms enhance the tamper resistance of critical metadata such as shadow stacks and verification tags, further ensuring secure protection of control flow integrity.

[0059] The technical solution of this invention firstly identifies the jump type of the currently executing instruction in the instruction stream of the target program during the execution of the target program in the embedded system, and verifies the currently executing instruction based on the jump type; targeted verification of the currently executing instruction based on the jump type improves the efficiency and accuracy of security verification; nextly, if the currently executing instruction successfully passes the verification, the currently executing instruction and its execution data are backed up at a hardware backup point in the register within the embedded system chip; successful verification and data backup ensure the traceability of the legal execution state and provide a reliable foundation for subsequent recovery from possible anomalies; finally, if the currently executing instruction fails the verification... In the case of verification, target backup data is obtained from the hardware backup point in the register of the embedded system chip, the target backup data is used to overwrite the current register value, and the target program is re-executed from the instruction corresponding to the target backup data. In the case of verification failure, the program is precisely rolled back from the hardware backup point and re-executed, avoiding the performance overhead and real-time loss caused by restarting the entire program. This greatly enhances the fault tolerance, robustness, and anti-attack resilience of the embedded system. It can achieve fast and accurate control flow integrity monitoring for different types of jump instructions, and can quickly restore the control flow after detecting attacks against the control flow. While ensuring the high real-time performance and low resource consumption of the embedded system, it achieves comprehensive and efficient protection of control flow integrity.

[0060] Example 2

[0061] Figure 2 This flowchart illustrates a control flow integrity protection method according to Embodiment 2 of the present invention, further describing the verification process of the currently executing instruction when the jump type is a direct jump instruction or a branch jump instruction. Optionally, the jump type includes direct jump instructions and branch jump instructions; the verification of the currently executing instruction based on the jump type includes: when the jump type is a direct jump instruction or a branch jump instruction, extracting the tag of the currently executing instruction and the tag of the next executing instruction from the target memory within the embedded system chip; wherein, the tag is determined based on the jump relationship between multiple instructions in the instruction flow of the target program and the expected Hamming distance; determining the actual Hamming distance between the tag of the currently executing instruction and the tag of the next executing instruction; if the actual Hamming distance is the expected Hamming distance, the currently executing instruction is determined to have successfully passed the verification; otherwise, the currently executing instruction is determined to have failed the verification. Specific implementation details can be found in the description of this embodiment. Technical features that are the same as or similar to those in the foregoing embodiments will not be repeated here. Figure 2 As shown, the method may specifically include:

[0062] S210. During the execution of the target program in the embedded system, the jump type of the currently executed instruction in the instruction stream of the target program is identified. If the jump type is a direct jump instruction or a branch jump instruction, the tag of the currently executed instruction and the tag of the next executed instruction are extracted from the target memory in the embedded system chip. The tag is determined based on the jump relationship between multiple instructions in the instruction stream of the target program and the expected Hamming distance.

[0063] Jump types can include direct jump instructions and branch jump instructions. Direct jump instructions are instructions in the target program that unconditionally change the execution order. Their jump address is determined at compile time and can be an absolute address or an offset relative to the current instruction counter. This address remains unchanged during execution, and no condition needs to be checked during execution; execution directly jumps to the specified jump address to continue. Branch jump instructions are conditional transfer instructions in the program that decide whether to jump based on specific conditions. Their jump address is fixed in the instruction, and the jump is only executed when the preset condition is met; otherwise, the next instruction is executed sequentially. Whether to jump or not is determined by the preset condition; for example, an if-else statement is a jump instruction.

[0064] The target memory can be a storage area within the embedded system chip used to store verification data related to control flow integrity. For example, the target memory can be a memory type such as control flow integrity parameter memory. The target memory can be used to support data reading during the control flow integrity verification process. The control flow integrity parameter memory is a preset on-chip secure static random-access memory (SRAM), and after loading control flow integrity tags, bitmaps, and other information, the control flow integrity parameters stored within it, i.e., the control flow integrity tags and bitmaps, cannot be modified.

[0065] Based on the above scheme, if the jump type of the currently executing instruction in the instruction stream of the target program is identified as a direct jump instruction or a branch jump instruction, the tag of the currently executing instruction and the tag of the next executing instruction can be extracted from the target memory within the embedded system chip. The tag can be a specific identifier assigned to jump instructions in the program instruction stream, used to verify the integrity of the program control flow. The tag can be pre-determined based on the jump relationships between multiple instructions in the target program's instruction stream and the expected Hamming distance, providing a clear basis for verifying the legality of direct jump instructions.

[0066] To provide basic data for verifying direct jump instructions or branch jump instructions, optionally, a mapping relationship between execution instructions and tags can be pre-established before retrieving the tag of the currently executed instruction and the tag of the next executed instruction from the target memory within the embedded system chip. Specifically, during the offline phase of the target program in the embedded system, the program code of the target program is preprocessed to obtain a disassembled file of the target program; wherein, the preprocessing includes compiling and linking the program code, and disassembling the executable file; a control flow graph of the target program is established based on the disassembled file; wherein, the control flow graph consists of multiple nodes and their edges, the nodes are the memory addresses of target jump instructions in the instruction flow of the target program, and the edges are the potential jump addresses of the target jump instructions; the target jump instructions include direct jump instructions and branch jump instructions; a label is determined for each node in the control flow graph based on the control flow graph and preset label constraints; wherein, the label constraints include the Hamming distance between the labels of parent nodes and child nodes in the multiple nodes of the control flow graph being the expected Hamming distance; the labels are stored in the target memory within the embedded system chip, and a mapping relationship is established between the labels and their corresponding target jump instructions.

[0067] Optionally, during the offline phase of the target program in the embedded system, preprocessing operations can be performed on the target program's code to support control flow integrity verification during program execution. This converts the original program code into a format easy to analyze and process, resulting in a disassembled file of the target program. The program code can be a code file written in high-level languages ​​such as C / C++, JAVA, or Python. An executable file is a .elf format file generated after the program code is compiled and linked using the GNU Compiler Collection (GCC), which can be loaded and executed by the embedded system chip. The disassembled file is a file obtained by translating the executable file of the target program into a txt format file containing assembly instructions, hexadecimal instruction code, and instruction addresses, clearly demonstrating the program's instruction composition and structure. By concentrating the preparation of key data for direct jump verification in the offline phase, complex calculations during real-time execution are effectively avoided, significantly reducing the impact on system operating efficiency.

[0068] Optionally, the preprocessing may include, but is not limited to, compiling and linking program code, as well as disassembling executable files.

[0069] Furthermore, a control flow graph (CFG) of the target program can be constructed based on the disassembled file to clearly identify the jump relationships in the program. A control flow graph is a graphical structure used to represent the program execution flow. The control flow graph can consist of multiple nodes and their edges. Nodes are elements representing the memory addresses of target jump instructions in the instruction stream of the target program, and are the basic units constituting the control flow graph. The edges represent the potential jump addresses of the target jump instructions.

[0070] The target jump instruction may include one or more instruction types such as direct jump instruction and branch jump instruction.

[0071] Optionally, establishing the control flow graph of the target program based on the disassembled file includes: performing static analysis on the disassembled file, extracting the target jump instruction from the instruction stream of the target program, and determining the potential jump address of the target jump instruction; establishing the control flow graph of the target program with the address of the target jump instruction as a node and the potential jump address of the target jump instruction as an edge.

[0072] Specifically, static analysis can be performed on the disassembled file to determine the instruction type based on the opcode of the assembly instructions, and to extract direct jump instructions and branch jump instructions from the instruction stream of the target program; based on the instruction type and its instruction address, the potential jump address of the target jump instruction can be determined.

[0073] If the target jump instruction is a direct jump instruction, then it has only one potential jump address, which is the immediate value of the target jump instruction plus the address of the target jump instruction. If the target jump instruction is a branch jump instruction, then it has two potential jump addresses. If the branch condition is met, a jump operation occurs, and its jump address is the immediate value of the target jump instruction plus the address of the target jump instruction; otherwise, if the branch condition is not met, no jump operation occurs, and its jump address is the address of the target jump instruction plus the hexadecimal 4 (0x4), which is the address of the next instruction to be executed.

[0074] Based on this, all paths traversed during the execution of the target program can be summarized to obtain all potential jump addresses included in the instruction flow of the target program, thus reflecting the possible flow of all executed instructions during the execution of the target program. Furthermore, the control flow graph of the target program can be constructed using the address of the target jump instruction as a node and the potential jump addresses of the target jump instruction as edges.

[0075] Alternatively, the control flow graph of the target program can be represented by the following formula:

[0076] ;

[0077] in, A set of nodes; Let it be the set of edges; It is the root node, which is the entry node of the control flow graph; To control the exit node of the flow graph.

[0078] A direct jump instruction has only one potential jump address, and therefore the node corresponding to a direct jump instruction in the control flow graph has only one edge. Similarly, a branch jump instruction has two potential jump addresses, and the node corresponding to a branch jump instruction has two edges.

[0079] In order for the labels to effectively verify the legality of the jump operation, the label of each node in the control flow graph can be determined according to the control flow graph and the preset label constraints, so that the legal jump operation presents a fixed feature on the label.

[0080] Label constraints refer to the rules that must be followed when determining node labels in the control flow graph. For example, label constraints may include conditions such as the Hamming distance between the labels of parent and child nodes in the control flow graph being the expected Hamming distance, to ensure the uniqueness and rationality of label assignment. A parent node is the node that serves as the starting point of a jump between two nodes with a jump relationship in the control flow graph, i.e., the node where the jump instruction is located. A child node is the node that serves as the ending point of a jump between two nodes with a jump relationship in the control flow graph, i.e., the node pointed to by the jump instruction.

[0081] Optionally, determining the label of each node in the control flow graph based on the control flow graph and preset label constraints includes: determining the total number of nodes, the maximum number of parent nodes, and the maximum number of child nodes in the control flow graph to determine the length of the label; obtaining an arbitrary binary number representing the length of the label to determine the label of the root node in the control flow graph; determining the labels of the child nodes of the root node based on the label of the root node and the expected Hamming distance of the root node; and using the child node as the parent node, determining the labels of the child nodes of the parent node based on the label of the parent node and the expected Hamming distance of the parent node to obtain the label of each node. By iteratively assigning labels layer by layer from the root node, it is ensured that the label of each node satisfies the Hamming distance constraint between the parent node and the child node, making the label system of the entire control flow graph form a self-consistent verification logic, covering all possible jump paths, and improving the completeness of verification.

[0082] To ensure the label length matches the actual jump scale of the target program, the total number of nodes, the maximum number of parent nodes, and the maximum number of child nodes in the control flow graph can be statistically determined. The label length is then determined based on these statistics, avoiding resource waste or insufficient length. The total number of nodes refers to the total number of all nodes in the control flow graph. This reflects the data scale of jump instructions in the target program. The maximum number of parent nodes refers to the number of child nodes of the parent node with the most child nodes among all nodes in the control flow graph, reflecting the upper limit of the number of addresses a given jump instruction in the program can jump to. The maximum number of child nodes refers to the number of parent nodes of the child node with the most parent nodes among all nodes in the control flow graph, reflecting the upper limit of how many jump instructions can point to a given address in the program.

[0083] The length of a label refers to the number of binary bits contained in each node label.

[0084] To ensure that the label length covers all nodes and adapts to the scale of jumps, optionally, determining the label length by determining the total number of nodes, the maximum number of parent nodes, and the maximum number of child nodes in the control flow graph may include: mapping the total number of nodes to a target value, and determining the label length based on the maximum value among the target value, the maximum number of parent nodes, and the maximum number of child nodes. By mapping the total number of nodes to a target value and combining it with the maximum value of the maximum number of parent nodes and the maximum number of child nodes to determine the label length, precise adaptation of the label length is achieved. This ensures that the label has enough bits to distinguish all nodes and adapts to the complexity of jump relationships in the program, while meeting security requirements and keeping label storage and computational overhead within a reasonable range.

[0085] Specifically, the label can be determined using the following formula. Length:

[0086] ;

[0087] in, The length of the label; The maximum number of parent nodes; This represents the maximum number of child nodes. This represents the total number of nodes. The target value is obtained by mapping the total number of nodes, which can be calculated by taking the logarithm of the total number of nodes as base 2 and then rounding it down.

[0088] The root node is the starting node in the control flow graph, that is, the node containing the first jump instruction in the instruction flow after the target program begins execution. Optionally, any binary number of the label length can be used to determine the label of the root node in the control flow graph. For example, the label of the root node can be... Any binary number of any size, and the labels of all nodes in the control flow graph are binary numbers.

[0089] Based on this, the labels of the root node's child nodes can be determined according to the root node label and the expected Hamming distance. Through an iterative process of promoting child nodes to parent nodes, using these child nodes as parent nodes, the labels of the corresponding child nodes are determined layer by layer according to the parent node label and the expected Hamming distance. This process traverses all nodes in the control flow graph layer by layer, assigning a unique label to each node, ultimately completing the label assignment and ensuring that the jump relationships are verifiable at the label level. The expected Hamming distance can be between 1 and... Any positive integer between 0 and 1.

[0090] The Hamming distance can be calculated using the following formula. :

[0091] ;

[0092] in, For two sizes The binary number of bits; Representing binary numbers The Bit; Representing binary numbers The Bit; This represents the XOR operation.

[0093] Optionally, after the tag is determined, it can be stored in the target memory within the embedded system chip, and a mapping relationship can be established between the tag and its corresponding target jump instruction, so that the tag can be quickly obtained and efficiently verified during program execution.

[0094] Specifically, the tag can be securely loaded into the control flow integrity parameter memory inside the embedded system chip. This secure loading method can be achieved by storing the tag in the memory through a preset secure interface, under authorized conditions within the embedded system.

[0095] To ensure secure storage of the label, the security interface can optionally be a Trusted Platform Module (TPM) interface, employing symmetric cryptographic algorithms such as Advanced Encryption Standard (AES) to ensure that the Control Flow Integrity label (CFIlabel) is stored in encrypted form at a designated location within the embedded system chip. This security interface uses token-based authorization and authentication to prevent unauthorized users from accessing information such as the CFIlabel.

[0096] S220. Determine the actual Hamming distance between the label of the currently executed instruction and the label of the next executed instruction. If the actual Hamming distance is the expected Hamming distance, determine that the currently executed instruction has successfully passed the test; otherwise, determine that the currently executed instruction has failed the test.

[0097] To determine whether a direct jump instruction or a branch jump instruction is valid, optionally, the actual Hamming distance between the label of the currently executed instruction and the label of the next executed instruction can be calculated and compared with the expected Hamming distance to determine whether the currently executed instruction passes the test.

[0098] Specifically, if the actual Hamming distance is the expected Hamming distance, the current instruction being executed is determined to have successfully passed the check; otherwise, the target program control flow is considered to have been tampered with and the current instruction being executed has failed the check, thus effectively identifying abnormal jumps.

[0099] S230. If the currently executed instruction successfully passes the verification, the currently executed instruction and its execution data are backed up at the hardware backup point in the register of the embedded system chip.

[0100] S240. If the currently executed instruction fails the verification, obtain the target backup data from the hardware backup point in the register of the embedded system chip, use the target backup data to overwrite the current register value, and re-execute the target program from the instruction corresponding to the target backup data.

[0101] The technical solution of this invention, firstly, when the jump type is a direct jump instruction or a branch jump instruction, extracts the tag of the currently executed instruction and the tag of the next executed instruction from the target memory within the embedded system chip; wherein, the tag is determined based on the jump relationship between multiple instructions in the instruction flow of the target program and the expected Hamming distance; embedding the program's control flow structure into the instruction tags, so that each jump path corresponds to a unique tag combination and distance feature, by securely storing tag information within the chip, not only is malicious tampering during runtime prevented, but low-latency data access is also achieved, resulting in a lightweight... This lays the foundation for high-level, time-sensitive integrity verification. Next, the actual Hamming distance between the label of the currently executed instruction and the label of the next executed instruction is determined. If the actual Hamming distance is the expected Hamming distance, the currently executed instruction is determined to have successfully passed the verification; otherwise, the currently executed instruction is determined to have failed the verification. Verification based on encoded distance can effectively identify illegal path splicing behavior. Even if a tampering attack jumps to other legitimate instruction segments in the program, it will still be detected and blocked as long as the distance between its preceding and following labels does not meet expectations. This achieves fine-grained, low-overhead control flow monitoring at runtime, significantly improving the defense capability against code reuse attacks.

[0102] Example 3

[0103] Figure 3 The flowchart of a control flow integrity protection method provided in Embodiment 3 of the present invention further describes the verification process of the currently executed instruction when the jump type is an indirect jump instruction. Optionally, the jump type includes an indirect jump instruction; the verification of the currently executed instruction according to the jump type includes: when the jump type is the indirect jump instruction, extracting the bitmap corresponding to the currently executed instruction from the target memory in the embedded system chip, and verifying the currently executed instruction according to the bitmap, wherein the value of the corresponding point of the indirect jump instruction in the instruction flow of the target program in the bitmap is a preset value. For detailed implementation, please refer to the description of this embodiment. Technical features that are the same as or similar to those in the foregoing embodiments will not be repeated here. Figure 3 As shown, the method may specifically include:

[0104] S310. During the execution of the target program in the embedded system, the jump type of the currently executed instruction in the instruction stream of the target program is identified. If the jump type is an indirect jump instruction, the bitmap corresponding to the currently executed instruction is extracted from the target memory in the embedded system chip. The currently executed instruction is checked according to the bitmap. The value of the corresponding point of the indirect jump instruction in the instruction stream of the target program in the bitmap is a preset value.

[0105] In this embodiment of the invention, an indirect jump instruction refers to a control transfer instruction that obtains the target address through indirect addressing. Its jump address is not directly encoded in the instruction but is stored in a designated register or memory unit, and is dynamically read and determined during program execution. A bitmap can be understood as a structure that uses binary bits to represent data. In indirect jump instruction verification, the bitmap can be used to mark the jump address of the indirect jump instruction. The value of the corresponding point in the bitmap for the indirect jump address corresponding to the indirect jump instruction in the instruction stream of the target program is a preset value, which can be used to quickly identify valid indirect jump addresses during verification.

[0106] To efficiently verify indirect jump instructions, when an indirect jump type is identified, the bitmap corresponding to the currently executed instruction can be extracted from the target memory, and the currently executed instruction can be verified by bitmap comparison.

[0107] To provide a data foundation for real-time verification of indirect jump instructions, before extracting the bitmap corresponding to the currently executed instruction from the target memory within the embedded system chip, the method further includes: preprocessing the program code of the target program during the offline phase of the target program in the embedded system to obtain a disassembled file of the target program; wherein, the preprocessing includes compiling and linking the program code, and disassembling the executable file; determining the target jump instructions in the instruction stream of the target program based on the disassembled file, instrumenting the indirect jump instructions in the target jump instructions, executing the target program based on a set of test cases to determine the jump address of the indirect jump instructions based on the instrumented code; mapping the jump address of the indirect jump instructions to a bitmap, and storing the bitmap in the target memory within the embedded system chip.

[0108] Furthermore, the target jump instruction in the instruction stream of the target program can be extracted based on the opcode of the assembly instructions included in the disassembled file.

[0109] Considering that static analysis cannot extract the jump addresses of indirect jump instructions, alternatively, a test case set can be generated using an instrumentation tool. For example, the instrumentation tool could be a pin, which instruments each indirect jump instruction and records the set of indirect jump addresses during dynamic analysis. Specifically, the indirect jump instructions in the target jump instructions can be instrumented, inserting instrumentation code into the program code. The target program is then executed based on the test case set to collect and determine the jump addresses of the indirect jump instructions during program execution based on the instrumented code.

[0110] The test case set refers to a set of input data used to test the target program. By executing different test cases, various indirect jumps in the program can be triggered, thereby determining the jump address of the indirect jump instruction.

[0111] The test case set may include, but is not limited to, a set of dynamic symbolic execution test cases. and a set of fuzz test cases generated based on fuzz testing tools. These are collection types. A dynamic symbolic execution test case set refers to a collection of test cases generated using dynamic symbolic execution technology. It combines symbolic execution and concrete execution, enabling a systematic exploration of program execution paths and generating test cases covering various indirect path scenarios. A fuzzing tool is a tool used to generate a large number of random or semi-random test cases. By inputting the generated test cases into the program and observing its execution, vulnerabilities in the program and the determination of indirect jump addresses can be discovered. A fuzzing test case set refers to a collection of test cases generated by a fuzzing tool, containing a large amount of diverse input data used to comprehensively trigger indirect jumps in the program.

[0112] Considering that dynamic symbolic execution test case sets have high path coverage but are slow, while fuzz testing tools generate fuzz test case sets that are fast but cannot cover some paths, we can take the union of the two, as shown in the following formula:

[0113] ;

[0114] This allows us to obtain a set of test cases. By combining dynamic symbolic execution test cases and fuzz test cases, comprehensive coverage of indirect jump paths is achieved. Dynamic symbolic execution can traverse the logical paths of the program, ensuring that regular jump addresses are not missed. Fuzz testing can trigger edge scenarios through random input to capture rare jump situations, making the jump addresses contained in the bitmap more comprehensive and significantly reducing verification vulnerabilities caused by missing addresses.

[0115] In order to quickly verify the legality of indirect jumps during the verification phase, the jump address of the indirect jump instruction can be mapped to a bitmap, and the bitmap can be stored in the target memory within the embedded system chip in the same storage method as the tag.

[0116] Optionally, mapping the jump address of the indirect jump instruction to a bitmap includes: constructing a one-dimensional array using the jump address of the indirect jump instruction as a first value and the jump addresses of target jump instructions in the instruction stream other than the indirect jump instruction as a second value; and mapping the one-dimensional array to a two-dimensional array to obtain the bitmap. By distinguishing between indirect jump addresses and other jump addresses to construct an array and mapping it to a bitmap, legitimate addresses have clear identification characteristics in the two-dimensional structure. This simplifies the bitmap construction logic and enables rapid location during verification. Legitimacy can be determined by directly querying the value at the corresponding position using an index, improving the intuitiveness and efficiency of indirect jump verification.

[0117] The first value refers to the value corresponding to the jump address of the jump instruction during the construction of the one-dimensional array. This first value can be used to distinguish the address values ​​of other types of jump instructions. The second value refers to the value corresponding to the jump address of other target jump instructions in the instruction stream, excluding indirect jump instructions, during the construction of the one-dimensional array. This value can clearly distinguish indirect jump addresses from other jump addresses during the subsequent verification stage.

[0118] Specifically, the jump address of the indirect jump instruction can be set to the first value, and the jump address of the target jump instruction in the instruction stream other than the indirect jump instruction can be set to the second value, thereby constructing a one-dimensional array. This represents all instruction jump addresses in the target program. A one-dimensional array is a data structure consisting of a series of elements arranged in a linear order, which can be used to temporarily store the values ​​corresponding to the jump addresses during the process of mapping indirect jump addresses to bitmaps.

[0119] Specifically, a one-dimensional array can be represented by the following formula:

[0120] ;

[0121] in, For the first in the target program A jump instruction; if If the jump address is the address corresponding to the indirect jump instruction, then Set to the default value; otherwise It can be any value other than the preset value; The total number of instructions in the target program.

[0122] Furthermore, a one-dimensional array can be mapped to a two-dimensional array, resulting in a bitmap, which facilitates quick lookup and verification of indirect jump addresses. A two-dimensional array is a data structure composed of multiple one-dimensional arrays organized in rows and columns. Specifically, a two-dimensional array can be represented by the following formula. :

[0123] ;

[0124] ;

[0125] ;

[0126] in, The number of rows in the two-dimensional data; The number of columns in the two-dimensional array; The bit size used to represent the data corresponding to a point in a bitmap.

[0127] After obtaining the bitmap and determining that the type of the currently executed instruction is an indirect jump instruction, the currently executed instruction can be checked through the bitmap. If the value of the jump address of the currently executed instruction at the corresponding point in the bitmap is a preset value, the check is passed; otherwise, it is determined that the target program control flow has been tampered with.

[0128] By constructing a bitmap based on the indirect jump address set, it is possible to quickly determine whether the jump address of the current indirect jump instruction is in the extracted set. This has low time complexity and low performance overhead. The data size of the bitmap is equivalent to the data size of the original indirect jump address set divided by 64, resulting in lower resource overhead. Furthermore, compared to storing the original data directly, bit-by-bit storage requires less space because each point on the bitmap can represent multiple bits of data.

[0129] S320. If the currently executed instruction successfully passes the verification, the currently executed instruction and its execution data are backed up at the hardware backup point in the register of the embedded system chip.

[0130] S330. If the currently executed instruction fails the verification, obtain the target backup data from the hardware backup point in the register of the embedded system chip, overwrite the current register value with the target backup data, and re-execute the target program from the instruction corresponding to the target backup data.

[0131] The technical solution of this invention, when the jump type is the indirect jump instruction, extracts the bitmap corresponding to the currently executed instruction from the target memory within the embedded system chip, and verifies the currently executed instruction based on the bitmap. The value of the corresponding point of the indirect jump instruction in the instruction flow of the target program is a preset value. The bitmap structure efficiently encodes all legal indirect jump target address information in the program control flow graph, enabling fine-grained jump constraints and effectively preventing tampering attacks from transferring control flow to illegal or unexpected locations. Simultaneously, the bitmap is stored in a secure area within the chip, possessing anti-tampering and fast access capabilities, ensuring the real-time performance and reliability of runtime verification. Compared to traditional complex mechanisms such as pointer encryption or shadow stacks, the bitmap-based verification method is logically simple, has low resource overhead, balances security and versatility, and significantly improves the defense capability against indirect jump-type control flow hijacking attacks.

[0132] Example 4

[0133] As an optional example of an embodiment of the present invention, such as Figure 4a As shown, the method for protecting control flow integrity may specifically include:

[0134] S410, during the offline stage of the embedded system program, the program to be executed is preprocessed to obtain a program disassembled file; the preprocessing includes compiling and linking the program code, as well as disassembling the executable file;

[0135] S420, perform static analysis on the disassembled file described in S410, extract key direct jump instructions and branch jump instructions, infer the jump addresses of the instructions, collect node information and edge information, and establish the control flow graph of the program; the node information is the address of the corresponding jump instruction; the edge information is the potential jump address of the corresponding jump instruction.

[0136] S430, the control flow graph described in S420 is analyzed to determine the number of nodes, the maximum number of parent nodes, and the maximum number of child nodes. The size of the control flow integrity label is determined, and the label value of the root node and the label allocation algorithm are set to assign a label to each node in the control flow graph. The label allocation algorithm is to randomly generate the control flow labels of the child nodes based on the control flow integrity labels of the parent nodes, ensuring that the Hamming distance between the label values ​​of the parent nodes and the child nodes is the expected set value, and that the control flow integrity labels of all nodes are unique.

[0137] S440: Perform dynamic analysis on the disassembled file described in S410, extract key indirect jump instructions, inject designed random samples at the indirect jump instructions using an instrumentation tool, extract the set of indirect jump addresses, and map the set into a bitmap according to the designed bitmap mapping algorithm; the bitmap mapping algorithm is to traverse all instruction addresses of the program, mark the indirect jump addresses among them, and map them to a point on the bitmap. The value of a point on the bitmap is a preset value, and the address corresponding to that point is a certain indirect jump address;

[0138] S450, the control flow integrity tag described in S430 and the bitmap shown in S440 are stored in the control flow integrity parameter memory inside the embedded system chip in a secure loading manner; the secure loading method is to store the control flow integrity tag and bitmap into the designated memory through a designed secure interface under system authorization.

[0139] S460: When the embedded system executes a program, the type of the currently executed instruction is identified. For direct jump instructions and branch jump instructions, the corresponding control flow integrity tag is extracted from the control flow integrity parameter memory mentioned in S450, and the Hamming distance between the tag values ​​of the current jump instruction and the next jump instruction is checked to see if it is the expected set value. For indirect jump instructions, the corresponding bitmap is extracted from the control flow integrity parameter memory mentioned in S450, and the value of the corresponding point on the bitmap at the jump address of the current instruction is checked to see if it is the preset value. If the check result is negative, it is considered that the current program control flow has been tampered with.

[0140] S470 is designed with a hardware-based fast program recovery mechanism. After S460 completes the verification of the executed program, if no control flow is found to have been tampered with, critical instructions and data are backed up at the hardware backup point in the embedded system chip register. If the control flow is found to have been tampered with, the fast control flow recovery mechanism is activated, and the system enters the recovery state, replacing the current data with the backed-up data.

[0141] The specific preprocessing operations described in S410 are as follows:

[0142] The program code is a code file written in high-level languages ​​such as C / C++, JAVA, and Python; the executable file refers to the .elf format file generated after the program code is compiled and linked by the GCC compiler, which can be loaded and executed by the embedded system chip; the disassembly operation refers to translating the executable file into a txt format disassembly file containing assembly instructions, hexadecimal instruction codes, and instruction addresses using the objdump command.

[0143] The specific operations of the static analysis described in S420 are as follows: Figure 4c As shown:

[0144] S421. Analyze the program disassembly file described in S410, determine the instruction type based on the opcode of the assembly instructions, and extract the key direct jump instructions and branch jump instructions.

[0145] S422. Based on the instruction type and its instruction address, deduce the jump address: For a direct jump instruction, there is only one possible jump address, which is the immediate value of the instruction plus the current instruction address; for a branch jump instruction, there are two possible jump addresses. If the branch condition is met, a jump occurs, and the jump address of the instruction is its immediate value plus its instruction address. If the branch condition is not met, no jump occurs, and the jump address of the instruction is the current address plus hexadecimal 4 (0x4), which is the address of the next instruction.

[0146] S423. The control flow graph mentioned above represents all paths traversed during program execution, that is, it represents the possible flow of all executed instructions in the form of a graph. Its formula is:

[0147] ;

[0148] Control Flow Graph Includes node set Edge set Root node (i.e.) (entry node) , export node The node information is the address of the jump instruction corresponding to the node; the edge information is the possible jump address of the jump instruction corresponding to the node. Therefore, the node corresponding to the direct jump instruction in the control flow graph has only one edge, while the node corresponding to the branch jump instruction has two edges.

[0149] like Figure 4c The control flow graph example shown is... There are only 5 nodes. Nodes 1 and 2 each have two possible jump addresses, indicating that the jump instruction type corresponding to these two nodes should be a branch jump instruction, so they have two edges. Nodes 3 and 4 each have only one possible jump address, indicating that the jump instruction type corresponding to these two nodes should be a direct jump instruction, so they have only one edge. Node 5 has no possible jump addresses, indicating that the jump instruction type corresponding to this node should be an indirect jump instruction, because the indirect jump address cannot be inferred through static analysis.

[0150] Node 1 is the root node The possible jump addresses of node 1 are 0x2020 and 0x2030, which are exactly the instruction addresses of nodes 2 and 3. Therefore, node 1 has two edges, one pointing to node 2 and the other to node 3. The possible jump addresses of node 2 are also 0x2020 and 0x2030, so node 2 has one edge pointing to itself and the other pointing to node 3. The possible jump address of node 3 is 0x159b4, which is the instruction address of node 4. Therefore, the edge of node 3 points to node 4. Similarly, the possible jump address of node 4 is 0xc518, which is the instruction address of node 5. The edge of node 4 points to node 5. Node 5 has no possible jump addresses, so it is the exit node of this CFG. .

[0151] Should Number of nodes 5. Maximum number of parent nodes 1. Maximum number of child nodes The value is 2. Therefore, according to the formula, the result is... Control flow integrity tags Size The value is 3. Assume... of The value is 000, representing the Hamming distance between parent and child nodes. Given a value of 1, based on the control flow integrity label design algorithm, nodes 2 and 3... For 001 and 100, node 4 For 110, node 5 The value is 111. During program execution, it is only necessary to check the currently executing direct jump instruction or branch jump instruction. , and the next jump instruction Between Whether it is the expected set value can quickly and accurately determine whether the current program control flow conforms to the settings. Jump rules, i.e. whether the current program control flow has been tampered with by an attacker.

[0152] The specific operation of the control flow integrity label described in S430 is as follows:

[0153] S431. Analyze the control flow graph described in S420 to obtain the number of nodes in the graph. Maximum number of parent nodes Maximum number of child nodes Calculate the control flow integrity label of the control flow graph. Size The formula is shown below:

[0154] ;

[0155] in, Indicates base 2, The logarithm of the integer part;

[0156] S432, Root Node of It can be Any binary number of any size;

[0157] S433, The label allocation algorithm is as follows: First, according to of Randomly generate its child nodes Guarantee the parent-child nodes The Hamming distance between them is the expected set value; the magnitude of this expected set value is 1 to... Any positive integer between, express Divide by 2 and take the integer part of the quotient; then iterate through the quotients. All nodes in the array are assigned a unique assignment to each node. ;

[0158] S434, Hamming Distance The calculation formula is as follows:

[0159] ;

[0160] in, For two sizes The binary number of bits; Representing binary numbers The Bit; Representing binary numbers The Bit; This represents the XOR operation.

[0161] The specific operations of the dynamic analysis described in S440 are as follows: Figure 4d As shown:

[0162] S441. Analyze the disassembled program file described in S410, and extract the key indirect jump instructions based on the opcodes of the assembly instructions. Since static analysis cannot extract the jump address of the indirect jump instruction, it is necessary to use various instrumentation tools to generate a test case set, insert instrumentation at the indirect jump instruction, and use the test case set as input to collect a set of possible indirect jump addresses.

[0163] S442. The instrumentation tool is Pin, which can instrument each indirect jump instruction and record the set of indirect jump addresses during dynamic analysis.

[0164] S443. There are two methods for generating the test case set: one is dynamic symbolic execution test case set. One approach offers high path coverage but is slow; the other is based on a set of fuzzy test cases generated by a fuzzing tool. It's fast, but it can't cover part of the path; the union of these two is shown in the following formula:

[0165] ;

[0166] Obtain the required set of test cases To minimize the omission of possible indirect jump addresses;

[0167] S444, The bitmap mapping algorithm is as follows:

[0168] First, based on the program disassembled file described in S410, extract the addresses of all instructions and mark all indirect jump addresses, i.e., use a one-dimensional array. The formula for representing the addresses of all program instructions is shown below:

[0169] ;

[0170] if If it is an indirect jump address, then It is the preset value, otherwise Values ​​other than the preset values;

[0171] Secondly, the one-dimensional array Mapping to a bitmap allows you to use a two-dimensional array. To indicate, position The value represents 1 bit. The value of , i.e., a point on the bitmap, is given by the following formula:

[0172] ;

[0173] ;

[0174] ;

[0175] in, for Divide by The positive integer obtained by rounding down is... for Divide by The remainder;

[0176] like Figure 4d As shown, assume the program has a total of One instruction, If it is 64, then From 0 to integers, express Divide by 64 and then round down. Integers from 0 to 64. In the example of the indirect jump address bitmap, ,because, , This means This means that the address of instruction 127 in the program is an indirect jump address. Based on the formula, it only takes one clock cycle to detect whether the jump address of the current indirect jump instruction is in the pre-extracted set. At the same time, the data size of the bitmap is equivalent to the data size of the original indirect jump address set divided by 64, so the resource overhead is smaller.

[0177] Therefore, the above formula can be used to quickly detect whether the value of a point in a bitmap is a preset value and determine whether the address corresponding to that point is an indirect jump address.

[0178] The specific operation of safe loading described in S450 is as follows: Figure 4e As shown:

[0179] S451, the security interface is the designed TPM (Trusted Platform Module) interface, which uses symmetric cryptographic algorithms such as AES (Advanced Encryption Standard) to ensure the control flow integrity label mentioned in S430 ( The bitmap shown in S440 and the other bitmap are stored in encrypted form at a designated location inside the embedded system chip; this secure interface uses token authorization authentication to prevent unauthorized users from accessing it. Information such as Bitmap;

[0180] S452, the control flow integrity parameter memory is a designed on-chip secure static random access memory (SRAM) during loading. Once information such as Bitmap is obtained, the control flow integrity parameters stored internally cannot be modified. And Bitmap.

[0181] The specific operations for control flow integrity monitoring described in S460 are as follows: Figure 4f As shown:

[0182] S461. Within the embedded system chip, key signals at the chip pipeline's decoding level, including instruction decoding signals, PC (Program Counter) signals, and key register signals (such as the instruction register IR signal), can be used to determine whether the jump instructions and jump addresses have been tampered with during program execution.

[0183] S462. Based on the opcode of the instruction decoding signal, identify the type of the currently executed instruction. For direct jump instructions and branch jump instructions, access the control flow integrity parameter memory mentioned in S450 and retrieve the corresponding parameter of the currently executed jump instruction. Check the jump instruction against the next jump instruction to be executed. Hamming distance between If the test result is negative, it is considered that the program control flow has been tampered with.

[0184] S463. For indirect jump instructions, extract the jump address of the instruction, access the control flow integrity parameter memory described in S450, extract the corresponding Bitmap, and check whether the value of the corresponding point on the Bitmap is 1. If it is not 1, it is considered that the program control flow has been tampered with.

[0185] The hardware-based fast program recovery mechanism described in S470 operates as follows:

[0186] S471. After S460 completes the integrity check of the current control flow, if no tampering attack is detected, critical instructions and data will be backed up at the hardware backup point in the embedded system chip register; the hardware backup point is also the designed secure SRAM.

[0187] S472. If S460 detects a tampering attack, it will stop the current pipeline operation of the embedded system chip, enter the recovery state, and replace the value of the current embedded system chip register with the key data stored in the hardware backup point to achieve rapid program recovery, that is, re-execute the program from the backup state.

[0188] The technical solution of this invention firstly involves preprocessing the program to be executed during the offline stage of the embedded system program to obtain a program disassembly file. This avoids the heavy parsing task at runtime, significantly reducing the computational overhead of the embedded system during execution. Simultaneously, by generating the disassembly file, the underlying instruction sequence can be accurately obtained, providing a complete and reliable input foundation for subsequent dynamic and static analysis, ensuring the accuracy and completeness of control flow modeling. Next, dynamic and static analysis is performed on the disassembly file, extracting direct jump instructions, branch jump instructions, and indirect jump instructions respectively. For direct jump instructions and branch jump instructions, corresponding control flow graphs are established, and labels are assigned to each node in the control flow graph according to a preset distance. For indirect jump instructions, an indirect jump address set is extracted and mapped to a bitmap. Combining the comprehensiveness of static disassembly with the context sensitivity of dynamic execution path deduction, key jump instructions can be more accurately distinguished and identified. The system performs fine-grained classification by type conversion, laying the foundation for subsequent implementation of differentiated protection strategies, improving the flexibility and targeting of the overall control flow integrity mechanism, and enhancing its adaptability to complex program structures. Next, during program execution, the instruction type of the currently executed instruction is identified, and the instruction is verified based on the control flow integrity label and bitmap. Verification strategies are dynamically selected according to the instruction type, taking into account the semantic features and security requirements of different jump types, thus achieving a fine-grained verification mechanism at runtime. Finally, if the control flow has not been tampered with, critical instructions and data are backed up at the hardware backup point in the embedded system chip register, providing a reliable basis for possible subsequent recovery operations. If the control flow has been tampered with, a rapid control flow recovery mechanism is activated, replacing the current data with the backed-up data, achieving rapid rollback of the control flow and system self-healing, preventing attack propagation, ensuring the continuity and availability of critical tasks, and greatly improving the resilience of the embedded system against attacks.

[0189] Example 5

[0190] Figure 5 This is a schematic diagram of a control flow integrity protection device provided in Embodiment 5 of the present invention. This device is used to execute the control flow integrity protection method provided in any of the above embodiments. This device and the control flow integrity protection methods of the above embodiments belong to the same inventive concept. Details not described in detail in the embodiments of the control flow integrity protection device can be referred to the embodiments of the control flow integrity protection methods described above. Figure 5 As shown, the device includes: a jump type determination module 510, a first inspection module 520, and a second inspection module 530.

[0191] The jump type determination module 510 is used to identify the jump type of the currently executing instruction in the instruction stream of the target program during the execution of the target program in the embedded system, and to verify the currently executing instruction according to the jump type; the first verification module 520 is used to back up the currently executing instruction and its execution data at a hardware backup point in the register within the embedded system chip if the currently executing instruction successfully passes the verification; the second verification module 530 is used to obtain target backup data from the hardware backup point in the register within the embedded system chip if the currently executing instruction fails the verification, overwrite the current register value with the target backup data, and re-execute the target program from the instruction corresponding to the target backup data.

[0192] The technical solution of this invention embodiment firstly involves the jump type determination module 510 identifying the jump type of the currently executing instruction in the instruction stream of the target program during the execution of the target program in the embedded system, and verifying the currently executing instruction based on the jump type. This targeted verification based on the jump type improves the efficiency and accuracy of security checks. Next, if the currently executing instruction successfully passes the verification, the first verification module 520 backs up the currently executing instruction and its execution data at a hardware backup point in the register within the embedded system chip. Successful verification and data backup ensure the traceability of the legitimate execution state, providing a reliable foundation for subsequent recovery from potential anomalies. Finally, the second verification module... 530 If the currently executed instruction fails the verification, target backup data is obtained from the hardware backup point in the register of the embedded system chip. The target backup data is used to overwrite the current register value, and the target program is re-executed from the instruction corresponding to the target backup data. If the verification fails, the program is precisely rolled back from the hardware backup point and re-executed, avoiding the performance overhead and real-time loss caused by restarting the entire program. This greatly enhances the fault tolerance, robustness, and anti-attack resilience of the embedded system. It can achieve fast and accurate control flow integrity monitoring for different types of jump instructions, and can quickly restore the control flow after detecting an attack on the control flow. While ensuring the high real-time performance and low resource consumption of the embedded system, it achieves comprehensive and efficient protection of control flow integrity.

[0193] Based on the above scheme, optionally, the jump type includes a direct jump instruction; the jump type determination module 510 includes an instruction tag extraction submodule and a tag distance verification submodule. The instruction tag extraction submodule is used to extract the tag of the currently executed instruction and the tag of the next executed instruction from the target memory within the embedded system chip when the jump type is the direct jump instruction; wherein the tag is determined based on the jump relationship between multiple instructions in the instruction stream of the target program and the expected Hamming distance; the tag distance verification submodule is used to determine the actual Hamming distance between the tag of the currently executed instruction and the tag of the next executed instruction; if the actual Hamming distance is the expected Hamming distance, the currently executed instruction is determined to have successfully passed the verification; otherwise, the currently executed instruction is determined to have failed the verification.

[0194] Based on the above scheme, optionally, the jump type determination module 510 further includes a first preprocessing submodule, a control flow graph construction submodule, a node label determination submodule, and a label storage submodule. The first preprocessing submodule is used to preprocess the program code of the target program during the offline stage of the target program in the embedded system chip before extracting the label of the currently executed instruction and the label of the next executed instruction from the target memory within the embedded system chip, to obtain a disassembled file of the target program; wherein the preprocessing includes compiling and linking the program code, and disassembling the executable file; the control flow graph construction submodule is used to construct a control flow graph of the target program based on the disassembled file; wherein the control flow graph consists of multiple nodes and their edges, and the nodes are the instructions of the target program. The control flow graph is defined by a node label determination submodule, which determines the label of each node in the control flow graph based on the control flow graph and preset label constraints. The label constraints include a Hamming distance between the labels of parent and child nodes in the control flow graph that is an expected Hamming distance. A label storage submodule stores the labels in the target memory within the embedded system chip and establishes a mapping relationship between the labels and their corresponding target jump instructions.

[0195] Based on the above scheme, optionally, the node label determination submodule includes a label length determination unit and a node label determination unit. The label length determination unit is used to determine the label length by determining the total number of nodes, the maximum number of parent nodes, and the maximum number of child nodes in the control flow graph. The node label determination unit is used to obtain any binary number representing the label length as the label of the root node in the control flow graph, determine the labels of the root node's child nodes based on the root node's label and the expected Hamming distance of the root node, and, using the child nodes as parent nodes, determine the labels of the parent node's child nodes based on the parent node's label and the expected Hamming distance of the parent node, thereby obtaining the label of each node.

[0196] Based on the above scheme, optionally, the label length determination unit includes a label length determination subunit. The label length determination subunit is used to map the total number of nodes to a target value, and determine the length of the label based on the maximum value among the target value, the maximum number of parent nodes, and the maximum number of child nodes.

[0197] Based on the above scheme, optionally, the jump type includes a branch jump instruction; the jump type determination module 510 includes a bitmap verification submodule. The bitmap verification submodule is used to, when the jump type is the branch jump instruction, extract the bitmap corresponding to the currently executed instruction from the target memory within the embedded system chip, and verify the currently executed instruction according to the bitmap, wherein the value of the corresponding point of the branch jump instruction in the instruction stream of the target program in the bitmap is a preset value.

[0198] Based on the above scheme, optionally, the jump type determination module 510 further includes a second preprocessing submodule, a branch jump address determination submodule, and a bitmap mapping storage submodule. The second preprocessing submodule is used to preprocess the program code of the target program during the offline stage of the target program in the embedded system chip before extracting the bitmap corresponding to the currently executed instruction from the target memory within the embedded system chip, to obtain a disassembled file of the target program; wherein the preprocessing includes compiling and linking the program code, and disassembling the executable file; the branch jump address determination submodule is used to determine the target jump instruction in the instruction stream of the target program based on the disassembled file, instrument the branch jump instruction in the target jump instruction, execute the target program based on a test case set, and determine the jump address of the branch jump instruction based on the instrumented code; the bitmap mapping storage submodule is used to map the jump address of the branch jump instruction to a bitmap and store the bitmap in the target memory within the embedded system chip.

[0199] Based on the above scheme, optionally, the bitmap mapping storage submodule includes a bitmap determination unit. The bitmap determination unit is used to construct a one-dimensional array using the jump address of the branch jump instruction as a first value and the jump address of the target jump instruction in the instruction stream (excluding the branch jump instruction) as a second value, and then map the one-dimensional array to a two-dimensional array to obtain a bitmap.

[0200] Based on the above scheme, optionally, the test case set includes a dynamic symbolic execution test case set and a fuzz test case set generated based on a fuzz testing tool.

[0201] The control flow integrity protection device provided in the embodiments of the present invention can execute the control flow integrity protection method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the method.

[0202] Example 6

[0203] Figure 6 A schematic diagram of an electronic device 10, which can be used to implement embodiments of the present invention, is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0204] like Figure 6 As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12 or a random access memory (RAM) 13, communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the ROM 12 or loaded from storage unit 18 into the RAM 13. The RAM 13 can also store various programs and data required for the operation of the electronic device 10. The processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0205] Multiple components in electronic device 10 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of displays, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0206] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above, such as methods for protecting control flow integrity.

[0207] In some embodiments, the control flow integrity protection method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on electronic device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the control flow integrity protection method described above may be performed. Alternatively, in other embodiments, processor 11 may be configured to perform the control flow integrity protection method by any other suitable means (e.g., by means of firmware).

[0208] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0209] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0210] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0211] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0212] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0213] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0214] In particular, according to embodiments of the present invention, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of the present invention include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via communication unit 19, or installed from storage unit 18, or installed from ROM 12. When the computer program is executed by processor 11, it performs the functions defined in the methods of the embodiments of the present invention.

[0215] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0216] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A method for protecting control flow integrity, characterized in that, include: During the execution of a target program in an embedded system, the jump type of the currently executed instruction in the instruction stream of the target program is identified, and the currently executed instruction is verified based on the jump type. If the currently executed instruction successfully passes the verification, the currently executed instruction and its execution data are backed up at the hardware backup point in the register within the embedded system chip; If the currently executed instruction fails the verification, target backup data is obtained from the hardware backup point in the register of the embedded system chip, the target backup data is used to overwrite the current register value, and the target program is re-executed from the instruction corresponding to the target backup data.

2. The method for protecting control flow integrity according to claim 1, characterized in that, The jump types include direct jump instructions and branch jump instructions; the verification of the currently executing instruction based on the jump type includes: When the jump type is the direct jump instruction or the branch jump instruction, the tag of the currently executed instruction and the tag of the next executed instruction are extracted from the target memory within the embedded system chip; wherein, the tag is determined based on the jump relationship between multiple instructions in the instruction stream of the target program and the expected Hamming distance; Determine the actual Hamming distance between the label of the currently executed instruction and the label of the next executed instruction. If the actual Hamming distance is the expected Hamming distance, the currently executed instruction is determined to have successfully passed the test; otherwise, the currently executed instruction is determined to have failed the test.

3. The method for protecting control flow integrity according to claim 2, characterized in that, Before retrieving the tag of the currently executed instruction and the tag of the next executed instruction from the target memory within the embedded system chip, the method further includes: In the offline stage of the target program in the embedded system, the program code of the target program is preprocessed to obtain the disassembled file of the target program; wherein, the preprocessing includes compiling and linking the program code, as well as disassembling the executable file; A control flow graph of the target program is constructed based on the disassembled file; wherein, the control flow graph consists of multiple nodes and their edges, the nodes are the memory addresses of target jump instructions in the instruction flow of the target program, and the edges are the potential jump addresses of the target jump instructions; the target jump instructions include direct jump instructions and branch jump instructions; The label of each node in the control flow graph is determined according to the control flow graph and the preset label constraints; wherein, the label constraints include the Hamming distance between the labels of the parent node and the child node in the multiple nodes of the control flow graph being the expected Hamming distance; The tag is stored in the target memory within the embedded system chip, and a mapping relationship is established between the tag and its corresponding target jump instruction.

4. The method for protecting control flow integrity according to claim 3, characterized in that, The step of determining the label of each node in the control flow graph based on the control flow graph and preset label constraints includes: The length of the label is determined by determining the total number of nodes, the maximum number of parent nodes, and the maximum number of child nodes of the multiple nodes in the control flow graph. The arbitrary binary number of the length of the label is determined as the label of the root node in the control flow graph, and the labels of the child nodes of the root node are determined according to the label of the root node and the expected Hamming distance of the root node. Using the child node as the parent node, the labels of the child nodes of the parent node are determined based on the label of the parent node and the expected Hamming distance of the parent node, so as to obtain the label of each node.

5. The method for protecting control flow integrity according to claim 4, characterized in that, The process of determining the total number of nodes, the maximum number of parent nodes, and the maximum number of child nodes in the control flow graph to determine the length of the label includes: The total number of nodes is mapped to a target value, and the length of the tag is determined based on the maximum value among the target value, the maximum number of parent nodes, and the maximum number of child nodes.

6. The method for protecting control flow integrity according to claim 1, characterized in that, The jump type includes indirect jump instructions; the verification of the currently executed instruction based on the jump type includes: When the jump type is the indirect jump instruction, the bitmap corresponding to the currently executed instruction is extracted from the target memory within the embedded system chip, and the currently executed instruction is checked according to the bitmap, wherein the value of the corresponding point of the indirect jump instruction in the instruction stream of the target program is a preset value.

7. The method for protecting control flow integrity according to claim 6, characterized in that, Before retrieving the bitmap corresponding to the currently executed instruction from the target memory within the embedded system chip, the method further includes: In the offline stage of the target program in the embedded system, the program code of the target program is preprocessed to obtain the disassembled file of the target program; wherein, the preprocessing includes compiling and linking the program code, as well as disassembling the executable file; Based on the disassembled file, the target jump instruction in the instruction stream of the target program is determined, the indirect jump instruction in the target jump instruction is instrumented, and the target program is executed based on the test case set to determine the jump address of the indirect jump instruction based on the instrumented code; The jump address of the indirect jump instruction is mapped to a bitmap, and the bitmap is stored in the target memory within the embedded system chip.

8. The method for protecting control flow integrity according to claim 7, characterized in that, The step of mapping the jump address of the indirect jump instruction to a bitmap includes: Using the jump address of the indirect jump instruction as the first value and the jump address of the target jump instruction in the instruction stream other than the indirect jump instruction as the second value, a one-dimensional array is constructed, and the one-dimensional array is mapped to a two-dimensional array to obtain a bitmap.

9. The method for protecting control flow integrity according to claim 7, characterized in that, The test case set includes a dynamic symbolic execution test case set and a fuzz test case set generated based on a fuzz testing tool.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the method for protecting control flow integrity as described in any one of claims 1-9.

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