Design method of semiconductor device terminal structure and semiconductor device structure

Abstract

The invention relates to a method for designing a semiconductor device terminal structure, which comprises the following steps of: preparing a semiconductor device which comprises an active region, a terminal region and a drift region; keeping the ring spacing and the ring number of the semiconductor device unchanged, and increasing the ring width of the field limiting ring; distinguishing a fully depleted region and a partially depleted region, and setting the ring spacing of the field limiting rings in the partially depleted region as an progressively increasing arithmetic progression from the inner side to the outer side; and reducing the ring width of the field limiting ring in the partial depletion region to obtain the semiconductor device terminal structure. The field limiting rings are isolated by preferentially depleting the junction termination extension structures below the field limiting rings, a path is provided for transverse extension of depletion layers between the field limiting rings, field limiting ring parameters of partially depleted and fully depleted regions are adjusted in combination with the mesa structure at the edge of the terminal, the curvature effect caused by terminal end junction electric field increase is reduced, and the terminal performance is improved. The electric field uniformity is further improved, and the utilization rate of the blocking voltage is improved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductor power devices, and particularly relates to a design method of a terminal structure of a semiconductor device and a semiconductor device structure. BACKGROUND

[0002] Wide bandgap semiconductors have wider bandgap, higher critical breakdown field and greater electron saturation velocity than other semiconductor materials, so that the power devices made of the wide bandgap semiconductors can withstand higher temperature, have greater breakdown voltage and faster switching speed, and are more suitable for application in the field of high frequency, high voltage and high power. As a third-generation semiconductor, gallium nitride (GaN) has a wider bandgap, higher breakdown field, higher mobility and higher figure of merit (FOM) than silicon carbide (SiC), another third-generation semiconductor, and has greater potential in the field of high frequency, high voltage and fast switching. At present, the commonly used power devices made of GaN material are mainly lateral devices. In comparison, vertical devices can achieve avalanche breakdown while avoiding a series of surface effects because the high electric field is located inside the device rather than on the surface, and the device area is saved, so that the vertical devices have greater current density and greater application potential under the same area.

[0003] For power devices, the upper limit of the withstand voltage capacity is related to the properties of the material itself, doping and epitaxial thickness, but the edge termination structure often determines the actual withstand voltage capacity of the device because the edge curvature effect cannot be avoided. The terminal structures commonly used for other semiconductor materials, such as junction termination extension (JTE) and field limiting ring (FLR), often need to rely on ion implantation or secondary epitaxy and other processes, which are not suitable for the manufacture of GaN devices. For GaN material, magnesium (Mg) is usually selected as the p-type dopant. The activation rate of Mg in GaN is low, and the diffusion coefficient is small, so it is difficult to achieve high doping by ion implantation, and defects caused by high-energy particle implantation cannot be avoided, so the GaN device needs to manufacture the terminal structure directly on a single epitaxial wafer as much as possible. Methods such as mesa and field plate (FP) that do not rely on these processes are often affected by inevitable factors such as deep etching defects and dielectric reliability, which greatly reduce the utilization rate of the blocking voltage of the device terminal structure. In addition, the terminal structure with greater utilization rate of the blocking voltage often has a more complex structure, which requires the introduction of other processes to manufacture the terminal structure, which does not meet the requirements in actual production.

[0004] In power devices, the area occupied by the terminal has always been a problem of concern, which directly affects the yield of the chip. Since the existing terminal structure is mostly a lateral structure and located outside the terminal, it inevitably occupies a large area in the device, usually more than 20%, and in most cases, the more the utilization rate of the blocking voltage, the more the area occupied due to the complexity of the structure.

[0005] As Figure 1 A structure diagram presented in a design method of a semiconductor device field limiting ring terminal structure in the prior art is shown, and the electric field distribution diagram can be seen from Figure 2 It can be seen that the electric field at the edge is much larger than the theoretical value, which greatly reduces the breakdown voltage of the power device.

[0006] Therefore, a design method is needed that effectively improves the terminal blocking voltage utilization rate, is more suitable for existing processes, can be manufactured on the basis of one epitaxy, does not introduce other processes on the basis of existing processes, and reduces the terminal area.

[0007] It should be noted that the above introduction to the technical background is only to facilitate a clear and complete description of the technical solutions of the present application, and to facilitate the understanding of those skilled in the art, and the above technical solutions cannot be considered as known to those skilled in the art merely because they are described in the background section of the present application. SUMMARY

[0008] The purpose of the present application is to provide a design method of a semiconductor device terminal structure and a semiconductor device structure, which is used to solve the technical problems mentioned in the background.

[0009] The technical solution adopted by the present application to solve its technical problems is to provide a design method of a semiconductor device terminal structure, comprising the following steps:

[0010] Step 1, preparing a semiconductor device, the main structure of the semiconductor device comprising an active region, a terminal region and a drift region, the active region being located at the central position, the terminal region surrounding the active region, the drift region being located below the active region and the terminal region, wherein the terminal region comprises a field limiting ring structure and a junction terminal extension structure, the junction terminal extension structure being located below the field limiting ring structure, the active region and the drift region forming a main junction, the field limiting ring structure and the junction terminal extension structure forming a field limiting ring junction, the junction terminal extension structure and the drift region forming a junction terminal extension junction, then setting the ring spacing of the field limiting ring structure in the initial state as the initial ring spacing, the ring width as the initial ring width, the ring number as the initial ring number, and the thickness of the junction terminal extension structure as the initial junction terminal extension thickness;

[0011] Step 2, keeping the values of the initial ring spacing and the initial ring number unchanged, increasing the current ring width of the field limiting ring to a rate at which the blocking voltage of the semiconductor device structure increases with the increase of the ring width is less than or equal to a preset rate;

[0012] Step 3, dividing the field limiting ring into a fully depleted region close to the active region and a partially depleted region away from the active region, wherein the outermost ring of the field limiting ring in the partially depleted region is called the final ring, setting the ring spacing of the field limiting ring in the partially depleted region from the inside to the outside as an increasing arithmetic sequence, and gradually adjusting the tolerance of the increasing arithmetic sequence to the main junction below the active region. The junction termination extension field is equal to or the difference is minimum.

[0013] Step 4, reducing the ring width of the field limiting ring in the partially depleted region to the minimum process size to obtain a semiconductor device terminal structure with a field limiting ring terminal combined with a junction termination extension, wherein in step 3, the field limiting ring is divided into a fully depleted region and a partially depleted region according to whether the drift region below it is fully depleted.

[0014] In step 1, the sum of the field limiting ring junction thickness of the field limiting ring and the junction termination extension thickness is equal to the main junction depth of the active region.

[0015] After performing step 1, the critical breakdown field E of the semiconductor device structure and the PN junction inner radius r p are substituted into the first equation: The final ring depletion layer extension width r is calculated, wherein the PN junction inner radius r p is the curvature radius at the PN junction corner of the semiconductor device structure, q is the charge amount of the elementary charge, N D is the ion concentration of N-type doping, and ε is the relative dielectric constant of the material between the field limiting rings; the critical breakdown field E of the semiconductor device structure and the ion concentration N A of P-type doping are substituted into the second equation: The P region maximum depletion width t p is calculated; according to the critical breakdown field E of the semiconductor device structure, the transverse electric field and the longitudinal electric field are the vector sum, the first relationship of the ring spacing s of the field limiting ring and the ring number n of the field limiting ring is calculated; the ring number n of the field limiting ring is substituted into the first relationship with different theoretical ring spacings greater than or equal to the minimum process size and less than the final ring depletion layer extension width r to obtain the corresponding different theoretical ring number; the theoretical junction termination extension thickness t p is less than the P region maximum depletion width t X ; the transverse electric field E X, PN junction inner diameter r p , the last ring depletion layer extension width r, the ring spacing s of the field limiting ring corresponding to different theoretical ring spacing, the junction terminal extension thickness t and the ring number n corresponding to different theoretical ring number are substituted into the fourth equation: Calculate the blocking voltage V corresponding to different blocking voltages, and the ring spacing corresponding to the maximum blocking voltage is the first theoretical optimal ring spacing, the junction terminal extension thickness corresponding to the maximum blocking voltage is the first theoretical optimal junction terminal extension thickness, and the blocking voltage of the semiconductor device structure at this time is the first blocking voltage.

[0016] Increase or decrease the junction terminal extension thickness to obtain a new blocking voltage V, and the junction terminal extension thickness corresponding to the maximum blocking voltage is selected as the first optimal junction terminal extension thickness; set the ring spacing of the field limiting ring to the theoretical ring spacing, and increase or decrease the theoretical ring number corresponding to the field limiting ring to the junction terminal extension junction electric field below the main junction of the active region and the junction terminal extension junction electric field below the last ring are equal or the difference is minimum, and the ring number of the field limiting ring at this time is the optimal ring number; set the ring spacing s to be different theoretical ring spacing, and the ring number n to be corresponding to different optimal ring number, to obtain a new blocking voltage V, and the ring spacing corresponding to the maximum blocking voltage is selected as the first optimal ring spacing. The ring number corresponding to the maximum blocking voltage is the first optimal ring number, the junction terminal extension thickness is the first optimal junction terminal extension thickness, the ring spacing is the first optimal ring spacing, the ring number is the first optimal ring number, and the above optimal data is substituted into the initial data to continue the step 2.

[0017] In the step 3, the ring spacing of the field limiting ring in the partial depletion region is set to a preset increasing arithmetic sequence from the inside to the outside, and the tolerance of the increasing arithmetic sequence is adjusted until the junction terminal extension junction electric field below the main junction of the active region and the junction terminal extension junction electric field below the last ring are equal or the difference is minimum; adjust the number of field limiting rings with ring spacing set according to the increasing arithmetic sequence, so that the field limiting rings with ring spacing set according to the increasing arithmetic sequence include part of the field limiting rings near the partial depletion region in the partial depletion region and / or do not include part of the field limiting rings near the quasi full depletion region in the partial depletion region, until the junction terminal extension junction electric field below the main junction of the active region and the junction terminal extension junction electric field below the last ring are equal or the difference is minimum. At this time, the field limiting rings with ring spacing set according to the increasing arithmetic sequence belong to the partial depletion region, and the field limiting rings with ring spacing set according to the equal spacing belong to the full depletion region.

[0018] Step 4 further comprises step 4.1: according to the full depletion region and the partial depletion region obtained in step 3, reducing the ring width of the field limiting ring in the partial depletion region to a minimum process size; adjusting the field limiting ring with the reduced ring width to the minimum process size so that the field limiting ring with the reduced ring width to the minimum process size comprises a partial field limiting ring close to the partial depletion region in the full depletion region and / or does not comprise a partial field limiting ring close to the full depletion region in the partial depletion region, until the junction termination extension junction electric field under the main junction of the active region is equal to or has the minimum difference from the junction termination extension junction electric field under the end ring, at which time the field limiting ring with the reduced ring width to the minimum process size belongs to the field limiting ring of the newly divided partial depletion region, and the field limiting ring with the ring width not reduced to the minimum process size belongs to the field limiting ring of the newly divided full depletion region.

[0019] After step 4.1, step 4.2 is performed: keeping the number of rings and the ring spacing of the field limiting ring of the newly divided full depletion region unchanged, and increasing the ring width of the field limiting ring in the newly divided full depletion region until the rate of increase of the blocking voltage of the semiconductor device terminal structure with the increase of the ring width is less than or equal to a preset rate.

[0020] To solve the above technical problems, the application further provides a semiconductor device structure, which is a longitudinal structure and comprises an active region, a terminal region and a drift region, the active region is located at a central position, the terminal region surrounds the active region, and the drift region is located below the active region and the terminal region, the terminal region comprises a field limiting ring structure and a junction termination extension structure, and the junction termination extension structure is located below the field limiting ring structure, wherein the active region and the drift region form a main junction, the field limiting ring structure and the junction termination extension structure form a field limiting ring junction, and the junction termination extension structure and the drift region form a junction termination extension junction, and the ring spacing, the ring width, the number of rings of the field limiting ring and the thickness of the junction termination extension structure in the semiconductor device structure are designed by using the semiconductor device terminal structure design method as described above.

[0021] The semiconductor device structure is used for a PN junction diode or a trench gate metal-oxide-semiconductor field effect transistor.

[0022] The beneficial effect is that: the application isolates the field limiting ring by the junction terminal expansion structure, and provides a path for the lateral expansion of the depletion layer, and increases the terminal end junction electric field by adjusting the field limiting ring parameters to improve the electric field uniformity, and then adjusts the field limiting ring parameters of the partial depletion and full depletion regions respectively, and combines the mesa structure of the terminal edge, to reduce the curvature effect caused by the increase of the terminal end junction electric field, further improve the electric field uniformity, improve the utilization rate of blocking voltage, and the vertically distributed terminal structure can also greatly reduce the terminal area. The semiconductor device structure designed according to the method can be used for a PN junction diode or a trench gate metal-oxide-semiconductor field effect tube, and the breakdown risk of the power device is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 The structure schematic diagram presented in the design method of the semiconductor device field limiting ring terminal structure in the prior art is shown.

[0024] Figure 2 The semiconductor device structure electric field distribution schematic diagram obtained by the design method of the semiconductor device field limiting ring terminal structure in the prior art is shown.

[0025] Figure 3 The structure schematic diagram presented in the design method of the semiconductor device terminal structure with the field limiting ring terminal combined with the junction terminal expansion in the application is shown.

[0026] Figure 4 The semiconductor device structure electric field distribution schematic diagram obtained by the design method of the semiconductor device terminal structure with the field limiting ring terminal combined with the junction terminal expansion in the application is shown.

[0027] Figure 5 The structure schematic diagram of the longitudinal PN junction diode obtained by the design method of the semiconductor device terminal structure with the field limiting ring terminal combined with the junction terminal expansion in the application is shown.

[0028] Figure 6 The longitudinal PN junction diode electric field distribution schematic diagram obtained by the design method of the semiconductor device terminal structure with the field limiting ring terminal combined with the junction terminal expansion in the application is shown.

[0029] Figure 7 The structure schematic diagram of the longitudinal trench gate metal-oxide-semiconductor field effect tube obtained by the design method of the semiconductor device terminal structure with the field limiting ring terminal combined with the junction terminal expansion in the application is shown.

[0030] Figure 8 The longitudinal trench gate metal-oxide-semiconductor field effect tube electric field distribution schematic diagram obtained by the design method of the semiconductor device terminal structure with the field limiting ring terminal combined with the junction terminal expansion in the application is shown.

[0031] Wherein, 1-active region; 2-terminal region; 21-field limiting ring structure; 22-junction terminal extension structure; 23-full depletion region; 24-partial depletion region; 3-depletion layer profile; 4-drift region; 5-substrate; 61-cathode electrode; 62-anode electrode; 63-source electrode; 64-gate electrode; 65-drain electrode.

[0032] The same reference signs in different figures represent the same component. DETAILED DESCRIPTION

[0033] The application will be further described below in connection with specific embodiments. It should be understood that these embodiments are only used to illustrate the application and not used to limit the scope of the application. Furthermore, it should be understood that after reading the content of the application, those skilled in the art can make various modifications or changes to the application, and these equivalent forms also fall within the scope of the appended claims.

[0034] Example 1:

[0035] The application provides a design method of a semiconductor device terminal structure, comprising the following steps:

[0036] Step 1, preparing a semiconductor device, the main structure of the semiconductor device comprising an active region, a terminal region and a drift region, the active region being arranged inside the device, the terminal region surrounding the active region, and the drift region being arranged below the active region and the terminal region, wherein the terminal region comprises a field limiting ring structure and a junction terminal extension structure, the junction terminal extension structure being arranged below the field limiting ring structure, a main junction being formed between the active region and the drift region, a field limiting ring junction being formed between the field limiting ring structure and the junction terminal extension structure, and a junction terminal extension junction being formed between the junction terminal extension structure and the drift region, and then setting the ring spacing of the field limiting ring structure in the initial state as an initial ring spacing, the ring width as an initial ring width, and the ring number as an initial ring number, and the thickness of the junction terminal extension structure as an initial junction terminal extension thickness;

[0037] Step 2, keeping the values of the initial ring spacing and the initial ring number unchanged, and increasing the current ring width of the field limiting ring to a rate at which the blocking voltage of the semiconductor device structure increases with the increase of the ring width being less than or equal to a preset rate;

[0038] Step 3, dividing the field limiting ring into a full depletion region close to the active region and a partial depletion region away from the active region, wherein the field limiting ring of the outermost ring in the partial depletion region is referred to as the last ring, setting the ring spacing of the field limiting ring in the partial depletion region from the inside to the outside as an increasing arithmetic sequence, and gradually adjusting the tolerance of the increasing arithmetic sequence to the condition that the junction terminal extension electric field below the main junction of the active region is equal to or has the minimum difference with the junction terminal extension junction electric field below the last ring.

[0039] Step 4, reducing the ring width of the field limiting ring in the partially depleted region to the minimum process size, obtaining a semiconductor device terminal structure with a field limiting ring terminal combined with a junction termination extension, wherein, in step 3, the field limiting ring is divided into a fully depleted region and a partially depleted region according to whether the drift region thereunder is fully depleted.

[0040] The design method of the semiconductor device terminal structure of the present application will be described in detail below with reference to the accompanying drawings, and it should be noted that the above sequence does not strictly represent the sequence of the design method of the semiconductor device terminal structure protected by the present application, and those skilled in the art can change it according to the actual preparation steps.

[0041] First, step 1 is performed to prepare a semiconductor device, the main structure of which includes an active region 1, a terminal region 2, and a drift region 4, the active region is located inside the device, the terminal region surrounds the active region 1, and the drift region 4 is located below the active region 1 and the terminal region, wherein the terminal region includes a field limiting ring structure 21 and a junction termination extension structure 22, the junction termination extension structure 22 is located below the field limiting ring structure 21, a main junction is formed between the active region 1 and the drift region 4, a field limiting ring junction is formed between the field limiting ring structure 21 and the junction termination extension structure 22, and a junction termination extension junction is formed between the junction termination extension structure 22 and the drift region 4, and then the ring spacing of the field limiting ring structure 21 in the initial state is set as the initial ring spacing, the ring width is set as the initial ring width, the number of rings is set as the initial number of rings, and the thickness of the junction termination extension structure is set as the initial junction termination extension thickness;

[0042] In one embodiment, in step 1, the sum of the field limiting ring junction thickness of the field limiting ring 21 and the junction termination extension thickness is equal to the main junction depth of the active region.

[0043] In one embodiment, the maximum lateral extension width of the depletion layer is measured, and the ring spacing in the design method is set to be less than the maximum lateral extension width.

[0044] After performing step 1, the critical breakdown electric field E of the semiconductor device structure and the PN junction inner radius r p Substitute the first equation: Calculate the depletion layer extension width r of the last ring, wherein the PN junction inner radius r p is the radius of curvature at the PN junction corner of the semiconductor device structure, q is the charge amount of the elementary charge, N D is the ion concentration of N-type doping, and ε is the relative dielectric constant of the material between the field limiting rings; the critical breakdown electric field E of the semiconductor device structure and the ion concentration N A Substitute the second equation: calculating the maximum depletion width t of the P region p ; the critical breakdown field E of the semiconductor device structure is a vector sum of a lateral electric field and a longitudinal electric field ; a first relationship between the ring spacing s of the field limiting ring and the number n of the field limiting ring is calculated; the number n of the field limiting ring corresponding to different theoretical numbers is obtained by substituting the ring spacing s and the junction terminal extension thickness t into the first relationship, the theoretical ring spacing being greater than or equal to the minimum process size and less than the final ring depletion layer extension width r, and the theoretical junction terminal extension thickness being less than the maximum depletion width t of the P region p ; the lateral electric field E X , the inner diameter r of the PN junction p , the final ring depletion layer extension width r, the ring spacing s of the field limiting ring with different theoretical ring spacing, the junction terminal extension thickness t, and the number n of the field limiting ring corresponding to different theoretical number of rings are substituted into the fourth equation: corresponding to different blocking voltages V, the ring spacing corresponding to the maximum blocking voltage is the first theoretical optimal ring spacing, the junction terminal extension thickness corresponding to the maximum blocking voltage is the first theoretical optimal junction terminal extension thickness, and the blocking voltage of the semiconductor device structure at this time is the first blocking voltage.

[0045] Specifically, the lateral electric field is an electric field parallel to the direction of the upper surface of the active region, and the longitudinal electric field is an electric field perpendicular to the direction of the upper surface of the active region.

[0046] Specifically, the ring spacing substituted into the first equation needs to be greater than or equal to the minimum process size and less than the final ring depletion layer extension width r, and in actual operation, the subsequent ring spacing is selected according to the transformation trend of the blocking voltage obtained by substitution until the maximum blocking voltage is obtained.

[0047] Specifically, the minimum process size refers to the minimum ring spacing processing size that can be achieved by the existing process.

[0048] Specifically, the inner diameter of the PN junction refers to the radius of curvature at the PN junction corner realized by the actual process.

[0049] Increase or decrease the junction terminal extension thickness to obtain a new blocking voltage V, and select the maximum blocking voltage corresponding to the junction terminal extension thickness as the first optimal junction terminal extension thickness; set the ring spacing of the field limiting ring as the theoretical ring spacing, and increase or decrease the theoretical ring number corresponding to the field limiting ring to the junction terminal extension junction field under the main junction of the active region and the junction terminal extension junction field under the last ring being equal or the difference being minimum, to obtain the ring number of the field limiting ring at this time as the optimal ring number; set the ring spacing s as different theoretical ring spacings, and the ring number n as corresponding to different optimal ring numbers, to obtain a new blocking voltage V, and select the maximum blocking voltage corresponding to the ring spacing as the first optimal ring spacing, and the ring number corresponding to the maximum blocking voltage as the first optimal ring number, and use the junction terminal extension thickness as the first optimal junction terminal extension thickness, the ring spacing as the first optimal ring spacing, and the ring number as the first optimal ring number, and continue to perform the step 2 by using the above optimal data as the initial data.

[0050] Specifically, the main junction field, the last ring junction field and the blocking voltage V can be obtained by a simulation model calculation or an actual device measurement method.

[0051] After obtaining the first relationship between the ring spacing and the ring number through theoretical calculation, the theoretical ring number corresponding to the theoretical ring spacing is obtained by using the first relationship, and then the ring number is adjusted to calculate the blocking voltage based on the theoretical ring number, and finally the actual maximum blocking voltage is obtained, which avoids the deviation of the calculated and actual fields, so that the actual obtained scheme is not the optimal scheme, and further improves the achievable blocking voltage.

[0052] Then, step 2 is performed, the ring spacing and the ring number of the field limiting ring 21 are kept unchanged, and the ring width of the field limiting ring 21 is increased until the rate at which the blocking voltage of the semiconductor device structure increases with the increase of the ring width is less than or equal to a preset rate.

[0053] Specifically, the initial value of the preset rate in step 2 is determined according to the actual experience to judge whether the increase rate of the blocking voltage significantly slows down, that is, the value at which the blocking voltage no longer increases with the increase of the current ring width.

[0054] Then, step 3 is performed, the field limiting ring is divided into a full depletion region 23 close to the active region and a partial depletion region 24 away from the active region, wherein the field limiting ring of the outermost ring in the partial depletion region 22 is referred to as the last ring, the ring spacing of the field limiting ring 2 in the partial depletion region 22 is set as an increasing arithmetic sequence from the inside to the outside, and the tolerance of the increasing arithmetic sequence is gradually adjusted until the junction terminal extension field under the main junction of the active region and the junction terminal extension field under the last ring are equal or the difference is minimum.

[0055] In one embodiment, the method of dividing the full depletion region 23 and the non-full depletion region 24 in step 3 is: first, dividing the field limiting ring 2 into a quasi-full depletion region 23 and a quasi-non-full depletion region 24 according to whether the drift region 4 below it is fully depleted.

[0056] In step 3, the ring spacing of the field limiting ring 21 in the partial depletion region 24 is set to a preset increasing arithmetic sequence from the inside to the outside, the tolerance of the increasing arithmetic sequence is adjusted until the junction termination extension junction field below the main junction of the active region 1 is equal to or has the minimum difference with the junction termination extension junction 22 below the last ring; the number of field limiting rings 21 with ring spacing set according to the increasing arithmetic sequence is adjusted so that the field limiting rings 21 with ring spacing set according to the increasing arithmetic sequence include the partial field limiting rings 21 near the partial depletion region 34 in the quasi-full depletion region 23 and / or do not include the partial field limiting rings 21 near the quasi-full depletion region 23 in the partial depletion region, until the junction termination extension junction 22 below the main junction of the active region 1 is equal to or has the minimum difference with the junction termination extension junction 22 below the last ring, at this time, the field limiting rings 21 with ring spacing set according to the increasing arithmetic sequence belong to the partial depletion region 24, and the field limiting rings 21 with equal ring spacing still belong to the full depletion region 23.

[0057] The present application adjusts the ring spacing near the depletion line, so that the adjustment of the ring spacing actually reflects the change of the depletion line, thereby avoiding a large deviation between the theoretical depletion line and the actual depletion line due to the change of the depletion line during the adjustment, improving the accuracy of the position of the actual curvature effect reduction, and maximizing the electric field uniformity and the utilization rate of the blocking voltage.

[0058] Specifically, the "partial field limiting ring 21" contained herein is determined according to the subsequent adjustment "until the main junction field of the active region 1 is equal to or has the minimum difference with the last ring junction field", and cannot be determined in advance before the adjustment.

[0059] Finally, step 4 is performed, the ring width of the field limiting ring 21 in the partial depletion region 24 is reduced to the minimum process size, and a semiconductor device terminal structure with a field limiting ring terminal combined with a junction termination extension is obtained, wherein in step 3, the field limiting ring is divided into a full depletion region 23 and a partial depletion region 24 according to whether the drift region 4 below it is fully depleted.

[0060] Step 4 further comprises step 4.1: according to the full depletion region 23 and the partial depletion region 24 obtained by step 3, reducing the ring width of the field limiting ring 21 in the partial depletion region 24 to a minimum process size; adjusting the field limiting ring with the reduced ring width to the minimum process size, so that the field limiting ring 21 with the reduced ring width to the minimum process size includes a part of the field limiting ring 21 near the partial depletion region 24 in the full depletion region 23 and / or does not include a part of the field limiting ring 21 near the full depletion region 23 in the partial depletion region 24, so that the electric field of the junction termination extension junction 222 under the main junction of the active region 21 is equal to or has the minimum difference with the electric field of the junction termination extension junction 22 under the last ring, and at this time, the field limiting ring with the reduced ring width to the minimum process size belongs to the field limiting ring of the newly divided partial depletion region, and the field limiting ring 21 with the ring width not reduced to the minimum process size belongs to the field limiting ring 21 of the newly divided full depletion region 23.

[0061] After step 4.1, step 4.2 is performed: keeping the number of rings and the ring spacing of the field limiting ring 21 of the newly divided full depletion region 23, and increasing the ring width of the field limiting ring 21 in the newly divided full depletion region 23, so that the increase rate of the blocking voltage of the semiconductor device termination structure with the increase of the ring width is less than or equal to a preset rate.

[0062] The present application further uniformly distributes the electric field by setting the ring width in the full depletion region 23 near the newly divided depletion line.

[0063] Specifically, the preset rate in step 4.2 is determined according to the actual experience to judge whether the increase rate of the blocking voltage is significantly slowed down.

[0064] In one embodiment, steps 3 to 4 are repeatedly performed for a preset number of times.

[0065] The present application adjusts the parameters of the field limiting ring 21 near the depletion line for multiple times, so that the parameters of the field limiting ring 2 near the depletion layer edge can be more accurately adjusted, the electric field uniformity is further improved, and the blocking voltage is improved.

[0066] In one embodiment, the number of rings of the field limiting ring 21 is increased or decreased, and steps 3 to 4 are repeatedly performed.

[0067] The present application verifies the actual optimal value of the number of rings by adjusting the number of rings of the field limiting ring 21 as a whole, so as to ensure that the obtained number of rings can obtain the maximum blocking voltage.

[0068] To solve the above technical problems, the present application further provides a semiconductor device structure, as shown in Figure 3As shown, the semiconductor device structure is a longitudinal structure, including an active region, a terminal region and a drift region, the active region is located inside the device, the terminal region surrounds the active region, and the drift region is located below the active region and the terminal region, the terminal region includes a field limiting ring structure and a junction terminal extension structure, and the junction terminal extension structure is located below the field limiting ring structure, wherein a main junction is formed between the active region and the drift region, a field limiting ring junction is formed between the field limiting ring structure and the junction terminal extension structure, and a junction terminal extension junction is formed between the junction terminal extension structure and the drift region, and the ring spacing, ring width, ring number of the field limiting ring and the thickness of the junction terminal extension structure in the semiconductor device structure are designed by using the semiconductor device terminal structure design method.

[0069] As Figure 1 shown, the existing semiconductor device structure field limiting ring 21 has no junction terminal extension structure 22 below, which is not suitable for GaN devices, and the terminal occupies a large area. After adjusting the overall field limiting ring 21 parameters, the ring spacing is not set in zones, but the overall ring spacing is S and the ring width is W, which will greatly increase the electric field of the last ring (the field limiting ring 21 farthest from the active region 1), so that the field limiting ring 21 terminal structure can share the main junction electric field of the active region 1, but at the same time, the curvature effect of the field limiting ring junction 21 on the last ring will be increased, and the electric field distribution as Figure 2 shown, the electric field of the last ring is very different from the peak value of the electric field of the adjacent field limiting ring 21, resulting in poor overall electric field uniformity and difficulty in achieving high blocking voltage. As Figure 4 shown, it can be seen that compared with the electric field distribution diagram generated by the existing semiconductor device structure Figure 1 ), Figure 2 ,

[0070] The present application sets the junction terminal extension structure 22 below the field limiting ring structure 21, so that the terminal structure is suitable for GaN devices, and adjusts the thickness of the junction terminal extension 22 to obtain the maximum blocking voltage. On the device structure parameters, after adjusting the overall field limiting ring 21 parameters, the field limiting ring 21 is divided into a fully depleted region 23 and a non-fully depleted region 24, and the ring spacing and ring width of the field limiting ring 21 in the non-fully depleted region 24 are adjusted, the ring spacing of the fully depleted region 23 is S, the ring width of the fully depleted region 23 is W1, the ring spacing of the partially depleted region 24 is S1, S2, S3, etc., and the ring width of the partially depleted region 24 is W2, to adjust the curvature of the depletion layer profile 3, so that the curvature effect of the fully depleted region 23 on the partially depleted region 24 can be reduced, as Figure 4As shown, the electric field peaks in the partial depletion region 24 are closer, thereby improving the overall electric field uniformity of the termination structure of the field limiting ring 21 with high precision, further improving the blocking voltage of the semiconductor device structure without additional process steps for processing the semiconductor device structure or adding additional structures, without increasing the on-resistance of the device, and the area of the termination structure 2 is greatly reduced by the vertically distributed field limiting ring 21 and the junction termination extension 22, so that the electric field uniformity is greatly improved. It can be seen that the novel semiconductor device structure prepared by the application increases the termination end junction electric field, improves the electric field uniformity, reduces the curvature effect caused by the increase of the termination end junction electric field, further improves the electric field uniformity, and improves the utilization rate of the blocking voltage.

[0071] In one embodiment, as shown in Figure 3 , a substrate 5 is arranged below the drift region 4.

[0072] In one embodiment, as shown in Figure 3 , the active region 1 is P-type, the drift region 4 is N-type, and the substrate 5 is N-type.

[0073] In one embodiment, the design and adjustment of the semiconductor device termination structure in the application are simulated and confirmed in a simulation model to improve the adjustment efficiency and calculation speed.

[0074] On this basis, the semiconductor device structure can be used for a PN junction diode or a trench gate metal-oxide-semiconductor field effect transistor.

[0075] Embodiment 2:

[0076] Referring to Figure 5 , the application provides a PN junction diode in embodiment 1, an anode electrode 62 is additionally arranged above the active region 1 of the semiconductor device structure prepared by the above method, and a cathode electrode 61 is additionally arranged below the substrate. As shown in Figure 6 , the electric field uniformity of the semiconductor device structure obtained by the design method in the application is greatly improved, and the area of the termination region is greatly reduced.

[0077] Embodiment 3:

[0078] Referring to Figure 7 , the application provides a trench gate metal-oxide-semiconductor field effect transistor in embodiment 2, a source electrode is additionally arranged above the active region of the semiconductor device structure prepared by the above method, and a drain electrode is additionally arranged below the drift region. As shown in Figure 8 , the electric field uniformity of the semiconductor device structure obtained by the design method in the application is greatly improved, and the area of the termination region is greatly reduced.

Claims

1. A method for designing a semiconductor device termination structure, characterized in that, Includes the following steps: Step 1: Prepare a semiconductor device. The main structure of the semiconductor device includes an active region, a termination region, and a drift region. The active region is located inside the device, the termination region surrounds the active region, and the drift region is located below the active region and the termination region. The terminal region includes a field-limiting loop structure and a junction terminal extension structure. The junction terminal extension structure is located below the field-limiting loop structure. A main junction is formed between the active region and the drift region. A field-limiting loop junction is formed between the field-limiting loop structure and the junction terminal extension structure. A junction terminal extension junction is formed between the junction terminal extension structure and the drift region. Subsequently, let the ring spacing of the field limiting ring structure in the initial state be the initial ring spacing, the ring width be the initial ring width, the number of rings be the initial number of rings, and the thickness of the junction terminal extension structure be the initial junction terminal extension thickness; Step 2: Keep the initial ring spacing and the initial number of rings unchanged, and increase the current ring width of the field limiting ring until the rate at which the blocking voltage of the semiconductor device structure increases with the increase of the ring width is less than or equal to a preset rate. Step 3: Divide the field limiting loop into a fully depleted region close to the active region and a partially depleted region far from the active region. The outermost loop in the partially depleted region is called the final loop. The ring spacing of the field limiting ring in the partially depleted region is set to an increasing arithmetic sequence from the inside to the outside, and the tolerance of the increasing arithmetic sequence is gradually adjusted until the electric field at the terminal extension of the main junction below the active region is equal to or the difference between the electric field at the terminal extension of the last ring below the active region is minimized. Step 4: Reduce the ring width of the field limiting ring in the partially depleted region to the minimum process dimension to obtain a semiconductor device termination structure with a field limiting ring termination that incorporates junction termination extension. In step 3, the field limiting ring is divided into a fully depleted region and a partially depleted region based on whether the drift region below it is completely depleted.

2. The design method for a semiconductor device termination structure according to claim 1, characterized in that, In step 1, the sum of the field limiting ring junction thickness and the junction terminal extension thickness is equal to the main junction depth of the active region.

3. The design method for a semiconductor device termination structure according to claim 1, characterized in that, After performing step 1, the critical breakdown electric field E of the semiconductor device structure is compared with the inner diameter r of the PN junction. p Substitute into the first equation: Calculate the final loop depletion layer expansion width r. Wherein, the inner diameter r of the PN junction p The radius of curvature at the PN junction turn of the semiconductor device structure is denoted by q, where q is the elementary charge and N is the radius of curvature. D ε represents the N-type doping ion concentration, and ε is the relative permittivity of the material between the field-limiting rings. The critical breakdown electric field E of the semiconductor device structure and the P-type doping ion concentration N A Substitute into the second equation: Calculate the maximum exhaustion width t of region P. p ; The critical breakdown electric field E of the semiconductor device structure is a transverse electric field. With longitudinal electric field The vector sum is used to calculate the first relationship between the ring spacing s of the field limiting loop and the number of rings n of the field limiting loop; Substituting the ring spacing s and junction termination thickness t into the first relationship, we obtain the number of field-limiting rings n, which corresponds to different theoretical ring numbers. The theoretical ring spacing is greater than or equal to the minimum process dimension and less than the final ring depletion layer extension width r. The theoretical junction termination extension thickness is less than the maximum depletion width t of the P-region. p ; The transverse electric field E of the critical breakdown electric field E of the semiconductor device structure X PN junction inner diameter r p Substituting the following into the fourth equation: the depletion layer extension width *r*, the ring spacing *s* of the field-limiting rings with different theoretical ring spacings, the junction terminal extension thickness *t*, and the number of field-limiting rings *n* corresponding to different theoretical ring numbers: Calculate the corresponding blocking voltage V for different blocking voltages, and obtain the ring spacing corresponding to the maximum blocking voltage as the first theoretical optimal ring spacing, the corresponding junction termination extension thickness as the first theoretical optimal junction termination extension thickness, and obtain the blocking voltage of the semiconductor device structure at this time as the first blocking voltage.

4. The design method for a semiconductor device termination structure according to claim 3, characterized in that, Increase or decrease the junction terminal extension thickness to obtain a new blocking voltage V, and select the junction terminal extension thickness corresponding to the largest blocking voltage as the first optimal junction terminal extension thickness; The ring spacing of the field limiting ring is set to the theoretical ring spacing. The number of theoretical rings corresponding to the field limiting ring is increased or decreased until the electric field of the extended junction at the lower junction of the main junction in the active region is equal to or the difference between the electric field of the extended junction at the lower junction of the last ring is minimized. The number of rings of the field limiting ring at this time is the preferred number of rings. Set the ring spacing s to different theoretical ring spacings and the number of rings n to different preferred ring numbers to obtain a new blocking voltage V. Select the ring spacing corresponding to the largest blocking voltage as the first optimal ring spacing and the number of rings corresponding to the largest blocking voltage as the first optimal number of rings. Use the junction termination extension thickness as the first optimal junction termination extension thickness, the ring spacing as the first optimal ring spacing, and the number of rings as the first optimal number of rings. Substitute the above optimal data into the initial data and continue with step 2.

5. The design method for a semiconductor device termination structure according to claim 1, characterized in that, In step 3, the ring spacing of the field limiting ring in the partially depleted region is set to a preset increasing arithmetic sequence from the inside to the outside. The tolerance of the increasing arithmetic sequence is adjusted until the electric field of the extended junction at the lower junction of the main junction in the active region is equal to or the difference between the extended junction at the lower junction of the last ring is minimized. Adjust the number of field limiting rings with the ring spacing set according to the aforementioned increasing arithmetic sequence, so that the field limiting rings with the ring spacing set according to the aforementioned increasing arithmetic sequence include some field limiting rings in the quasi-fully depleted region that are close to the partially depleted region and / or do not include some field limiting rings in the partially depleted region that are close to the quasi-fully depleted region, until the electric field of the extended junction below the main junction of the active region is equal to or the difference between the extended junction below the end ring is minimal. At this time, the field limiting rings with the ring spacing set according to the aforementioned increasing arithmetic sequence belong to the partially depleted region, and the field limiting rings still set according to the equal ring spacing belong to the fully depleted region.

6. The design method for a semiconductor device termination structure according to claim 1, characterized in that, Step 4 further includes step 4.1: Based on the fully depleted region and partially depleted region obtained in step 3, reduce the ring width of the field limiting ring in the partially depleted region to the minimum process size; adjust the field limiting ring whose ring width is reduced to the minimum process size so that the field limiting ring whose ring width is reduced to the minimum process size includes the field limiting rings in the fully depleted region that are close to the partially depleted region and / or does not include the field limiting rings in the partially depleted region that are close to the fully depleted region, until the electric field of the extended junction below the main junction of the active region is equal to or has the smallest difference with the electric field of the extended junction below the end ring. At this time, the field limiting ring whose ring width is reduced to the minimum process size belongs to the field limiting ring of the newly divided partially depleted region, and the field limiting ring whose ring width is not reduced to the minimum process size belongs to the field limiting ring of the newly divided fully depleted region.

7. The design method for a semiconductor device termination structure according to claim 6, characterized in that, After step 4.1, proceed to step 4.2: Maintain the number of field limiting rings and the ring spacing in the newly divided full depletion region, and increase the ring width of the field limiting rings in the newly divided full depletion region until the rate at which the blocking voltage of the semiconductor device terminal structure increases with the increase of the ring width is less than or equal to a preset rate.

8. A semiconductor device structure, characterized in that, The semiconductor device has a vertical structure, including an active region, a termination region, and a drift region. The active region is located in the center, the termination region surrounds the active region, and the drift region is located below the active region and the termination region. The termination region includes a field-limiting ring structure and a junction termination extension structure, with the junction termination extension structure located below the field-limiting ring structure. Wherein, a main junction is formed between the active region and the drift region, a field-limiting ring junction is formed between the field-limiting ring structure and the junction termination extension structure, and a junction termination extension junction is formed between the junction termination extension structure and the drift region. The ring spacing, ring width, number of rings, and thickness of the junction termination extension structure of the field-limiting ring in the semiconductor device structure are all designed using the semiconductor device termination structure design method described in any one of claims 1 to 7.

9. A semiconductor device structure according to claim 8, characterized in that, The semiconductor device structure is used for PN junction diodes or trench gate metal-oxide-semiconductor field-effect transistors.

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