Method and system for processing multiple driving signals of power supply in chip packaging and electronic equipment

Abstract

The invention discloses a method and a system for processing multiple driving signals of a power supply in chip packaging and electronic equipment, and relates to the technical field of chip development. The method comprises the following steps: acquiring a chip item name and / or serial number input by a user; obtaining a chip packaging specification file and an initial packaging PKG file according to the chip item name and / or serial number; extracting packaging layer electrical network information related to power supply and / or ground connection from a chip packaging specification file according to power supply and / or ground connection signal data recorded in an initial packaging PKG file; and according to the file format and the data structure of the initially packaged PKG file, generating a multi-drive PKG file which has the same file format and data structure and is configured with power supply and / or ground multi-drive connection information. According to the method, the chip packaging design process is standardized, the error rate caused by manual participation is reduced, and the chip development efficiency is improved.

Description

Technical Field

[0001] This invention relates to the field of chip development technology, and in particular to a method, system, and electronic device for processing multiple power drive signals in chip packaging. Background Technology

[0002] In chip development projects, once the system-on-a-chip design is frozen (i.e., SOC Freeze), the chip's functional design (mainly RTL code) is finalized and can no longer be modified arbitrarily.

[0003] After the SOC Freeze, the chip project enters the physical implementation and packaging co-design phase. During this phase, the chip needs to be verified and approved to ensure the integrity, connectivity, and reliability of the entire power / ground network, from the chip's pads to the packaging (PKG) substrate and then to the PCB board. This phase requires close collaboration between the chip backend team, the packaging design team, and verification personnel. For example, based on the chip package coordinates provided by the backend team, the packaging design team needs to rewrite a version of the top-level PKG file pkg_top (the top-level file of the packaging design, which defines the physical structure and electrical connections of the package substrate or leadframe, including the configuration, routing information, and electrical connections of the chip-side pads and PCB-side solder balls / pins) and the top-level PCB file pcb_top (the top-level file of the printed circuit board design, which defines the physical structure and electrical connections of the entire PCB board, including the layout, routing information, and electrical connections of the packaged chip and other components) and provide them to the verification personnel. The verification personnel will then use the received files to verify whether there are any problems with the wire bonding of the power, ground, and other multi-drive signals on the package, thereby ensuring that the physical connections of the power and ground networks are correct. In particular, special attention needs to be paid to the wiring and port declarations of the PADs for different power / ground (such as VDDCORE / VDDCPU / VDDNPU / VSSCORE, also known as power domains). For example, when writing the pkg_top top-level file with multiple power drive signals, engineers need to instantiate PADs with different numbers based on the connections and PORT declarations of different PADs, and then connect the PADs corresponding to each PAD number to the same PCBBALL (i.e., PCB solder balls) on the PCB layer. A typical configuration for multiple power drive signals can be found in [reference needed]. Figure 1 As shown. Figure 1The power multi-drive signal connections configured in the system are as follows: For the chip project PROJECTA, the power domain VDDCORE of the top-level PROJECTA_TOP layer is connected to four power supplies of the top-level PROJECTA_PKG_TOP layer of the package substrate, namely VDDCORE_1, VDDCORE_23, VDDCORE_42, and VDDCORE_53. Simultaneously, the four power supplies VDDCORE_1, VDDCORE_23, VDDCORE_42, and VDDCORE_53 of the PROJECTA_PKG_TOP layer are connected to the power supply VDDCORE of the top-level PROJECTA_PCB_TOP layer of the PCB board. During actual development, it was found that due to the large number of functional modules and complex hierarchical relationships within the system chip, the connection paths of the chip project's power / ground networks are complex, especially for the connections of multi-drive signals such as power and ground. Connection errors are prone to occur when updating PKG and PCB top-level files containing multi-drive power signals. For example, an engineer might mistakenly connect a VDDCORE to VSS (ground), creating an unexpected physical connection that could lead to a power short circuit during verification. This document processing method, which relies heavily on manual searching, comparison, and writing, hinders chip development efficiency.

[0004] On the other hand, existing technologies also provide some automated chip packaging design solutions to improve chip development efficiency. For example, Chinese patent ZL202310439986.1 discloses a chip packaging design method, including: 1. A packaging design program developed using a standard programming language, with pad generation subroutines and SIP import generation subroutines; 2. A packaging design program, with pad generation subroutines and SIP import generation subroutines; 3. Creating RedPAD pad data on a computer; 4. Setting packaging design parameters and generating bounding boxes in the packaging design program; 5. Importing Excel parameters by executing the SIP import generation subroutine, thus associating the network corresponding to the pads on the chip with the corresponding package pins within the bounding box; 6. Completing the processing of package network relationships: after the SIP is imported, a large number of flying lines are generated on the substrate and the chip (die), i.e., the pads, which are indicator lines for the relevant network relationships. Further steps by designers are required: routing, copper pouring, and bonding wire connection will connect entities with corresponding network relationships. Simple rotation and movement can achieve rapid network relationship processing for the package. Seven: Adjusting the stack-up, routing, and bonding wire connections: Determine the physical stack-up structure of the substrate based on the number of dies and the added package and die stacking method. For multi-die cavities, increase the number of layers. Routing refers to using the package routing interactive command; clicking on a pad allows dragging out a line segment with electrical network attributes, and clicking on other pads with the same network attributes completes the electrical connection of the same network. Eight: Saving the package file: After the initial chip package design is completed, executing the save command will save the file to the specified path. Nine: Setting rule checks: This includes routing constraints, layout constraints, electrical rules, checking for short circuits, checking for single-node networks, checking for drive signals in the network, checking for pin connection conflicts, physical line width, line spacing, and height, as well as bonding. Line rules; if a problem occurs during rule checking, return to step seven and start again. If the rule check passes, use the RedPKG packaging design program to generate industry-standard production and processing documents, data exchange documents, Gerber, ODB++, drill tables, and PDF files, and then complete the product design and file archiving. This solution makes the chip packaging design process more standardized and efficient, reduces the error rate, and improves work efficiency.

[0005] However, the above solution still fails to solve the problem of connection errors that easily occur when writing top-level files of packages with multiple drive signals such as power and ground. Summary of the Invention

[0006] The purpose of this invention is to overcome the shortcomings of existing technologies and provide a method, system, and electronic device for processing multiple power drive signals in chip packaging. This invention can automatically generate a multi-drive PKG file containing multiple drive signals such as power and ground based on the chip package specification file and the initial package PKG file of a chip project. Furthermore, it can check whether the multi-drive signals in the multi-drive PKG file are consistent with the configuration information in the package specification, thus standardizing the chip packaging design process, reducing the error rate caused by manual intervention, and improving chip development efficiency.

[0007] To achieve the above objectives, the present invention provides the following technical solution: A method for processing multiple power supply drive signals in a chip package includes the following steps: Obtain the chip project name and / or number input by the user; Based on the chip project name and / or number, obtain the chip package specification file and initial package PKG file for the chip project; the chip package specification file contains chip package-related information; the initial package PKG file is a Verilog file that describes the pin definitions and top-level connection information of the chip package. Based on the power and / or ground connection signal data recorded in the initial package PKG file, extract the package layer electrical network information related to the power and / or ground connection from the chip package specification file, including the package layer signal line PACKAGE_NET_NAME, pad name PAD_NAME, and pad number PAD_NUM information of the power and / or ground at the top layer of the package; Based on the file format and data structure of the initial package PKG file, a multi-driver PKG file with the same file format and data structure, and configured with power and / or ground multi-driver connection information, is generated. The configuration of power and / or ground multi-driver connection information is as follows: in the multi-driver PKG file, based on the aforementioned package layer signal line PACKAGE_NET_NAME, pad name PAD_NAME, and pad number PAD_NUM information, the pad number PAD_NUM is used to distinguish multiple signal lines connected to the same pad domain. The same pad domain refers to pad bumps with the same pad name PAD_NAME.

[0008] Furthermore, the initial package PKG file is a Verilog netlist file of the chip project, which is generated by existing package design tools and uploaded to the chip project database. In the chip project database, the initial package PKG file of each chip project is associated with its respective chip project and stored in a way that the initial package PKG file can be obtained by the chip project name and / or number name. In the initial package PKG file, the connection information for power and / or ground signals shows the connected pad fields without distinguishing the specific signal lines connected to the same pad field.

[0009] Furthermore, a backend user interaction interface is provided to receive chip packaging specification files uploaded by backend users for chip projects and store them in the chip project database. In the chip project database, the chip packaging specification files of each chip project are associated with the chip project to which they belong and stored. The corresponding chip packaging specification file can be obtained by the chip project name and / or number name of the chip project. The chip package specification document records the electrical network information of the top layer of the package for the chip project, including the name of all pad bumps (BUMP_NAME) on the chip that serve as connection points, the X and Y axis coordinates, the solder mask opening information (Pad Opening) of the pad bumps, the package layer signal line (PACKAGE_NET_NAME) to which the pad bumps are connected, and the name of the pad to which the pad bumps belong (PAD_NAME). One pad name (PAD_NAME) corresponds to one pad field, and one pad field includes one or more pad bumps. Pad bumps belonging to the same pad field are distinguished by configuring the pad number (PAD_NUM).

[0010] Furthermore, the chip packaging specification document is an Excel file, and the file names of the chip packaging specification document and the initial packaging PKG file contain the name and / or number information of the chip project to which they belong.

[0011] Furthermore, the method of distinguishing multiple signal lines connected to the same pad domain using the pad number PAD_NUM is as follows: Add the value of pad number PAD_NUM after the package layer signal line PACKAGE_NET_NAME using the identifier character "_"; or add the value of pad number PAD_NUM after the package layer signal line PACKAGE_NET_NAME using the identifier string "_pad_".

[0012] Furthermore, it also includes a multi-driver PKG file verification step, as follows: Obtain the generated multi-driver PKG file; Compare the power and / or ground connection information in the multi-driver PKG file with the contents of the initial package PKG file and chip package specification file for the same chip project; Based on the comparison results, determine whether the multi-drive PKG file is missing power and / or ground connection information, and generate a verification result file based on the comparison results.

[0013] Furthermore, the verification result file is configured with at least the initial package PKG file field, the multi-driver PKG file field, and the package specification file field; When a missing connection signal is detected in a multi-drive PKG file, the corresponding missing pad number is marked in the package specification file field to indicate that the multi-drive PKG file is missing the connection of the pad bump.

[0014] Furthermore, when generating multi-driver PKG files, a Python script is used to extract power and / or ground connection information from the chip package specification file and the initial package PKG file.

[0015] The present invention also provides a system for processing multiple power supply drive signals in a chip package, the system comprising: The user interaction interface is used to obtain the chip project name and / or number input by the user; The data acquisition unit is used to obtain the chip package specification file and the initial package PKG file of the chip project according to the chip project name and / or number; the chip package specification file contains chip package-related information; the initial package PKG file is a Verilog file that describes the pin definitions and top-level connection information of the chip package. The data extraction unit is used to extract package layer electrical network information related to the power and / or ground connection from the chip package specification file based on the power and / or ground connection signal data recorded in the initial package PKG file. This includes package layer signal lines PACKAGE_NET_NAME, pad name PAD_NAME, and pad number PAD_NUM information of power and / or ground on the top layer of the package. The multi-driver PKG file generation unit is used to generate a multi-driver PKG file with the same file format and data structure as the initial package PKG file, and configured with power and / or ground multi-driver connection information. The configuration of power and / or ground multi-driver connection information is as follows: in the multi-driver PKG file, based on the aforementioned package layer signal line PACKAGE_NET_NAME, pad name PAD_NAME, and pad number PAD_NUM information, the pad number PAD_NUM is used to distinguish multiple signal lines connected to the same pad domain, where the same pad domain refers to pad bumps with the same pad name PAD_NAME.

[0016] The present invention also provides an electronic device, comprising: At least one processor; and A memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method as described in any of the preceding methods.

[0017] Compared with the prior art, this invention, by adopting the above technical solution, has the following advantages and positive effects: This invention can automatically generate a multi-drive PKG file with multiple drive signals such as power and ground based on the chip package specification file and the initial package PKG file of the chip project. Furthermore, it can check whether the multi-drive signals in the multi-drive PKG file are consistent with the configuration information in the package specification, thus standardizing the chip package design process, reducing the error rate caused by manual intervention, and improving chip development efficiency. Attached Figure Description

[0018] Figure 1 A connection example diagram of multiple power drive signals provided by the prior art.

[0019] Figure 2 This is an example diagram of the data structure of a chip packaging specification document provided in an embodiment of the present invention.

[0020] Figure 3 This is an example diagram of the data structure of a multi-drive PKG file provided in an embodiment of the present invention.

[0021] Figure 4 This is a flowchart of a method for processing multiple power drive signals in a chip package according to an embodiment of the present invention.

[0022] Figure 5 This is an example diagram of the data structure of the verification result file provided in an embodiment of the present invention. Detailed Implementation

[0023] The method, system, and electronic device for processing multiple power drive signals in a chip package disclosed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features or combinations of technical features described in the following embodiments should not be considered isolated; they can be combined with each other to achieve better technical effects. In the accompanying drawings of the following embodiments, the same reference numerals appearing in each drawing represent the same features or components, which can be applied to different embodiments. Therefore, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0024] It should be noted that the structures, proportions, sizes, etc., illustrated in the accompanying drawings are merely for illustrative purposes and to aid those skilled in the art in understanding and reading the invention. They are not intended to limit the conditions under which the invention can be implemented. Any modifications to the structure, changes in proportions, or adjustments to size, provided they do not affect the effectiveness or purpose of the invention, should fall within the scope of the technical content disclosed in the invention. The scope of the preferred embodiments of the present invention includes other implementations, wherein functions may be performed not in the order stated or discussed, including substantially simultaneously or in reverse order, depending on the functions involved. This should be understood by those skilled in the art to which the embodiments of the present invention pertain.

[0025] Techniques, methods, and apparatus known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and apparatus should be considered part of the specification. In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0026] Explanation of technical terms: Packaging (PKG) refers to the process of arranging, fixing, and connecting semiconductor components and other constituent elements on a frame or substrate using film technology and micro-connection technology, leading out terminals, and then encapsulating and fixing them with plastic insulating media, ceramic media, or metal media to form the overall main structure.

[0027] A bare die is a chip produced in a foundry. It is a chip that has been diced and tested but has not yet been packaged. This type of die only has solder pads (or bonding pads) for packaging and cannot be directly used in actual circuits. After the dies are diced, they need to undergo electrical testing, packaging, and final application in electronic systems.

[0028] Wire bonding refers to the process of using metal wires (gold wire, aluminum wire, etc.) and employing heat pressing or ultrasonic energy to complete the internal interconnection of circuits in microelectronic devices, i.e., the connection between chips and circuits.

[0029] Chip package specification sheet: The package specification sheet is an important part of the overall chip specification sheet. It is a technical document that specifically describes the characteristics of the chip package. It records the basic information of the chip package (such as package name, model, package type, lead-free and RoHS compliance, etc.), mechanical and physical dimensions, pin definitions, thermal characteristics, etc. Example

[0030] This embodiment provides a method for processing multiple power supply drive signals in chip packaging, including the following steps: S100: Obtain the chip project name and / or number input by the user.

[0031] Preferably, a chip item acquisition field can be configured for users to input the name and / or number of the chip item to be processed. As an example and not a limitation, if the user enters the string "PROJECTB" through the chip item acquisition field and confirms, it means that the chip item to be processed is "PROJECTB".

[0032] S200, based on the chip project name and / or number, obtain the chip package specification document and initial package PKG file for that chip project. The chip package specification document contains chip package-related information. The initial package PKG file is a Verilog file that describes the pin definitions and top-level connection information of the chip package.

[0033] In this embodiment, the initial package PKG file is preferably a Verilog netlist file of the chip project, which can be generated by existing package design tools and uploaded to a pre-configured chip project database. In the chip project database, the initial package PKG file of each chip project is stored in association with its respective chip project, and the corresponding initial package PKG file can be obtained through the chip project name and / or number name.

[0034] In the initial package PKG file, the connection information for power and / or ground signals shows the connected pad fields without distinguishing the specific signal lines connected to the same pad field.

[0035] Furthermore, a backend user interaction interface is provided to receive chip packaging specification files uploaded by backend users for chip projects and store them in the chip project database. In the chip project database, the chip packaging specification files for each chip project are stored in association with their respective chip projects. The corresponding chip packaging specification file can be retrieved by the chip project name and / or its serial number.

[0036] The chip package specification document records the electrical network information of the top layer of the package for the chip project, including the pad bump name (BUMP_NAME) of all pad bumps (BUMPs are metal bumps made on the chip that serve as "point" interfaces for chip electrical interconnection), the X and Y axis coordinates (X,Y) of the pad bumps, the pad opening information (Pad Opening) of the pad bumps, the package layer signal line (PACKAGE_NET_NAME) to which the pad bumps are connected, and the pad name (PAD_NAME) to which the pad bumps belong. Each pad name (PAD_NAME) corresponds to a pad field, and a pad field includes one or more pad bumps. Pad bumps belonging to the same pad field are distinguished by configuring pad numbers (PAD_NUM).

[0037] See Figure 2 The diagram illustrates a typical data structure in a chip package specification document. It displays the standard pad bump name field BUMP_NAME, the pad name field PAD_NAME (indicating the pad field to which the bump belongs), the bump's X and Y coordinates (layout X (center), layout Y (center)), the bump's solder mask opening information PadOpening, and the package layer signal line field PACKAGE_NET_NAME to which the bump is connected. One pad name PAD_NAME corresponds to one pad field, and one pad field can include one or more pad bumps BUMP. Pad bumps belonging to the same pad field are distinguished by configuring the pad number PAD_NUM. Figure 2 Taking the power supply VDDCORE as an example, there are multiple signal lines with the pad name PAD_NAME as VDDCORE (the value under the PAD_NAME field is "VDDCORE"), corresponding to multiple pad bumps. Each pad bump PAD (BUMP_NAME) of VDDCORE corresponds to a signal of power supply VDDCORE in the PROJECTB_PKG_TOP layer (PROJECTB represents the name and / or number of the chip project). When configuring the chip package specification, the pad bumps PAD (BUMP_NAME) are distinguished by PAD_NUM.

[0038] In this embodiment, the chip packaging specification document can be an Excel file. The file names of the chip packaging specification document and the initial package PKG file contain the name and / or number information of the chip project to which they belong.

[0039] For example, Figure 2The filename of the chip packaging specification file can be "PROJECTB_FCCSP1.xlsx", where PROJECTB represents the name and / or number of the chip project, and FCCSP1 represents the file version information. The filename of the initial package PKG file can be "PROJECTB_ddr_noswap_pkg_top.v", where PROJECTB represents the name and / or number of the chip project, and ".v" represents a Verilog file.

[0040] S300, based on the power and / or ground connection signal data recorded in the initial package PKG file, extract package layer electrical network information related to the power and / or ground connection from the chip package specification file, including the package layer signal lines PACKAGE_NET_NAME, pad name PAD_NAME, and pad number PAD_NUM information of power and / or ground on the top layer of the package.

[0041] S400: Based on the file format and data structure of the initial package PKG file, generate a multi-driver PKG file with the same file format and data structure, configured with power and / or ground multi-driver connection information. The configuration of the power and / or ground multi-driver connection information is as follows: In the multi-driver PKG file, based on the aforementioned package layer signal line PACKAGE_NET_NAME, pad name PAD_NAME, and pad number PAD_NUM information, the pad number PAD_NUM is used to distinguish multiple signal lines connected to the same pad domain. The same pad domain refers to pad bumps with the same pad name PAD_NAME.

[0042] In other words, based on the initial PKG file and chip package specification information, a new version of the multi-drive PKG file with multiple power / ground connection signals is updated. The file format of the multi-drive PKG file is the same as that of the initial package PKG file, both being Verilog files, and the data structure of the multi-drive PKG file is the same as that of the initial package PKG file (with the same data fields). The difference is that the multi-drive PKG file distinguishes the signal lines of the power multi-drive signals by adding pad numbers.

[0043] Preferably, the method of using the pad number PAD_NUM to distinguish multiple signal lines connected to the same pad domain can be as follows: The value of the pad number PAD_NUM can be appended to the package layer signal line PACKAGE_NET_NAME using the identifier character "_"; or, the value of the pad number PAD_NUM can be appended to the package layer signal line PACKAGE_NET_NAME using the identifier string "_pad_". See also Figure 3As shown, in a generated power multi-drive file PROJECTB_pkg_top_mdrive.v (PROJECTB represents the chip project name and / or number), taking the signal line whose original PACKAGE_NET_NAME was "VDDNPU" as an example, the signal lines that were originally only displayed as "VDDNPU" in the initial package PKG file are distinguished by "VDDNPU_pad_940", "VDDNPU_pad_942", "VDDNPU_pad_944", and "VDDNPU_pad_946".

[0044] In this embodiment, when generating the multi-driver PKG file, power and / or ground connection information can be extracted from the chip package specification file and the initial package PKG file using a Python script. See [link to documentation]. Figure 4 As shown, pkg_gen.py represents a Python script.

[0045] In another embodiment of this example, a multi-driver PKG file verification step is also included, as follows: obtaining the generated multi-driver PKG file; comparing the power and / or ground connection information in the multi-driver PKG file with the contents of the initial package PKG file and the chip package specification file of the same chip project; determining whether the multi-driver PKG file is missing power and / or ground connection information based on the comparison result, and generating a verification result file based on the comparison result.

[0046] Thus, the verification result file can be used to compare the multi-drive signal connection information in the multi-drive PKG file with the configuration information in the package specification to check for omissions. The verification result file is preferably a log file, and the filename also includes the name and / or number information of the chip project, see [link to relevant documentation]. Figure 4 As shown, the generated file is "xx_pkg_top.log", where "xx" represents the project name and / or number, and ".log" represents the log file.

[0047] Preferably, the verification result file includes at least an initial package PKG file field, a multi-driver PKG file field, and a package specification file field. Each field lists the power and ground signal lines from the corresponding file. In the multi-driver PKG file field and the package specification file field, the signal lines are distinguished by pad numbers PAD_NUM and ordered according to the size of the PAD_NUM number. When a connection signal is found to be missing in the multi-driver PKG file, the corresponding missing pad number is marked in the package specification file field to indicate that the multi-driver PKG file is missing a connection to that pad bump.

[0048] See Figure 5The diagram illustrates a typical data structure for the verification result file. If any signals are missing in the generated multi-driver PKG file (i.e., the multi-driver pkg file in the diagram), the corresponding column will be highlighted in red under the package specification field of the verification result file. For example... Figure 5 The fact that VDDCORE_27 is highlighted in red indicates that a signal line VDDCORE_27 is missing from the multi-driver PKG file. Furthermore, based on the verification results, the corresponding columns of signal lines missing from the multi-driver PKG file can be clearly identified in the chip package specification document.

[0049] Another embodiment of the present invention provides a system for processing multiple power supply drive signals in a chip package. The system includes a user interface, a data acquisition unit, a data extraction unit, and a multi-drive PKG file generation unit.

[0050] The user interaction interface is used to obtain the chip project name and / or number input by the user.

[0051] The data acquisition unit is used to obtain the chip package specification document and the initial package PKG file for the chip project based on the chip project name and / or number. The chip package specification document contains chip package-related information. The initial package PKG file is a Verilog file that describes the pin definitions and top-level connection information of the chip package.

[0052] The data extraction unit is used to extract package layer electrical network information related to the power and / or ground connection from the chip package specification file based on the power and / or ground connection signal data recorded in the initial package PKG file. This includes package layer signal lines PACKAGE_NET_NAME, pad name PAD_NAME, and pad number PAD_NUM information for power and / or ground on the top layer of the package.

[0053] The multi-driver PKG file generation unit is used to generate a multi-driver PKG file with the same file format and data structure as the initial package PKG file, and configured with power and / or ground multi-driver connection information, according to the file format and data structure of the initial package PKG file. The configuration of power and / or ground multi-driver connection information is as follows: in the multi-driver PKG file, according to the aforementioned package layer signal line PACKAGE_NET_NAME, pad name PAD_NAME, and pad number PAD_NUM information, the pad number PAD_NUM is used to distinguish multiple signal lines connected to the same pad domain, where the same pad domain refers to pad bumps with the same pad name PAD_NAME.

[0054] Other technical features are described in the previous embodiments and will not be repeated here.

[0055] Another embodiment of the present invention also provides an electronic device, comprising: At least one processor; and A memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method as described in any of the preceding methods.

[0056] Other technical features are described in the previous embodiments and will not be repeated here.

[0057] In the above description, the disclosure of this invention is not intended to limit itself to these aspects. Rather, within the scope of the objectives of this disclosure, components can be selectively and operationally combined in any number. Furthermore, terms such as “comprising,” “encompassing,” and “having” should be interpreted by default as inclusive or open-ended, rather than exclusive or closed, unless explicitly defined as such. All technical, scientific, or other terms are to be understood by those skilled in the art, unless defined as such. Public terms found in dictionaries should not be interpreted in the context of the relevant technical documents in an overly idealistic or impractical manner, unless explicitly defined as such in this disclosure. Any modifications or alterations made by those skilled in the art based on the foregoing disclosure are within the scope of the claims.

Claims

1. A method for processing multiple power supply drive signals in a chip package, characterized in that... Including the following steps: Obtain the chip project name and / or number input by the user; Based on the chip project name and / or number, obtain the chip packaging specification document and initial package PKG file for the chip project; the chip packaging specification document contains chip packaging-related information. The initial package PKG file is a Verilog file that describes the pin definitions and top-level connection information of the chip package. Based on the power and / or ground connection signal data recorded in the initial package PKG file, extract the package layer electrical network information related to the power and / or ground connection from the chip package specification file, including the package layer signal line PACKAGE_NET_NAME, pad name PAD_NAME, and pad number PAD_NUM information of the power and / or ground at the top layer of the package; Based on the file format and data structure of the initial package PKG file, a multi-driver PKG file with the same file format and data structure, and configured with power and / or ground multi-driver connection information, is generated. The configuration of power and / or ground multi-driver connection information is as follows: in the multi-driver PKG file, based on the aforementioned package layer signal line PACKAGE_NET_NAME, pad name PAD_NAME, and pad number PAD_NUM information, the pad number PAD_NUM is used to distinguish multiple signal lines connected to the same pad domain. The same pad domain refers to pad bumps with the same pad name PAD_NAME.

2. The method according to claim 1, characterized in that, The initial package PKG file is a Verilog netlist file of the chip project, which is generated by an existing package design tool and uploaded to the chip project database. In the chip project database, the initial package PKG file of each chip project is associated with its respective chip project and stored. The corresponding initial package PKG file can be obtained by the chip project name and / or number name. In the initial package PKG file, the connection information for power and / or ground signals shows the connected pad fields without distinguishing the specific signal lines connected to the same pad field.

3. The method according to claim 1 or 2, characterized in that, A backend user interaction interface is provided to receive chip packaging specification files uploaded by backend users for chip projects and store them in the chip project database. In the chip project database, the chip packaging specification files of each chip project are stored in association with the chip project to which they belong. The corresponding chip packaging specification file can be obtained by the chip project name and / or number name. The chip package specification document records the electrical network information of the top layer of the package for the chip project, including the name of all pad bumps (BUMP_NAME) on the chip that serve as connection points, the X and Y axis coordinates, the solder mask opening information (Pad Opening) of the pad bumps, the package layer signal line (PACKAGE_NET_NAME) to which the pad bumps are connected, and the name of the pad to which the pad bumps belong (PAD_NAME). One pad name (PAD_NAME) corresponds to one pad field, and one pad field includes one or more pad bumps. Pad bumps belonging to the same pad field are distinguished by configuring the pad number (PAD_NUM).

4. The method according to claim 3, characterized in that, The chip packaging specification document is an Excel file, and the file names of the chip packaging specification document and the initial packaging PKG file contain the name and / or number information of the chip project to which they belong.

5. The method according to claim 1, characterized in that, The method for distinguishing multiple signal lines connected to the same pad domain using the pad number PAD_NUM is as follows: Add the value of pad number PAD_NUM after the package layer signal line PACKAGE_NET_NAME using the identifier character "_"; or add the value of pad number PAD_NUM after the package layer signal line PACKAGE_NET_NAME using the identifier string "_pad_".

6. The method according to claim 1, characterized in that, It also includes a multi-driver PKG file verification step, as follows: Obtain the generated multi-driver PKG file; Compare the power and / or ground connection information in the multi-driver PKG file with the contents of the initial package PKG file and chip package specification file for the same chip project; Based on the comparison results, determine whether the multi-drive PKG file is missing power and / or ground connection information, and generate a verification result file based on the comparison results.

7. The method according to claim 6, characterized in that, The verification result file is configured with at least the initial package PKG file field, the multi-driver PKG file field, and the package specification file field; When a missing connection signal is detected in a multi-drive PKG file, the corresponding missing pad number is marked in the package specification file field to indicate that the multi-drive PKG file is missing the connection of the pad bump.

8. The method according to claim 1, characterized in that, When generating multi-driver PKG files, a Python script is used to extract power and / or ground connection information from the chip package specification file and the initial package PKG file.

9. A system for processing multiple power supply drive signals in a chip package, characterized in that... include: The user interaction interface is used to obtain the chip project name and / or number input by the user; The data acquisition unit is used to obtain the chip packaging specification file and the initial packaging PKG file of the chip project according to the chip project name and / or number; the chip packaging specification file contains chip packaging-related information. The initial package PKG file is a Verilog file that describes the pin definitions and top-level connection information of the chip package. The data extraction unit is used to extract package layer electrical network information related to the power and / or ground connection from the chip package specification file based on the power and / or ground connection signal data recorded in the initial package PKG file. This includes package layer signal lines PACKAGE_NET_NAME, pad name PAD_NAME, and pad number PAD_NUM information of power and / or ground on the top layer of the package. The multi-driver PKG file generation unit is used to generate a multi-driver PKG file with the same file format and data structure as the initial package PKG file, and configured with power and / or ground multi-driver connection information. The configuration of power and / or ground multi-driver connection information is as follows: in the multi-driver PKG file, based on the aforementioned package layer signal line PACKAGE_NET_NAME, pad name PAD_NAME, and pad number PAD_NUM information, the pad number PAD_NUM is used to distinguish multiple signal lines connected to the same pad domain, where the same pad domain refers to pad bumps with the same pad name PAD_NAME.

10. An electronic device, characterized in that, include: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method as described in any one of claims 1-8.

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