Detection circuit, detection method and display panel

Abstract

The invention belongs to the technical field of display driving, and particularly relates to a detection circuit, a detection method and a display panel, the detection circuit comprises a sensing module arranged in a noise reduction unit, and the sensing module is electrically connected with a noise reduction control node of the noise reduction unit; the detection module is used for controlling the voltage of each end of the sensing module in a non-detection stage so as to simulate the voltage stress borne by a target transistor in the noise reduction unit; in the detection stage, at least one voltage parameter output by the sensing module is detected; through aging simulation and parameter detection, on-line monitoring and real-time compensation are carried out on the drifting condition of the transistor in the noise reduction unit under the conditions that GOA space layout is not increased and the original reliability of the circuit is not affected, the threshold voltage drifting problem of the transistor in the noise reduction unit is effectively solved, and the reliability of the circuit is improved. And the long-term noise reduction stability of the noise reduction unit is maintained and improved.

Description

Technical Field

[0001] This application belongs to the field of display driver technology, specifically relating to a detection circuit, a detection method, and a display panel. Background Technology

[0002] GOA (Gate Driver on Array) is a key circuit for achieving progressive scanning in TFT-LCD (Thin-Film Transistor Liquid Crystal Display). Among them, the noise reduction unit, which performs noise reduction processing on key nodes inside the GOA, is the core module to ensure the stability of the GOA circuit and the reliability of the display.

[0003] However, during long-term operation, the threshold voltage of each transistor in the noise reduction unit will drift to varying degrees, thereby reducing the noise reduction capability of the circuit. Currently, in order to improve this problem, two sets of noise reduction units with identical structures are usually used to work alternately. However, this not only increases the number of transistors and layout space, but also essentially only delays the aging process and cannot improve the problem of transistor threshold voltage drift after long-term operation.

[0004] Therefore, how to effectively improve the threshold voltage drift of transistors in noise reduction units is a problem that urgently needs to be solved. Summary of the Invention

[0005] This application provides a detection circuit, detection method, and display panel. By aging simulation and parameter detection, this application can monitor and compensate for the drift of transistors in the noise reduction unit in real time without increasing the GOA space layout or affecting the original reliability of the circuit. This effectively improves the threshold voltage drift problem of transistors in the noise reduction unit and maintains and improves the long-term noise reduction stability of the noise reduction unit.

[0006] In a first aspect, this application provides a detection circuit applied to a gate drive circuit having a noise reduction unit. The detection circuit includes: a sensing module disposed in the noise reduction unit, the sensing module being electrically connected to a noise reduction control node of the noise reduction unit; and a detection module connected to the sensing module and an external control device. The detection module is configured to: in a non-detection phase, control the voltage at each terminal of the sensing module to simulate the voltage stress borne by the target transistor in the noise reduction unit; and in a detection phase, detect at least one voltage parameter output by the sensing module, causing the external control device to compensate for the threshold voltage drift of the transistor in the noise reduction unit based on the at least one voltage parameter.

[0007] Optionally, the detection module includes: a first detection unit configured to be connected to the control terminal of the sensing module and the external control device, for acquiring a first voltage on the noise reduction control node during the detection phase; a second detection unit configured to be connected to the first terminal of the sensing module and the external control device, for setting the voltage of the first terminal of the sensing module to a low level during the non-detection phase; and a third detection unit configured to be connected to the second terminal of the sensing module and the external control device, for setting the voltage of the second terminal of the sensing module to a low level during the non-detection phase and acquiring a second voltage output by the sensing module during the detection phase; wherein the at least one voltage parameter includes the first voltage and the second voltage.

[0008] Optionally, the sensing module includes a sensing transistor, the control terminal of which is connected to the noise reduction control node; wherein the sensing transistor has the same device parameters as the noise reduction transistor in the noise reduction unit.

[0009] Optionally, the first detection unit includes: a first transistor, the control terminal of the first transistor being connected to the first control terminal of the external control device, the first terminal of the first transistor being connected to the control terminal of the sensing transistor, and the second terminal of the first transistor serving as the output terminal of the first detection unit.

[0010] Optionally, the second detection unit includes: a second transistor, the control terminal of which is connected to the second control terminal of the external control device, the first terminal of which is connected to the first terminal of the sensing transistor, and the second terminal of which is connected to a power supply terminal; and a third transistor, the control terminal of which is connected to the third control terminal of the external control device, the first terminal of which is connected to the first terminal of the second transistor, and the second terminal of which is connected to a low-level terminal.

[0011] Optionally, the third detection unit includes: a fourth transistor, the control terminal of which is connected to the fourth control terminal of the external control device, and the first terminal of which is connected to the second terminal of the sensing transistor; an amplifier, the first input terminal of which is connected to a low-level terminal, and the second input terminal of which is connected to the second terminal of the fourth transistor; a capacitor, the first terminal of which is connected to the second input terminal of the amplifier, and the second terminal of which is connected to the output terminal of the amplifier; a fifth transistor, the control terminal of which is connected to the fifth control terminal of the external control device, the first terminal of which is connected to the second input terminal of the amplifier, and the second terminal of which is connected to the output terminal of the amplifier; and a sixth transistor, the control terminal of which is connected to the sixth control terminal of the external control device, the first terminal of which is connected to the output terminal of the amplifier, and the second terminal of which serves as the output terminal of the third detection unit.

[0012] Optionally, the second detection unit includes: a second transistor, the control terminal of which is connected to the second control terminal of the external control device, the first terminal of which is connected to the control terminal of the sensing transistor, and the second terminal of which is connected to the first terminal of the sensing transistor; and a third transistor, the control terminal of which is connected to the third control terminal of the external control device, the first terminal of which is connected to the second terminal of the second transistor, and the second terminal of which is connected to a low-level terminal.

[0013] Optionally, the third detection unit includes: a fourth transistor, the control terminal of which is connected to the fourth control terminal of the external control device, the first terminal of which is connected to a low-level terminal, and the second terminal of which is connected to the second terminal of the sensing transistor; and a fifth transistor, the control terminal of which is connected to the fifth control terminal of the external control device, the first terminal of which is connected to the second terminal of the fourth transistor, and the second terminal of which serves as the output terminal of the third detection unit.

[0014] Secondly, this application provides a detection method applied to a detection circuit. The detection method includes: in a non-detection phase, controlling the voltage at each terminal of a sensing module through a detection module to simulate the voltage stress borne by the target transistor in the noise reduction unit; in a detection phase, detecting at least one voltage parameter output by the sensing module through the detection module, so that an external control device compensates for the threshold voltage drift of the transistor in the noise reduction unit according to the at least one voltage parameter.

[0015] Thirdly, this application provides a display panel, the display panel comprising: a detection circuit; a gate driving circuit, the gate driving circuit comprising N cascaded gate driving modules, each gate driving module having a noise reduction unit; wherein, the sensing module of the detection circuit is disposed in the noise reduction unit of any one of the gate driving modules.

[0016] The technical solutions provided in this application have at least the following beneficial effects: This application integrates the sensing module within the noise reduction unit and connects it to the noise reduction control node. This allows the sensing module to withstand the same voltage stress as the target transistor during the non-detection phase, thus achieving synchronous aging simulation with the target transistor. During the detection phase, the detection module switches the connection state of the sensing module and acquires its voltage parameters. An external control device then detects the transistor drift in the noise reduction unit based on these voltage parameters and performs corresponding compensation. Therefore, this application obtains the threshold voltage drift changes of all transistors in the noise reduction unit through aging simulation and parameter detection. This constructs a detection window for the aging state of the internal transistors without interfering with the normal operation of the noise reduction unit or occupying effective display area layout space, providing a reliable basis for subsequent performance maintenance. Thus, this application achieves online monitoring and real-time compensation of the threshold voltage drift of transistors in the noise reduction unit without increasing chip area or affecting the original reliability of the circuit, maintaining and improving the long-term noise reduction stability of the noise reduction unit. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0018] Figure 1 The diagram shown is a structural schematic of a gate driving module provided in an embodiment of this application.

[0019] Figure 2 The diagram shown is a circuit diagram of a noise reduction unit provided in an embodiment of this application.

[0020] Figure 3 The figure shown is a timing diagram of a noise reduction unit provided in an embodiment of this application.

[0021] Figure 4 The diagram shown is a schematic diagram of a detection circuit provided in an embodiment of this application.

[0022] Figure 5The diagram shown is a schematic diagram of the first detection circuit provided in the embodiment of this application.

[0023] Figure 6 The diagram shown is a schematic diagram of a driving waveform provided in an embodiment of this application.

[0024] Figure 7 The diagram shown is a schematic diagram of the second detection circuit provided in an embodiment of this application.

[0025] Figure 8 The diagram shown is another driving waveform provided in an embodiment of this application.

[0026] Figure 9 The diagram shown is a flowchart of a detection method provided in an embodiment of this application.

[0027] Figure 10 The diagram shown is a structural schematic of a display panel provided in an embodiment of this application.

[0028] Explanation of reference numerals in the attached figures: 100. Detection circuit; 110. Sensing module; 120. Detection module; 121. First detection unit; 122. Second detection unit; 123. Third detection unit; 200. External control device; 300. Noise reduction unit; M1, First control transistor; M2, Second control transistor; M3, Third control transistor; M4, Fourth control transistor; J1, First noise reduction transistor; J2, Second noise reduction transistor; J3, Third noise reduction transistor; L, Detection line; N0, Sensing transistor; N1, First transistor; N2, Second transistor; N3, Third transistor; N4, Fourth transistor; N5, Fifth transistor; N6, Sixth transistor; C, Capacitor; OP, Amplifier; SW1, First control terminal; SW2, Second control terminal; SW3, Third control terminal; SW4, Fourth control terminal; SW5, Fifth control terminal; SW6, Sixth control terminal; VSS, Low-level terminal; VDD, Power supply terminal. Detailed Implementation

[0029] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0030] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0031] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0032] The working principle of liquid crystal in a TFT-LCD is as follows: when an external voltage is applied to a single pixel in the display area, the liquid crystal molecules within the pixel rotate, causing a change in light transmittance and thus color transmission. All pixels in the display area array switch frame by frame, achieving dynamic display. The progressive scanning of the display panel is mainly achieved through the GOA (Gateway Assignment) circuit. The gate driving circuit includes N cascaded gate driving modules, such as... Figure 1 As shown, the nth-level gate driver module mainly includes pull-up units, pull-down units, output units, reset units, and noise reduction units. The pull-up and pull-down units generate the Q-point voltage. The pull-up and pull-down units need to obtain multiple stage transmission signals from the upper and lower gate driver modules. The Q-point voltage is the turn-on voltage of the output unit, which enables the output unit to output the gate drive signal to provide the turn-on voltage for the display area. The reset unit is used to avoid the influence between frames. The noise reduction unit performs noise reduction processing on the signals at each key node. Among them, Qn represents the drive control node of the nth-level gate driver module, Gn represents the drive output terminal of the nth-level gate driver module, Fn represents the stage transmission output terminal of the nth-level gate driver module, CKn represents the clock signal terminal of the nth-level gate driver module, Reset represents the reset signal terminal, LC represents the noise reduction control terminal, Gn-i represents the drive output terminal of the nith-level gate driver module, Fn-i represents the stage transmission output terminal of the nith-level gate driver module, and Fn+j represents the stage transmission output terminal of the (n+j)th-level gate driver module.

[0033] A normal output from the gate drive module is essential for ensuring proper image display; therefore, the noise reduction unit plays a crucial role in suppressing signal noise. Figure 2The diagram shows a circuit diagram of a noise reduction unit in related technologies. It mainly consists of a first control transistor M1, a second control transistor M2, a third control transistor M3, a fourth control transistor M4, a first noise reduction transistor J1, a second noise reduction transistor J2, and a third noise reduction transistor J3. When the drive control node (i.e., point Q) in the nth stage gate drive module is at a low level, the noise reduction control terminal LC continuously outputs a high level. At this time, the first control transistor M1 and the second control transistor M2 are turned on, while the third control transistor M3 and the fourth control transistor M4 are turned off, making the noise reduction control node Pn high. This turns on the first noise reduction transistor J1, the second noise reduction transistor J2, and the third noise reduction transistor J3, thereby continuously pulling the signals on the drive output terminal Gn, the drive control node Qn, and the stage transmission output terminal Fn low, achieving noise reduction processing for each important node in the gate drive module. In other words, the noise reduction unit mainly consists of a noise reduction control unit and a noise reduction execution unit. The noise reduction control unit is an inverter composed of Darlington circuits, which inverts the voltage at point Q in the GOA circuit to obtain the voltage at point P (i.e., the noise reduction control node). The voltage at point P then controls the transistors in the noise reduction execution unit to perform noise reduction processing on various signals. The waveform diagram is shown below. Figure 3 As shown, when the voltage at point Q is high, the voltage at point P is low, and when the voltage at point Q is low, the voltage at point P is high.

[0034] The inventors of this application discovered that the noise reduction unit experiences a decline in performance during aging. Specifically: ① The Darlington circuit characteristics in the noise reduction control unit exhibit drift (drift in the circuit output characteristics caused by the drift in the characteristics of each control transistor), meaning that with the same input Q-point voltage, the P-point voltage drifts. Figure 3 As shown, the solid line represents the waveform before the Darlington circuit characteristics drift, and the dashed line represents the waveform after the Darlington circuit characteristics drift, which leads to a decrease in noise reduction capability; ② Each noise reduction transistor in the noise reduction execution unit is in a high Vgs state for a long time (gate is always high, source is always low), and its threshold voltage and electron mobility drift, especially in high temperature environment, which also leads to a decrease in noise reduction capability.

[0035] Due to the aging issue of the aforementioned noise reduction units, current gate drive circuits typically employ a method of alternating use of two sets of noise reduction units to mitigate the rapid decline in noise reduction capability. However, this method increases the number of transistors, occupies layout space, and cannot completely avoid the problem of declining noise reduction capability. After prolonged aging, there is still a risk of cascade failure.

[0036] To improve the threshold voltage drift problem of transistors in noise reduction units, this application provides a detection circuit, specifically including the following embodiments: Figure 4 The diagram shown is a schematic representation of a detection circuit 100 provided in an embodiment of this application; as shown Figure 4 As shown, the detection circuit 100 in this embodiment is applied to the gate drive circuit with the noise reduction unit 300, specifically including a sensing module 110, which is disposed in the noise reduction unit 300, and the sensing module 110 is electrically connected to the noise reduction control node of the noise reduction unit 300.

[0037] It should be noted that the sensing module 110 in this embodiment is only used to simulate the aging of the target transistor (which can be any noise reduction transistor) in the noise reduction unit 300. In other words, the sensing module 110 can be integrated into the noise reduction unit 300 of the virtual driving module (i.e., DUMMY level) of the gate driving circuit. This allows the sensing module 110 to be placed in a local environment (such as temperature, process fluctuations, power supply noise) that is highly similar to or even the same as the target transistor, thus realizing the physical basis for accurate aging simulation and ensuring that the parameter changes detected subsequently can truly reflect the aging stress experienced by the target transistor.

[0038] like Figure 4 As shown, the detection circuit 100 further includes a detection module 120 connected to the sensing module 110 and the external control device 200. The detection module 120 is configured to: control the voltage at each terminal of the sensing module 110 during the non-detection phase to simulate the voltage stress borne by the target transistor in the noise reduction unit 300; and switch the connection state of the sensing module 110 during the detection phase to detect at least one voltage parameter of the sensing module 110, so that the external control device 200 compensates for the threshold voltage drift of the transistor in the noise reduction unit 300 according to at least one voltage parameter.

[0039] It should be noted that during the non-detection phase, the detection module 120 uses an internal switching network to forcibly bias the other ports of the sensing module 110 (such as the source and drain) to specific potentials, excluding the aforementioned control terminals. For example, by pulling both its source and drain low to the reference ground, the sensing module 110, driven by the gate voltage (from point P), is in a specific bias state with a high gate-source voltage (Vgs) and a low drain-source voltage (Vds). This state is designed to be highly similar to that of the target transistor during periods when it is not performing active noise reduction but is subjected to static stress (or its main aging stress conditions).

[0040] Furthermore, during the detection phase, the detection module 120 changes the connection circuit of the sensing module 110 by switching an internal switch, causing the sensing module 110 to output one or more voltage parameters. The external control device 200 receives the voltage parameters output by the detection module 120, which directly or indirectly characterize the current value or drift of the target transistor threshold voltage (Vth), thereby calculating the compensation amount required to maintain the noise reduction performance (usually increasing a certain driving voltage supplied to the noise reduction unit 300, such as VGH, LC voltage, etc.) and performing the adjustment.

[0041] Additionally, it should be noted that the detection module 120 in this embodiment is a module independent of the gate drive circuit and can be placed on a circuit board outside the array substrate. This does not occupy the layout space of the gate drive circuit and can achieve a narrow bezel design.

[0042] Therefore, this application achieves synchronous aging simulation with the target transistor by placing the sensing module 110 in the noise reduction unit 300 and connecting it to the noise reduction control node, so that the sensing module 110 is subjected to the same voltage stress as the target transistor during the non-detection phase. During the detection phase, the detection module 120 switches the connection state of the sensing module 110 and obtains its voltage parameters, allowing the external control device 200 to detect the drift of the transistors in the noise reduction unit 300 based on these voltage parameters and perform corresponding compensation. Thus, this application obtains the threshold voltage drift changes of all transistors in the noise reduction unit 300 through aging simulation and parameter detection. Without interfering with the normal operation of the noise reduction unit 300 and without occupying effective display area layout space, it constructs a detection window for the aging state of the internal transistors, providing a reliable basis for subsequent performance maintenance. Therefore, this application achieves online monitoring and real-time compensation of the threshold voltage drift of the transistors in the noise reduction unit 300 without increasing the GOA space layout or affecting the original reliability of the circuit, maintaining and improving the long-term noise reduction stability of the noise reduction unit 300.

[0043] In one embodiment, the detection module 120 includes a first detection unit 121, a second detection unit 122, and a third detection unit 123; wherein, the first detection unit 121 is configured to be connected to the control terminal of the sensing module 110 and the external control device 200, and is used to acquire a first voltage on the noise reduction control node during the detection phase; the second detection unit 122 is configured to be connected to the first terminal of the sensing module 110 and the external control device 200, and is used to set the voltage of the first terminal of the sensing module 110 to a low level during the non-detection phase; the third detection unit 123 is configured to be connected to the second terminal of the sensing module 110 and the external control device 200, and is used to set the voltage of the second terminal of the sensing module 110 to a low level during the non-detection phase, and acquire a second voltage output by the sensing module 110 during the detection phase; wherein, at least one voltage parameter includes the first voltage and the second voltage.

[0044] Figure 5 The diagram shown is a circuit diagram of the first detection circuit 100 provided in an embodiment of this application. Figure 5 As shown, the sensing module 110 includes a sensing transistor N0, and the control terminal of the sensing transistor N0 is connected to the noise reduction control node; wherein, the sensing transistor N0 has the same device parameters as the noise reduction transistor in the noise reduction unit 300.

[0045] It should be noted that the sensing transistor N0 is integrated into the final stage dummy drive unit (DummyGOA) of the gate drive circuit. This dummy drive unit is located in the non-display area of ​​the display panel, typically near the source drive circuit. The control terminal of the sensing transistor N0 is directly electrically connected to the noise reduction control node (i.e., P-point) of the noise reduction unit 300 in the same GOA unit or an adjacent standard GOA unit via internal wiring. Simultaneously, the control terminal, the first terminal, and the second terminal of the sensing transistor N0 are each led out to the panel bezel area via independent metal traces for connection to the detection module 120.

[0046] It is worth noting that the device parameters of the sensing transistor N0 in this embodiment, including but not limited to the channel width (W), length (L), oxide capacitance C (Cox), and specific layout pattern, are all designed to be consistent with the target transistor in the noise reduction unit 300 to be monitored (e.g., Figure 2 The first noise reduction transistor J1 in the target transistor is exactly the same, so that the sensing transistor N0 and the target transistor have a high degree of matching and consistency in electrical characteristics. This ensures that the aging degree of the two is highly synchronized under the same stress conditions, so that the aging characteristics such as threshold voltage drift of the noise reduction transistor can be accurately obtained by detecting the characteristics of the sensing transistor N0.

[0047] like Figure 5 As shown, the first detection unit 121 includes: a first transistor N1, the control terminal of the first transistor N1 is connected to the first control terminal SW1 of the external control device 200, the first terminal of the first transistor N1 is connected to the control terminal of the sensing transistor N0, and the second terminal of the first transistor N1 serves as the output terminal of the first detection unit 121.

[0048] It should be noted that when it is necessary to detect the voltage of the noise reduction control node (that is, during the node voltage extraction period of the detection phase), the first control terminal SW1 of the external control device 200 outputs a high level, and the first transistor N1 is turned on. Thus, the external control device 200 collects the first voltage Vout1 on the noise reduction control node through the turned-on first transistor N1. During other periods of normal display and detection phase, the first control terminal SW1 of the external control device 200 outputs a low level, and the first transistor N1 is turned off. This achieves bidirectional isolation between the detection circuit 100 and the internal nodes of the noise reduction unit 300, preventing the stability of the noise reduction control node voltage from being affected during non-detection phases.

[0049] like Figure 5As shown, the second detection unit 122 includes a second transistor N2 and a third transistor N3; the control terminal of the second transistor N2 is connected to the second control terminal SW2 of the external control device 200, the first terminal of the second transistor N2 is connected to the first terminal of the sensing transistor N0, and the second terminal of the second transistor N2 is connected to the power supply terminal VDD; the control terminal of the third transistor N3 is connected to the third control terminal SW3 of the external control device 200, the first terminal of the third transistor N3 is connected to the first terminal of the second transistor N2, and the second terminal of the third transistor N3 is connected to the low-level terminal VSS.

[0050] It is worth noting that a frame includes a scanning period and a blanking period. In this embodiment, the detection phase is located within the blanking period, such as... Figure 6 As shown, the blanking period in this embodiment includes a first normal display period T0, a detection phase, and a second normal display period T3. The detection phase includes a node voltage extraction period T1 and a threshold voltage extraction period T2. The threshold voltage extraction period T2 includes a charge accumulation sub-period t1 and a voltage reading sub-period t2.

[0051] This combination Figure 6 The timing diagram shown below provides a detailed explanation of the working principle of the second detection unit 122 in this embodiment: (1) During the normal display phase (i.e., the non-detection period or the aging simulation period): the second control terminal SW2 of the external control device 200 outputs a low level, the third control terminal SW3 outputs a high level, the second transistor N2 is turned off, and the third transistor N3 is turned on, so that the first terminal (drain) of the sensing transistor N0 is set to a low level. At the same time, the second terminal (i.e., the source) of the sensing transistor N0 is also set to a low level through the third detection unit 123. Here, combined with the fact that the control terminal of the sensing transistor N0 is in a high level state determined by the noise reduction unit 300 circuit itself, the sensing transistor N0 is in a stress state of high Vgs and low Vds, which is completely consistent with the noise reduction transistor in operation, so as to achieve accurate aging simulation.

[0052] (2) During the node voltage extraction period T1 in the detection phase: its control state is consistent with that of the newspaper during the normal display period. The second control terminal SW2 of the external control device 200 outputs a low level, the third control terminal SW3 outputs a high level, the second transistor N2 is turned off, and the third transistor N3 is turned on. That is to say, when extracting the noise reduction control node voltage, the bias state of the sensing transistor N0 is kept unchanged to ensure the continuity of the aging simulation and avoid the introduction of measurement error by the bias change.

[0053] (3) During the threshold voltage extraction period T2 in the detection phase (corresponding to the charge accumulation sub-period t1): the second control terminal SW2 of the external control device 200 outputs a high level, the third control terminal SW3 of the external control device 200 outputs a low level, the second transistor N2 is turned on and the third transistor N3 is turned off, and the first terminal (drain) of the sensing transistor N0 is connected to the power supply voltage (such as VDD, +5V or +8V) to provide the necessary voltage bias for the sensing transistor N0 to generate the driving current.

[0054] like Figure 5 As shown, the third detection unit 123 includes a fourth transistor N4, an amplifier OP, a capacitor C, a fifth transistor N5, and a sixth transistor N6. Specifically, the control terminal of the fourth transistor N4 is connected to the fourth control terminal SW4 of the external control device 200, and the first terminal of the fourth transistor N4 is connected to the second terminal of the sensing transistor N0. The first input terminal of the amplifier OP is connected to the low-level terminal VSS, and the second input terminal of the amplifier OP is connected to the second terminal of the fourth transistor N4. The first terminal of the capacitor C is connected to the second input terminal of the amplifier OP, and the second terminal of the capacitor C is connected to the output terminal of the amplifier OP. The control terminal of the fifth transistor N5 is connected to the fifth control terminal SW5 of the external control device 200, the first terminal of the fifth transistor N5 is connected to the second input terminal of the amplifier OP, and the second terminal of the fifth transistor N5 is connected to the output terminal of the amplifier OP. The control terminal of the sixth transistor N6 is connected to the sixth control terminal SW6 of the external control device 200, the first terminal of the sixth transistor N6 is connected to the output terminal of the amplifier OP, and the second terminal of the sixth transistor N6 serves as the output terminal of the third detection unit 123.

[0055] This combination Figure 6 The timing diagram shown below provides a detailed explanation of the working principle of the third detection unit 123 in this embodiment: (1) During the normal display period (voltage follower mode): the fourth control terminal SW4 outputs a high level, the fifth control terminal SW5 outputs a high level, and the sixth control terminal SW6 outputs a low level, thereby turning on the fourth transistor N4, turning on the fifth transistor N5, and turning off the sixth transistor N6. Due to the forced short circuit of the fifth transistor N5, the amplifier OP works in the voltage follower state. According to the virtual short characteristic of the op-amp, the potential of the inverting input terminal is forced to follow the potential of the non-inverting input terminal. Therefore, the second terminal of the sensing transistor N0 is clamped to a low level by the feedback mechanism of the amplifier OP.

[0056] (2) During the node voltage extraction period in the detection phase: the control state is the same as the normal display period. The fourth control terminal SW4 outputs a high level, the fifth control terminal SW5 outputs a high level and the sixth control terminal SW6 outputs a low level, so that the fourth transistor N4 is turned on, the fifth transistor N5 is turned on and the sixth transistor N6 is turned off; during the measurement of the voltage at point P, the bias state of the sensing transistor N0 is kept unchanged to avoid the source potential fluctuation affecting the gate-source voltage Vgs of the sensing transistor N0, thereby ensuring the accuracy of the voltage measurement at point P.

[0057] (3) During the threshold voltage extraction period in the detection phase, this period is further divided into two sub-periods: ① Charge accumulation sub-period t1: The fourth control terminal SW4 outputs a high level, the fifth control terminal SW5 outputs a low level, and the sixth control terminal SW6 outputs a low level. The conduction of the fourth transistor N4 maintains the connection between the second terminal of the sensing transistor N0 and the inverting input terminal of the amplifier OP. At this time, the amplifier OP and the capacitor C form an integrator (or current-to-voltage converter). The inverting input terminal of the amplifier OP becomes a virtual ground node. The current flowing from the second terminal of the sensing transistor N0 is injected into the capacitor C. The voltage rise ΔV across the capacitor C is directly proportional to the current of the sensing transistor N0, and the current... .

[0058] ② Voltage reading sub-period t2: The fourth control terminal SW4 outputs a low level, the fifth control terminal SW5 outputs a low level, and the sixth control terminal SW6 outputs a high level. The turn-off of the fourth transistor N4 physically disconnects the connection between the sensing transistor N0 and the integrator, locking the charge on capacitor C. The conduction of the sixth transistor N6 establishes a reading path between the output of amplifier OP and external control device 200. At this time, the charge on capacitor C is preserved due to the turn-off of the fourth transistor N4, and the voltage at the output of amplifier OP is Vout2 = VSS + ΔV. External control device 200 reads Vout2 and calculates the charging voltage by calculating ΔV = Vout2 - VSS. Combining the known t1 and C values, the charging voltage can be deduced. = C×ΔV / t1.

[0059] In summary, the collaborative working process of the first detection unit 121, the second detection unit 122, and the third detection unit 123 in this embodiment is as follows: (1) During the normal display stage: the first terminal (i.e., drain) of the sensing transistor N0 is set to a low level through the second detection unit 122, and the second terminal (source) of the sensing transistor N0 is set to a low level through the third detection unit 123. At this time, the control terminal (gate) of the sensing transistor N0 is in a high level state determined by the noise reduction unit 300 circuit itself, so that the sensing transistor N0 is in a stress state of high Vgs and low Vds, which is completely consistent with the noise reduction transistor in operation, and achieves accurate aging simulation.

[0060] (2) During the node voltage extraction period T1 in the detection phase: the first voltage Vout1 (i.e. Vp) on the noise reduction control node is extracted by the first detection unit 121. At this time, the second and third terminals of the sensing transistor N0 are still set to low level by the second detection unit 122 and the third detection unit 123, keeping the bias state of the sensing transistor N0 unchanged, ensuring the continuity of the aging simulation, and avoiding the introduction of measurement error by the bias change.

[0061] (3) Threshold voltage extraction period T2 during the detection phase: This period is further divided into two sub-phases: ① Charge accumulation sub-period (t1): The first terminal of sensing transistor N0 is connected to the power supply terminal VDD through the second detection unit 122, providing a bias voltage for the driving current generated by sensing transistor N0; at the same time, the driving current flowing out from the second terminal of sensing transistor N0... The capacitor C of the third detection unit 123 is charged.

[0062] ② Voltage reading sub-period; then the second voltage Vout2 across capacitor C is obtained through the third detection unit 123.

[0063] (4) Parameter calculation and dynamic compensation: The external control device 200 (such as a timing controller) performs the following calculations and compensations based on the read voltage: ①Based on the second voltage Vout2, calculate the charging voltage ΔV on capacitor C = Vout2 - VSS.

[0064] ② Combining the known charge accumulation time t1 and capacitance C, deduce the driving current of sensing transistor N0 in the current state: = C×ΔV / t1.

[0065] ③ The driving current The electrical parameters of the sensing transistor N0 satisfy the following relationship: Where Vp is the first voltage Vout1, W, L, and C_OX are known device parameters, and Vth and μ are variables that drift with aging.

[0066] ④ Compensation execution: The external control device 200 internally stores the key parameters of the noise reduction unit 300 in the initial (unaged) state, such as the initial P-point voltage and the initial current I0 of the sensing transistor N0. The external control device 200 compares the current driving current with the initial current I0; if <I0, it indicates that the comprehensive driving ability of the noise reduction unit 300 (including the drift of the Darlington circuit output Vp and the threshold voltage drift of the noise reduction transistor) has decreased. At this time, the external control device 200 will increase the driving voltage supplied to the noise reduction unit 300 (such as Figure 2 the LC voltage); the increase in the LC voltage will have a dual effect: 1) directly increase the P-point voltage Vp output by the noise reduction control unit; 2) increase its driving current by increasing the gate-source overdrive voltage (Vp - VSS - Vth) of the sensing transistor N0. Through closed-loop control, the LC voltage is continuously adjusted until the currently detected driving current returns to the preset level of the initial current I0. At this time, the equivalent driving ability of the noise reduction unit 300 is compensated back to the initial state, thus offsetting the performance decline caused by aging.

[0067] Figure 7 The circuit schematic diagram of the second detection circuit 100 provided by the embodiment of the present application is shown; Figure 7 The difference between the detection circuit 100 shown and Figure 5 the detection circuit 100 shown is that: the circuit structures and driving timings of the second detection unit 122 and the third detection unit 123 are different; specifically as Figure 7 shown: The second detection unit 122 includes a second transistor N2 and a third transistor N3; the control end of the second transistor N2 is connected to the second control end SW2 of the external control device 200, the first end of the second transistor N2 is connected to the control end of the sensing transistor N0, and the second end of the second transistor N2 is connected to the first end of the sensing transistor N0; the control end of the third transistor N3 is connected to the third control end SW3 of the external control device 200, the first end of the third transistor N3 is connected to the second end of the second transistor N2, and the second end of the third transistor N3 is connected to the low-level end VSS.

[0068] It should be noted that a frame of the picture includes a scanning period and a blanking period. The detection stage of this embodiment is located in the blanking period. As Figure 8 shown, the blanking period of this embodiment includes a first normal display period T0, a detection stage, and a second normal display period T3. The detection stage further includes a node voltage extraction period T1 and a threshold voltage extraction period T2.

[0069] Herein, in combination with Figure 8The timing diagram shown below provides a detailed explanation of the working principle of the second detection unit 122 in this embodiment: (1) During the normal display phase (i.e., the non-detection phase, or the aging simulation period): the second control terminal SW2 of the external control device 200 outputs a low level, the third control terminal SW3 outputs a high level, the second transistor N2 is turned off, and the third transistor N3 is turned on, so that the first terminal (drain) of the sensing transistor N0 is set to a low level. At the same time, the second terminal (i.e., the source) of the sensing transistor N0 is also set to a low level through the third detection unit 123. Here, combined with the control terminal of the sensing transistor N0 being in a high-level state, the sensing transistor N0 is in a stress state of high Vgs and low Vds, which is completely consistent with the noise reduction transistor in operation, thus achieving accurate aging simulation.

[0070] (2) During the node voltage extraction period in the detection phase: the second control terminal SW2 of the external control device 200 outputs a low level, the third control terminal SW3 outputs a high level, the second transistor N2 is turned off, and the third transistor N3 is turned on. That is to say, when extracting the noise reduction control node voltage, the bias state of the sensing transistor N0 is kept unchanged to ensure the continuity of the aging simulation and avoid the introduction of measurement error by the bias change.

[0071] (3) During the threshold voltage extraction period in the detection phase: the second control terminal SW2 of the external control device 200 outputs a high level, the third control terminal SW3 of the external control device 200 outputs a low level, the second transistor N2 is turned on and the third transistor N3 is turned off. Due to the short circuit of the second transistor N2, the control terminal and the first terminal (drain) of the sensing transistor N0 are forced to be at the same potential (both are the voltage Vp at point P). According to the physical characteristics of MOSFET, when the gate and drain are shorted and a positive bias is applied to the source, the transistor automatically enters the saturation region and behaves as a diode connection device. At this time, the source voltage (Vs) will be automatically adjusted so that it eventually stabilizes at Vgs ≈ Vth.

[0072] like Figure 7 As shown, the third detection unit 123 in this embodiment includes a fourth transistor N4 and a fifth transistor N5; the control terminal of the fourth transistor N4 is connected to the fourth control terminal SW4 of the external control device 200, the first terminal of the fourth transistor N4 is connected to the low-level terminal VSS, and the second terminal of the fourth transistor N4 is connected to the second terminal of the sensing transistor N0; the control terminal of the fifth transistor N5 is connected to the fifth control terminal SW5 of the external control device 200, the first terminal of the fifth transistor N5 is connected to the second terminal of the fourth transistor N4, and the second terminal of the fifth transistor N5 serves as the output terminal of the third detection unit 123.

[0073] This combination Figure 8The timing diagram shown below provides a detailed explanation of the working principle of the third detection unit 123 in this embodiment: It should be noted that the specific working principle of the third detection unit 123 in this embodiment is as follows: (1) During the normal display period (aging simulation period): the fourth control terminal SW4 outputs a high level and the fifth control terminal SW5 outputs a low level, thereby turning on the fourth transistor N4 and turning off the fifth transistor N5. The second terminal of the sensing transistor N0 is clamped at a low level by the fourth transistor N4 which is turned on.

[0074] (2) During the node voltage extraction period in the detection phase: the fourth control terminal SW4 outputs a high level and the fifth control terminal SW5 outputs a low level. During the node voltage measurement, the bias state of the sensing transistor N0 remains unchanged to avoid the source potential fluctuation affecting the gate-source voltage Vgs of the sensing transistor N0, thereby ensuring the accuracy of the voltage measurement at point P.

[0075] (3) During the threshold voltage extraction period of the detection phase, the fourth control terminal SW4 outputs a low level and the fifth control terminal SW5 outputs a high level. The fourth transistor N4 is turned off, causing the source of the sensing transistor N0 to float. The fifth transistor N5 is turned on to establish a reading path. The external control device 200 obtains the second voltage Vout2 of the source of the sensing transistor N0 through the turned-on fifth transistor N5.

[0076] In summary, the collaborative working process of the first detection unit 121, the second detection unit 122, and the third detection unit 123 in this embodiment is as follows: (1) During the normal display stage: the first terminal (i.e., drain) of the sensing transistor N0 is set to a low level through the second detection unit 122, and the second terminal (source) of the sensing transistor N0 is set to a low level through the third detection unit 123. At this time, the control terminal (gate) of the sensing transistor N0 is in a high level state determined by the noise reduction unit 300 circuit itself, so that the sensing transistor N0 is in a stress state of high Vgs and low Vds, which is completely consistent with the noise reduction transistor in operation, and achieves accurate aging simulation.

[0077] (2) During the node voltage extraction period in the detection phase: the first voltage Vout1 (i.e. Vp) on the noise reduction control node is extracted by the first detection unit 121. At this time, the drain and source of the sensing transistor N0 are still set to low level by the second detection unit 122 and the third detection unit 123, keeping the bias state of the sensing transistor N0 unchanged, ensuring the continuity of the aging simulation, and avoiding measurement errors introduced by the bias change.

[0078] (3) During the threshold voltage extraction period of the detection phase: the control terminal and the first terminal of the sensing transistor N0 are shorted through the second detection unit 122, so that the sensing transistor N0 forms a diode connection device. At the same time, the second voltage Vout2 output from the source of the sensing transistor N0 is obtained through the third detection unit 123.

[0079] (4) Parameter calculation: The external control device 200 (such as a timing controller) directly calculates the current threshold voltage Vth = Vout1 of the sensing transistor N0 based on the first and second voltages read. Vout2. The external control device 200 internally stores key parameters of the noise reduction unit 300 in its initial (unaged) state, including the initial P-point voltage V. P0 and the initial threshold voltage V of sensing transistor N0 th0 By comparison, the threshold voltage drift ΔVth = Vth - V can be obtained. th0 And the voltage drift at point P, ΔVp = Vout1 - V P0 .

[0080] (5) Compensation Execution: The external control device 200 calculates the required total compensation voltage ΔV_comp = ΔVp + ΔVth based on the aforementioned drift amount. Subsequently, the control device increases the driving voltage (such as LC voltage) supplied to the noise reduction unit 300. The increase in LC voltage has a dual effect: ① It directly compensates for the output drift of the noise reduction control unit itself, causing the voltage at point P to increase by ΔVp; ② It indirectly compensates for the decrease in driving capability caused by the increase in Vth (ΔVth) by increasing the gate-source overdrive voltage (Vgs) of the sensing transistor N0 (and the target transistor). Through closed-loop control, the LC voltage is continuously adjusted until the combined effect of Vth and Vp obtained by real-time detection and calculation meets the noise reduction capability requirements, or the voltage at point P reaches V_comp = ΔVp. P0 The target value of +ΔV_comp is used to offset the performance degradation caused by aging.

[0081] Figure 9 The diagram shown is a flowchart illustrating a detection method provided in an embodiment of this application; as follows: Figure 9 As shown, the detection method of this embodiment is applied to the detection circuit shown in the above embodiment, and specifically includes the following steps: Step S100: In the non-detection phase, the voltage at each terminal of the sensing module is controlled by the detection module to simulate the voltage stress borne by the target transistor in the noise reduction unit.

[0082] Step S200: In the detection phase, at least one voltage parameter output by the sensing module is detected by the detection module, so that the external control device compensates for the threshold voltage drift of the transistor in the noise reduction unit according to the at least one voltage parameter.

[0083] It should be noted that the working principle of the detection method provided in this embodiment is the same as that of the detection circuit described above, and will not be repeated here.

[0084] Figure 10 The diagram shown is a structural schematic of a display panel provided in an embodiment of this application; as follows: Figure 10 As shown, the display panel includes the detection circuit and gate driving circuit shown in the above embodiment; specifically, the gate driving circuit includes N cascaded gate driving modules, each gate driving module having a noise reduction unit; wherein, the sensing module of the detection circuit is disposed in the noise reduction unit of any one of the gate driving modules.

[0085] It should be noted that the sensing module can be located within the final-level dummy GOA module. This final-level dummy GOA module is the first-level GOA module closest to the external control device (such as a timing controller or COF chip). Furthermore, the sensing module is electrically connected to the detection module via three detection lines L, such as... Figure 10 As shown, since the sensing module is only placed in the dummy GOA and does not generate transmission or output, it has virtually no impact on the transmission and output of the normal GOA. Furthermore, since it is located on the source side, its three external detection lines L only need to occupy a small portion of the array wiring area, and there is no additional requirement for the bezel width. This enables online monitoring and real-time compensation of the threshold voltage drift of the transistors in the noise reduction unit without increasing the chip area or affecting the original reliability of the circuit, thus maintaining and improving the long-term noise reduction stability of the noise reduction unit.

[0086] Furthermore, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0087] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0088] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A detection circuit, characterized by, The application is applied to a gate drive circuit with a noise reduction unit, and the detection circuit comprises: a sensing module arranged in the noise reduction unit and electrically connected to a noise reduction control node of the noise reduction unit; a detection module connected to the sensing module and an external control device, configured to control voltages of each end of the sensing module to simulate voltage stress borne by a target transistor in the noise reduction unit in a non-detection stage, and detect at least one voltage parameter output by the sensing module in a detection stage, so that the external control device compensates threshold voltage drift of transistors in the noise reduction unit according to the at least one voltage parameter.

2. The detection circuit of claim 1, wherein The detection module comprises: a first detection unit connected to a control end of the sensing module and the external control device, configured to acquire a first voltage on the noise reduction control node in the detection stage; a second detection unit connected to a first end of the sensing module and the external control device, configured to set the first end voltage of the sensing module to a low level in the non-detection stage; a third detection unit connected to a second end of the sensing module and the external control device, configured to set the second end voltage of the sensing module to a low level in the non-detection stage, and acquire a second voltage output by the sensing module in the detection stage; wherein the at least one voltage parameter comprises the first voltage and the second voltage.

3. The detection circuit of claim 2, wherein, The sensing module comprises a sensing transistor, a control end of the sensing transistor is connected to the noise reduction control node, and device parameters of the sensing transistor are the same as those of a noise reduction transistor in the noise reduction unit.

4. The detection circuit of claim 3, wherein, The first detection unit comprises: a first transistor, a control end of the first transistor is connected to a first control end of the external control device, a first end of the first transistor is connected to a control end of the sensing transistor, and a second end of the first transistor serves as an output end of the first detection unit.

5. The detection circuit of claim 3, wherein, The second detection unit comprises: a second transistor, a control end of the second transistor is connected to a second control end of the external control device, a first end of the second transistor is connected to a first end of the sensing transistor, and a second end of the second transistor is connected to a power supply end; a third transistor, a control end of the third transistor is connected to a third control end of the external control device, a first end of the third transistor is connected to a first end of the second transistor, and a second end of the third transistor is connected to a low level end.

6. The detection circuit of claim 3, wherein, The third detection unit comprises: a fourth transistor, a control end of the fourth transistor is connected to a fourth control end of the external control device, and a first end of the fourth transistor is connected to a second end of the sensing transistor; an amplifier, a first input end of the amplifier is connected to a low level end, and a second input end of the amplifier is connected to a second end of the fourth transistor; a capacitor, a first end of the capacitor is connected to the second input end of the amplifier, and a second end of the capacitor is connected to an output end of the amplifier. a fifth transistor, a control terminal of the fifth transistor being connected with a fifth control terminal of the external control device, a first terminal of the fifth transistor being connected with a second input terminal of the amplifier, and a second terminal of the fifth transistor being connected with an output terminal of the amplifier; a sixth transistor, a control terminal of the sixth transistor being connected with a sixth control terminal of the external control device, a first terminal of the sixth transistor being connected with the output terminal of the amplifier, and a second terminal of the sixth transistor being used as an output terminal of the third detection unit.

7. The detection circuit of claim 3, wherein, The second detection unit comprises: a second transistor, a control terminal of the second transistor being connected with a second control terminal of the external control device, a first terminal of the second transistor being connected with the control terminal of the sensing transistor, and a second terminal of the second transistor being connected with the first terminal of the sensing transistor; a third transistor, a control terminal of the third transistor being connected with a third control terminal of the external control device, a first terminal of the third transistor being connected with the second terminal of the second transistor, and a second terminal of the third transistor being connected with a low voltage terminal.

8. The detection circuit of claim 3, wherein, The third detection unit comprises: a fourth transistor, a control terminal of the fourth transistor being connected with a fourth control terminal of the external control device, a first terminal of the fourth transistor being connected with the low voltage terminal, and a second terminal of the fourth transistor being connected with a second terminal of the sensing transistor; a fifth transistor, a control terminal of the fifth transistor being connected with a fifth control terminal of the external control device, a first terminal of the fifth transistor being connected with the second terminal of the fourth transistor, and a second terminal of the fifth transistor being used as the output terminal of the third detection unit.

9. A detection method, comprising: The detection method is applied to the detection circuit according to any one of claims 1-8, and the detection method comprises: in a non-detection stage, controlling voltages of each terminal of the sensing module by the detection module to simulate voltage stress borne by a target transistor in the noise reduction unit; in a detection stage, detecting at least one voltage parameter output by the sensing module by the detection module, so that the external control device compensates threshold voltage drift of transistors in the noise reduction unit according to the at least one voltage parameter.

10. A display panel, characterized by, The display panel comprises: the detection circuit according to any one of claims 1-8; a gate drive circuit, the gate drive circuit comprising N cascaded gate drive modules, each gate drive module having a noise reduction unit; wherein the sensing module of the detection circuit is arranged in the noise reduction unit in any one of the gate drive modules.

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