Display device and display driving method

Abstract

The invention discloses a display device and a display driving method. A time sequence control module judges that a display picture of a current frame of a display panel is one of a light-load display picture and a heavy-load display picture, and when a display picture of a to-be-displayed frame is the other one of the light-load display picture and the heavy-load display picture, the time sequence control module controls the display panel to display the light-load display picture and the heavy-load display picture; and controlling the generated enable signal to have an effective level at a vertical blanking interval between the current frame and the frame to be displayed, so that the power management module adjusts a compensation value applied to the analog power supply voltage according to the effective level of the enable signal at the vertical blanking interval, the voltage offset of the generated analog power supply voltage relative to the reference voltage in at least one of the starting time period and the ending time period of the vertical blanking interval is reduced, so that the stability of the analog power supply voltage in the time period where ripples are easy to generate is improved, and the ripples of the analog power supply voltage are reduced. And the problem of water ripples or crosstalk occurring during display of the display panel is solved.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display device and a display driving method. Background Technology

[0002] The source driver chip receives the analog power supply voltage to generate a gamma voltage, and then provides a data signal to the display panel based on the gamma voltage. This allows the display panel to charge multiple sub-pixels within a frame, achieving different grayscale levels. During the vertical blanking interval between frames, the sub-pixels maintain the display state of the previous frame. Therefore, charging multiple sub-pixels within a frame de-loads the analog power supply voltage. During the vertical blanking interval, not charging multiple sub-pixels prevents this de-loading of the analog power supply voltage. When entering a vertical blanking interval from a heavily loaded display frame, or vice versa, the analog power supply voltage may experience a slow response due to the instantaneous switch from light to heavy load. This results in significant ripple in the analog power supply voltage, causing water ripple or crosstalk issues on the display panel. Summary of the Invention

[0003] This application provides a display device and a display driving method to reduce the ripple of analog power supply voltage and improve the water ripple or crosstalk problems that occur when the display panel is displayed.

[0004] This application provides a display device, including a display panel, a source driver module, a timing control module, and a power management module. The display panel includes multiple sub-pixels. The source driver module is electrically connected to the multiple sub-pixels and is configured to receive an analog power supply voltage to generate multiple data signals and output them to the corresponding sub-pixels. The timing control module is configured to control a generated enable signal to have an effective level during the vertical blanking interval between the current frame and the frame to be displayed when it is determined that the display screen of the current frame of the display panel is either a light-load display screen or a heavy-load display screen, and the display screen of the frame to be displayed is either a light-load display screen or a heavy-load display screen. The power management module is electrically connected to the source driver module and the timing control module and is configured to adjust the compensation value applied to the analog power supply voltage according to the effective level of the enable signal during the vertical blanking interval, so as to reduce the voltage offset of the generated analog power supply voltage relative to a reference voltage during at least one of the start and end periods of the vertical blanking interval.

[0005] This application also provides a display driving method, comprising: when it is determined that the displayed image of the current frame of the display panel is one of a light-load display image and a heavy-load display image, and the displayed image of the frame to be displayed is the other of a light-load display image and a heavy-load display image, controlling an enable signal to have an effective level during a vertical blanking interval between the current frame and the frame to be displayed. During the vertical blanking interval, adjusting a compensation value applied to the analog power supply voltage according to the effective level of the enable signal, so as to reduce the voltage offset of the generated analog power supply voltage relative to a reference voltage during at least one time period during the end period of the current frame and the beginning period of the frame to be displayed. Wherein, multiple sub-pixels of the display panel are displayed in each frame according to multiple data signals, and the voltages of the multiple data signals are generated based on the image data of each frame and the analog power supply voltage.

[0006] In the above technical solution, when the timing control module determines that the current frame of the display panel is either a light-load display or a heavy-load display, and the frame to be displayed is either a light-load display or a heavy-load display, the generated enable signal is controlled to have an effective level in the vertical blanking interval between the current frame and the frame to be displayed. This allows the power management module to adjust the compensation value applied to the analog power supply voltage according to the effective level of the enable signal during the vertical blanking interval. This reduces the voltage offset of the generated analog power supply voltage relative to the reference voltage during at least one period in the beginning and end of the vertical blanking interval, thereby improving the stability of the analog power supply voltage during periods prone to ripple. This helps reduce the amplitude of the ripple, which in turn helps improve the water ripple or crosstalk problems that occur when the display panel is displaying. Attached Figure Description

[0007] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0008] Figure 1 This is a schematic diagram of the structure of the display device provided in the embodiments of this application; Figure 2 A schematic block diagram of the power management module provided in an embodiment of this application; Figure 3 Circuit diagrams of the boost unit and compensation adjustment unit provided in the embodiments of this application; Figure 4 The signal timing diagrams for the enable signal and analog power supply voltage provided in the embodiments of this application; Figures 5A-5B Simulation comparison diagram of simulated power supply voltage provided for embodiments of this application; Figure 6 A flowchart of a display driving method provided in an embodiment of this application.

[0009] The realization of the objectives, functional features and advantages of the embodiments of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0010] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0011] It should be noted that the electrical connection referred to in this application can include both direct and indirect connections. Indirect connections can include connections between connected modules, devices, and nodes achieved through electrical components, wired or wireless media, etc. An electrical connection can refer to a physically existing connection or a connection established through signals.

[0012] Furthermore, descriptions involving "first," "second," etc., in the embodiments of this application are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the various technical features in this application can be applied to achieve different combinations, and are not limited to the technical solutions formed by the combinations listed in the embodiments. Technical solutions between different embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed in this application. The terms "optionally" and "in some embodiments" used in this application indicate that the technical content they refer to can be selectively configured.

[0013] Furthermore, the descriptions provided in the Background section should not be presumed to be prior art simply because they are mentioned in or associated with the description in the Background section. The Background section may include information describing one or more aspects of the subject matter, and the description in this section does not limit the invention.

[0014] The display panel continuously switches between frames and vertical blanking intervals during operation. The sub-pixels of the display panel are charged only within a frame, not during the vertical blanking interval. Therefore, the source driver module, which charges the sub-pixels, experiences a significant load during the time period corresponding to a frame. During the time period corresponding to the vertical blanking interval, the load on the source driver module decreases. The source driver module generates multiple data signals based on the analog power supply voltage to charge multiple sub-pixels. The increased load on the source driver module causes a drain of the analog power supply voltage. Conversely, a decreased load on the source driver module reduces the drain of the analog power supply voltage. Therefore, the analog power supply voltage switches between heavy and light loads corresponding to the switching between frames and the vertical blanking interval.

[0015] When the display panel transitions from a frame of heavy-load display to a vertical blanking interval, or from a blanking interval to a frame of heavy-load display, the load corresponding to the analog power supply voltage may experience a slow response due to the instantaneous switching between light and heavy loads. This results in a large ripple in the analog power supply voltage, causing water ripples or crosstalk issues to appear on the display panel.

[0016] Therefore, this application provides a display device and a display driving method to reduce the ripple of analog power supply voltage and improve the water ripple or crosstalk problems that occur when the display panel is displayed.

[0017] like Figure 1 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. This application discloses a display device including a display panel 10, a source driving module 20, a timing control module 30, and a power management module 40.

[0018] The display panel 10 includes multiple sub-pixels Spx, which are used to implement the display function of the display panel 10.

[0019] The source drive module 20 is electrically connected to multiple sub-pixels Spx. The source drive module 20 is configured to receive an analog power supply voltage AVDD to generate multiple data signals and output them to the corresponding sub-pixels Spx.

[0020] In some embodiments, the source drive module 20 is configured to generate multiple gamma-binding point voltages based on the analog power supply voltage AVDD, so as to generate multiple data signals based on the multiple gamma-binding point voltages. The display panel 10 may also include data lines DL and scan lines SL, such as... Figure 1 As shown, the data line DL is used to transmit data signals, the scan line SL is used to transmit scan signals, and the sub-pixel Spx receives data signals according to the corresponding scan signals to achieve charging of the sub-pixel Spx.

[0021] The timing control module 30 is configured to control the generated enable signal TRE_EN to have an effective level in the vertical blanking interval Vbl between the current frame Fc and the frame to be displayed Fd when it is determined that the display screen of the current frame Fc of the display panel 10 is either a light-load display screen or a heavy-load display screen, and the display screen of the frame to be displayed Fd is either a light-load display screen or a heavy-load display screen.

[0022] The power management module 40 is electrically connected to the timing control module 30. The power management module 40 is configured to adjust the compensation value applied to the analog power supply voltage AVDD during the vertical blanking interval Vbl according to the effective level of the enable signal TRE_EN. This reduces the voltage offset of the generated analog power supply voltage AVDD relative to the reference voltage Vref during at least one period in the beginning and end of the vertical blanking interval Vbl. This improves the stability of the analog power supply voltage AVDD during periods prone to ripple, helps reduce the amplitude of ripple, and further helps improve the water ripple and crosstalk problems that occur when the display panel 10 is displayed.

[0023] Optionally, the source driver module 20 can be a source driver chip, the timing control module 30 can be a timing controller, and the power management module 40 can be a power management chip.

[0024] It should be noted that the form presented by the overloaded display screen varies depending on the type of display panel 10. In some embodiments, the overloaded display screen can be a display screen with a large grayscale jump variable. Here, a large grayscale jump variable can mean that the grayscale jump variable obtained by comparing two adjacent display frames by region is greater than a preset value, or it can mean that the grayscale jump variable corresponding to adjacent sub-pixels Spx in the same display frame is greater than a preset value. The preset value can be greater than or equal to 127. The grayscale comparison between two adjacent display frames by region can be performed by comparing the positions of sub-pixels Spx one-to-one, or by comparing the average grayscale corresponding to multiple adjacent sub-pixels Spx. The current frame Fc and the frame to be displayed Fd are two adjacent frames displayed by the display panel 10.

[0025] In some embodiments, the timing control module 30 determines whether the load types of the current frame Fc and the frame Fd to be displayed are consistent based on the image data corresponding to the display screen of the current frame Fc and the image data corresponding to the display screen of the frame Fd to be displayed. The image data may be provided by at least one of the central processing unit and the graphics processing unit.

[0026] When it is determined that the display screen of the current frame Fc and the display screen of the frame to be displayed Fd are load screens of different load types, the enable signal TRE_EN can be controlled to be active at the vertical blanking interval Vbl to adjust the compensation value applied to the analog power supply voltage AVDD.

[0027] It should be noted that the reference voltage Vref can refer to the voltage that the simulated power supply voltage AVDD is expected to reach. Adjusting the compensation value applied to the simulated power supply voltage AVDD can mean that the voltage value corresponding to the actual simulated power supply voltage changes after adjustment. For example, in some embodiments, adjusting the compensation value applied to the simulated power supply voltage AVDD can increase or decrease the voltage value corresponding to the simulated power supply voltage AVDD.

[0028] It should be noted that the start time of the blanking interval can refer to the period between the end time of the current frame Fc and the time when the analog power supply voltage AVDD recovers and stabilizes. The end time of the vertical blanking interval Vbl can be determined based on the frame start signal STV. For example, in some embodiments, the period between the start time of the effective pulse of the frame start signal STV and the start time of the frame to be displayed Fd corresponds to the end time of the vertical blanking interval Vbl. In some embodiments, the period between the start time of the effective pulse of the frame start signal STV and the time when the analog power supply voltage AVDD recovers and stabilizes corresponds to the end time of the vertical blanking interval Vbl. The frame start signal STV can be output by the level conversion circuit controlled by the timing control module 30.

[0029] Optionally, the display device may further include a gate driving circuit 50, a first circuit board 60, a control circuit board 70, and a main control circuit board, such as... Figure 1 As shown. The gate drive circuit 50 generates scan signals. The first circuit board 60 is electrically connected to the display panel 10, the control circuit board 70 is electrically connected to the first circuit board 60, and the main control circuit board is electrically connected to the control circuit board 70. At least one of the central processing unit and the graphics processor may be located on the main control circuit board. The timing control module 30 and the power management module 40 may be located on the control circuit board 70. The timing control module 30 and the power management module 40 are electrically connected to the gate drive circuit 50 and the source drive module 20 through the first circuit board 60.

[0030] In some embodiments, the first circuit board 60 and the source drive module 20 and the gate drive circuit 50 can be electrically connected through devices such as flexible circuit boards, and the control circuit board 70 can be electrically connected to the first circuit board 60 and the main control circuit board through devices such as flexible circuit boards.

[0031] Figure 2 The schematic diagram of the power management module provided in the embodiment of this application shows that, in order to adjust the compensation value of the analog power supply voltage AVDD, the power management module 40 includes a boost unit 401 and a compensation adjustment unit 402.

[0032] The boost unit 401 is electrically connected to the first input terminal and the signal output terminal of the power management module 40. The first input terminal is configured to receive the input voltage VIN, and the signal output terminal is configured to output the analog power supply voltage AVDD.

[0033] The compensation adjustment unit 402 is electrically connected to the boost unit 401 and the timing control module 30. The compensation adjustment unit 402 is configured to control the boost ratio of the boost unit 401 according to the enable signal TRE_EN and the feedback signal, so as to control the compensation value applied to the analog power supply voltage AVDD. The feedback signal is the analog power supply voltage AVDD output from the signal output terminal.

[0034] Optionally, the boost ratio of the boost unit 401 can be adjusted by the action of at least one of the feedback signal and the enable signal TRE_EN, thereby correspondingly adjusting the compensation value applied to the analog power supply voltage AVDD. That is, since the analog power supply voltage AVDD output from the signal output terminal is used as the feedback signal, a change in the analog power supply voltage AVDD output from the signal output terminal will cause a corresponding change in the boost ratio of the boost unit 401, thereby adjusting the compensation value applied to the analog power supply voltage AVDD accordingly. When the enable signal TRE_EN is active, the ratio of the boost unit 401 can also be adjusted, so that the compensation value applied to the analog power supply voltage AVDD can also be adjusted according to the enable signal TRE_EN.

[0035] Optionally, in order to control the boost ratio of the boost unit 401 and output the analog power supply voltage AVDD, the boost unit 401 may include a first energy storage element, a first switching element, an isolation element, and a second energy storage element.

[0036] The first energy storage element is electrically connected between the first input terminal and the first node No.1.

[0037] The first switching element is electrically connected between the first node No1 and the ground terminal GND, and the first switching element is configured to control the on / off state of the current path between the first node No1 and the ground terminal GND.

[0038] An isolation element is electrically connected between the first node No1 and the signal output terminal. The isolation element is configured to disconnect the current path between the first node No1 and the signal output terminal during the period when the first switching element connects the current path between the first node No1 and the ground terminal GND; and to connect the current path between the first node No1 and the signal output terminal during the period when the first switching element disconnects the current path between the first node No1 and the ground terminal GND.

[0039] The second energy storage element is electrically connected between the signal output terminal and the ground terminal GND, and is configured to maintain the potential of the signal output terminal. The compensation adjustment unit 402 is configured to control the on-time of the first switching element based on the enable signal TRE_EN and the feedback signal, thereby controlling the boost ratio of the boost unit 401.

[0040] Figure 3 This is a circuit diagram of the boost unit and compensation adjustment unit provided in an embodiment of this application. For ease of understanding of the boost unit 401 of this application, [the following is a description of the circuit diagram]. Figure 3 Let's take an example to illustrate.

[0041] Optionally, the first energy storage element may include an inductor L, and the first energy storage element is configured to convert electrical energy provided by the input voltage VIN received at the first input terminal into magnetic energy for storage. The first energy storage element may also be configured to convert the stored magnetic energy into electrical energy to charge the second energy storage element.

[0042] Optionally, the first switching element may include a first transistor Ts1, the control terminal of the first transistor Ts1 is configured to be electrically connected to the compensation adjustment unit 402, the first source-drain terminal of the first transistor Ts1 is electrically connected to the first node No1, the second source-drain terminal of the first transistor Ts1 is electrically connected to the ground terminal GND, and the first transistor Ts1 is configured to connect or disconnect the current path between the first node No1 and the ground terminal GND.

[0043] Optionally, the isolation element may include an isolation diode Ld, the anode of which is electrically connected to the first node No1, and the cathode of which is electrically connected to the signal output terminal.

[0044] Optionally, the second energy storage element may include a storage capacitor Cs, which is electrically connected between the signal output terminal and the ground terminal GND.

[0045] When the first switching element is turned on, the first energy storage element stores electrical energy, the isolation element disconnects the current path between the first node No1 and the signal output terminal, and the second energy storage element maintains the stability of the analog power supply voltage AVDD output by the signal output terminal. When the first switching element is turned off, the isolation element connects the current path between the first node No1 and the signal output terminal, the first energy storage element and the input voltage VIN signal output terminal provide electrical energy, and the energy stored in the first energy storage element charges the second energy storage element. Therefore, the amount of energy stored in the first energy storage element affects the potential of the first node No1, thereby affecting the analog power supply voltage AVDD output by the voltage management module. The amount of energy stored in the first energy storage element is controlled by the on-time of the first transistor Ts1. Therefore, to control the boost ratio of the boost unit 401, the on-time of the first switching element can be controlled.

[0046] In some embodiments, to enable the compensation adjustment unit 402 to control the conduction duration of the first switching element according to the enable signal TRE_EN and the feedback signal, the compensation adjustment unit 402 may include a parameter adjustment controller 4021, a feedback adjustment controller 4022, and a pulse output controller 4023, such as Figure 3 As shown.

[0047] The parameter adjustment controller 4021 is electrically connected between the second input terminal of the power management module 40 and the second node No2. The parameter adjustment controller 4021 is configured to control the voltage applied to the second node No2 according to the enable signal TRE_EN received at the second input terminal during the vertical blanking interval Vbl. In some embodiments, the second input terminal is electrically connected to the timing control module 30.

[0048] The feedback control controller 4022 is electrically connected between the signal output terminal and the second node No2. The feedback control controller 4022 is configured to adjust the voltage of the second node No2 according to the reference voltage Vref and the feedback signal.

[0049] The pulse output controller 4023 is electrically connected between the first switching element and the second node No2. The pulse output controller 4023 is configured to output a pulse width modulation signal according to the signal of the second node No2 to control the on-time of the first switching element.

[0050] Since both the parameter adjustment controller 4021 and the feedback adjustment controller 4022 can affect the voltage of the second node No2, the state of the pulse width modulation signal output by the pulse output controller 4023 can be adjusted according to the action of at least one of the enable signal TRE_EN and the feedback signal, thereby adjusting the conduction time of the first switching element and subsequently adjusting the boost ratio of the boost unit 401.

[0051] Optionally, the duty cycle of the pulse width modulation signal output by the pulse output controller 4023 can be adjusted according to the action of at least one of the enable signal TRE_EN and the feedback signal, so as to control the conduction time of the first switching element.

[0052] In some embodiments, when the enable signal TRE_EN has an effective level in the vertical blanking interval Vbl, the parameter adjustment controller 4021 is configured to apply a voltage to the second node No2 in the vertical blanking interval Vbl according to the effective level of the enable signal TRE_EN, so that the pulse output controller 4023 adjusts the duty cycle of the pulse width modulation signal according to the signal of the second node No2, thereby adjusting the on-time of the first switching element.

[0053] In other embodiments, the feedback regulation controller 4022 is configured to adjust the voltage of the second node No2 according to the reference voltage Vref and the feedback signal, so that the pulse output controller 4023 adjusts the duty cycle of the pulse width modulation signal according to the signal of the second node No2, thereby adjusting the on-time of the first switching element.

[0054] In some other embodiments, parameter adjustment controller 4021 is configured to apply a voltage to the second node No2 at the vertical blanking interval Vbl according to the effective level of the enable signal TRE_EN, and feedback adjustment controller 4022 is configured to adjust the voltage of the second node No2 according to the reference voltage Vref and the feedback signal, so that the signal of the second node No2 is affected by the enable signal TRE_EN and the feedback signal, thereby making the duty cycle adjustment of the pulse width modulation signal affected by the enable signal TRE_EN and the feedback signal.

[0055] Optionally, the parameter regulation controller 4021 may include a digital-to-analog converter, a voltage follower UF, and a second switching element, such as... Figure 3 As shown.

[0056] The digital-to-analog converter (DAC) is configured to output a first voltage signal. A voltage follower (UF) is electrically connected to the DAC and configured to output a second voltage signal based on the first voltage signal. A second switching element is electrically connected to the voltage follower (UF), the second node No2, and the second input terminal. The second switching element is configured to control the duration for which the second voltage signal is transmitted to the second node No2 based on an enable signal TRE_EN.

[0057] In some embodiments, the second switching element is a second transistor Ts2, the control terminal of the second transistor Ts2 is configured to receive an enable signal TRE_EN, the first source-drain terminal of the second transistor Ts2 is electrically connected to the voltage follower UF, and the second source-drain terminal of the second transistor Ts2 is electrically connected to the second node No2.

[0058] It should be noted that the voltage value of the first voltage signal can be set differently depending on factors such as the type of display panel 10, manufacturing process, and environment. In some embodiments, the voltage values ​​of the first voltage signal corresponding to different situations can be obtained during the debugging phase. The voltage values ​​of multiple first voltage signals can be stored in a storage unit so that different voltage values ​​of the first voltage signal can be switched and called according to different situations to meet the expected requirements of the display panel 10 for different applications. In some embodiments, the timing control module 30 is used to realize the switching and calling of different voltage values ​​of the first voltage signal.

[0059] In some embodiments, to reduce the effects of electrostatic discharge, the parameter adjustment controller 4021 may further include a first resistor R1 and a second resistor R2. The first resistor R1 is connected in series between the digital-to-analog converter and the voltage follower UF, and the second resistor R2 is connected in series between the voltage follower UF and the second switching element.

[0060] Optionally, the feedback regulation controller 4022 may include a voltage divider element, an operational amplifier OP, a third resistor R3, and a first capacitor C1.

[0061] The voltage divider element is electrically connected to the signal output terminal, the ground terminal GND, and the third node No3. The voltage divider element is configured to adjust the potential of the third node No3 according to the feedback signal.

[0062] Optionally, the voltage divider element may include a fourth resistor R4 and a fifth resistor R5, wherein the fourth resistor R4 is electrically connected between the third node No3 and the signal output terminal, and the fifth resistor R5 is electrically connected between the third node No3 and the ground terminal GND.

[0063] Operational amplifier OP is electrically connected between the third node No3 and the second node No2. Operational amplifier OP is configured to adjust the potential of the second node No2 according to the signal of the third node No3 and the reference voltage Vref.

[0064] Optionally, the non-inverting input of the operational amplifier OP is configured to receive a reference voltage Vref, and the inverting input of the operational amplifier OP is electrically connected to the third node No3.

[0065] The third resistor R3 and the first capacitor C1 are connected in series between the second node No2 and the ground terminal GND. Specifically, the third resistor R3 is electrically connected between the second node No2 and the first capacitor C1, and the first capacitor C1 is electrically connected between the third resistor R3 and the ground terminal GND.

[0066] The values ​​of the third resistor R3 and the first capacitor C1 affect the response speed of the pulse output controller 4023, thus influencing the instantaneously generated peak inductor current. Specifically, when the value of the first capacitor C1 is constant, a larger value of the third resistor R3 results in a faster response from the pulse output controller 4023, a larger instantaneously generated peak inductor current, and a larger increment of the analog power supply voltage AVDD relative to the reference voltage Vref at that instant. Conversely, when the value of the first capacitor C1 is constant, a smaller value of the third resistor R3 results in a slower response from the pulse output controller 4023, a smaller instantaneously generated peak inductor current, and a smaller increment of the analog power supply voltage AVDD relative to the reference voltage Vref at that instant. Finally, when the value of the third resistor R3 is constant, a smaller value of the first capacitor C1 results in a faster response from the pulse output controller 4023, a larger instantaneously generated peak inductor current, and a larger increment of the analog power supply voltage AVDD relative to the reference voltage Vref at that instant. When the value of the third resistor R3 remains constant, the larger the value of the first capacitor C1, the slower the response of the pulse output controller 4023, the smaller the instantaneously generated peak current of the inductor L, and the smaller the instantaneous increment of the analog power supply voltage AVDD relative to the reference voltage Vref. Therefore, adjusting the values ​​of the third resistor R3 and the first capacitor C1 can adjust the deviation between the analog power supply voltage AVDD and the reference voltage Vref.

[0067] It should be noted that the first transistor Ts1 and the second transistor Ts2 can be implemented as bipolar junction transistors (BJTs), field-effect transistors (FETs), or thin-film transistors (TFTs), respectively. When the transistors are implemented as FETs or TFTs, the control terminal can be the gate, the first source-drain terminal can be one of the source and drain, and the second source-drain terminal can be the other of the source and drain. When the transistors are implemented as bipolar junction transistors (BJTs), the control terminal can be the base, the first source-drain terminal can be one of the collector and emitter, and the second source-drain terminal can be the other of the collector and emitter. Each transistor can employ a single-gate or dual-gate design. The active layer of each transistor can include silicon semiconductor materials or oxide semiconductor materials. The silicon semiconductor materials include monocrystalline silicon, polycrystalline silicon, or amorphous silicon, etc. The oxide semiconductor materials include indium gallium zinc oxide or indium zinc oxide, etc.

[0068] It should be understood that, Figure 3 This design is merely illustrative and is not limited to the above-described design of the boost unit 401 and compensation adjustment unit 402. Those skilled in the art can still modify the design of the boost unit 401 and compensation adjustment unit 402 based on the disclosure of this application, implementing the functions of the boost unit 401 and compensation adjustment unit 402 in a simpler or more complex form or with a greater number of components. These components include, but are not limited to, transistors, capacitors, resistors, and other devices.

[0069] Please continue reading. Figure 1 When the display screen of the current frame Fc and the display screen of the frame to be displayed Fd are of the same type of load screen, the compensation value applied to the analog power supply voltage AVDD can be adjusted through the function of the enable signal TRE_EN, so as to reduce the frequency of the enable signal TRE_EN output by the timing control module 30, thereby reducing the power consumption of the timing control module 30.

[0070] In some embodiments, the timing control module 30 is configured to, when determining that the display screen of the current frame Fc and the display screen of the frame to be displayed Fd are of the same type of load screen, control the enable signal TRE_EN to be at an invalid level during the vertical blanking interval Vbl, so that the compensation value applied to the analog power supply voltage AVDD is not adjusted due to the influence of the enable signal TRE_EN. Here, the load screen is either a lightly loaded display screen or a heavily loaded display screen.

[0071] In some embodiments, the parameter adjustment controller 4021 is configured to stop applying voltage to the second node No2 at the vertical blanking interval Vbl based on the invalid level of the enable signal TRE_EN, so that the signal of the second node No2 is no longer affected by the enable signal TRE_EN, thereby making the conduction duration of the first switching element unaffected by the enable signal TRE_EN.

[0072] It should be noted that even when the compensation value of the analog power supply voltage AVDD is not adjusted due to the influence of the enable signal TRE_EN, the compensation value of the analog power supply voltage AVDD can still be adjusted due to the influence of the feedback signal.

[0073] Furthermore, to further reduce the power consumption of the timing control module 30, the enable signal TRE_EN can be kept at an invalid level for at least one frame's corresponding time period. During this time period, the boost ratio of the boost unit 401 can be adjusted through the feedback signal, thereby correspondingly adjusting the compensation value applied to the analog power supply voltage AVDD. This allows for compensation of fluctuations in the analog power supply voltage AVDD caused by load variations within a frame.

[0074] In some embodiments, during the current frame Fc and the frame to be displayed Fd, the timing control module 30 is configured to control the enable signal TRE_EN to be at an invalid level, and the parameter adjustment controller 4021 is configured to stop applying voltage to the second node No2 according to the enable signal TRE_EN, so as to adjust the boost ratio of the boost unit 401 through the action of the feedback signal during the time period corresponding to the current frame Fc and the frame to be displayed Fd, thereby correspondingly adjusting the compensation value applied to the analog power supply voltage AVDD.

[0075] Figure 4The following is a timing diagram of the enable signal and analog power supply voltage provided for embodiments of this application. For ease of understanding, [the following is used as a reference]. Figures 1-4 This application will be illustrated with examples. Wherein, Figure 4 The dashed line in the diagram represents the signal changes when the power management module 40 is not configured with parameter adjustment controller 4021. tsb represents the duration corresponding to the start of the vertical blanking interval Vbl when the power management module 40 is not configured with parameter adjustment controller 4021. teb represents the duration corresponding to the end of the vertical blanking interval Vbl when the power management module 40 is not configured with parameter adjustment controller 4021. STV represents the frame start signal; Comp_s represents the signal of the second node No2; the high-level period corresponding to the first signal P_GOA represents the sum of the periods when the multiple scan signals output by the gate drive circuit 50 have valid pulses sequentially, and the low-level period corresponding to the first signal P_GOA represents the period when the multiple scan signals output by the gate drive circuit 50 are all invalid. Therefore, the high-level period corresponding to the first signal P_GOA is the period corresponding to the frame, and the low-level period corresponding to the first signal P_GOA is the vertical blanking interval Vbl period.

[0076] The timing control module 30 determines whether the display screens of the current frame Fc and the display screens of the frame to be displayed Fd are of the same type of load screen based on the image data corresponding to the display screen of the current frame Fc and the image data corresponding to the display screen of the frame to be displayed Fd.

[0077] When it is determined that the display screen of the current frame Fc and the display screen of the frame to be displayed Fd are the same type of load screen, the control enable signal TRE_EN has an invalid level within the vertical blanking interval Vbl between the current frame Fc and the frame to be displayed Fd, so that the parameter adjustment controller 4021 stops applying voltage to the second node No2 in the vertical blanking interval Vbl according to the enable signal TRE_EN, and then the pulse output controller 4023 adjusts the conduction time of the first switching element only according to the effect of the feedback signal.

[0078] The feedback signal is the analog power supply voltage AVDD output from the signal output terminal. Therefore, changes in the analog power supply voltage AVDD will affect the potential of the third node No3. This causes the operational amplifier OP to calculate the deviation between the actual output analog power supply voltage AVDD and the reference voltage Vref based on the signal from the third node No3 and the reference voltage Vref. The operational amplifier OP then uses the third resistor R3 and the first capacitor C1 to filter and compensate the phase of the output signal of the operational amplifier OP, generating a stable and smooth signal for the second node No2. The pulse output controller 4023 compares the signal from the second node No2 with a reference signal (such as a sawtooth wave signal or a triangular wave signal). When the voltage value of the signal from the second node No2 is greater than the voltage value of the reference signal, it controls the first switching element to conduct. When the voltage value of the signal from the second node No2 is less than the voltage value of the reference signal, it controls the first switching element to turn off, thereby controlling the conduction time of the first switching element.

[0079] A longer on-time of the first switching element increases the energy stored in the first energy storage element. When supplying energy to the signal output terminal and charging the second energy storage element, this raises the potential at the signal output terminal, thus increasing the analog power supply voltage AVDD output. Conversely, a shorter on-time of the first switching element decreases the energy stored in the first energy storage element. When supplying energy to the signal output terminal and charging the second energy storage element, this lowers the potential at the signal output terminal, thus decreasing the analog power supply voltage AVDD output. Therefore, there will be a change in the analog power supply voltage AVDD relative to the reference voltage Vref, and this change in the analog power supply voltage AVDD corresponds to a change in the compensation value applied to the analog power supply voltage AVDD.

[0080] When it is determined that the display screen of the current frame Fc and the display screen of the frame to be displayed Fd are different types of load screens, the control enable signal TRE_EN has an effective level within the vertical blanking interval Vbl between the current frame Fc and the frame to be displayed Fd, so that the parameter adjustment controller 4021 applies a voltage to the second node No2 in the vertical blanking interval Vbl according to the enable signal TRE_EN, and then the pulse output controller 4023 adjusts the conduction time of the first switching element according to the feedback signal and the effect of the enable signal TRE_EN.

[0081] Taking the current frame Fc as a light-load display and the next frame Fd as a heavy-load display as an example, when the timing control module 30 determines that the current frame Fc is a light-load display and the next frame Fd is a heavy-load display, the timing control module 30 controls the enable signal TRE_EN to have an effective level within the vertical blanking interval Vbl between the current frame Fc and the next frame Fd, and controls the digital-to-analog converter to output a first voltage signal corresponding to this condition. The voltage follower UF generates a corresponding second voltage signal based on the first voltage signal, and the second switching element connects the current path between the second node No2 and the voltage follower UF according to the enable signal TRE_EN, so as to apply the second voltage signal to the second node No2. The signal at the second node No2 is affected by the feedback signal and the enable signal TRE_EN, making it the sum of the output signals of the feedback control controller 4022 and the parameter control controller 4021. This causes the pulse output controller 4023 to increase the duty cycle of its output pulse width control signal based on the feedback signal and the enable signal TRE_EN, thereby increasing the on-time of the first switching element and thus increasing the energy stored in the first energy storage element. When switching from the vertical blanking interval Vbl to the frame to be displayed Fd, the increment of the actual output analog power supply voltage AVDD compared to the reference voltage Vref becomes larger. Therefore, when switching from the vertical blanking interval Vbl to the frame to be displayed Fd, the load corresponding to the analog power supply voltage AVDD increases, and the energy stored in the first energy storage element can be released to the signal output terminal when the isolation element connects the current path between the first energy storage element and the signal output terminal, thus buffering the drop in the analog power supply voltage AVDD. At the same time, the feedback control controller 4022 will increase the output voltage of the feedback control controller 4022 according to the actual output analog power supply voltage AVDD, so as to further alleviate the drop of analog power supply voltage AVDD, thereby reducing the offset of analog power supply voltage AVDD relative to reference voltage Vref at the end of the vertical blanking interval Vbl.

[0082] It should be noted that when switching from the current frame Fc displaying a lightly loaded image to the vertical blanking interval Vbl, the analog power supply voltage AVDD may also fluctuate due to changes in load. When switching from the current frame Fc display to the vertical blanking interval Vbl, the power management module 40 can adjust the voltage applied to the second node No2 based on the effective level of the enable signal TRE_EN. Therefore, when switching from the current frame Fc display to the vertical blanking interval Vbl, the feedback signal and the enable signal TRE_EN can still be used to adjust the signal of the second node No2, thereby adjusting the energy supplied by the first energy storage element at the beginning of the vertical blanking interval Vbl (ts), thus buffering the rise of the analog power supply voltage AVDD and reducing the offset of the analog power supply voltage AVDD relative to the reference voltage Vref.

[0083] Similarly, when the timing control module 30 determines that the display screen of the current frame Fc is a heavy-load display screen and the display screen of the frame to be displayed Fd is a light-load display screen, the timing control module 30 controls the enable signal TRE_EN to have an effective level within the vertical blanking interval Vbl between the current frame Fc and the frame to be displayed Fd, and controls the digital-to-analog converter to output a first voltage signal corresponding to this condition. The voltage follower UF generates a corresponding second voltage signal based on the first voltage signal. The second switching element connects the current path between the second node No2 and the voltage follower UF according to the enable signal TRE_EN, so as to apply the second voltage signal to the second node No2. The signal of the second node No2 is affected by the feedback signal and the enable signal TRE_EN, so that the signal of the second node No2 is the sum of the output signal of the feedback adjustment controller 4022 and the output signal of the parameter adjustment controller 4021. As a result, the pulse output controller 4023 controls the duty cycle of the output pulse width control signal to decrease according to the feedback signal and the enable signal TRE_EN, so as to reduce the conduction time of the first switching element, thereby reducing the energy stored in the first energy storage element. When switching from the current frame Fc to the vertical blanking interval Vbl and from the vertical blanking interval Vbl to the frame to be displayed Fd, the increment of the actual output analog power supply voltage AVDD compared to the reference voltage Vref decreases. Therefore, when switching from the current frame Fc to the vertical blanking interval Vbl, the load corresponding to the analog power supply voltage AVDD is relatively small, and the signal of the second node No2 can still be adjusted by the feedback signal and the enable signal TRE_EN to adjust the energy that the first energy storage element can supply at the beginning of the vertical blanking interval Vbl, thereby buffering the rise of the analog power supply voltage AVDD and reducing the offset of the analog power supply voltage AVDD relative to the reference voltage Vref. When switching from the vertical blanking interval Vbl to the frame to be displayed Fd, the energy stored in the first energy storage element and the energy released when the isolation element connects the current path between the first energy storage element and the signal output terminal buffer the drop of the analog power supply voltage AVDD. Furthermore, when switching from the vertical blanking interval Vbl to the frame to be displayed Fd, the feedback adjustment controller 4022 will adjust the output voltage of the feedback adjustment controller 4022 according to the actual output analog power supply voltage AVDD, so as to further alleviate the drop of the analog power supply voltage AVDD, thereby reducing the offset of the analog power supply voltage AVDD relative to the reference voltage Vref at the end of the vertical blanking interval Vbl.

[0084] In summary, this application can determine whether to enable the parameter adjustment controller 4021 during the vertical blanking interval Vbl based on the load type of the display screen of the current frame Fc and the display screen of the frame to be displayed Fd. This allows for dynamic compensation of the analog power supply voltage AVDD according to the load changes, thereby reducing the amplitude of the analog power supply voltage ripple and improving the duration of the ripple.

[0085] like Figures 5A-5B This is a simulation comparison diagram of the simulated power supply voltage provided in the embodiments of this application. Simulation was performed using the power management module 40 excluding the parameter adjustment controller 4021, and the results are as follows. Figure 5A The simulation curves shown are obtained by simulating the power management module 40, including the parameter adjustment controller 4021. Figure 5B The simulation curve shown is illustrated. Here, Vdata represents the data signal.

[0086] according to Figures 5A-5B It can be seen that when the power management module 40 does not include the parameter regulation controller 4021, the deviation of the analog power supply voltage AVDD relative to the reference voltage Vref can reach 390 millivolts. When the power management module 40 includes the parameter regulation controller 4021, the deviation of the analog power supply voltage AVDD relative to the reference voltage Vref is reduced to 145 millivolts. Therefore, according to Figures 5A-5B It can be seen that when the power management module 40 includes the parameter adjustment controller 4021, the offset of the analog power supply voltage AVDD relative to the reference voltage Vref is reduced at the beginning and end of the corresponding vertical blanking interval Vbl, and the reduction is greater than 50%, which reduces the ripple amplitude of the analog power supply voltage AVDD.

[0087] Furthermore, verification using a neutral density filter to address crosstalk and water ripple issues revealed that when the power management module 40 includes a parameter adjustment controller 4021, the water ripple and crosstalk issues could only be detected by switching from a neutral density filter with a transmittance of 0.0001% to a neutral density filter with a transmittance of 0.000001%, thus improving the water ripple and crosstalk problem.

[0088] Figure 6 This is a flowchart illustrating a display driving method provided in an embodiment of this application. This application also provides a display driving method for driving any of the aforementioned display devices.

[0089] Please continue reading. Figure 6 The display driving method may include: Step S10: When it is determined that the display screen of the current frame Fc of the display panel 10 is either a light-load display screen or a heavy-load display screen, and the display screen of the frame to be displayed Fd is either a light-load display screen or a heavy-load display screen, the control enable signal TRE_EN has an effective level in the vertical blanking interval Vbl between the current frame Fc and the frame to be displayed.

[0090] Step S20: During the vertical blanking interval Vbl, adjust the compensation value applied to the analog power supply voltage AVDD according to the effective level of the enable signal TRE_EN, so as to reduce the voltage offset of the generated analog power supply voltage AVDD relative to the reference voltage Vref during at least one period in the end period of the current frame Fc and the start period of the frame to be displayed Fd.

[0091] In this process, multiple sub-pixels Spx of the display panel 10 are displayed in each frame according to multiple data signals, and the voltage of the multiple data signals is generated based on the image data of each frame and the analog power supply voltage AVDD.

[0092] In some embodiments, the timing control module 30 may execute step S1, the power management module 40 may execute step S2, the source drive module 20 may generate multiple data signals, and at least one of the graphics processor and the central processing unit may provide graphics data. The specific manner in which the power management module 40 executes step S2 can be obtained by referring to the design of the power management module 40 in the aforementioned display device, and will not be elaborated further here.

[0093] Optionally, prior to step S1, the display driving method further includes: Step S01: Based on the image data corresponding to the display screen of the current frame Fc and the image data corresponding to the display screen of the frame to be displayed Fd, determine whether the display screen of the current frame Fc and the display screen of the frame to be displayed Fd are the same type of load screen; wherein, the load screen is a light load display screen or a heavy load display screen.

[0094] If it is determined that the display screen of the current frame Fc and the display screen of the frame to be displayed Fd are not of the same type of load screen, then step S10 is executed.

[0095] If it is determined that the display screen of the current frame Fc and the display screen of the frame to be displayed Fd are of the same type of load screen, then steps S02 to S03 are executed.

[0096] In step S02: when it is determined that the display screen of the current frame Fc and the display screen of the frame to be displayed Fd are the same type of load screen, the control enable signal TRE_EN is at an invalid level during the vertical blanking interval Vbl.

[0097] Step S03: During the vertical blanking interval Vbl, stop adjusting the compensation value applied to the analog power supply voltage AVDD based on the invalid level of the enable signal TRE_EN.

[0098] Optionally, the timing control module 30 can be used to execute the above steps S01 to S02, and the power management module 40 can be used to execute the above step S03.

[0099] Optionally, in the current frame Fc and the frame to be displayed Fd, the compensation value applied to the analog power supply voltage AVDD may not be adjusted using the enable signal TRE_EN, but only based on the effect of the feedback signal. Accordingly, the display driving method further includes: controlling the enable signal TRE_EN to be at an invalid level in the current frame Fc and the frame to be displayed Fd; and generating the compensation value applied to the analog power supply voltage AVDD according to the feedback signal and the reference voltage Vref, and stopping the adjustment of the compensation value according to the invalid level of the enable signal TRE_EN.

[0100] It should be understood that the display driving method of this application corresponds to the above-described display device, and the display driving method of this application can be applied to the above-described display device. Therefore, the display driving method of this application has at least all the beneficial effects brought about by the technical solutions of the above-described embodiments, which will not be described in detail here.

[0101] The above description is merely an optional embodiment of this application and does not limit the patent scope of this application. Any equivalent structural transformations made based on the inventive concept of this application and the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this application.

Claims

1. A display device, characterized by comprising: include: The display panel includes multiple sub-pixels; The source drive module, electrically connected to multiple sub-pixels, is configured to receive analog power supply voltage to generate multiple data signals and output them to the corresponding sub-pixels; The timing control module is configured to control the generated enable signal to have an effective level in the vertical blanking interval between the current frame and the frame to be displayed when it is determined that the display screen of the current frame of the display panel is one of the light load display screen and the heavy load display screen, and the display screen of the frame to be displayed is the other of the light load display screen and the heavy load display screen. A power management module, electrically connected to the source drive module and the timing control module, is configured to adjust the compensation value applied to the analog power supply voltage during the vertical blanking interval according to the effective level of the enable signal, so as to reduce the voltage offset of the generated analog power supply voltage relative to the reference voltage during at least one period during the start and end periods of the vertical blanking interval.

2. The display device according to claim 1, wherein The power management module includes: The boost unit is electrically connected to the first input terminal and the signal output terminal of the power management module. The first input terminal is configured to receive the input voltage, and the signal output terminal is configured to output the analog power supply voltage. The compensation adjustment unit, electrically connected to the boost unit and the timing control module, is configured to control the boost ratio of the boost unit according to the enable signal and the feedback signal, so as to control the compensation value applied to the analog power supply voltage. The feedback signal is the analog power supply voltage output from the signal output terminal.

3. The display device according to claim 2, wherein The boost unit includes: The first energy storage element is electrically connected between the first input terminal and the first node; A first switching element, electrically connected between the first node and the ground terminal, is configured to control the on / off state of the current path between the first node and the ground terminal; An isolation element, electrically connected between the first node and the signal output terminal, is configured to disconnect the current path between the first node and the signal output terminal during a period when the first switching element connects the current path between the first node and the ground terminal; and is configured to connect the current path between the first node and the signal output terminal during a period when the first switching element disconnects the current path between the first node and the ground terminal; and The second energy storage element is electrically connected between the signal output terminal and the ground terminal and is configured to maintain the potential of the signal output terminal; The compensation adjustment unit is configured to control the conduction duration of the first switching element according to the enable signal and the feedback signal, so as to control the boost ratio of the boost unit.

4. The display device according to claim 3, wherein The compensation adjustment unit includes: A parameter adjustment controller, electrically connected between the second input terminal and the second node of the power management module, is configured to control the voltage applied to the second node according to the enable signal received at the second input terminal during the vertical blanking interval. A feedback regulation controller, electrically connected between the signal output terminal and the second node, is configured to regulate the voltage of the second node according to the reference voltage and the feedback signal; A pulse output controller, electrically connected between the first switching element and the second node, is configured to output a pulse width modulation signal according to the signal from the second node to control the on-time of the first switching element.

5. The display device according to claim 4, wherein When the enable signal has an effective level in the vertical blanking interval, the parameter adjustment controller is configured to apply a voltage to the second node in the vertical blanking interval according to the effective level of the enable signal, so that the pulse output controller adjusts the duty cycle of the pulse width modulation signal according to the signal of the second node.

6. The display device according to claim 4, wherein The timing control module is configured to control the enable signal to be at an invalid level during the vertical blanking interval when it is determined that the display screen of the current frame and the display screen of the frame to be displayed are of the same type of load screen. The parameter adjustment controller is configured to stop applying voltage to the second node during the vertical blanking interval based on the invalid level of the enable signal; the load screen is either the light load display screen or the heavy load display screen.

7. A display device according to any one of claims 4 to 6, wherein In the current frame and the frame to be displayed, the timing control module is configured to control the enable signal to be at an invalid level, and the parameter adjustment controller is configured to stop applying voltage to the second node according to the enable signal.

8. The display device according to any one of claims 4 to 6, wherein The parameter adjustment controller includes: The digital-to-analog converter is configured to output a first voltage signal; A voltage follower, electrically connected to the digital-to-analog converter, is configured to output a second voltage signal based on the first voltage signal; and The second switching element, electrically connected to the voltage follower, the second node, and the second input, is configured to control the duration for which the second voltage signal is transmitted to the second node according to the enable signal.

9. The display device of claim 8, wherein, The parameter adjustment controller includes: A first resistor is connected in series between the digital-to-analog converter and the voltage follower; and The second resistor is connected in series between the voltage follower and the second switching element.

10. The display device according to any one of claims 4 to 6, characterized in that, The feedback control controller includes: A voltage divider element, electrically connected to the signal output terminal, the ground terminal, and the third node, is configured to adjust the potential of the third node according to the feedback signal; An operational amplifier, electrically connected between the third node and the second node, is configured to adjust the potential of the second node according to the signal from the third node and the reference voltage; and A third resistor and a first capacitor are electrically connected between the second node and the ground terminal and connected in series.

11. A display driving method, characterized in that, include: When it is determined that the display screen of the current frame of the display panel is one of the light load display screen and the heavy load display screen, and the display screen of the frame to be displayed is the other of the light load display screen and the heavy load display screen, the control enable signal has an effective level in the vertical blanking interval between the current frame and the frame to be displayed. During the vertical blanking interval, the compensation value applied to the analog power supply voltage is adjusted according to the effective level of the enable signal to reduce the voltage offset of the generated analog power supply voltage relative to the reference voltage during at least one period in the end period of the current frame and the beginning period of the frame to be displayed. In this process, multiple sub-pixels of the display panel are displayed in each frame according to multiple data signals, and the voltage of the multiple data signals is generated based on the image data of each frame and the analog power supply voltage.

12. The display driving method according to claim 11, characterized in that, The display driving method further includes: Based on the image data corresponding to the display screen of the current frame and the image data corresponding to the display screen of the frame to be displayed, it is determined whether the display screen of the current frame and the display screen of the frame to be displayed are load screens of the same type; wherein, the load screen is the light load display screen or the heavy load display screen; When it is determined that the display screen of the current frame and the display screen of the frame to be displayed are the same type of load screen, the enable signal is controlled to be at an invalid level during the vertical blanking interval; During the vertical blanking interval, the adjustment of the compensation value applied to the analog power supply voltage stops according to the invalid level of the enable signal.

13. The display driving method according to claim 11, characterized in that, The display driving method further includes: In the current frame and the frame to be displayed, the enable signal is controlled to be at an invalid level; The compensation value applied to the analog power supply voltage is generated based on the feedback signal and the reference voltage, and the adjustment of the compensation value is stopped based on the invalid level of the enable signal.

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