Multi-mode refresh rate switching method and system, electronic equipment and storage medium
By introducing GPIO level combinations and equal-length traces between the SOC and TCON board, the problem of the serial bus being susceptible to electromagnetic interference was solved, stable refresh rate mode switching was achieved, the risk of display abnormalities was reduced, and the dependence on software communication was decreased.
Patent Information
- Application Number
- CN202511709869.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-20
- Publication Date
- 2026-02-17
AI Technical Summary
In the complex internal environment of a television, serial buses such as I²C and SPI are susceptible to electromagnetic interference, which makes it difficult to guarantee the integrity of communication signals between the motherboard SOC and the TCON board. This may cause mode switching failures or parameter configuration errors, leading to display abnormalities.
By introducing a combination of levels between three GPIO pins at the SOC end, it can be directly matched with the TCON board, eliminating the need for complex software communication protocols and using hardware level recognition to achieve mode switching. Equal-length traces and shielding measures are used to reduce the impact of electromagnetic interference.
It achieves stable and reliable refresh rate mode switching within the TV's internal environment, reduces the risk of display anomalies caused by communication errors, and reduces dependence on the software stack.
Smart Images
Figure CN121545467A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of display module technology, and in particular to a multi-mode refresh rate switching method, system, electronic device, and storage medium. Background Technology
[0002] In related technologies, communication between the motherboard SOC and the TCON board is typically achieved via serial buses such as I²C and SPI. Refresh rate mode switching is generally transmitted and identified through software commands. When a display mode switch is required, the SOC sends a command to the TCON board through these communication interfaces. Upon receiving the command, the TCON board retrieves the corresponding parameter configuration from its internal memory. This mode switching method relies entirely on the reliability and real-time performance of the software communication.
[0003] However, serial buses such as I²C and SPI are susceptible to electromagnetic interference, and signal integrity cannot be absolutely guaranteed in the complex internal environment of a television. Errors during communication can lead to mode switching failures or incorrect parameter configurations, resulting in display abnormalities. Summary of the Invention
[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a multi-mode refresh rate switching method, system, electronic device and storage medium that can achieve mode switching between the motherboard SOC and TCON board through level matching combination, eliminating the need for complex software communication protocols.
[0005] The objective of this invention is achieved through the following technical solution: The first aspect of this application provides a multi-mode refresh rate switching method, comprising: acquiring a first level of a first GPIO pin, a second level of a second GPIO pin, and a third level of a third GPIO pin defined from the SOC terminal; pairing the first level, the second level, and the third level; outputting several level combination information; saving the current display state according to the level combination information; calling the refresh rate mode configuration corresponding to the level combination information; loading the refresh rate mode configuration; and completing the refresh rate mode switching.
[0006] The method further includes: obtaining a first level of the first GPIO pin defined from the SOC end through a first trace, obtaining a second level of the first GPIO pin defined from the SOC end through a second trace, and obtaining a third level of the first GPIO pin defined from the SOC end through a third trace, wherein the lengths of the first trace, the second trace, and the third trace are equal.
[0007] The method further includes: pre-creating several refresh rate mode configurations, and matching each refresh rate mode configuration with the multi-mode refresh rate switching method, system, electronic device and storage medium according to each level combination information.
[0008] A second aspect of this application provides a multi-mode refresh rate switching system, comprising: a data acquisition module, configured to acquire a first level of a first GPIO pin, a second level of a second GPIO pin, and a third level of a third GPIO pin defined from the SOC terminal, pair the first level, the second level, and the third level, and output several level combination information; a calling module, configured to save the current display state according to the level combination information and call the refresh rate mode configuration corresponding to the level combination information; and a switching module, configured to load the refresh rate mode configuration and complete the refresh rate mode switching.
[0009] The acquisition module is further configured to acquire the first level of the first GPIO pin defined from the SOC end through the first trace, acquire the second level of the first GPIO pin defined from the SOC end through the second trace, and acquire the third level of the first GPIO pin defined from the SOC end through the third trace, wherein the lengths of the first trace, the second trace and the third trace are equal.
[0010] The system also includes a matching module, which is used to pre-create several refresh rate mode configurations and match each refresh rate mode configuration with the multi-mode refresh rate switching method, system, electronic device and storage medium according to each level combination information.
[0011] A third aspect of this application provides an electronic device, comprising: Processor; and A memory that stores executable code, which, when executed by the processor, causes the processor to perform the method described above.
[0012] A fourth aspect of this application provides a computer-readable storage medium having executable code stored thereon, which, when executed by a processor of an electronic device, causes the processor to perform the method described above.
[0013] Compared with the prior art, the present invention has at least the following advantages: This application introduces a combination of voltage levels between three GPIO pins on the SOC side to match the various refresh rate parameter configurations inside the TCON board, thereby enabling direct communication between the SOC side and the TCON board. This eliminates the need for complex software communication protocols and reduces reliance on the software stack through hardware voltage level recognition, thus reducing mode switching failures caused by communication errors. Attached Figure Description
[0014] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly described below.
[0015] Figure 1 This is a flowchart of a multi-mode refresh rate switching method according to an embodiment of the present invention; Figure 2 This is a functional block diagram of a multi-mode refresh rate switching system according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the structure of an electronic device according to an embodiment of the present invention. Detailed Implementation
[0016] Embodiments of this application will now be described in more detail with reference to the accompanying drawings. While embodiments of this application are shown in the drawings, it should be understood that this application may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to make this application more thorough and complete, and to fully convey the scope of this application to those skilled in the art.
[0017] It should be understood that although the terms "first," "second," "third," etc., may be used in this application to describe various information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0018] Unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.
[0019] Communication between the motherboard SOC and the TCON board is typically achieved via serial buses such as I²C and SPI. Refresh rate mode switching is generally transmitted and identified through software commands. When a display mode switch is needed, the SOC sends a command to the TCON board through these communication interfaces. The TCON board receives the command and then retrieves the corresponding parameter configuration from its internal memory. This mode switching method relies entirely on the reliability and real-time performance of software communication. However, serial buses such as I²C and SPI are susceptible to electromagnetic interference, and signal integrity cannot be absolutely guaranteed in the complex internal environment of a television. Errors during communication can lead to mode switching failures or incorrect parameter configurations, resulting in display abnormalities.
[0020] To address the aforementioned issues, this application provides a multi-mode refresh rate switching method, system, electronic device, and storage medium that enables mode switching between the motherboard SOC and TCON board through level matching combinations, eliminating the need for complex software communication protocols.
[0021] The technical solutions of the embodiments of this application are described in detail below with reference to the accompanying drawings.
[0022] Figure 1 This is a flowchart illustrating a multi-mode refresh rate switching method according to an embodiment of this application.
[0023] See Figure 1 A multi-mode refresh rate switching method, comprising: Step S101: Obtain the first level of the first GPIO pin, the second level of the second GPIO pin, and the third level of the third GPIO pin defined from the SOC terminal; pair the first level, the second level, and the third level; and output several level combination information.
[0024] It should be noted that the TCON board acquires the first level of the first GPIO pin, the second level of the second GPIO pin, and the third level of the third GPIO pin defined from the SOC in real time. The first level can be defined as P0, the second level can be defined as P1, and the third level can be defined as P2. The three can be randomly combined to obtain 8 level combinations.
[0025] Step S102: Based on the level combination information, save the current display state and call the refresh rate mode configuration corresponding to the level combination information.
[0026] Step S103: Load refresh rate mode configuration and complete refresh rate mode switching.
[0027] It should be noted that the current display state is saved before switching refresh rates to ensure a smooth transition. After the TCON board recognizes the new level combination information, it calls the refresh rate mode corresponding to the new level combination and then loads and runs it. The refresh rate mode configuration includes GOA timing control, RX and TX interface information, color calibration parameters, overdrive intensity information, gamma, etc.
[0028] Furthermore, in one embodiment, a multi-mode refresh rate switching method further includes: obtaining a first level of a first GPIO pin defined from the SOC end through a first trace, obtaining a second level of the first GPIO pin defined from the SOC end through a second trace, and obtaining a third level of the first GPIO pin defined from the SOC end through a third trace, wherein the lengths of the first trace, the second trace, and the third trace are equal.
[0029] It should be noted that the TCON board integrates a level status detection circuit, which can monitor the level status of three GPIO pins in real time. The three GPIO pins are directly connected to the corresponding level status detection circuit identification interface on the TCON board via traces. These traces should be as short and of equal length as possible to reduce signal transmission delay and differences. At the same time, appropriate shielding measures need to be taken to prevent electromagnetic interference from affecting the GOA timing parameters of the level identification.
[0030] Furthermore, in one embodiment, the multi-mode refresh rate switching method further includes: pre-creating several refresh rate mode configurations, and matching each refresh rate mode configuration with the multi-mode refresh rate switching method, system, electronic device and storage medium corresponding to each level combination information.
[0031] It should be noted that the refresh rate mode configuration includes 8 level combinations, such as P2 / P1 / P0=0 / 0 / 0, P2 / P1 / P0=0 / 0 / 1, P2 / P1 / P0=0 / 1 / 0, P2 / P1 / P0=0 / 1 / 1, P2 / P1 / P0=1 / 0 / 0, P2 / P1 / P0=1 / 0 / 1, P2 / P1 / P0=1 / 1 / 0, and P2 / P1 / P0=1 / 1 / 1. Each combination corresponds to a different refresh rate mode.
[0032] Corresponding to the aforementioned application function implementation method embodiments, this application also provides a multi-mode refresh rate switching system, electronic device, and corresponding embodiments.
[0033] Figure 2 This is a functional block diagram of a multi-mode refresh rate switching system shown in an embodiment of this application.
[0034] See Figure 2A multi-mode refresh rate switching system includes a data acquisition module 100, a calling module 200, and a switching module 300. The data acquisition module 100 is used to acquire the first level of a first GPIO pin, the second level of a second GPIO pin, and the third level of a third GPIO pin defined from the SOC terminal, pair the first level, the second level, and the third level, and output several level combination information. The calling module 200 is used to save the current display state according to the level combination information and call the refresh rate mode configuration corresponding to the level combination information. The switching module 300 is used to load the refresh rate mode configuration and complete the refresh rate mode switching.
[0035] See Figure 2 In one embodiment, the acquisition module 100 is further configured to acquire a first level of a first GPIO pin defined from the SOC end through a first trace, acquire a second level of a first GPIO pin defined from the SOC end through a second trace, and acquire a third level of a first GPIO pin defined from the SOC end through a third trace, wherein the lengths of the first trace, the second trace, and the third trace are equal.
[0036] See Figure 2 In one embodiment, the multi-mode refresh rate switching system further includes a matching module, which is used to pre-create several refresh rate mode configurations and match each refresh rate mode configuration with the multi-mode refresh rate switching method, system, electronic device and storage medium according to each level combination information.
[0037] Regarding the system in the above embodiments, the specific ways in which each module performs operations have been described in detail in the embodiments related to the method, and will not be elaborated further here.
[0038] Figure 3 This is a schematic diagram of the structure of an electronic device shown in an embodiment of this application.
[0039] See Figure 3 The electronic device 1000 includes a memory 1010 and a processor 1020.
[0040] The processor 1020 can be a central processing unit (CPU), or it can be an integrated circuit composed of other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be any conventional processor that can run the Linux kernel.
[0041] Memory 1010 may include various types of storage units, such as system memory, read-only memory (ROM), and permanent storage devices. ROM may store static data or instructions required by processor 1020 or other modules of the computer. Permanent storage devices may be read-write storage devices. Permanent storage devices may be non-volatile storage devices that retain stored instructions and data even when the computer is powered off. In some embodiments, permanent storage devices use mass storage devices (e.g., magnetic or optical disks, flash memory) as permanent storage devices. In other embodiments, permanent storage devices may be removable storage devices (e.g., floppy disks, optical drives). System memory may be a read-write storage device or a volatile read-write storage device, such as dynamic random access memory. System memory may store some or all of the instructions and data required by the processor during operation. Furthermore, memory 1010 may include any combination of computer-readable storage media, including various types of semiconductor memory chips (e.g., DRAM, SRAM, SDRAM, flash memory, programmable read-only memory), and disks and / or optical disks may also be used. In some embodiments, the memory 1010 may include a removable storage device that is readable and / or writable, such as a laser disc (CD), a read-only digital multifunction optical disc (e.g., DVD-ROM, dual-layer DVD-ROM), a read-only Blu-ray disc, an ultra-high density optical disc, a flash memory card (e.g., SD card, mini SD card, Micro-SD card, etc.), a magnetic floppy disk, etc. Computer-readable storage media do not contain carrier waves or transient electronic signals transmitted wirelessly or via wired connections.
[0042] The memory 1010 stores executable code, which, when processed by the processor 1020, can cause the processor 1020 to execute part or all of the methods described above.
[0043] Furthermore, the method according to this application can also be implemented as a computer program or computer program product, which includes computer program code instructions for performing some or all of the steps in the method described above.
[0044] Alternatively, this application may be implemented as a computer-readable storage medium (or a non-transitory machine-readable storage medium or a machine-readable storage medium) storing executable code (or computer program or computer instruction code) thereon, which, when executed by a processor of an electronic device (or server, etc.), causes the processor to perform part or all of the steps of the methods described above according to this application.
[0045] The solution of this application has been described in detail above with reference to the accompanying drawings. In the above embodiments, the descriptions of each embodiment have different focuses; for parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. Those skilled in the art should also understand that the actions and modules involved in the specification are not necessarily essential to this application. Furthermore, it is understood that the steps in the method of this application embodiment can be adjusted, combined, and deleted according to actual needs, and the modules in the device of this application embodiment can be combined, divided, and deleted according to actual needs. The various embodiments of this application have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.
Claims
1. A multi-mode refresh rate switching method, characterized in that, include: The system acquires the first level of the first GPIO pin, the second level of the second GPIO pin, and the third level of the third GPIO pin defined from the SOC side; pairs the first level, the second level, and the third level; and outputs several level combination information. Based on the level combination information, save the current display state and call the refresh rate mode configuration corresponding to the level combination information; Load the refresh rate mode configuration to complete the refresh rate mode switching.
2. The multi-mode refresh rate switching method according to claim 1, characterized in that, The method further includes: The first level of the first GPIO pin defined from the SOC is obtained through a first trace, the second level of the first GPIO pin defined from the SOC is obtained through a second trace, and the third level of the first GPIO pin defined from the SOC is obtained through a third trace, wherein the lengths of the first trace, the second trace, and the third trace are equal.
3. The multi-mode refresh rate switching method according to claim 1, characterized in that, The method further includes: Several refresh rate mode configurations are pre-created, and each refresh rate mode configuration is matched with the multi-mode refresh rate switching method, system, electronic device and storage medium according to the level combination information.
4. A multi-mode refresh rate switching system, characterized in that, include: The acquisition module is used to acquire the first level of the first GPIO pin, the second level of the second GPIO pin, and the third level of the third GPIO pin defined from the SOC terminal, pair the first level, the second level, and the third level, and output several level combination information; The calling module is used to save the current display state according to the level combination information and call the refresh rate mode configuration corresponding to the level combination information; The switching module is used to load the refresh rate mode configuration and complete the refresh rate mode switching.
5. The multi-mode refresh rate switching system according to claim 4, characterized in that, The acquisition module is further configured to acquire the first level of the first GPIO pin defined from the SOC end through the first trace, acquire the second level of the first GPIO pin defined from the SOC end through the second trace, and acquire the third level of the first GPIO pin defined from the SOC end through the third trace, wherein the lengths of the first trace, the second trace and the third trace are equal.
6. The multi-mode refresh rate switching system according to claim 4, characterized in that, The system also includes a matching module, which is used to pre-create several refresh rate mode configurations and match each refresh rate mode configuration with the multi-mode refresh rate switching method, system, electronic device and storage medium according to each level combination information.
7. An electronic device, characterized in that, include: processor; as well as A memory having executable code stored thereon, which, when executed by the processor, causes the processor to perform the method as described in any one of claims 1-3.
8. A computer-readable storage medium having executable code stored thereon, which, when executed by a processor of an electronic device, causes the processor to perform the method as described in any one of claims 1-3.