Address comparison circuit, semiconductor memory and electronic equipment

Abstract

The embodiment of the invention discloses an address comparison circuit, a semiconductor memory and electronic equipment, and relates to the technical field of semiconductors. Address comparison delay can be reduced. Comprising a plurality of address matching units, each address matching unit comprises a plurality of switch circuits, the input end of each switch circuit receives a one-bit one-hot coding address signal, and the control end of each switch circuit receives a one-bit pre-stored fault address signal; the output ends of the plurality of switching circuits are connected in parallel so as to generate a matching result signal of each address matching unit; when a pre-stored fault address signal corresponding to a target switch circuit corresponding to an effective level bit in the one-hot coded address signal is an effective level, indicating that the address is matched; and the matching logic unit is respectively connected with the output ends of the address matching units, and outputs an address comparison result based on the matching result signals output by the address matching units. The present invention adapts to a memory scenario configured with an address bus input signal mode as multi-group one-hot coding.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to an address comparison circuit, a semiconductor memory, and an electronic device. Background Technology

[0002] As semiconductor technology evolves, memory integration becomes increasingly sophisticated. During manufacturing, the failure of entire rows or columns of memory cells frequently occurs, and the probability of such failures increases with the increase in memory capacity used in circuits. To improve the overall yield of memory, redundancy repair functions have become indispensable in memory.

[0003] In the redundancy repair function, the address comparison circuit is an indispensable part. However, the traditional address comparison circuit requires several levels of logic gates to complete the matching work of a certain length of address bus. Moreover, as the address bus length increases, the number of logic gates required by the address comparison circuit will also increase, which will continuously increase the delay of the address comparison circuit. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide an address comparison circuit, a semiconductor memory, and an electronic device that can reduce the latency of address comparison.

[0005] In a first aspect, embodiments of the present invention provide an address comparison circuit, comprising: a plurality of address matching units, each address matching unit comprising a plurality of switching circuits, the plurality of switching circuits having the same number of bit widths as a one-hot encoded address signal; an input terminal of each switching circuit configured to receive one bit of a one-hot encoded address signal, wherein only one bit of the one-hot encoded address signal is at a valid level; a control terminal of each switching circuit configured to receive one bit of a pre-stored fault address signal; the output terminals of the plurality of switching circuits in each address matching unit are connected in parallel to generate a matching result signal for each address matching unit; wherein, when the pre-stored fault address signal corresponding to the target switching circuit corresponding to the valid level bit in the one-hot encoded address signal is at a valid level, it indicates an address match; and a matching logic unit connected to the output terminals of the plurality of address matching units, configured to output an address comparison result based on the matching result signals output by the plurality of address matching units.

[0006] Optionally, the effective level of the one-hot encoded address signal and the pre-stored fault address signal is high.

[0007] Optionally, the one-hot encoded address signal includes at least: a least significant bit one-hot encoded address signal and a most significant bit one-hot encoded address signal; the address comparison result is determined jointly based on the matching result signal of the least significant bit one-hot encoded address signal and the matching result signal of the most significant bit one-hot encoded address signal.

[0008] Optionally, the matching logic unit includes a first inverter corresponding to each of the plurality of address matching units, wherein the input terminal of each first inverter is connected to the parallel output terminal of a plurality of switching circuits in each address matching unit, and is configured to receive the matching result signal of each address matching unit.

[0009] Optionally, the matching logic unit further includes a NOR gate, a second inverter, and a third inverter. The input of the NOR gate is connected to the output of each of the first inverters, the output of the NOR gate is connected to the input of the second inverter, the output of the NOR gate is connected to the input of the second inverter, and the output of the second inverter is connected to the input of the third inverter.

[0010] Optionally, the address comparison circuit further includes a redundancy signal generator. The output of the redundancy signal generator is connected to the input of the NOR gate and is configured to generate a redundancy enable signal. Based on the redundancy enable signal and the matching result signals output by multiple address matching units, the address comparison result is output.

[0011] Optionally, the redundancy enable signal is a low-level active signal.

[0012] Optionally, the switching circuit includes a switching transistor circuit, the input of which is configured to receive a one-hot encoded address signal, the control terminal of which is configured to receive a one-bit pre-stored fault address signal, and the outputs of multiple switching transistor circuits are connected in parallel, with the parallel outputs connected to the matching logic unit; the parallel outputs are configured to generate a matching result signal for each address matching unit; or, the switching circuit includes a logic gate switching unit, the input of which is configured to receive a one-hot encoded address signal and a one-bit pre-stored fault address signal, the outputs of multiple logic gate units are connected in parallel, the parallel outputs are connected to the matching logic unit, and the parallel outputs are configured to generate a matching result signal for each address matching unit.

[0013] Secondly, embodiments of the present invention also provide a semiconductor memory, including a fault address storage unit, a redundant storage unit, and an address comparison circuit as described in any of the first aspects above. The fault address storage unit is connected to the control terminal of the switching circuit, the redundant storage unit is connected to the output terminal of the address comparison circuit, and the address matching unit is configured to compare the current one-hot encoded address with the fault address stored in the fault address storage unit. When the address comparison result is a match, the address comparison circuit outputs a matching signal to trigger the redundant storage unit, so that the one-hot encoded address is remapped to the redundant storage unit.

[0014] Optionally, the redundant storage unit may include a row-redundant storage unit or a column-redundant storage unit.

[0015] Thirdly, embodiments of the present invention also provide an electronic device, including a semiconductor memory, a processor, and a circuit board, wherein the processor is disposed on the circuit board, and the semiconductor memory is disposed on the circuit board and connected to the processor; wherein the semiconductor memory is the semiconductor memory described in any of the second aspects.

[0016] This invention provides an address comparison circuit, a semiconductor memory, and an electronic device. Based on one-hot encoded address signals, the address comparison circuit incorporates multiple address matching units. Each address matching unit includes a switching circuit with the same number of bits as the current one-hot encoded address signal. The control terminal of each switching circuit receives one bit of a pre-stored fault address signal, and the input terminal of each switching circuit receives one bit of the one-hot encoded address signal. The output terminals of the multiple switching circuits in each address matching unit are connected in parallel. Based on the characteristics of the one-hot encoding mode, when the one-hot encoded address signal corresponding to the target switching circuit corresponding to the valid level bit in the pre-stored fault address signal is also valid, it indicates an address match. At this time, the entire address matching unit outputs a matching result signal. The matching result signals output by multiple address matching units are logically combined using a matching logic unit to complete the comparison of multiple sets of one-hot encoded address signals, ultimately obtaining a complete address comparison result. Thus, a single set of one-hot encoded addresses can be compared using a single parallel switching circuit, and multiple sets can be compared using matching logic units, thereby quickly completing the entire address comparison function and significantly reducing signal delay during address comparison. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a diagram of a redundancy repair function module in a semiconductor memory in the prior art; Figure 2 This is a schematic diagram of the address comparison circuit architecture in a semiconductor memory in the prior art; Figure 3 A schematic diagram of the address comparison circuit architecture provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of a single address matching unit architecture provided in an embodiment of the present invention; Figure 5A This is a schematic diagram illustrating the working principle of a single address matching unit provided in an embodiment of the present invention; Figure 5B This is a schematic diagram illustrating the working principle of a single address matching unit according to another embodiment of the present invention; Figure 6 A circuit diagram of an address comparison circuit provided in an embodiment of the present invention; Figure 7 A schematic diagram of a semiconductor memory architecture provided in an embodiment of the present invention; Figure 8 This is a schematic diagram of an electronic device module architecture provided in an embodiment of the present invention. Detailed Implementation

[0019] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0020] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0021] To facilitate the description and understanding of the technical solutions provided in the embodiments of this application, some English abbreviations or symbols used in the text will be briefly explained below before proceeding with the description: Red_ADD[n:0]bus: Pre-stored fault address bus information; Red_ADD[n:0]: Pre-stored fault address; ADD[n:0]: Memory address information; ADDin[n:0]bus: Input address bus information; ADDin[n:0]: Input address information; CCLK: External clock signal; Match: Output of the address comparison circuit. When match is high, it means that the two input address information are matched bit by bit. When match is low, it means that the two input address information are not matched.

[0022] See Figure 1 As shown, the redundancy repair function in semiconductor memory mainly refers to the process during memory testing where one or more rows / columns of memory cells in a conventional memory array / cell are found to be malfunctioning and unable to be read or written. The external control circuit records the row / column addresses of these malfunctioning memory cells and uses this address information as the address information of the faulty cell. This information is then inserted into the faulty address memory cell after memory startup via a scan chain insertion method and latched as the faulty address bus information Red_ADD[n:0]bus. Subsequently, during normal read / write operations, when the external control circuit inputs address information ADD[n:0] to the memory, ADD[n:0] is first latched by the address latch as the internal ADDin[n:0]bus, and then enters the decoder module for address information decoding and is compared with the clk of the external clock signal CCLK. In combination; at the same time, ADDin[n:0]bus will enter the address comparison circuit module and compare the address with the pre-stored fault address bus information Red_ADD[n:0]bus in the memory. The address comparison circuit module will output the match signal to enter the Disable Logic. When the current input address information ADDin[n:0] is exactly the same as the fault address information Red_ADD[n:0], the match signal is a high level signal. The disable logic module will set the disable signal high. The disable signal will enter the decoder to turn off the decoding logic of the normal address to ensure that the normal word line driver is not activated. At the same time, a redundant (row or column) word line driver is activated, and the redundant (row or column) address stored in the redundant address storage array is used to replace the current address for read and write operations.

[0023] However, in traditional address comparison circuits, both the input address bus and the fault address bus are binary encoded. When performing address comparisons, refer to... Figure 2As shown, a two-input XOR gate, with the same number of bits as the input address bus, is typically used as the first-stage address comparison logic gate. The two inputs of the XOR gate are connected to the memory address inputs ADD_in[15:0] and the pre-stored fault address Red_ADD[15:0] in memory, respectively. When the two input addresses are the same, the XOR gate outputs a high-level signal. Subsequent stages of logic gate circuits (such as...) are required depending on the number of two-input XOR gates. Figure 2 The second-level logic gates (multiple NAND gates, third-level logic gates, and fourth-level logic gates, etc.) are used to ensure that the output signal `match` of the entire logic circuit is high if and only if the outputs of all two-input XOR gates are high, otherwise the output of `match` is low. Therefore, in traditional address comparison circuits, address information must pass through several levels of logic gates to obtain the final `match` result. Furthermore, as the address bus width increases, multiple-input NAND and NOR gates need to be added to the logic transistors, which increases the delay of the address comparison circuit. This delay is reflected in the setup time of the memory address input `ADD_in[n:0]` relative to the clock signal, thus affecting the overall performance of the memory.

[0024] It should be noted that in on-chip integrated semiconductor memory, the data input format of its address bus is usually divided into two types: binary address encoding mode and multi-group one-hot address encoding mode. This embodiment is for memory with address bus input signal encoding method of multi-group one-hot encoded signal, and uses the characteristics of one-hot encoded signal to complete address comparison.

[0025] See Figure 3 As shown, the address comparison circuit 1 provided in this embodiment of the invention includes: a plurality of address matching units 11 (such as...) Figure 3 (11A and 11B) and logic matching unit 12.

[0026] Each of the multiple address matching units 11 includes multiple switching circuits (such as...) Figure 3 (110-113 and 114-117 in the diagram), the plurality of switching circuits have the same number of bit widths as the one-hot encoded address signals; the input terminal of each switching circuit is configured to receive one bit of the one-hot encoded address signal, wherein only one bit of the one-hot encoded address signal is at an active level; the control terminal of each switching circuit 11 is configured to receive one bit of a pre-stored fault address signal.

[0027] The outputs of multiple switching circuits in each address matching unit 11 are connected in parallel to generate a matching result signal for each address matching unit 11; wherein, when the pre-stored fault address signal corresponding to the target switching circuit corresponding to the effective level bit in the one-hot encoded address signal is at an effective level, it indicates that the address is matched.

[0028] The matching logic unit 12 is connected to the output terminals of the plurality of address matching units 11 respectively, and is configured to output the address comparison result based on the matching result signal output by the plurality of address matching units.

[0029] The address comparison circuit provided in this embodiment utilizes the characteristics of one-hot encoded signals: a set of one-hot encoded signal buses, regardless of the signal length, has only one address bit that is high, while all other bits are low. The high-level position represents the address position that needs to be activated by this set of address buses.

[0030] The address comparison circuit 1 provided in this embodiment adopts a multi-group one-hot encoding mode for the address bus and sets up multiple address matching units 11. Each address matching unit 11 includes a number of switching circuits with the same bit width as the current one-hot encoded address signal. The control terminal of each switching circuit receives a pre-stored fault address signal, and the input terminal of each switching circuit receives a one-hot encoded address signal. The output terminals of the multiple switching circuits in each address matching unit 11 are connected in parallel. Based on the characteristics of the one-hot encoding mode, only one of the multiple switching circuits in an address matching unit 11 has a valid pre-stored fault address signal. When the one-hot encoded address signal corresponding to the target switching circuit corresponding to the valid level bit in the pre-stored fault address signal is also valid, it indicates that the address is matched. At this time, the entire address matching unit 11 outputs a matching result signal. The matching result signals output by the multiple address matching units 11 are logically combined using the matching logic unit 12 to complete the comparison of multiple groups of one-hot encoded address signals, so as to finally obtain a complete address comparison result. In this way, a set of one-hot encoded addresses can be compared through a single-level parallel switching circuit, and multiple sets of one-hot encoded addresses can be compared through the matching logic unit 12, thereby quickly completing the entire address comparison function. Compared with the traditional address comparison which requires several levels of logic gate circuits, this greatly saves the signal delay of address comparison and improves the performance of the memory.

[0031] In some embodiments, when each set of one-hot encoded address signals successfully matches the pre-stored fault address signals, the entire address comparison circuit outputs a high-level matching signal, indicating that the current input address of the memory being compared matches the fault address pre-stored in the memory. At this time, the redundant array stored in the redundant address storage array needs to be activated, while the corresponding conventional storage array is turned off for read and write operations. When any set of one-hot encoded address signals does not match the pre-stored fault address signals, the entire address comparison circuit outputs a low-level matching signal, indicating that the current input address of the memory being compared does not match the fault address pre-stored in the memory. At this time, the redundant array stored in the redundant address storage array will not be activated, and the memory will perform read and write operations on the conventional storage array.

[0032] Optionally, in some embodiments, the effective level of the one-hot encoded address signal and the pre-stored fault address signal is high.

[0033] In this embodiment, due to the characteristics of one-hot encoded signals—regardless of signal length—one and only one address bit in a set of one-hot encoded signals is high, while all other bits are low—the effective level of the pre-stored fault address signal is set to high. This means that only one of the multiple switching circuits in an address matching unit will be open. When the current one-hot encoded address signal received at the input of this open switching circuit is also high, it indicates an address match.

[0034] Specifically, taking a single address matching unit as an example, see... Figure 4 As shown, Figure 4 In the diagram, Redlsb[15:0] is the pre-stored fault address, Redlsbx[15:0] is the inverted signal of Redlsb[15:0], and RdIdxlsb[15:0] is the current input address of the memory. For a single hot-swappable address bus, the address matching can be achieved by connecting the output terminals of a set of switch circuits with the same width as the hot-swappable address bus in parallel. Redlsb is connected to the control terminal of the switch circuit to receive the pre-stored fault address, and RdIdxlsb is connected to the input terminal of the switch circuit to receive the current input address. The parallel output terminal of the switch circuit outputs the matching result signal match, and matchx is the equivalent matching result signal with the opposite phase to match.

[0035] When performing address matching, see Figure 5A and Figure 5BAs shown, since this embodiment adopts a one-hot encoding mode, the Redlsb signal bus is in one-hot mode. Only one address bit in the 16 Redlsb bits is high level. Only the corresponding switch circuit will be turned on among the 16 switch circuits. At this time, when the RdIdxlsb[0] address bit connected to the switch circuit turned on by Redlsb[0] is low level, the matching result signal match of the entire address matching unit will be the same as the potential of the RdIdxlsb address bit, which is low level, and matchx will be high level, indicating that the address comparison result is mismatched. If the RdIdxlsb[1] address bit connected to the switch circuit turned on by Redlsb[1] is also high level at the same time, the matching result signal match output by the entire address matching unit will be high level, and matchx will be low level, indicating that the address comparison result is matched.

[0036] Optionally, in some embodiments, the one-hot encoded address signal includes at least: a least significant bit one-hot encoded address signal and a most significant bit one-hot encoded address signal; the address comparison result is determined jointly based on the matching result signal of the least significant bit one-hot encoded address signal and the matching result signal of the most significant bit one-hot encoded address signal.

[0037] In this embodiment, when converting the data format of the address bus to one-hot encoding mode, a complete binary encoded input address signal can be converted into multiple sets of one-hot encoded address signals, including at least the least significant bit one-hot encoded address signal and the most significant bit one-hot encoded address signal. For example, a binary encoded input address signal: ADD[5:0]=000100 can be converted into two sets of one-hot encoded address signals: the most significant bit one-hot encoded address signal ADDmsb[3:0]=0001 and the least significant bit one-hot encoded address signal ADDlsb[15:0]=0000000000010000, where ADDmsb[3:0]=0001 corresponds to the high 2 bits 00, and the 0th bit of the one-hot encoding is 1; ADDlsb[15:0]=0000000000010000 corresponds to the low 4 bits 0100 (i.e., decimal 4), and the 4th bit (counting from 0) in the one-hot encoding is 1, and the rest are 0. Each set of one-hot encoded address signals corresponds to an address matching unit and a matching result signal. The address comparison result of the entire address comparison circuit is determined jointly by the matching result signals of the least significant bit one-hot encoded address signal and the most significant bit one-hot encoded address signal. For example, Figure 6 As shown, the address comparison circuit includes two address matching units, one set corresponding to the least significant bit one-hot encoded address signal RdIdxlsb[15:0], and the other set corresponding to the most significant bit one-hot encoded address signal RdIdxlsb[3:0].

[0038] Optionally, in some embodiments, the matching logic unit 12 includes a first inverter 121 corresponding to each of the plurality of address matching units 11, wherein the input terminal of each first inverter 121 is connected to the parallel output terminal of a plurality of switching circuits in each address matching unit 11, and is configured to receive the matching result signal of each address matching unit 11.

[0039] Optionally, in some embodiments, the matching logic unit 12 further includes a NOR gate 122, a second inverter 123, and a third inverter 124. The input of the NOR gate 122 is connected to the output of each of the first inverters 121, the output of the NOR gate 122 is connected to the input of the second inverter 123, the output of the NOR gate 122 is connected to the input of the second inverter 123, and the output of the second inverter 123 is connected to the input of the third inverter 124.

[0040] In this embodiment, a set of one-hot encoded address signals is compared through a single-stage parallel switching circuit (one address matching unit). For the entire address signal, the matching logic unit is used to merge and compare the matching result signals output by multiple address matching units. When the matching result signal output by each address matching unit indicates a successful match, the final address comparison result indicates a successful match.

[0041] Among them, see Figure 6 As shown, the matching logic unit 12 includes a first inverter 121 (121A and 121B) corresponding to each address matching unit in a plurality of address matching units 11 (11A and 11B). The input of each first inverter 121 (121A and 121B) is connected to the parallel output of a plurality of switching circuits in each address matching unit 11 (11A and 11B) and is configured to receive the matching result signal of each address matching unit 11 (11A and 11B). The output of the first inverter 121 (121A and 121B) is connected to the input of the NOR gate 122. The output of the NOR gate 122 is connected to the input of the second inverter 123. The output of the second inverter 123 is connected to the input of the third inverter 124. The outputs of the second inverter 123 and the third inverter 124 output the address comparison result of the entire address comparison circuit.

[0042] For details, please refer to Figure 6The implementation principle of the entire address comparison circuit in this embodiment is as follows: the output terminals of multiple switching circuits in each address matching unit 11 (11A and 11B) are connected in parallel, and the input terminal of each switching circuit receives a one-hot encoded address signal (the current address adopts one-hot encoding mode). Based on the characteristics of the one-hot encoding mode, only one of the multiple switching circuits in an address matching unit has a valid fault address signal stored in the pre-stored fault address signal. When the one-hot encoded address signal corresponding to the target switching circuit corresponding to the valid level bit in the pre-stored fault address signal is also valid, it indicates that the address matching is successful. At this time, the entire address matching unit outputs a high-level matching signal. After each address matching unit 11 (11A and 11B) successfully matches, the high-level matching result signal output by each address matching unit 11 (11A and 11B) is output to the first inverter 121 (121A and 121B) connected to it. The first inverter 121 (121A and 121B) outputs a low-level signal to the NOR gate 122. Utilizing the principle of the NOR gate, a high-level output is generated when all inputs are low, thus completing the comparison of the entire address. Then, using the INV transistor (inverter) as the driver, the weak signal output by the NOR gate is restored to a complete standard digital signal with strong driving capability, so as to drive the memory to perform read and write operations based on the signal.

[0043] Optionally, in some embodiments, the address comparison circuit further includes a redundancy signal generator, the output of which is connected to the input of the NOR gate, configured to generate a redundancy enable signal, and output an address comparison result based on the redundancy enable signal and the matching result signals output by multiple address matching units.

[0044] Optionally, in some embodiments, the redundancy enable signal is a low-level active signal.

[0045] In this embodiment, to implement the redundancy repair function, a redundancy signal generator is also included. The output of the redundancy signal generator is connected to the input of a NOR gate to generate a redundancy enable signal REENX, thereby controlling the activation of the redundancy repair function. For details, see [link to documentation]. Figure 6The above describes the use of two sets of one-hot encoded address signals: one set is the least significant bit one-hot encoded address signal RdIdxlsb[15:0], and the other set is the most significant bit one-hot encoded address signal RdIdxlsb[3:0]. These are matched with the pre-stored fault address signals Redlsb[15:0] and Redlsb[3:0], respectively. When both sets of one-hot encoded address signals successfully match the one-hot encoded address signals, and the low-level redundancy enable signal REENX generated by the redundancy signal generator enables the entire comparison circuit, the entire address comparison circuit will output a high-level match signal and a low-level matchx signal, indicating that... When the current input address RdIdxlsb of the memory being compared matches the pre-stored fault address Redlsb, the redundant array stored in the redundant address storage array needs to be activated, while the corresponding regular storage array is turned off for read and write operations. Conversely, when any one-hot encoded address signal does not match the pre-stored fault address signal, or when the redundancy enable signal REENX does not enable the redundancy repair function, the entire address comparison circuit outputs a low-level match signal and a high-level matchx signal. In this case, the redundant array stored in the redundant address storage array will not be activated, and the memory will perform read and write operations on the regular storage array.

[0046] Optionally, in some embodiments, the switching circuit includes a switching transistor circuit, the input of which is configured to receive a one-bit one-hot encoded address signal, the control terminal of which is configured to receive a one-bit pre-stored fault address signal, and the outputs of multiple switching transistor circuits are connected in parallel, the parallel outputs being connected to the matching logic unit; the parallel outputs are configured to generate a matching result signal for each address matching unit; or, The switching circuit includes a logic gate switching unit. The input terminal of the logic gate unit is configured to receive a one-bit one-hot encoded address signal and a one-bit pre-stored fault address signal. The output terminals of multiple logic gate units are connected in parallel, and the parallel output terminals are connected to the matching logic unit. The parallel output terminals are configured to generate a matching result signal for each address matching unit.

[0047] In this embodiment, the switching circuit can be a switching transistor circuit, such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) circuit. Taking this embodiment as an example, the switching circuit is a switching transistor circuit. The input terminal of each switching transistor circuit receives a one-hot encoded address signal, and the control terminal receives a one-pre-stored fault address signal. The output terminals of multiple switching transistor circuits are connected in parallel to output a matching result signal of an address matching unit.

[0048] In other embodiments, the switching circuit can also be a logic gate switching unit that replaces the parallel switching transistor circuit. Combining the characteristics of one-hot encoding, the address comparison in the entire address comparison circuit is realized through simple logic comparison. Specifically, the input terminal of the logic gate unit is configured to receive one one-hot encoded address signal and one pre-stored fault address signal. The output terminals of multiple logic gate units are connected in parallel to jointly output the matching result signal of each address matching unit. At the same time, the parallel output terminals of multiple address matching units are connected to the matching logic unit to complete the comparison of multiple sets of one-hot encoded addresses and quickly output the address comparison results match and matchx.

[0049] See Figure 7 As shown, this embodiment of the invention also provides a semiconductor memory 70, including: a fault address storage unit 2, a redundant storage unit 3, and the address comparison circuit 1 described in the foregoing embodiment. The fault address storage unit 2 is connected to the control terminal of the switching circuit, and the redundant storage unit 3 is connected to the output terminal of the address comparison circuit 1. The address matching units 11A and 11B are configured to compare the current one-hot encoded address with the fault address stored in the fault address storage unit 2. When the address comparison result is a match, the address comparison circuit 1 outputs a matching signal to trigger the redundant storage unit 3, so that the one-hot encoded address is remapped to the redundant storage unit 3.

[0050] In this embodiment, through the combined action of the address comparison circuit, the fault address storage unit, and the redundant storage unit, the fault address storage unit stores the fault address signal, the redundant storage unit stores the redundant address signal that replaces the fault address signal, and the address matching unit compares the current one-hot encoded address of the memory with the fault address stored in the fault address storage unit. When the address comparison result is a match, the address comparison circuit outputs a high-level match signal, triggering the redundant storage unit so that the one-hot encoded address is remapped to the redundant storage unit, and read and write operations are performed using the redundant address. The address matching unit can realize the comparison of a set of one-hot encoded addresses through a single-level parallel switching circuit, and realize the comparison of multiple sets of one-hot encoded addresses through the matching logic unit, thereby quickly completing the entire address comparison function. Compared with the traditional address comparison which requires several levels of logic gate circuits, this greatly saves the signal delay of address comparison and improves the performance of the memory.

[0051] Optionally, in some embodiments, the redundant storage unit includes a row redundant storage unit or a column redundant storage unit, where the row redundant storage unit stores row redundant addresses and the column redundant storage unit stores column redundant addresses. Similarly, the fault address storage unit stores both row fault addresses and column fault addresses to achieve the memory's redundancy repair function.

[0052] See Figure 8 As shown, this embodiment of the invention also provides an electronic device 80, including a semiconductor memory 70, a processor 4, and a circuit board 5. The processor 4 is disposed on the circuit board 5, and the semiconductor memory 70 is disposed on the circuit board 5 and connected to the processor 4; wherein, the semiconductor memory 70 is the aforementioned semiconductor memory.

[0053] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0054] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. Connections in this specification include electrical connections via lines or wireless connections.

[0055] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. An address comparison circuit, characterized by, The address comparison circuit comprises: a plurality of address matching units, each of the address matching units comprising a plurality of switch circuits, the plurality of switch circuits being the same as the number of bits of a one-hot encoded address signal; an input end of each of the switch circuits being configured to receive a bit of the one-hot encoded address signal, wherein only one bit of the one-hot encoded address signal is at a valid level; and a control end of each of the switch circuits being configured to receive a bit of a pre-stored fault address signal; output ends of the plurality of switch circuits in each of the address matching units being connected in parallel to generate a matching result signal of each of the address matching units; wherein when the valid level bit of the one-hot encoded address signal corresponds to a pre-stored fault address signal of a target switch circuit at the valid level, address matching is indicated. a matching logic unit connected to output ends of the plurality of address matching units and configured to output an address comparison result based on the matching result signals output by the plurality of address matching units.

2. The address comparison circuit of claim 1, wherein, The valid level of the one-hot encoded address signal and the pre-stored fault address signal is a high level.

3. The address comparison circuit of claim 1, wherein, The one-hot encoded address signal comprises at least a least significant bit one-hot encoded address signal and a most significant bit one-hot encoded address signal; and the address comparison result is determined based on the matching result signal of the least significant bit one-hot encoded address signal and the matching result signal of the most significant bit one-hot encoded address signal.

4. The address comparison circuit of claim 1, wherein, The matching logic unit comprises a first inverter corresponding to each of the address matching units, wherein an input end of each of the first inverters is connected to a parallel output end of the plurality of switch circuits in each of the address matching units and configured to receive the matching result signal of each of the address matching units.

5. The address comparison circuit of claim 4, wherein, The matching logic unit further comprises an NOR gate, a second inverter, and a third inverter, input ends of the NOR gate being connected to output ends of each of the first inverters, an input end of the second inverter being connected to an output end of the NOR gate, an input end of the second inverter being connected to an output end of the NOR gate, an input end of the second inverter being connected to an output end of the second inverter, and an output end of the second inverter being connected to an input end of the third inverter.

6. The address comparison circuit of claim 5, wherein, The address comparison circuit further comprises a redundancy signal generator, an output end of the redundancy signal generator being connected to an input end of the NOR gate and configured to generate a redundancy enable signal and output the address comparison result based on the redundancy enable signal and the matching result signals output by the plurality of address matching units.

7. The address comparison circuit of claim 6, wherein, The redundancy enable signal is a low-level valid signal.

8. The address comparison circuit of claim 1, wherein, The switch circuit comprises a switch tube circuit, an input end of the switch tube circuit being configured to receive a bit of the one-hot encoded address signal, a control end of the switch tube circuit being configured to receive a bit of the pre-stored fault address signal, output ends of a plurality of the switch tube circuits being connected in parallel, and the parallel output end being connected to the matching logic unit; and the parallel output end being configured to generate the matching result signal of each of the address matching units; or The switch circuit comprises a logic gate switch unit, an input end of the logic gate unit is configured to receive a one-bit unique hot encoding address signal and a one-bit pre-stored fault address signal, outputs of a plurality of the logic gate units are connected in parallel, and the parallel outputs are connected to the matching logic unit, and the parallel outputs are configured to generate a matching result signal of each of the address matching units.

9. A semiconductor memory, characterized by comprising: The address comparison circuit comprises a fault address storage unit, a redundant storage unit and the address comparison circuit of any one of the preceding claims 1-8, the fault address storage unit is connected to a control end of the switch circuit, the redundant storage unit is connected to an output end of the address comparison circuit, the address matching unit is configured to compare a current unique hot encoding address with a fault address stored in the fault address storage unit, when the address comparison result is matching, the address comparison circuit outputs a matching signal to trigger the redundant storage unit, so that the unique hot encoding address is remapped to the redundant storage unit.

10. The semiconductor memory according to claim 9, wherein The redundant storage unit comprises a row redundant storage unit or a column redundant storage unit.

11. An electronic device, comprising: The semiconductor memory, the processor and the circuit board, the processor is arranged on the circuit board, the semiconductor memory is arranged on the circuit board and connected with the processor; wherein, the semiconductor memory is the semiconductor memory of any one of the preceding claims 9-10.

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