Zero crossing point current stress limiting method and device

Abstract

The invention discloses a zero crossing point current stress limiting method and device. The zero crossing point current stress limiting method comprises the following steps: sampling an input voltage signal of a totem pole PFC (Power Factor Correction) circuit; determining a current working stage according to the input voltage signal; and determining the time of entering a power frequency dead zone, and controlling the high-frequency main switching tube to release energy kept in a junction capacitor of the power frequency switching tube. According to the totem pole PFC circuit, the energy in the junction capacitor of the power frequency tube is released through the switching action of the high-frequency main switching tube in the power frequency dead zone, so that the problem that the zero crossing point current stress is too high when the totem pole PFC circuit is in a rectification or inversion working state is effectively solved.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and specifically to a method and apparatus for limiting zero-crossing current stress. Background Technology

[0002] Totem-pole PFC circuits use SiC or GAN devices as high-frequency switches, and silicon MOSFETs can replace power frequency rectifier diodes as low-frequency switches to adapt to the positive and negative half-cycle switching of AC input. Therefore, they have low transmission loss and high conversion efficiency, and are widely used in medium and high power AC / DC applications, and can also be applied to bidirectional applications. When the input voltage of the totem-pole circuit is near zero, the inductor current is very small. At this time, the voltage difference across the comparator used for zero-crossing detection of the inductor current is also very small, which can lead to the loss or error of the inductor current zero-crossing detection signal, resulting in a spike in the inductor current. To avoid problems with the inductor current zero-crossing detection signal, a power frequency dead time needs to be set near the zero-crossing of the input voltage. During this time, both the high-frequency transistor and the power frequency transistor will be in the off state, and the drain-source voltage of the MOSFET remains basically unchanged. Taking the switching from the power frequency dead zone to the negative half-cycle during rectification operation as an example, the lower power frequency transistor is turned off during the dead time, and the voltage in the junction capacitance of the upper power frequency transistor cannot be released. As a result, when the upper high frequency transistor is turned on as the high frequency main switch in the negative half-cycle, the voltage on the junction capacitance of the power frequency transistor is too high, resulting in an excessively high excitation slope when the high frequency main switch is turned on. This generates extremely high current stress, which may damage the power device. It also generates input current harmonics and electromagnetic interference.

[0003] Many people have proposed solutions to this problem, such as adding auxiliary circuits, using digital soft-start control, or controlling after detecting a zero-crossing signal. However, these methods are cumbersome and difficult to implement, and cannot effectively solve the problem. Summary of the Invention

[0004] To address the aforementioned technical problems in the existing technology, this invention proposes a method and device for limiting zero-crossing current stress, which can improve the current stress problem at the zero-crossing point of the totem pole PFC circuit during rectification or inversion, and effectively reduce input current harmonics and electromagnetic interference.

[0005] To achieve the above objectives, the technical solution adopted by this invention is as follows: In a first aspect, the present invention provides a method for limiting zero-crossing current stress, applied to a totem-pole PFC circuit, the method comprising the following steps: Sample the input voltage signal of the totem pole PFC circuit; The current operating stage is determined based on the input voltage signal; The dead time at the power frequency is determined, and the energy held in the junction capacitance of the power frequency switch is released by controlling the high-frequency main switch.

[0006] Optional, also includes: When switching between the positive and negative half-cycles of the power frequency by the power frequency dead time, the conduction time of the high-frequency main switch is limited.

[0007] Optionally, determining the current operating stage based on the input voltage signal includes: If the input voltage signal increases to a level greater than or equal to a preset first voltage threshold and the polarity of the input voltage signal is positive, then the current working stage is transitioning from the power frequency dead time to the positive half-cycle of the power frequency. If the input voltage signal is determined to decrease to less than or equal to the first voltage threshold and the polarity of the input voltage signal is positive, then the current working stage is the transition from the positive half-cycle of the power frequency to the dead time of the power frequency. If the input voltage signal increases to a level greater than or equal to a preset second voltage threshold, and the polarity of the input voltage signal is negative, then the current working stage is transitioning from the power frequency dead time to the negative half-cycle of the power frequency. If the input voltage signal is determined to decrease to less than or equal to the second voltage threshold, and the polarity of the input voltage signal is negative, then the current working stage is the transition from the negative half-cycle of the power frequency to the dead time of the power frequency.

[0008] Optionally, determining the entry into the power frequency dead time and controlling the high-frequency main switch to release the energy held in the junction capacitance of the power frequency switch specifically includes: Once the dead time of entering the power frequency is determined, the power frequency switch is turned off, and the high-frequency main switch is controlled to continue to be turned on in the form of a high-frequency narrow pulse and then turned off before entering the next working stage.

[0009] Secondly, this invention provides a zero-crossing current stress limiting method applied to a totem-pole PFC circuit. The totem-pole PFC circuit includes an inductor L1, a high-frequency bridge arm switch upper transistor S1, a high-frequency bridge arm switch lower transistor S2, a power frequency upper transistor S3, a power frequency lower transistor S4, and a bus capacitor C. The zero-crossing current stress limiting method includes the following steps: The process is determined to start from the dead time of the power frequency and switch to the positive half-cycle of the power frequency. The lower tube S2 of the high-frequency bridge arm switch is turned on as the high-frequency main switch, the upper tube S1 of the high-frequency bridge arm switch is turned on as the synchronization tube, the lower tube S4 of the power frequency switch is kept on, and the upper tube S3 of the power frequency switch is kept off. Determine the time from the positive half-cycle of the power frequency to the dead time of the power frequency, control the lower tube S2 and the lower tube S4 of the high-frequency bridge arm switch to turn off, and control the upper tube S1 of the high-frequency bridge arm switch to continue to be turned on in the form of a high-frequency narrow pulse and turn off before entering the next negative half-cycle of the power frequency. The circuit is switched from the power frequency dead time to the negative half-cycle of the power frequency. The upper transistor S1 of the high-frequency bridge arm switch is turned on as the high-frequency main switch, the lower transistor S2 of the high-frequency bridge arm switch is turned on as the synchronizing transistor, the upper power frequency transistor S3 is kept on, and the lower power frequency transistor S4 is kept off. Determine the cut-in time from the negative half-cycle of the power frequency to the dead time of the power frequency, control the upper transistor S1 of the high-frequency bridge arm switch and the upper transistor S3 of the power frequency to turn off, and control the lower transistor S2 of the high-frequency bridge arm switch to continue to be turned on in the form of high-frequency narrow pulses and turn off before entering the next positive half-cycle of the power frequency.

[0010] Optionally, when the power frequency dead time is cut into the positive half-cycle of the power frequency, the conduction time of the lower transistor S2 of the high-frequency bridge arm switch is limited.

[0011] Optionally, the conduction time of the upper transistor S1 of the high-frequency bridge arm switch is limited by determining the transition from the power frequency dead time to the negative half-cycle of the power frequency.

[0012] Thirdly, the present invention provides a zero-crossing current stress limiting method applied to an interleaved totem pole PFC circuit. The interleaved totem pole PFC circuit includes a main phase inductor L1, a main phase high-frequency bridge arm switch upper transistor S1, a main phase high-frequency bridge arm switch lower transistor S2, a slave phase inductor L2, a slave phase high-frequency bridge arm switch upper transistor S3, a slave phase high-frequency bridge arm switch lower transistor S4, a power frequency upper transistor S5, a power frequency lower transistor S6, and a bus capacitor C. The zero-crossing current stress limiting method includes a rectification working mode and an inverter working mode. The rectification operating modes include: When the power frequency dead time is cut into the positive half-cycle of the power frequency, the lower tube S2 of the main phase high-frequency bridge arm switch and the lower tube S4 of the slave phase high-frequency bridge arm switch are turned on as high-frequency main switches, the lower tube S1 of the main phase high-frequency bridge arm switch and the upper tube S3 of the slave phase high-frequency bridge arm switch are turned on as synchronizing tubes, the lower tube S6 of the power frequency switch is always on, and the upper tube S5 of the power frequency switch is always off. Determine the time from the positive half-cycle of the power frequency to the dead time of the power frequency. The lower tube S2 of the main phase high-frequency bridge arm switch, the lower tube S4 of the slave phase high-frequency bridge arm switch, and the lower tube S6 of the power frequency switch are turned off. The upper tube S1 of the main phase high-frequency bridge arm switch and the upper tube S3 of the slave phase high-frequency bridge arm switch continue to be turned on in the form of high-frequency narrow pulses and are turned off before entering the next negative half-cycle of the power frequency. When the power frequency dead time is used to switch to the negative half-cycle of the power frequency, the upper tube S1 of the main phase high-frequency bridge arm switch and the upper tube S3 of the slave phase high-frequency bridge arm switch are turned on as high-frequency main switches, the lower tube S2 of the main phase high-frequency bridge arm switch and the lower tube S4 of the slave phase high-frequency bridge arm switch are turned on as synchronizing tubes, the upper tube S5 of the power frequency is always on, and the lower tube S6 of the power frequency is always off. The time from the negative half-cycle of the power frequency to the dead time of the power frequency is determined. The upper tube S1 of the main phase high-frequency bridge arm switch, the upper tube S3 of the slave phase high-frequency bridge arm switch, and the upper tube S5 of the power frequency switch are turned off. The lower tube S2 of the main phase high-frequency bridge arm switch and the lower tube S4 of the slave phase high-frequency bridge arm switch continue to be turned on in the form of high-frequency narrow pulses and are turned off before entering the next positive half-cycle of the power frequency.

[0013] Optionally, the inverter operating mode includes: When the power frequency dead time is cut into the positive half-cycle of the power frequency, the upper tube S1 of the main phase high-frequency bridge arm switch and the upper tube S3 of the slave phase high-frequency bridge arm switch are turned on as high-frequency main switches, the lower tube S2 of the main phase high-frequency bridge arm switch and the lower tube S4 of the slave phase high-frequency bridge arm switch are turned on as synchronizing tubes, the lower tube S6 of the power frequency is always on, and the upper tube S5 of the power frequency is always off. Determine the time from the positive half-cycle of the power frequency to the dead zone of the power frequency. The lower tube S2 of the main phase high-frequency bridge arm switch, the lower tube S4 of the slave phase high-frequency bridge arm switch, and the lower tube S6 of the power frequency switch are turned off. The upper tube S1 of the main phase high-frequency bridge arm switch and the upper tube S3 of the slave phase high-frequency bridge arm switch continue to be turned on in the form of high-frequency narrow pulses and are turned off before entering the next negative half-cycle of the power frequency. When the power frequency dead time is cut into the negative half-cycle of the power frequency, the lower tube S2 of the main phase high-frequency bridge arm switch and the lower tube S4 of the slave phase high-frequency bridge arm switch are turned on as high-frequency main switches, the upper tube S1 of the main phase high-frequency bridge arm switch and the upper tube S3 of the slave phase high-frequency bridge arm switch are turned on as synchronizing tubes, the upper tube S5 of the power frequency switch is always on, and the lower tube S6 of the power frequency switch is always off. The time from the negative half-cycle of the power frequency to the dead time of the power frequency is determined. The upper tube S1 of the main phase high-frequency bridge arm switch, the upper tube S3 of the slave phase high-frequency bridge arm switch, and the upper tube S5 of the power frequency switch are turned off. The lower tube S2 of the main phase high-frequency bridge arm switch and the lower tube S4 of the slave phase high-frequency bridge arm switch continue to be turned on in the form of high-frequency narrow pulses, and are turned off before entering the next positive half-cycle of the power frequency.

[0014] Fourthly, the present invention also provides a zero-crossing current stress limiting device applied to a totem pole PFC circuit, the zero-crossing current stress limiting device comprising: A sampling unit is used to sample the input voltage signal of the totem pole PFC circuit; The judgment unit is used to determine the current working stage based on the input voltage signal; The release unit is used to determine the time to enter the power frequency dead zone and control the high-frequency main switch to release the energy held in the junction capacitance of the power frequency switch.

[0015] The present invention has the following beneficial effects: This invention releases the energy in the junction capacitance of the power frequency transistor by switching the high-frequency main switch within the power frequency dead zone, which can significantly suppress the current stress generated at the zero crossing of the input, improve the total harmonic distortion of the current to a certain extent, and avoid problems such as input current harmonics and electromagnetic interference. Thus, it can effectively solve the problem of excessive zero-crossing current stress in totem-pole PFC circuits during rectification or inversion operation. In addition, the whole solution is easy to implement and does not require additional detection and control. Attached Figure Description

[0016] Figure 1 This is a topology diagram of the totem pole PFC circuit used in this invention.

[0017] Figure 2 This is a topology diagram of a bidirectional interleaved parallel totem pole PFC circuit in one embodiment of a zero-crossing current stress limiting method of the present invention.

[0018] Figure 3 This is a flowchart of a method for suppressing zero-crossing current spikes in a bidirectional interleaved parallel totem pole PFC circuit, as described in one embodiment of the zero-crossing current stress limiting method of the present invention.

[0019] Figure 4 This is a schematic diagram of the driving state waveforms of the main phase high-frequency bridge arm switch and the power frequency switch in the rectification working mode of an embodiment of the zero-crossing current stress limiting method of the present invention.

[0020] Figure 5 This is a schematic diagram of the driving state waveforms of the high-frequency bridge arm switch and the power frequency switch in the rectification working mode of an embodiment of the zero-crossing current stress limiting method of the present invention.

[0021] Figure 6 This is a schematic diagram of the driving state waveforms of the main phase high-frequency bridge arm switch and the power frequency switch in the inverter operating mode of an embodiment of the zero-crossing current stress limiting method of the present invention.

[0022] Figure 7 This is a schematic diagram of the driving state waveforms of the high-frequency bridge arm switch and the power frequency switch in the inverter operating mode of an embodiment of the zero-crossing current stress limiting method of the present invention. Detailed Implementation

[0023] The present invention and its beneficial effects will be further described in detail below with reference to specific embodiments and accompanying drawings. However, the specific embodiments of the present invention are not limited thereto.

[0024] Figure 1 This is a topology diagram of a totem-pole PFC circuit in an application environment according to an embodiment of the present invention. For example... Figure 1As shown, the totem pole PFC circuit includes an inductor L1, a high-frequency bridge arm switch upper transistor S1, a high-frequency bridge arm switch lower transistor S2, a power frequency upper transistor S3, a power frequency lower transistor S4, and a bus capacitor C. This invention provides a method for limiting zero-crossing current stress, applied to a totem-pole PFC circuit. The method includes the following steps: S100, Sample the input voltage signal of the totem pole PFC circuit; S200. Determine the current operating stage based on the input voltage signal; S300: Determine the entry dead time at the power frequency and control the high-frequency main switch to release the energy held in the junction capacitance of the power frequency switch.

[0025] Furthermore, the zero-crossing current stress limiting method also includes: S400. When switching between the positive half-cycle and negative half-cycle of the power frequency by the power frequency dead time, the conduction time of the high-frequency main switch is limited.

[0026] The conduction time limitation can be achieved using either Scheme 1 or Scheme 2, or other methods that can limit the conduction time of the switching transistor. Scheme 1 involves setting a limit on the current sampling threshold used by the comparator during the initial switching to the positive and negative half-cycle phases. When the sampled current reaches the limit, the comparator flips, pulling the PWM wave low to limit the PWM conduction time. The limit is then lifted in subsequent phases. Scheme 2 involves directly limiting the PWM conduction time within the software during the initial switching to the positive and negative half-cycle phases. Since the system's voltage loop is controlled by a PI loop, the PI loop's output corresponds to the PWM conduction time. Limiting the maximum value of the PI loop's final output during the initial phase of switching to the positive and negative half-cycle phases also achieves the effect of limiting the conduction time.

[0027] It should be noted that energy release is achieved through a portion of the driving in step S300. Regarding the on-time limitation, if the energy on the junction capacitance of the switching transistor is completely released through step S300, the on-time limitation at the moment of switching from the dead zone to the positive and negative half-cycles is unnecessary. However, when the input low-voltage load is relatively large, the energy cannot be completely released through the partial driving in step S300. In this case, limiting the on-time of the switching transistor will have a certain effect on limiting the current stress at the zero-crossing point of the input voltage.

[0028] The step of determining the current operating stage based on the input voltage signal includes: S210. If the input voltage signal increases to a value greater than or equal to a preset first voltage threshold and the polarity of the input voltage signal is positive, then the current working stage is from the power frequency dead time to the positive half-cycle of the power frequency. S220. If the input voltage signal is determined to be reduced to less than or equal to the first voltage threshold and the polarity of the input voltage signal is positive, then the current working stage is from the positive half-cycle of the power frequency to the dead time of the power frequency. S230. If the input voltage signal increases to a level greater than or equal to a preset second voltage threshold and the polarity of the input voltage signal is negative, then the current working stage is from the power frequency dead time to the negative half-cycle of the power frequency. S240. If the input voltage signal is determined to be reduced to less than or equal to the second voltage threshold, and the polarity of the input voltage signal is negative, then the current working stage is from the negative half-cycle of the power frequency to the dead time of the power frequency.

[0029] It should be noted that the switching between the power frequency dead time and the positive and negative half-cycles of the power frequency is mainly determined by the voltage detection on the input L / N line. After processing by external devices, a positive swivel signal is generated and input to the control IC. The switching between the dead time and the positive and negative half-cycles is performed by detecting the instantaneous value of the input voltage. In order to avoid malfunctions, hysteresis logic can be added to the detection in this embodiment, which can effectively improve reliability.

[0030] Furthermore, the determination of the entry into the power frequency dead time and the control of the high-frequency main switch to release the energy held in the junction capacitance of the power frequency switch specifically includes: Once the dead time of entering the power frequency is determined, the power frequency switch is turned off, and the high-frequency main switch is controlled to continue to be turned on in the form of a high-frequency narrow pulse and then turned off before entering the next working stage.

[0031] refer to Figure 1 This invention also provides a zero-crossing current stress limiting method applied to a totem pole PFC circuit. The totem pole PFC circuit includes an inductor L1, a high-frequency bridge arm switch upper transistor S1, a high-frequency bridge arm switch lower transistor S2, a power frequency upper transistor S3, a power frequency lower transistor S4, and a bus capacitor C. The zero-crossing current stress limiting method includes the following steps: The process is determined to start from the dead time of the power frequency and switch to the positive half-cycle of the power frequency. The lower tube S2 of the high-frequency bridge arm switch is turned on as the high-frequency main switch, the upper tube S1 of the high-frequency bridge arm switch is turned on as the synchronization tube, the lower tube S4 of the power frequency switch is kept on, and the upper tube S3 of the power frequency switch is kept off. Determine the time from the positive half-cycle of the power frequency to the dead time of the power frequency, control the lower tube S2 and the lower tube S4 of the high-frequency bridge arm switch to turn off, and control the upper tube S1 of the high-frequency bridge arm switch to continue to be turned on in the form of a high-frequency narrow pulse and turn off before entering the next negative half-cycle of the power frequency. The process is determined to start from the dead time of the power frequency and switch to the negative half-cycle of the power frequency. The upper tube S1 of the high-frequency bridge arm switch is controlled to turn on as the high-frequency main switch, the lower tube S2 of the high-frequency bridge arm switch is controlled to turn on as the synchronization tube, the upper tube S3 of the power frequency switch is controlled to remain on, and the lower tube S4 of the power frequency switch is controlled to remain off. Determine the cut-in time from the negative half-cycle of the power frequency to the dead time of the power frequency, control the upper transistor S1 of the high-frequency bridge arm switch and the upper transistor S3 of the power frequency to turn off, and control the lower transistor S2 of the high-frequency bridge arm switch to continue to be turned on in the form of high-frequency narrow pulses and turn off before entering the next positive half-cycle of the power frequency.

[0032] Specifically, when the power frequency dead time is cut into the positive half-cycle of the power frequency, the conduction time of the lower transistor S2 of the high-frequency bridge arm switch is limited.

[0033] Specifically, the conduction time of the upper transistor S1 of the high-frequency bridge arm switch is limited by determining that the switch is cut from the dead time of the power frequency to the negative half-cycle of the power frequency.

[0034] Figure 2 This is a topology diagram of a bidirectional interleaved parallel totem pole PFC circuit provided in an embodiment of the present invention, as shown below. Figure 2 As shown, the bidirectional interleaved parallel totem pole PFC circuit includes a main phase inductor L1, a main phase high-frequency bridge arm switch upper transistor S1, a main phase high-frequency bridge arm switch lower transistor S2, a slave phase inductor L2, a slave phase high-frequency bridge arm switch upper transistor S3, a slave phase high-frequency bridge arm switch lower transistor S4, a power frequency upper transistor S5, a power frequency lower transistor S6, and a bus capacitor C. Figure 3 The flowchart of the zero-crossing current spike suppression method for the bidirectional interleaved parallel totem pole PFC circuit provided in this embodiment of the invention is as follows: Figure 4 , 5 This is a schematic diagram of the drive state waveforms of the master-slave phase high-frequency and power frequency switching transistors under rectification operation in the embodiment of the present invention. In rectification operation mode: The interval [t0~t1]: At time t0, the system is determined to have transitioned from the power frequency dead time to the positive half-cycle of the power frequency. The lower transistor S2 of the main phase high-frequency bridge arm switch and the lower transistor S4 of the slave phase high-frequency bridge arm switch are turned on as high-frequency main switches. The lower transistor S1 of the main phase high-frequency bridge arm switch and the upper transistor S3 of the slave phase high-frequency bridge arm switch are turned on as synchronizing transistors. The lower transistor S6 of the power frequency switch is always on, and the upper transistor S5 of the power frequency switch is always off. At the same time, the conduction time of the lower transistor S2 of the main phase high-frequency bridge arm switch and the lower transistor S4 of the slave phase high-frequency bridge arm switch at the beginning of time t0 is limited. The interval [t1~t2]: At time t1, the system is judged to switch from the positive half-cycle of the power frequency to the dead time of the power frequency. At this time, the lower tube S2 of the main phase high-frequency bridge arm switch, the lower tube S4 of the slave phase high-frequency bridge arm switch, and the lower tube S6 of the power frequency switch are turned off. The upper tube S1 of the main phase high-frequency bridge arm switch and the upper tube S3 of the slave phase high-frequency bridge arm switch continue to be turned on in the form of high-frequency narrow pulses and are turned off before time t2. The interval [t2~t3]: At time t2, it is determined that the system has switched from the power frequency dead time to the negative half-cycle of the power frequency. The upper tube S1 of the main phase high-frequency bridge arm switch and the upper tube S3 of the slave phase high-frequency bridge arm switch are turned on as high-frequency main switches, and the lower tube S2 of the main phase high-frequency bridge arm switch and the lower tube S4 of the slave phase high-frequency bridge arm switch are turned on as synchronizing tubes. The upper tube S5 of the power frequency is always on and the lower tube S6 of the power frequency is always off. At the same time, the conduction time of the upper tube S1 of the main phase high-frequency bridge arm switch and the upper tube S3 of the slave phase high-frequency bridge arm switch at the beginning of time t2 is limited. The interval [t3~t4]: At time t3, the system is judged to have switched from the negative half-cycle of the power frequency to the dead time of the power frequency. At this time, the upper tube S1 of the main phase high-frequency bridge arm switch, the upper tube S3 of the slave phase high-frequency bridge arm switch, and the upper tube S5 of the power frequency switch are turned off. The lower tube S2 of the main phase high-frequency bridge arm switch and the lower tube S4 of the slave phase high-frequency bridge arm switch continue to be turned on in the form of high-frequency narrow pulses and are turned off before time t4.

[0035] Figure 6 , 7 This is a schematic diagram of the drive state waveforms of the master-slave phase high-frequency and power-frequency switching transistors under inverter operation in the embodiment of the present invention. In inverter operation mode: The interval [t0~t1]: At time t0, it is determined that the system has switched from the power frequency dead time to the power frequency positive half-cycle. The upper tube S1 of the main phase high frequency bridge arm switch and the upper tube S3 of the slave phase high frequency bridge arm switch are turned on as high frequency main switches, and the lower tube S2 of the main phase high frequency bridge arm switch and the lower tube S4 of the slave phase high frequency bridge arm switch are turned on as synchronizing tubes. The lower tube S6 of the power frequency is always on, and the upper tube S5 of the power frequency is always off. At the same time, the conduction time of the upper tube S1 of the main phase high frequency bridge arm switch and the upper tube S3 of the slave phase high frequency bridge arm switch is limited when the system just enters time t0. The interval [t1~t2]: At time t1, the system is judged to switch from the positive half-cycle of the power frequency to the dead time of the power frequency. At this time, the lower tube S2 of the main phase high-frequency bridge arm switch, the lower tube S4 of the slave phase high-frequency bridge arm switch, and the lower tube S6 of the power frequency switch are turned off. The upper tube S1 of the main phase high-frequency bridge arm switch and the upper tube S3 of the slave phase high-frequency bridge arm switch continue to be turned on in the form of high-frequency narrow pulses and are turned off before time t2. The interval [t2~t3]: At time t2, it is determined that the system has switched from the power frequency dead time to the negative half-cycle of the power frequency. The lower tube S2 of the main phase high-frequency bridge arm switch and the lower tube S4 of the slave phase high-frequency bridge arm switch are turned on as high-frequency main switches. The upper tube S1 of the main phase high-frequency bridge arm switch and the upper tube S3 of the slave phase high-frequency bridge arm switch are turned on as synchronizing tubes. The upper tube S5 of the power frequency is always on and the lower tube S6 of the power frequency is always off. At the same time, the conduction time of the lower tube S2 of the main phase high-frequency bridge arm switch and the lower tube S4 of the slave phase high-frequency bridge arm switch at the beginning of time t2 is limited. The interval [t3~t4]: At time t3, the system is judged to have switched from the negative half-cycle of the power frequency to the dead time of the power frequency. At this time, the upper tube S1 of the main phase high-frequency bridge arm switch, the upper tube S3 of the slave phase high-frequency bridge arm switch, and the upper tube S5 of the power frequency switch are turned off. The lower tube S2 of the main phase high-frequency bridge arm switch and the lower tube S4 of the slave phase high-frequency bridge arm switch continue to be turned on in the form of high-frequency narrow pulses and are turned off before time t4.

[0036] When the AC input voltage is detected and determined to be the dead time of the power frequency, the drive of all switching transistors except the high-frequency main switching transistor is turned off to release the energy of the junction capacitance of the power frequency switching transistor. At the same time, a strategy of limiting the conduction time of the switching transistor after the power frequency dead time is implemented. Although some current will be sacrificed at the zero crossing point, the above control strategy can effectively suppress the peak stress problem caused by the current zero crossing.

[0037] The above embodiments are only for illustrating the technical concept and features of the present invention. Their purpose is to enable those skilled in the art to understand the content of the present invention and implement it. They should not be used to limit the scope of protection of the present invention. All equivalent changes or modifications made in accordance with the spirit and essence of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A zero-crossing current stress limiting method applied to a totem-pole PFC circuit, characterized in that: The zero-crossing current stress limiting method comprises the following steps: sampling an input voltage signal of the totem pole PFC circuit; determining a current working stage according to the input voltage signal; determining an entering power frequency dead time, and controlling the high-frequency main switch tube to release the energy kept in the junction capacitor of the power frequency switch tube.

2. A zero-crossing current stress limiting method as recited in claim 1, wherein: Further comprising: limiting the on time of the high-frequency main switch tube when switching from the power frequency positive half cycle or the power frequency negative half cycle by the power frequency dead time.

3. A zero-crossing current stress limiting method as recited in claim 1, wherein: The step of determining the current working stage according to the input voltage signal comprises: determining that the input voltage signal increases to be greater than or equal to a preset first voltage threshold and the polarity of the input voltage signal is positive, and then determining that the current working stage is switching from the power frequency dead time to the power frequency positive half cycle; determining that the input voltage signal decreases to be less than or equal to the first voltage threshold and the polarity of the input voltage signal is positive, and then determining that the current working stage is switching from the power frequency positive half cycle to the power frequency dead time; determining that the input voltage signal increases to be greater than or equal to a preset second voltage threshold and the polarity of the input voltage signal is negative, and then determining that the current working stage is switching from the power frequency dead time to the power frequency negative half cycle; determining that the input voltage signal decreases to be less than or equal to the second voltage threshold and the polarity of the input voltage signal is negative, and then determining that the current working stage is switching from the power frequency negative half cycle to the power frequency dead time.

4. A zero-crossing current stress limiting method as recited in claim 1, wherein: The step of determining the entering power frequency dead time and controlling the high-frequency main switch tube to release the energy kept in the junction capacitor of the power frequency switch tube comprises: determining the entering power frequency dead time, controlling the power frequency switch tube to be turned off, and controlling the high-frequency main switch tube to be turned on in the form of a high-frequency narrow pulse and then turned off before entering the next working stage.

5. A zero-crossing current stress limiting method applied to a totem-pole PFC circuit, the totem-pole PFC circuit comprising an inductor L1, a high-frequency bridge-arm upper switch S1, a high-frequency bridge-arm lower switch S2, a line-frequency upper switch S3, a line-frequency lower switch S4, and a bus capacitor C, characterized in that: The zero-crossing current stress limiting method comprises the following steps: determining switching from the power frequency dead time to the power frequency positive half cycle, controlling the high-frequency bridge arm lower switch tube S2 to be turned on as the high-frequency main switch tube, controlling the high-frequency bridge arm upper switch tube S1 to be turned on as the synchronous tube, controlling the power frequency lower switch tube S4 to be turned on for a long time, and controlling the power frequency upper switch tube S3 to be always turned off; determining switching from the power frequency positive half cycle to the power frequency dead time, controlling the high-frequency bridge arm lower switch tube S2 and the power frequency lower switch tube S4 to be turned off, and controlling the high-frequency bridge arm upper switch tube S1 to be turned on in the form of a high-frequency narrow pulse and then turned off before entering the next power frequency negative half cycle; determining switching from the power frequency dead time to the power frequency negative half cycle, controlling the high-frequency bridge arm upper switch tube S1 to be turned on as the high-frequency main switch tube, controlling the high-frequency bridge arm lower switch tube S2 to be turned on as the synchronous tube, controlling the power frequency upper switch tube S3 to be turned on for a long time, and controlling the power frequency lower switch tube S4 to be always turned off; determining switching from the power frequency negative half cycle to the power frequency dead time, controlling the high-frequency bridge arm upper switch tube S1 and the power frequency upper switch tube S3 to be turned off, and controlling the high-frequency bridge arm lower switch tube S2 to be turned on in the form of a high-frequency narrow pulse and then turned off before entering the next power frequency positive half cycle.

6. A zero-crossing current stress limiting method as claimed in claim 5, characterized in that: Limiting the on time of the high-frequency bridge arm lower switch tube S2 when switching from the power frequency dead time to the power frequency positive half cycle.

7. A zero-crossing current stress limiting method as recited in claim 5, wherein: Limiting the on time of the high-frequency bridge arm upper switch tube S1 when switching from the power frequency dead time to the power frequency negative half cycle.

8. A zero-crossing current stress limiting method applied to an interleaved totem pole PFC circuit, the interleaved totem pole PFC circuit comprising a main phase inductor L1, a main phase high frequency bridge arm upper switch S1, a main phase high frequency bridge arm lower switch S2, a slave phase inductor L2, a slave phase high frequency bridge arm upper switch S3, a slave phase high frequency bridge arm lower switch S4, a line frequency upper switch S5, a line frequency lower switch S6 and a bus capacitor C, characterized in that: The zero-crossing current stress limiting method comprises a rectification working mode and an inversion working mode; The rectification working mode comprises: It is determined that the dead time of the power frequency is cut into the positive half cycle, the high-frequency main switch tube S2 of the main phase high-frequency bridge arm switch and the high-frequency main switch tube S4 of the slave phase high-frequency bridge arm switch are turned on, the synchronous tube S1 of the main phase high-frequency bridge arm switch and the synchronous tube S3 of the slave phase high-frequency bridge arm switch are turned on, the power frequency lower tube S6 is long, and the power frequency upper tube S5 is always off; It is determined that the positive half cycle of the power frequency is cut into the dead time of the power frequency, the high-frequency main switch tube S2 of the main phase high-frequency bridge arm switch, the high-frequency main switch tube S4 of the slave phase high-frequency bridge arm switch and the power frequency lower tube S6 are turned off, and the high-frequency main switch tube S1 of the main phase high-frequency bridge arm switch and the high-frequency main switch tube S3 of the slave phase high-frequency bridge arm switch continue to be turned on in the form of high-frequency narrow pulse and are turned off before entering the next negative half cycle of the power frequency; It is determined that the dead time of the power frequency is cut into the negative half cycle of the power frequency, the high-frequency main switch tube S1 of the main phase high-frequency bridge arm switch and the high-frequency main switch tube S3 of the slave phase high-frequency bridge arm switch are turned on, the synchronous tube S2 of the main phase high-frequency bridge arm switch and the synchronous tube S4 of the slave phase high-frequency bridge arm switch are turned on, the power frequency upper tube S5 is long, and the power frequency lower tube S6 is always off; It is determined that the negative half cycle of the power frequency is cut into the dead time of the power frequency, the high-frequency main switch tube S1 of the main phase high-frequency bridge arm switch, the high-frequency main switch tube S3 of the slave phase high-frequency bridge arm switch and the power frequency upper tube S5 are turned off, and the synchronous tube S2 of the main phase high-frequency bridge arm switch and the synchronous tube S4 of the slave phase high-frequency bridge arm switch continue to be turned on in the form of high-frequency narrow pulse and are turned off before entering the next positive half cycle of the power frequency.

9. A zero-crossing current stress limiting method as claimed in claim 8, characterized in that: The inversion working mode comprises: It is determined that the dead time of the power frequency is cut into the positive half cycle of the power frequency, the high-frequency main switch tube S1 of the main phase high-frequency bridge arm switch and the high-frequency main switch tube S3 of the slave phase high-frequency bridge arm switch are turned on, the synchronous tube S2 of the main phase high-frequency bridge arm switch and the synchronous tube S4 of the slave phase high-frequency bridge arm switch are turned on, the power frequency lower tube S6 is long, and the power frequency upper tube S5 is always off; It is determined that the positive half cycle of the power frequency is cut into the dead time of the power frequency, the high-frequency main switch tube S2 of the main phase high-frequency bridge arm switch, the high-frequency main switch tube S4 of the slave phase high-frequency bridge arm switch and the power frequency lower tube S6 are turned off, and the high-frequency main switch tube S1 of the main phase high-frequency bridge arm switch and the high-frequency main switch tube S3 of the slave phase high-frequency bridge arm switch continue to be turned on in the form of high-frequency narrow pulse and are turned off before entering the next negative half cycle of the power frequency; It is determined that the dead time of the power frequency is cut into the negative half cycle of the power frequency, the high-frequency main switch tube S2 of the main phase high-frequency bridge arm switch and the high-frequency main switch tube S4 of the slave phase high-frequency bridge arm switch are turned on, the synchronous tube S1 of the main phase high-frequency bridge arm switch and the synchronous tube S3 of the slave phase high-frequency bridge arm switch are turned on, the power frequency upper tube S5 is long, and the power frequency lower tube S6 is always off; It is determined that the negative half cycle of the power frequency is cut into the dead time of the power frequency, the high-frequency main switch tube S1 of the main phase high-frequency bridge arm switch, the high-frequency main switch tube S3 of the slave phase high-frequency bridge arm switch and the power frequency upper tube S5 are turned off, and the synchronous tube S2 of the main phase high-frequency bridge arm switch and the synchronous tube S4 of the slave phase high-frequency bridge arm switch continue to be turned on in the form of high-frequency narrow pulse and are turned off before entering the next positive half cycle of the power frequency.

10. A zero-crossing current stress limiting device applied to a totem-pole PFC circuit, characterized in that: The zero-crossing current stress limiting device comprises: A sampling unit is configured to sample an input voltage signal of the totem column PFC circuit; A judgment unit is configured to determine a current working stage according to the input voltage signal. The release unit is used for determining the time of entering the power frequency dead zone, and controlling the high-frequency main switch tube to release the energy kept in the junction capacitor of the power frequency switch tube.

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