Low dropout regulator (LDO) over-current protection circuit, method and equipment without static power consumption and medium

Abstract

The invention discloses an LDO (Low Dropout Regulator) overcurrent protection circuit without static power consumption, a method, equipment and a medium, and relates to the technical field of overcurrent protection circuits. The circuit comprises a current sampling module which is used for collecting the output current of a power tube of the LDO according to a first proportion; the switch module is connected with the grid electrode of the power tube; the current limiting module is used for collecting the output current collected by the current sampling module according to a second proportion, the current limiting module is connected with the switch module and the current sampling module, and the current limiting module is further used for controlling whether the switch module is switched on or not; the overcurrent starting module is connected with the current limiting module and the current sampling module, and the overcurrent starting module is used for controlling whether the current sampling module and the current limiting module are started or not; when the output current continues to rise to the overcurrent value, the switch module is conducted, the grid voltage of the power tube is limited, and therefore the output current is limited to continue to rise. The first preset value is smaller than the overcurrent value. The circuit can perform overcurrent protection on the LDO and reduce power consumption.

Description

Technical Field

[0001] This invention relates to the field of overcurrent protection circuit technology, and in particular to an LDO overcurrent protection circuit, method, device and medium with no static power consumption. Background Technology

[0002] Low dropout regulators (LDOs) are widely used in integrated circuits, providing high-precision, low-noise, and highly stable power supplies to various modules within the circuitry. However, LDOs are susceptible to burnout under conditions of current overload or short circuit. Overcurrent protection circuits, acting as auxiliary circuits for LDOs, can quickly adjust the LDO's operating state to prevent damage when a short circuit or excessive load current occurs.

[0003] Currently, there are two main types of overcurrent protection circuits used for LDOs: one is the traditional fixed overcurrent limit LDO protection circuit (such as...). Figure 1 As shown), one type is the foldback overcurrent protection circuit (such as...). Figure 2 (As shown).

[0004] The maximum output current of a traditional fixed overcurrent limit protection circuit is a fixed value, and it is mainly divided into three parts (such as...). Figure 1 (As shown): A current sampling module consisting of NM1 and PM1; a current comparison module consisting of PM2, NM2, and NM3; and a switching transistor consisting of NM4. The current sampling module collects the current of the power transistor (M POWER) and mirrors it from PM1 to PM2. NM3 mirrors the reference current flowing through NM2. When the power transistor current increases, the gate voltage of PM2 decreases, and the current flowing through PM2 tends to increase. However, NM3 is biased by a fixed gate voltage. Therefore, in response to the current increase, the voltage at point P will rise. When the current rises to a certain level, the switching transistor NM4 starts to conduct, clamping the gate voltage of the power transistor, thereby limiting the current from continuing to rise.

[0005] When the current in a foldback overcurrent protection circuit reaches the overcurrent limit, the reference current continuously decreases, thus the LDO's output current also decreases, eventually reaching a lower level. It mainly consists of four parts (as shown in Figure 2): a current acquisition circuit composed of NM1 and PM1; a current comparison module composed of PM2 and NM3; a switching transistor composed of NM2; and a current foldback module composed of NM4, PM3, PM4, NM5, resistors R1 and R2, and error amplifier EA1. Its current acquisition circuit, switching transistor, and current comparison circuit operate on the same principle as traditional fixed overcurrent limit protection circuits. The positive input of the error amplifier EA1 in its current foldback module is connected to the LDO's output voltage. When the LDO is working normally, the error amplifier's output voltage remains stable, and the current limit value remains stable at its initial value. When the load continues to increase, but the load current cannot continue to rise, the LDO's output voltage will decrease. Therefore, the error amplifier will cause the reference current to decrease, thus decreasing the overcurrent value. The LDO's output current will also decrease accordingly until it reaches a lower level.

[0006] Depend on Figure 1 It can be seen that the fixed overcurrent limit LDO protection circuit will continue to work even when the LDO is not overcurrent, which will increase the power consumption of the LDO during normal operation. Furthermore, when the LDO is powered on, the gate voltage of the switching transistor is not low. Although the switching transistor is in the off state, it still has the tendency to limit the gate voltage of the power transistor from continuing to rise, which will have a significant impact on the LDO's settling time.

[0007] The folded-back overcurrent protection circuit remains operational even when the LDO is not experiencing an overcurrent, thus incurring static power consumption and impacting overall system power consumption. It also affects the LDO's settling time. Furthermore, the folded-back overcurrent protection circuit suffers from latch-up, posing a risk of failing to start the load. Additionally, its complex structure and large footprint limit its practicality compared to other overcurrent protection circuits. Summary of the Invention

[0008] The present invention aims to at least solve one of the technical problems existing in the prior art. To this end, the present invention proposes an LDO overcurrent protection circuit, method, device, and medium with zero static power consumption, which can protect the LDO from overcurrent and reduce power consumption.

[0009] In a first aspect, according to an embodiment of the present invention, an LDO overcurrent protection circuit with no static power consumption includes: The current sampling module is used to sample the output current of the power transistor of the LDO according to a first ratio; A switching module is connected to the gate of the power transistor; A current limiting module is used to collect the output current collected by the current sampling module according to a second ratio. The current limiting module is connected to the switching module and the current sampling module. The current limiting module is also used to control whether the switching module is turned on. An overcurrent start-up module is connected to the current limiting module and the current sampling module. The overcurrent start-up module is used to control whether the current sampling module and the current limiting module are started. Specifically, when the output current of the LDO is lower than a first preset value, the current sampling module, the switching module, the current limiting module, and the overcurrent activation module are all inactive; when the output current rises to the first preset value, the current limiting module and the overcurrent activation module start working, and the switching module is in an off state; when the output current continues to rise to the overcurrent value, the switching module turns on, limiting the gate voltage of the power transistor, thereby limiting the output current from continuing to rise; the first preset value is less than the overcurrent value.

[0010] According to some embodiments of the present invention, the current sampling module includes: The first MOSFET has its gate connected to the gate of the power transistor, and its source connected to the source of the power transistor. The second MOSFET has its drain connected to the drain of the first MOSFET, and its gate connected to the current limiting module and the overcurrent start-up module. The third MOS transistor has its drain connected to the source of the second MOS transistor, its source connected to a power supply, and its gate connected to the current limiting module and the overcurrent start-up module.

[0011] According to some embodiments of the present invention, the current limiting module includes: The fourth MOS transistor has its gate connected to the gate of the second MOS transistor and the overcurrent startup module. The drain of the fourth MOS transistor is grounded through multiple resistors connected in series. One end of one of the resistors is connected to the overcurrent startup module, and one end of the other resistor is connected to the switching module. The fifth MOS transistor has its drain connected to the source of the fourth MOS transistor, its source connected to the power supply, and its gate connected to the gate of the third MOS transistor and the overcurrent startup module.

[0012] According to some embodiments of the present invention, the overcurrent startup module includes: The sixth MOS transistor has its source connected to the power supply, and its gate is connected to its drain, the gate of the third MOS transistor, and the gate of the fifth MOS transistor. The seventh MOS transistor has its source connected to the drain of the sixth MOS transistor, and its gate connected to the gate of the second MOS transistor, the gate of the fourth MOS transistor, and the drain of the first MOS transistor. The eighth MOS transistor has its drain connected to the drain of the seventh MOS transistor, its gate connected to one end of one of the resistors, and its source grounded.

[0013] According to some embodiments of the present invention, the switching module includes a ninth MOS transistor, the drain of the ninth MOS transistor is connected to the gate of the first MOS transistor and the gate of the power transistor, the source of the ninth MOS transistor is grounded, and the gate of the ninth MOS transistor is connected to one end of another resistor.

[0014] According to some embodiments of the present invention, the gate length of the first MOS transistor is the same as the gate length of the power transistor, and the ratio of the gate width of the first MOS transistor to the gate width of the power transistor is equal to the first ratio.

[0015] According to some embodiments of the present invention, the setting of the gate length to gate width ratio of the second MOS transistor and the gate length to gate width ratio of the third MOS transistor is such that when the output current rises to the overcurrent value, the first MOS transistor operates in the nonlinear region.

[0016] In a second aspect, according to an embodiment of the present invention, an overcurrent protection method based on an LDO overcurrent protection circuit with no static power consumption as described in the first aspect embodiment, the method includes: The output current of the LDO's power transistor is acquired by the current sampling module at a first ratio. The output current collected by the current sampling module is acquired by the current limiting module at a second ratio; When the output current is lower than the first preset value, the current sampling module, the switching module, the current limiting module, and the overcurrent start module are all disabled. When the output current rises to the first preset value, the current sampling module, the current limiting module and the overcurrent start module start working, and the switching module is in the off state. When the output current continues to rise to the overcurrent value, the switching module is turned on to limit the gate voltage of the power transistor and limit the output current from rising further; the first preset value is less than the overcurrent value.

[0017] Thirdly, an electronic device according to an embodiment of the present invention includes the LDO overcurrent protection circuit with no static power consumption described in the first aspect embodiment.

[0018] Fourthly, according to an embodiment of the present invention, the storage medium stores computer-executable instructions for causing a computer to perform the overcurrent protection method described in the second aspect embodiment.

[0019] The LDO overcurrent protection circuit, method, device, and medium with zero static power consumption according to embodiments of the present invention have at least the following beneficial effects: The overcurrent activation module controls whether the current sampling module and the current limiting module are activated. When the output current of the LDO's power transistor is small, the LDO operates normally, and there is no risk of overcurrent. The current sampling module, switching module, current limiting module, and overcurrent activation module are all inactive, thus saving the LDO's static power consumption. When the output current of the LDO's power transistor gradually increases and reaches a set first preset value, it is close to overcurrent but not yet truly overcurrent. At this point, the overcurrent activation module is activated first, driving the current sampling module and the current limiting module to activate as well. When the output current of the LDO's power transistor continues to increase to the overcurrent value, the current limiting module controls the switching module to conduct, causing the switching module to limit the gate voltage of the power transistor, thereby limiting the output current from continuing to rise and achieving overcurrent protection for the LDO. This circuit only operates when the output current is large, thus reducing the circuit's static power consumption.

[0020] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0021] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is a circuit diagram of a fixed overcurrent limit LDO protection circuit in the prior art; Figure 2 This is a circuit diagram of a foldback overcurrent protection circuit according to an embodiment of the present invention; Figure 3 This is a block diagram of an LDO overcurrent protection circuit with no static power consumption according to an embodiment of the present invention. Figure 4 The circuit diagram is shown for an LDO overcurrent protection circuit with no static power consumption according to an embodiment of the present invention. Figure 5 This is a graph showing the change in output current of the power transistor as a function of load impedance in an embodiment of the present invention. Figure 6This is a graph showing the change of current in the first MOS transistor as a function of load impedance in an embodiment of the present invention. Figure 7 This is a graph showing the change of the gate voltage of the power transistor as a function of the load impedance in an embodiment of the present invention. Figure 8 This is a flowchart illustrating the steps of an overcurrent protection method according to an embodiment of the present invention. Detailed Implementation

[0022] The embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. The step numbers in the following embodiments are set only for ease of explanation, and there is no limitation on the order between the steps. The execution order of each step in the embodiments can be adaptively adjusted according to the understanding of those skilled in the art.

[0023] In the description of this invention, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., are based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0024] The terms "first," "second," "third," and "fourth," etc., used in the specification, claims, and accompanying drawings of this invention are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0025] In this invention, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0026] This invention provides an LDO overcurrent protection circuit, method, device, and medium with no static power consumption. The circuit includes: a current sampling module for sampling the output current of the LDO's power transistor at a first ratio; a switching module connected to the gate of the power transistor; a current limiting module for sampling the output current sampled by the current sampling module at a second ratio, the current limiting module being connected to the switching module and the current sampling module, and the current limiting module also controlling whether the switching module is turned on; and an overcurrent activation module connected to the current limiting module and the current sampling module, the overcurrent activation module being used to control... The system controls whether the current sampling module and the current limiting module are activated; wherein, when the output current of the LDO is lower than a first preset value, the current sampling module, the switching module, the current limiting module, and the overcurrent activation module are all inactive; when the output current rises to the first preset value, the current limiting module and the overcurrent activation module start working, and the switching module is in an off state; when the output current continues to rise to the overcurrent value, the switching module is activated, limiting the gate voltage of the power transistor, thereby limiting the output current from continuing to rise; the first preset value is less than the overcurrent value. This circuit uses an overcurrent activation module to control the startup of the current sampling module and the current limiting module. When the output current of the LDO's power transistor is low, the LDO operates normally, posing no overcurrent risk. The current sampling module, switching module, current limiting module, and overcurrent activation module are all inactive, thus saving the LDO's static power consumption. As the LDO's power transistor's output current gradually increases and reaches a preset first value, it approaches an overcurrent but hasn't actually become one. At this point, the overcurrent activation module activates first, triggering the current sampling module and the current limiting module. When the LDO's power transistor's output current continues to increase to the overcurrent value, the current limiting module controls the switching module to conduct, limiting the gate voltage of the power transistor and thus preventing the output current from rising further, achieving overcurrent protection for the LDO. This circuit only activates when the output current is high, thereby reducing the circuit's static power consumption.

[0027] The following describes in detail, with reference to the accompanying drawings, the LDO overcurrent protection circuit, method, device and medium with no static power consumption according to embodiments of the present invention.

[0028] On the one hand, embodiments of the present invention propose an LDO overcurrent protection circuit with no static power consumption, such as... Figure 3As shown, the circuit includes a current sampling module 100, a current limiting module 200, an overcurrent start-up module 300, and a switching module 400. The current sampling module 100 is used to sample the output current of the LDO's power transistor (M POWER) at a first ratio. The current limiting module 200 is connected to the switching module 400, the overcurrent start-up module 300, and the current sampling module 100. The current limiting module 200 is used to sample the output current sampled by the current sampling module 100 at a second ratio and also controls whether the switching module 400 is turned on. The switching module 400 is connected to the gate of the power transistor. The overcurrent start-up module 300 is connected to the current limiting module 200 and the current sampling module 100 and controls whether the current sampling module 100 and the current limiting module 200 are activated. When the LDO... When the output current is lower than the first preset value, the current sampling module 100, the switching module 400, the current limiting module 200, and the overcurrent start-up module 300 are all inactive. When the output current rises to the first preset value, the current sampling module 100, the current limiting module 200, and the overcurrent start-up module 300 start working, and the switching module 400 is in the off state. When the output current continues to rise to the overcurrent value, the switching module 400 turns on, limiting the gate voltage of the power transistor, thereby limiting the output current from continuing to rise. The first preset value is less than the overcurrent value.

[0029] According to the LDO overcurrent protection circuit with no static power consumption according to the embodiments of this application, the overcurrent activation module 300 controls whether the current sampling module 100 and the current limiting module 200 are activated. When the output current of the LDO power transistor is small, the LDO is working normally and there is no risk of overcurrent. The current sampling module 100, the switching module 400, the current limiting module 200, and the overcurrent activation module 300 are all inactive, thereby saving the static power consumption of the LDO. When the output current of the LDO power transistor gradually increases and reaches a set first preset value, it is close to overcurrent but has not yet actually become overcurrent. At this time, the overcurrent activation module 300 is activated, which also drives the current sampling module 100 and the current limiting module 200 to activate. When the output current of the LDO power transistor continues to increase to the overcurrent value, the current limiting module 200 controls the switching module 400 to conduct, so that the switching module 400 limits the gate voltage of the power transistor, thereby limiting the output current from continuing to rise and realizing overcurrent protection for the LDO. This circuit only operates when the output current is large, thereby reducing the static power consumption of the circuit.

[0030] Furthermore, such as Figure 4As shown, in some embodiments of this application, the current sampling module 100 includes a first MOSFET NM6, a second MOSFET PM5, and a third MOSFET PM6. The gate of the first MOSFET NM6 is connected to the gate of the power transistor (M POWER), the source of the first MOSFET NM6 is connected to the source of the power transistor, the drain of the power transistor is connected to the power supply (VDD), and the source of the power transistor is grounded through a feedback resistor R. The source of the power transistor is also used to output the output current (ILOAD) of the LDO. The drain of the second MOSFET PM5 is connected to the drain of the first MOSFET NM6, and the gate of the second MOSFET PM5 is connected to the current limiting module 200 and the overcurrent startup module 300. The drain of the third MOSFET PM6 is connected to the source of the second MOSFET PM5, the source of the third MOSFET PM6 is connected to the power supply VDD, and the gate of the third MOSFET PM6 is connected to the current limiting module 200 and the overcurrent startup module 300.

[0031] In this example, the current sampling module 100 consists of NM6, PM5, and PM6. The first MOSFET NM6 accurately replicates the current of the power transistor. Since the gate-source of the first MOSFET NM6 is connected to the gate-source of the power transistor M POWER, their VGS (Voltage between Gate and Source) are equal, enabling sampling of the power transistor's current. To improve sampling accuracy, the gate length of the first MOSFET NM6 is made consistent with the gate length of the power transistor. Because the current of the power transistor is too large, we need to scale down the current. We sample the power transistor's output current according to a first ratio, ensuring consistent gate lengths. The sampled current is K1 times the power transistor's load current ILOAD (K1...). 1. K1 is the first ratio. We only need to adjust the gate width of the first MOSFET NM6 to K1 times the gate width of the power transistor. The second MOSFET PM5 and the third MOSFET PM6 carry current through the first MOSFET NM6. The second MOSFET PM5 is connected as a diode with a self-biased gate voltage. The gate voltages of both the second MOSFET PM5 and the third MOSFET PM6 are provided by the overcurrent start-up module 300. The overcurrent start-up module 300 controls that the second MOSFET PM5 and the third MOSFET PM6 are not conducting when there is no overcurrent. However, when there is an overcurrent, the voltage drop from the second MOSFET PM5 and the third MOSFET PM6 to the drain terminal of the first MOSFET NM6 is the VDSAT (saturation drain-source voltage) of PM6 and the VGS of PM5. To prevent the first MOSFET NM6 from entering the linear region during overcurrent operation, we can set the width-to-length ratio of both the second MOSFET PM5 and the third MOSFET PM6 to be larger, so that the VDSAT of PM6 and the VGS of PM5 are slightly smaller during overcurrent operation, thus preventing the first MOSFET NM6 from entering the linear region and causing inaccurate current sampling.

[0032] Furthermore, such as Figure 4 As shown, in some embodiments of this application, the current limiting module 200 includes: a fourth MOSFET PM8 and a fifth MOSFET PM7. The gate of the fourth MOSFET PM8 is connected to the gate of the second MOSFET PM5 and the overcurrent startup module 300. The drain of the fourth MOSFET PM8 is grounded through a plurality of resistors connected in series. One end of one resistor is connected to the overcurrent startup module 300, and one end of the other resistor is connected to the switching module 400. The drain of the fifth MOSFET PM7 is connected to the source of the fourth MOSFET PM8. The source of the fifth MOSFET PM7 is connected to the power supply. The gate of the fifth MOSFET PM7 is connected to the gate of the third MOSFET PM6 and the overcurrent startup module 300. In this example, multiple resistors connected in series include resistors R3, R4, and R5. One end of resistor R3 is connected to the drain of the fourth MOSFET PM8, the other end of resistor R3 is connected to one end of resistor R4, the other end of resistor R4 is connected to one end of resistor R5, and the other end of resistor R5 is grounded. One end of resistor R4 is connected to the overcurrent startup module 300, and the other end of resistor R5 is connected to the switching module 400. It should be noted that the number of resistors connected in series can be set according to actual needs, and is not limited to this.

[0033] In this example, PM7, PM8, R3, R4, and R5 constitute the current limiting module 200. Within the current limiting module 200, PM7 and PM8 precisely replicate the output current collected by the current sampling module 100, and the connected resistors generate a voltage to provide a gate voltage to the switching module 400, controlling whether the switching module 400 is turned on. Since one end of resistor R4 is connected to the overcurrent startup module 300, the voltage at one end of resistor R4 can control whether the overcurrent startup module 300 operates. The overcurrent startup module 300 then controls whether PM5, PM6, PM7, and PM8 are turned on, thereby controlling the operating state of the current limiting module 200 and the current sampling module 100. Because the gate of PM7 is connected to the gate of PM6, and the gate of PM8 is connected to the gate of PM5, PM8 and PM7 form a common-source, common-gate current mirror, which can precisely replicate the currents of PM6 and PM5 at a second ratio. Even after the current sampling module (100) reduces the current by a factor of 1, the output current of the power transistor is still relatively large. We need to further reduce it. Therefore, we make the gate length of PM7 equal to that of PM5, and the gate width of PM7 K2 times that of PM5 (K2 is less than 1, so K2 is the second factor). The gate length of PM8 is equal to that of PM5, and the gate width of PM8 is K2 times that of PM5. Therefore, the current flowing through PM8 and PM7 when they are turned on is ILOAD. K2 K1. This current then passes through resistors R3, R4, and R5, generating a voltage at the positive terminal of the resistors. The positive terminal of R5 is connected to the switch module 400 to control whether the switch module 400 is turned on, and the positive terminal of R4 is connected to the overcurrent start module 300 to control whether the overcurrent start module 300 is started.

[0034] Furthermore, such as Figure 4 As shown, in some embodiments of this application, the overcurrent start-up module 300 includes a sixth MOSFET PM9, a seventh MOSFET PM10, and an eighth MOSFET NM8. The source of the sixth MOSFET PM9 is connected to the power supply, and the gate of the sixth MOSFET PM9 is connected to the drain of the sixth MOSFET PM9, the gate of the third MOSFET PM6, and the gate of the fifth MOSFET PM7. The source of the seventh MOSFET PM10 is connected to the drain of the sixth MOSFET PM9, and the gate of the seventh MOSFET PM10 is connected to the gate of the second MOSFET PM5, the gate of the fourth MOSFET PM8, and the drain of the first MOSFET NM6. The drain of the eighth MOSFET NM8 is connected to the drain of the seventh MOSFET PM10, the gate of the eighth MOSFET NM8 is connected to one end of the resistor R4, and the source of the eighth MOSFET NM8 is grounded.

[0035] In the overcurrent startup module 300, the sixth MOSFET PM9 is connected as a diode, and its gate voltage generated by self-biasing is provided to PM6 and PM7 to control whether the entire circuit works. The gate voltage of the seventh MOSFET PM10 is provided by the gate voltage generated by the self-biasing of PM5. PM9 and PM10 form a pseudo common-source common-gate current mirror, the purpose of which is to make its current consistent with that of PM7 and PM8 when it is turned on.

[0036] Furthermore, such as Figure 4 As shown, in some embodiments of this application, the switching module 400 includes a ninth MOSFET NM7. The drain of the ninth MOSFET NM7 is connected to the gate of the first MOSFET NM6 and the gate of the power transistor. The source of the ninth MOSFET NM7 is grounded, and the gate of the ninth MOSFET NM7 is connected to one end of a resistor R5. The gate of the first MOSFET NM6 and the gate of the power transistor are also connected to a bias voltage VGAT.

[0037] The following details how the entire overcurrent protection circuit works: When the load current of the power transistor is small, if the current limiting module 200 is turned on, the current flowing through PM7 and PM8 should be ILOAD. K2 If K1 is given, then the voltage at the gate of NM8 should be (R4 + R5). ILOAD K2 K1. When this voltage is less than the turn-on voltage V of NM8. ON·NM8At this time, the overcurrent startup module 300 is not turned on, the gate voltage generated by PM9's self-biasing is close to VDD, and PM7 and PM6 are not turned on. Therefore, the entire circuit does not start, and the actual current flowing through the resistor is 0, and the gate voltage of NM8 is also 0. As the load current of the power transistor increases, although no current flows through the resistor, it tends to generate voltage. Once (R4+R5) ILOAD K2 K1 is greater than V ON·NM8 When NM8 has a tendency to conduct, PM9 generates a gate voltage through self-biasing, which is supplied to PM7 and PM6, causing PM7 and PM6 to conduct. At this point, the protection circuit is officially activated. To ensure that the entire protection circuit is activated when the overcurrent start-up module 300 has a conduction tendency, we can make the aspect ratio of PM9 slightly larger than that of PM7, and keep the aspect ratio of PM10 the same as that of PM8. In this way, when the overcurrent start-up module 300 is activated, the VGS generated by PM9 is slightly larger than the VGS required by PM7 and PM6, and the circuit will definitely conduct. Therefore, we can see that when the protection circuit is activated, the load current of the power transistors is: ; To ensure more stable operation of the protection circuit, we avoid simultaneously turning on the protection circuit and the switching module 400. Doing so would cause extreme instability in the gate voltage of NM7, resulting in the overcurrent protection circuit switching back and forth between on and off states. Therefore, we enable the entire overcurrent protection circuit to conduct at a certain current value (i.e., a first preset value) before reaching the overcurrent value, and only turn on NM7 when the overcurrent value is reached. Let the overcurrent value be I. OVERLOAD , then I START OVERLOAD .

[0038] After the overcurrent protection circuit is activated, as the load current of the power transistor continues to increase, the current flowing through R3 will continue to increase, and its gate voltage R3 will rise. ILOAD K2 As K1 increases, when the gate voltage exceeds the turn-on voltage VON·NM2 of the switching transistor, the switching transistor turns on, thus limiting the gate voltage of the power transistor and consequently limiting the current of the power transistor from rising further. The overcurrent value at this point is: .

[0039] Next, we will perform simulation verification on the circuit, such as... Figure 5 The graph shown is a graph of the power transistor's output current versus load impedance. The vertical axis represents the IPOWERMOS output current, and the horizontal axis represents the RLOAD load impedance. Figure 6 The image shows the current of the first MOSFET NM6 as a function of the load impedance, with the vertical axis representing the current of NM6; Figure 7 ​The image shows the change in voltage VGAT as a function of load impedance. As the load impedance decreases, the output current of the power transistor gradually increases. At point A, with a load of approximately 80 ohms, the load current of the power transistor is about 67mA. At this time, the current of the first MOSFET NM6 in the current sampling module 100 is 21.4nA, approaching zero, and the gate voltage provided by the switching transistor NM7 is about 0.7mV. It can be seen that at this time, the current limiting module 200, the overcurrent start-up module 300, and the switching module 400 are not operating. When the load impedance decreases to around 29 ohms, the load current of the power transistor is 180mA, and the current of the first MOSFET NM6 begins to rise to 25uA. The current limiting module 200 and the overcurrent start-up module 300 begin to operate. At this time, the gate voltage of NM7 begins to rise, but it has not reached the turn-on condition and does not begin to limit the current. When the load impedance decreases to around 20 ohms, the gate voltage of NM7 rises to 850mV, begins to conduct, and begins to limit the current and slowly reduce it to a lower level.

[0040] As can be seen, when the LDO is working normally, the entire overcurrent protection circuit is not activated and there is no static power consumption. When the LDO load current is large, the current limiting module 200 and the overcurrent activation module 300 are activated first, and NM7 is not turned on at this time. When the load current reaches the set overcurrent value, NM7 turns on, and the load current is limited. The activation current and overcurrent current of the entire overcurrent protection circuit can be adjusted by adjusting the resistor value and the MOSFET size.

[0041] The LDO overcurrent protection circuit with no static power consumption according to this application has no static power consumption, no impact on the LDO set-up process, no latch-up effect, fast recovery capability, and simple structure and small area compared with traditional fixed-limit overcurrent protection circuits and foldback overcurrent protection circuits. It also has strong practicality.

[0042] On the other hand, such as Figure 8 As shown, based on the above-described LDO overcurrent protection circuit with no static power consumption, this application embodiment also proposes an overcurrent protection method, which includes the following steps: Step S100: The output current of the LDO's power transistor is acquired by the current sampling module 100 according to the first ratio; Step S200: The current limiting module 200 collects the output current collected by the current sampling module 100 according to the second ratio; Step S300: When the output current is lower than the first preset value, the current sampling module 100, the switching module 400, the current limiting module 200 and the overcurrent start module 300 are all disabled. Step S400: When the output current rises to the first preset value, the current sampling module 100, the current limiting module 200 and the overcurrent start module 300 are activated, and the switch module 400 is put into the off state. Step S500: When the output current continues to rise to the overcurrent value, the switching module 400 is turned on to limit the gate voltage of the power transistor and limit the output current from continuing to rise; the first preset value is less than the overcurrent value.

[0043] Specifically, see Figure 4 In this example, the current sampling module 100 is composed of NM6, PM5, and PM6. The first MOSFET NM6 accurately replicates the current of the power transistor. Since the gate-source of the first MOSFET NM6 is connected to the gate-source of the power transistor M POWER, their VGS (Voltage between Gate and Source) are equal, enabling sampling of the power transistor's current. To improve sampling accuracy, the gate length of the first MOSFET NM6 is made consistent with the gate length of the power transistor. Because the current of the power transistor is too large, we need to scale down the current. We sample the power transistor's output current according to a first ratio, ensuring consistent gate lengths. The sampled current is K1 times the power transistor's load current ILOAD (K1...). 1. K1 is the first ratio. We only need to adjust the gate width of the first MOSFET NM6 to K1 times the gate width of the power transistor. The second MOSFET PM5 and the third MOSFET PM6 carry current through the first MOSFET NM6. The second MOSFET PM5 is connected as a diode with a self-biased gate voltage. The gate voltages of both the second MOSFET PM5 and the third MOSFET PM6 are provided by the overcurrent start-up module 300. The overcurrent start-up module 300 controls that the second MOSFET PM5 and the third MOSFET PM6 are not conducting when there is no overcurrent. However, when there is an overcurrent, the voltage drop from the second MOSFET PM5 and the third MOSFET PM6 to the drain terminal of the first MOSFET NM6 is the VDSAT (saturation drain-source voltage) of PM6 and the VGS of PM5. To prevent the first MOSFET NM6 from entering the linear region during overcurrent operation, we can set the width-to-length ratio of both the second MOSFET PM5 and the third MOSFET PM6 to be larger, so that the VDSAT of PM6 and the VGS of PM5 are slightly smaller during overcurrent operation, thus preventing the first MOSFET NM6 from entering the linear region and causing inaccurate current sampling.

[0044] like Figure 4As shown, in this example, PM7, PM8, R3, R4, and R5 constitute the current limiting module 200. Within the current limiting module 200, PM7 and PM8 precisely replicate the output current collected by the current sampling module 100, and the connected resistors generate a voltage to provide a gate voltage to the switching module 400, controlling whether the switching module 400 is turned on. Since one end of resistor R4 is connected to the overcurrent startup module 300, the voltage at one end of resistor R4 can control whether the overcurrent startup module 300 operates. The overcurrent startup module 300 then controls whether PM5, PM6, PM7, and PM8 are turned on, thereby controlling the operating state of the current limiting module 200 and the current sampling module 100. Because the gate of PM7 is connected to the gate of PM6, and the gate of PM8 is connected to the gate of PM5, PM8 and PM7 form a common-source, common-gate current mirror, which can precisely replicate the currents of PM6 and PM5 at a second ratio. Even after the current sampling module (100) reduces the current by a factor of 1, the output current of the power transistor is still relatively large. We need to further reduce it. Therefore, we make the gate length of PM7 equal to that of PM5, and the gate width of PM7 K2 times that of PM5 (K2 is less than 1, so K2 is the second factor). The gate length of PM8 is equal to that of PM5, and the gate width of PM8 is K2 times that of PM5. Therefore, the current flowing through PM8 and PM7 when they are turned on is ILOAD. K2 K1. This current then passes through resistors R3, R4, and R5, generating a voltage at the positive terminal of the resistors. The positive terminal of R5 is connected to the switch module 400 to control whether the switch module 400 is turned on, and the positive terminal of R4 is connected to the overcurrent start module 300 to control whether the overcurrent start module 300 is started.

[0045] Furthermore, such as Figure 4 As shown, in some embodiments of this application, the overcurrent start-up module 300 includes a sixth MOSFET PM9, a seventh MOSFET PM10, and an eighth MOSFET NM8. The source of the sixth MOSFET PM9 is connected to the power supply, and the gate of the sixth MOSFET PM9 is connected to the drain of the sixth MOSFET PM9, the gate of the third MOSFET PM6, and the gate of the fifth MOSFET PM7. The source of the seventh MOSFET PM10 is connected to the drain of the sixth MOSFET PM9, and the gate of the seventh MOSFET PM10 is connected to the gate of the second MOSFET PM5, the gate of the fourth MOSFET PM8, and the drain of the first MOSFET NM6. The drain of the eighth MOSFET NM8 is connected to the drain of the seventh MOSFET PM10, the gate of the eighth MOSFET NM8 is connected to one end of the resistor R4, and the source of the eighth MOSFET NM8 is grounded.

[0046] In the overcurrent startup module 300, the sixth MOSFET PM9 is connected as a diode, and its gate voltage generated by self-biasing is provided to PM6 and PM7 to control whether the entire circuit works. The gate voltage of the seventh MOSFET PM10 is provided by the gate voltage generated by the self-biasing of PM5. PM9 and PM10 form a pseudo common-source common-gate current mirror, the purpose of which is to make its current consistent with that of PM7 and PM8 when it is turned on.

[0047] Furthermore, such as Figure 4 As shown, in some embodiments of this application, the switching module 400 includes a ninth MOSFET NM7. The drain of the ninth MOSFET NM7 is connected to the gate of the first MOSFET NM6 and the gate of the power transistor. The source of the ninth MOSFET NM7 is grounded, and the gate of the ninth MOSFET NM7 is connected to one end of a resistor R5. The gate of the first MOSFET NM6 and the gate of the power transistor are also connected to a bias voltage VGAT.

[0048] The following details how the entire overcurrent protection circuit works: When the load current of the power transistor is small, if the current limiting module 200 is turned on, the current flowing through PM7 and PM8 should be ILOAD. K2 If K1 is given, then the voltage at the gate of NM8 should be (R4 + R5). ILOAD K2 K1. When this voltage is less than the turn-on voltage V of NM8. ON·NM8 At this time, the overcurrent startup module 300 is not turned on, the gate voltage generated by PM9's self-biasing is close to VDD, and PM7 and PM6 are not turned on. Therefore, the entire circuit does not start, and the actual current flowing through the resistor is 0, and the gate voltage of NM8 is also 0. As the load current of the power transistor increases, although no current flows through the resistor, it tends to generate voltage. Once (R4+R5) ILOAD K2 K1 is greater than V ON·NM8 When NM8 has a tendency to conduct, PM9 generates a gate voltage through self-biasing, which is supplied to PM7 and PM6, causing PM7 and PM6 to conduct. At this point, the protection circuit is officially activated. To ensure that the entire protection circuit is activated when the overcurrent start-up module 300 has a conduction tendency, we can make the aspect ratio of PM9 slightly larger than that of PM7, and keep the aspect ratio of PM10 the same as that of PM8. In this way, when the overcurrent start-up module 300 is activated, the VGS generated by PM9 is slightly larger than the VGS required by PM7 and PM6, and the circuit will definitely conduct. Therefore, we can see that when the protection circuit is activated, the load current of the power transistors is: ; To ensure more stable operation of the protection circuit, we avoid simultaneously turning on the protection circuit and the switching module 400. Doing so would cause extreme instability in the gate voltage of NM7, resulting in the overcurrent protection circuit switching back and forth between on and off states. Therefore, we enable the entire overcurrent protection circuit to conduct at a certain current value (i.e., a first preset value) before reaching the overcurrent value, and only turn on NM7 when the overcurrent value is reached. Let the overcurrent value be I. OVERLOAD , then I START OVERLOAD .

[0049] After the overcurrent protection circuit is activated, as the load current of the power transistor continues to increase, the current flowing through R3 will continue to increase, and its gate voltage R3 will rise. ILOAD K2 As K1 increases, when the gate voltage exceeds the turn-on voltage VON·NM2 of the switching transistor, the switching transistor turns on, thus limiting the gate voltage of the power transistor and consequently limiting the current of the power transistor from rising further. The overcurrent value at this point is: .

[0050] Next, we will perform simulation verification on the circuit, such as... Figure 5 The graph shown is a graph of the power transistor's output current versus load impedance. The vertical axis represents the IPOWERMOS output current, and the horizontal axis represents the RLOAD load impedance. Figure 6 The image shows the current of the first MOSFET NM6 as a function of the load impedance, with the vertical axis representing the current of NM6; Figure 7 The image shows the change in voltage VGAT as a function of load impedance. As the load impedance decreases, the output current of the power transistor gradually increases. At point A, with a load of approximately 80 ohms, the load current of the power transistor is about 67mA. At this time, the current of the first MOSFET NM6 in the current sampling module 100 is 21.4nA, approaching zero, and the gate voltage provided by the switching transistor NM7 is about 0.7mV. It can be seen that at this time, the current limiting module 200, the overcurrent start-up module 300, and the switching module 400 are not operating. When the load impedance decreases to around 29 ohms, the load current of the power transistor is 180mA, and the current of the first MOSFET NM6 begins to rise to 25uA. The current limiting module 200 and the overcurrent start-up module 300 begin to operate. At this time, the gate voltage of NM7 begins to rise, but it has not reached the turn-on condition and does not begin to limit the current. When the load impedance decreases to around 20 ohms, the gate voltage of NM7 rises to 850mV, begins to conduct, and begins to limit the current and slowly reduce it to a lower level.

[0051] ​As can be seen, when the LDO is working normally, the entire overcurrent protection circuit is not activated and there is no static power consumption. When the LDO load current is large, the current limiting module 200 and the overcurrent activation module 300 are activated first, and NM7 is not turned on at this time. When the load current reaches the set overcurrent value, NM7 turns on, and the load current is limited. The activation current and overcurrent current of the entire overcurrent protection circuit can be adjusted by adjusting the resistor value and the MOSFET size.

[0052] The LDO overcurrent protection circuit with no static power consumption according to this application has no static power consumption, no impact on the LDO set-up process, no latch-up effect, fast recovery capability, and simple structure and small area compared with traditional fixed-limit overcurrent protection circuits and foldback overcurrent protection circuits. It also has strong practicality.

[0053] Thirdly, embodiments of this application also provide an electronic device, including an LDO overcurrent protection circuit with no static power consumption as described in the first aspect embodiment.

[0054] Fourthly, in another aspect, embodiments of the present invention also provide a storage medium, which is a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described overcurrent protection method.

[0055] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. Furthermore, memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory may optionally include memory remotely located relative to the processor, and these remote memories can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof. The device embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separate, and may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0056] Although specific embodiments are described herein, those skilled in the art will recognize that many other modifications or alternative embodiments are also within the scope of this disclosure. For example, any of the functions and / or processing capabilities described in connection with a particular device or component can be performed by any other device or component. Furthermore, while various exemplary embodiments and architectures have been described according to embodiments of this disclosure, those skilled in the art will recognize that many other modifications to the exemplary embodiments and architectures described herein are also within the scope of this disclosure.

[0057] The foregoing description, with reference to block diagrams and flowcharts of systems, methods, systems, and / or computer program products according to exemplary embodiments, has described certain aspects of this disclosure. It should be understood that one or more blocks in the block diagrams and flowcharts, as well as combinations of blocks in the block diagrams and flowcharts, can be implemented by executing computer-executable program instructions, respectively. Similarly, according to some embodiments, some blocks in the block diagrams and flowcharts may not need to be executed in the order shown, or may not all need to be executed. Furthermore, additional components and / or operations beyond those shown in the blocks in the block diagrams and flowcharts may exist in some embodiments.

[0058] Therefore, blocks in block diagrams and flowcharts support combinations of means for performing a specified function, combinations of elements or steps for performing a specified function, and program instruction means for performing a specified function. It should also be understood that each block in a block diagram and flowchart, and combinations of blocks in block diagrams and flowcharts, can be implemented by a dedicated hardware computer system or a combination of dedicated hardware and computer instructions that performs a specific function, element, or step.

[0059] The program modules, applications, etc., described herein may include one or more software components, including, for example, software objects, methods, data structures, etc. Each such software component may include computer-executable instructions that, in response to execution, cause at least a portion of the functionality described herein (e.g., one or more operations of the exemplary methods described herein) to be performed.

[0060] Software components can be coded using any of a variety of programming languages. An exemplary programming language could be a low-level programming language, such as assembly language associated with a specific hardware architecture and / or operating system platform. Software components including assembly language instructions may need to be converted into executable machine code by an assembler before being executed by the hardware architecture and / or platform. Another exemplary programming language could be a higher-level programming language that is portable across multiple architectures. Software components including higher-level programming languages ​​may need to be converted into an intermediate representation by an interpreter or compiler before execution. Other examples of programming languages ​​include, but are not limited to, macro languages, shell or command languages, job control languages, scripting languages, database query or search languages, or report writing languages. In one or more exemplary embodiments, a software component containing instructions from one of the above-described programming language examples can be executed directly by the operating system or other software components without first being converted into another form.

[0061] Software components can be stored as files or other data storage structures. Software components of similar type or related function can be stored together in a specific directory, folder, or library. Software components can be static (e.g., pre-defined or fixed) or dynamic (e.g., created or modified at runtime).

[0062] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present invention.

Claims

1. An LDO overcurrent protection circuit with no static power consumption, characterized in that, include: The current sampling module is used to sample the output current of the power transistor of the LDO according to a first ratio; A switching module is connected to the gate of the power transistor; A current limiting module is used to collect the output current collected by the current sampling module according to a second ratio. The current limiting module is connected to the switching module and the current sampling module. The current limiting module is also used to control whether the switching module is turned on. An overcurrent start-up module is connected to the current limiting module and the current sampling module. The overcurrent start-up module is used to control whether the current sampling module and the current limiting module are started. Specifically, when the output current of the LDO is lower than a first preset value, the current sampling module, the switching module, the current limiting module, and the overcurrent activation module are all inactive; when the output current rises to the first preset value, the current limiting module and the overcurrent activation module start working, and the switching module is in an off state; when the output current continues to rise to the overcurrent value, the switching module turns on, limiting the gate voltage of the power transistor, thereby limiting the output current from continuing to rise; the first preset value is less than the overcurrent value.

2. The LDO overcurrent protection circuit with no static power consumption according to claim 1, characterized in that, The current sampling module includes: The first MOS transistor has its gate connected to the gate of the power transistor, and its source connected to the source of the power transistor. The second MOSFET has its drain connected to the drain of the first MOSFET, and its gate connected to the current limiting module and the overcurrent start-up module. The third MOS transistor has its drain connected to the source of the second MOS transistor, its source connected to a power supply, and its gate connected to the current limiting module and the overcurrent start-up module.

3. The LDO overcurrent protection circuit with no static power consumption according to claim 2, characterized in that, The current limiting module includes: The fourth MOS transistor has its gate connected to the gate of the second MOS transistor and the overcurrent startup module. The drain of the fourth MOS transistor is grounded through multiple resistors connected in series. One end of one of the resistors is connected to the overcurrent startup module, and one end of the other resistor is connected to the switching module. The fifth MOS transistor has its drain connected to the source of the fourth MOS transistor, its source connected to the power supply, and its gate connected to the gate of the third MOS transistor and the overcurrent startup module.

4. The LDO overcurrent protection circuit with no static power consumption according to claim 3, characterized in that, The overcurrent startup module includes: The sixth MOS transistor has its source connected to the power supply, and its gate is connected to its drain, the gate of the third MOS transistor, and the gate of the fifth MOS transistor. The seventh MOS transistor has its source connected to the drain of the sixth MOS transistor, and its gate connected to the gate of the second MOS transistor, the gate of the fourth MOS transistor, and the drain of the first MOS transistor. The eighth MOS transistor has its drain connected to the drain of the seventh MOS transistor, its gate connected to one end of one of the resistors, and its source grounded.

5. The LDO overcurrent protection circuit with no static power consumption according to claim 3, characterized in that, The switching module includes a ninth MOS transistor, the drain of which is connected to the gate of the first MOS transistor and the gate of the power transistor, the source of which is grounded, and the gate of which is connected to one end of another resistor.

6. The LDO overcurrent protection circuit with no static power consumption according to claim 2, characterized in that, The gate length of the first MOS transistor is the same as the gate length of the power transistor, and the ratio of the gate width of the first MOS transistor to the gate width of the power transistor is equal to the first ratio.

7. The LDO overcurrent protection circuit with no static power consumption according to claim 2, characterized in that, The setting of the gate length to gate width ratio of the second MOSFET and the gate length to gate width ratio of the third MOSFET ensures that when the output current rises to the overcurrent value, the first MOSFET operates in the nonlinear region.

8. An overcurrent protection method, characterized in that, Based on the LDO overcurrent protection circuit with no static power consumption as described in any one of claims 1-7, the method includes: The output current of the LDO's power transistor is collected by the current sampling module at a first ratio. The output current collected by the current sampling module is acquired by the current limiting module at a second ratio; When the output current is lower than the first preset value, the current sampling module, the switching module, the current limiting module, and the overcurrent start module are all disabled. When the output current rises to the first preset value, the current sampling module, the current limiting module and the overcurrent start module start working, and the switching module is in the off state. When the output current continues to rise to the overcurrent value, the switching module is turned on to limit the gate voltage of the power transistor and limit the output current from rising further; the first preset value is less than the overcurrent value.

9. An electronic device, characterized in that, Includes an LDO overcurrent protection circuit with no static power consumption as described in any one of claims 1-7.

10. A storage medium, characterized in that, The storage medium stores computer-executable instructions for causing a computer to execute the overcurrent protection method of claim 8.

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