DC-DC converter with frequency locking control loop and control method thereof

Abstract

The invention discloses a DC-DC converter with a frequency locking control loop and a control method of the DC-DC converter, and belongs to the technical field of analog integrated circuits. The converter comprises an error amplifier, a pulse width modulation module, a turn-off time control module and a power tube driving module. According to the method, the output voltage is quickly stabilized and the conduction time is determined through the voltage loop and the current loop; meanwhile, the innovative frequency locking loop detects the switching frequency in real time, compares the switching frequency with an external reference clock, generates a turn-off time reference signal after frequency error integration, further dynamically adjusts the turn-off time of each period by comparing the reference signal with a synchronously generated linear ramp signal, and finally forms closed-loop negative feedback. And the switching frequency is accurately locked at a target value. On the premise that input voltage does not need to be sampled completely, rapid dynamic response comparable with frequency conversion control and accurate frequency locking and excellent EMI characteristics comparable with fixed frequency control are achieved at the same time, and system safety, reliability and electromagnetic compatibility are remarkably improved.

Description

Technical Field

[0001] This invention relates to the field of analog integrated circuit technology, and more specifically to a DC-DC converter with a frequency-locked control loop and its control method. Background Technology

[0002] Switching power supplies are widely used in automotive electronics, industrial electronics, and consumer electronics due to their efficient and flexible voltage conversion capabilities. As the core of a switching power supply, the performance of the DC-DC converter directly affects the stability, efficiency, and reliability of the entire electronic system. With increasingly demanding application scenarios, especially the electrification and intelligentization of automotive electronics, automotive-grade DC-DC converters face challenges such as high-voltage input, high-current loads, ultra-wide operating temperature ranges, and stringent electromagnetic compatibility (EMC) requirements.

[0003] To meet the demands for high efficiency and high power density, switching power supplies commonly employ pulse width modulation (PWM) technology. Traditional fixed-frequency PWM control, where the switching frequency is determined by an internal oscillator or an external clock source, has a simple structure. However, limited by the fixed switching cycle, this mode exhibits slow dynamic response when load or input voltage changes abruptly, failing to meet the rapid transient response requirements of modern high-performance applications.

[0004] To improve dynamic performance, peak current control modes based on constant on-time (COT) or constant off-time (COT) have emerged. These control modes belong to frequency conversion control, where the switching frequency is not a fixed value but changes with the input voltage, output voltage, and load current. By designing the on-time or off-time as a function of parameters such as input and output voltage, a relatively stable operating frequency can theoretically be obtained under specific operating conditions. For example, see attached... Figure 1 The TPS61087 series boost DC-DC converter chip shown employs a peak current control mode with constant off-time. In this system, the off-time (and thus indirectly affect the operating frequency) is set by a dedicated off-time control module (t_OFFGenerator) based on the input voltage (IN) information. While this approach balances dynamic response and frequency stability to some extent, its core drawback lies in the fact that the calculation and setting of the off-time depends on the direct or indirect detection of the input voltage. In many high-reliability applications, especially automotive-grade applications, considerations for electrical isolation, high-voltage safety, and functional safety (such as ISO 26262) prohibit or strictly limit the direct introduction of high-potential, high-noise input voltage signals to sensitive control chip pins. This makes such control strategies requiring input voltage information difficult to implement in practice, or even impossible.

[0005] Furthermore, the inherent frequency variation characteristics of variable frequency control mode also bring significant electromagnetic interference (EMI) challenges. Voltage and current spikes generated by power switches during high-speed switching are the main sources of EMI noise. If the switching frequency itself fluctuates or drifts with operating conditions, the resulting noise energy will be distributed over a wide frequency range, making it difficult to effectively suppress using preset filtering methods. This wide-spectrum noise may interfere with other sensitive circuits in the system, and may even fall into the automotive radio frequency (such as AM / FM broadcasting, GPS, V2X communication) bands, causing serious electromagnetic interference and endangering the functional safety and reliability of the entire vehicle. Summary of the Invention

[0006] To address the shortcomings of existing technologies, this invention provides a DC-DC converter with a frequency-locked control loop and its control method. This invention overcomes the deficiencies of existing technologies, is rationally designed, and achieves both fast dynamic response comparable to frequency conversion control and precise frequency locking and excellent EMI characteristics of fixed-frequency control without requiring input voltage sampling. This significantly improves system safety, reliability, and electromagnetic compatibility.

[0007] To achieve the above objectives, the present invention provides the following technical solution:

[0008] A DC-DC converter with a frequency-locked control loop includes an error amplifier, a pulse width modulation module, a turn-off time control module, and a power transistor drive module.

[0009] The first input terminal of the error amplifier receives the output voltage feedback signal of the DC-DC converter, and the second input terminal of the error amplifier receives the reference voltage signal. The error amplifier is used to amplify the error between the output voltage feedback signal and the reference voltage signal and output the error amplification signal.

[0010] The first input terminal of the pulse width modulation module is connected to the output terminal of the error amplifier to receive the error amplification signal. The second input terminal of the pulse width modulation module receives a sampling signal characterizing the inductor current, which is used to generate a first control signal to end the conduction phase of the power switch when the sampling signal reaches the error amplification signal. The third and fourth input terminals of the pulse width modulation module receive a turn-off time reference signal and a turn-off time ramp signal, respectively, which are used to generate a second control signal to end the turn-off phase of the power switch when the turn-off time ramp signal reaches the turn-off time reference signal.

[0011] The first input terminal of the turn-off time control module is connected to the feedback node of the drive signal of the power switch, and the second input terminal of the turn-off time control module receives an externally provided reference clock signal. The first output terminal of the turn-off time control module outputs a turn-off time reference signal to the third input terminal of the pulse width modulation module, and the second output terminal of the turn-off time control module outputs a turn-off time ramp signal to the fourth input terminal of the pulse width modulation module. The turn-off time control module is used to detect the error between the actual switching frequency of the drive signal and the target frequency of the reference clock signal, and generate a turn-off time reference signal based on the error to adjust the turn-off time of the power switch in a closed loop, so that the actual switching frequency is locked to the target frequency.

[0012] The input terminal of the power transistor drive module is connected to the output terminal of the pulse width modulation module, and is used to generate and output a drive signal according to the first control signal and the second control signal to control the power switch transistor to turn on and off.

[0013] Preferably, the shutdown time control module includes:

[0014] The first frequency discriminator has its input terminal connected to the feedback node of the drive signal, and is used to convert the frequency of the drive signal into a first voltage signal.

[0015] The second frequency discriminator receives the reference clock signal at its input terminal and is used to convert the frequency of the reference clock signal into a second voltage signal.

[0016] A switched capacitor integrator receives a first voltage signal at its first differential input terminal and a second voltage signal at its second differential input terminal. It is used to perform integration on the difference between the first voltage signal and the second voltage signal and output the integration result as a turn-off time reference signal.

[0017] A ramp signal generator, whose input is connected to the feedback node of the drive signal, is used to generate a linearly rising turn-off time ramp signal during the period when the drive signal indicates that the power switch is turned off.

[0018] Preferably, the first frequency discriminator and the second frequency discriminator have the same structure; both the first frequency discriminator and the second frequency discriminator include: a frequency division unit, a frequency to voltage conversion unit, and a filtering unit;

[0019] The frequency division unit includes a D flip-flop, the clock terminal of the D flip-flop receives the input clock signal, the D terminal of the D flip-flop is connected to its own inverted output terminal (QN), and the non-inverted output terminal (Q) of the D flip-flop outputs the frequency division control signal.

[0020] The frequency-to-voltage conversion unit includes a first capacitor (C). A ), constant current source (I)BIAS1 ), third switch (MOS3), fourth switch (MOS4) and second capacitor (C) S The constant current source (I) BIAS1 The first end of the capacitor (C) is connected to the power supply, and the second end is connected to the first node (N1); the first capacitor (C) A The third switch (MOS3) is connected between the first node (N1) and ground; the source of the third switch (MOS3) is connected to the first node (N1), the drain is connected to the second node (N2), and the gate receives the frequency division control signal; the second capacitor (C) is connected between the first node (N1) and ground. S The fourth switch (MOS4) is connected between the second node (N2) and ground; the fourth switch (MOS4) is connected in parallel with the second capacitor (C). S At both ends of the circuit, the gate of the fourth switch (MOS4) receives the frequency division control signal, and the conduction state of the fourth switch (MOS4) is opposite to that of the third switch (MOS3).

[0021] The input terminal of the filtering unit is connected to the first node (N1) and is used to filter the voltage signal on the first node (N1) and output a first voltage signal (V). DE ) or second voltage signal (V RE ).

[0022] Preferably, the ramp signal generator includes: a second capacitor (Cr) and a charging constant current source (I). BIAS2 ), the fifth switch (MOS5), and the sixth switch (MOS6);

[0023] The charging constant current source (I) BIAS2 The first terminal of the transistor is connected to the power supply, and the second terminal is connected to the source of the fifth switching transistor (MOS5); the drain of the fifth switching transistor (MOS5) is connected to the third node (N3), and the gate receives the drive signal (V) from the power switching transistor. DRV The second capacitor (Cr) is connected between the third node (N3) and ground; the sixth switch (MOS6) is connected in parallel across the second capacitor (Cr), and the gate of the sixth switch (MOS6) receives the drive signal (V) from the power switch. DRV );

[0024] The third node (N3) outputs the turn-off time ramp signal (Toff_ramp); when the drive signal (V DRV When the signal is low, the power switch is turned off. At this time, the fifth switch (MOS5) is turned on and the sixth switch (MOS6) is turned off, and the charging constant current source (I) BIAS2 The second capacitor (Cr) is charged with a constant current, causing the turn-off time ramp signal (Toff_ramp) to rise linearly; when the drive signal (V)DRV When the signal is high, it indicates that the power switch is turned on. At this time, the fifth switch (MOS5) is turned off and the sixth switch (MOS6) is turned on. The second capacitor (Cr) discharges rapidly through the sixth switch (MOS6), causing the turn-off time ramp signal (Toff_ramp) to reset to a low level.

[0025] Preferably, the switched capacitor integrator includes: an integrating operational amplifier, an integrating capacitor (Ci), a sampling capacitor (Cq), a first switching transistor (MOS1), a second switching transistor (MOS2), a first voltage buffer, and a second voltage buffer;

[0026] The input terminal of the first voltage buffer receives the first voltage signal (V). DE The output of the first voltage buffer is connected to the source of the first switching transistor (MOS1); the input of the second voltage buffer receives the second voltage signal (V). RE The output of the second voltage buffer is connected to the lower plate of the sampling capacitor (Cq) and the non-inverting input of the integrating operational amplifier; the inverting input of the integrating operational amplifier is connected to the source of the second switching transistor (MOS2) and the first terminal of the integrating capacitor (Ci); the output of the integrating operational amplifier outputs a turn-off time reference signal (Toff_ref) and is connected to the second terminal of the integrating capacitor (Ci); the upper plate of the sampling capacitor (Cq) is connected to the drain of the first switching transistor (MOS1) and the drain of the second switching transistor (MOS2); the gates of the first switching transistor (MOS1) and the second switching transistor (MOS2) receive a set of first clock signals (Φ1) and second clock signals (Φ2) that are out of phase and do not overlap.

[0027] When the first clock signal (Φ1) is valid, the first switch (MOS1) is turned on and the second switch (MOS2) is turned off, and the sampling capacitor (Cq) is charged to the first voltage signal (V). DE ) and the second voltage signal (V RE The difference voltage between the two; when the second clock signal (Φ2) is valid, the first switch (MOS1) is turned off and the second switch (MOS2) is turned on, the sampling capacitor (Cq) is connected between the inverting input terminal and the non-inverting input terminal of the integrating operational amplifier, and the charge corresponding to the difference voltage is transferred to the integrating capacitor (Ci), thereby adjusting the off-time reference signal (Toff_ref) output by the integrating operational amplifier.

[0028] Preferably, the sampling signal characterizing the inductor current is obtained by connecting a sampling resistor in series between the source of the power switch and the power supply ground, and obtaining the sampling signal by detecting the voltage across the sampling resistor.

[0029] Preferably, the DC-DC converter is a boost converter.

[0030] This invention also discloses a frequency locking control method for a DC-DC converter, comprising the following steps:

[0031] S1: Voltage error detection and amplification; detects the output voltage of the DC-DC converter and obtains the output voltage feedback signal through voltage division; compares and amplifies the output voltage feedback signal with a reference voltage signal to generate an error amplification signal;

[0032] S2: Inductor current sampling; detects the inductor current flowing through the power switch and converts it into a current sampling signal through the sampling circuit;

[0033] S3: On-time control; In each switching cycle, the current sampling signal is compared with the error amplification signal; When the current sampling signal reaches the error amplification signal, an on-end signal is generated to control the power switch to turn off, thereby determining and ending the on-time of that cycle;

[0034] S4: Acquisition of actual switching frequency; Acquire the drive signal of the power switch transistor, and determine the actual switching frequency of the DC-DC converter based on the edge or period of the drive signal.

[0035] S5: Frequency error detection; provides an external reference clock signal with the target locking frequency; compares the actual switching frequency with the target locking frequency to obtain frequency error information;

[0036] S6: Generation of turn-off time reference signal; The frequency error information is converted into an analog voltage error signal, and the voltage error signal is integrated to generate a turn-off time reference signal; wherein, the level of the turn-off time reference signal is related to the frequency error and is used to indicate the required turn-off time length.

[0037] S7: Turn-off time ramp signal generation; During the power switch turn-off period, a turn-off time ramp signal that rises linearly from an initial level is generated; During the power switch turn-on period, the turn-off time ramp signal is reset to the initial level;

[0038] S8: Turn-off time control; During the turn-off phase of each switching cycle, the turn-off time ramp signal is compared with the turn-off time reference signal; When the turn-off time ramp signal reaches the turn-off time reference signal, a turn-off end signal is generated, and the power switch is controlled to turn on, thereby determining and ending the turn-off time of the cycle.

[0039] S9: Drive signal generation; Based on the turn-on end signal and turn-off end signal, generate and output the drive signal of the power switch to control its alternating turn-on and turn-off;

[0040] S10: Frequency locking closed-loop adjustment; by repeatedly executing steps S4 to S9, the frequency error between the actual switching frequency and the target locking frequency is fed back to the turn-off time control loop via the turn-off time reference signal; the turn-off time of each cycle is adjusted through closed-loop negative feedback so that the actual switching frequency dynamically converges and locks to the target locking frequency.

[0041] This invention provides a DC-DC converter with a frequency-locked control loop and its control method, which has the following advantages:

[0042] (1) High-precision active locking of the switching frequency is achieved. By introducing an independent frequency feedback loop, the switching frequency is locked with high precision to a stable external reference clock frequency. This makes the spectral energy of the switching noise highly concentrated at a fixed narrowband frequency and its harmonics, realizing a fundamental transformation from "broadband noise" to "narrowband noise". This greatly simplifies the design of system-level EMI filters and significantly reduces the filter size, cost and design difficulty.

[0043] (2) It eliminates the need for direct detection of the input voltage, greatly improving system safety and application flexibility. By using frequency feedback instead of voltage feedforward, the frequency-locked loop only needs to obtain the switch drive signal (reflecting the actual frequency) and the external low-frequency reference clock, completely eliminating the need to sample the input voltage from the chip pins. This avoids the risks to electrical isolation, chip stress, and functional safety caused by the introduction of high voltage.

[0044] (3) It retains the fast dynamic response capability of the peak current control mode, realizing the superposition of performance. The inner loop adopts the peak current control mode, which can make rapid adjustments cycle by cycle when the load or input changes suddenly, and the dynamic response speed is no different from that of traditional excellent frequency converters. The bandwidth of the outer loop is designed to be much lower than that of the inner loop, so it has almost no impact during the dynamic process.

[0045] (4) Ensures ultra-high precision, high stability, and strong robustness of the frequency locking loop. The frequency locking function is implemented using a fully analog circuit. The gain and time constant of the switched capacitor integrator are determined by the capacitance ratio, achieving near-perfect matching accuracy and temperature stability in integrated circuit technology; the ramp generator uses constant current charging, resulting in excellent linearity. Therefore, the accuracy, temperature drift, and long-term stability of the frequency locking loop mainly depend on the easily controllable capacitance ratio and reference current, without relying on absolute device parameters, thus maintaining excellent locking performance over a wide temperature range and throughout its entire lifespan.

[0046] (5) Enhanced predictability and reliability of system operation. Since the switching frequency is precisely locked to a known and stable value, its spectral behavior is completely predictable. This avoids the risk of accidentally falling into the operating frequency band or resonant point of other sensitive circuits in the system due to random frequency drift, thereby effectively eliminating potential electromagnetic interference problems. Attached Figure Description

[0047] To more clearly illustrate the technical solutions in this invention or the prior art, the accompanying drawings used in the description of this invention or the prior art will be briefly introduced below.

[0048] Figure 1 This is a system architecture diagram of a certain TPS61087 series chip in the existing technology;

[0049] Figure 2 This is a simplified diagram of the system structure of the present invention;

[0050] Figure 3 This is a structural diagram of the shutdown time control module in this invention;

[0051] Figure 4 This is a structural diagram of the first or second frequency discriminator in this invention;

[0052] Figure 5 This is a structural diagram of the ramp signal generator in this invention;

[0053] Figure 6 This is a structural diagram of the switched capacitor integrator in this invention;

[0054] Figure 7 This is a flowchart of the overall system control logic for the frequency locking control method of the present invention. Detailed Implementation

[0055] To make the objectives, technical solutions, and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings.

[0056] Example 1, as Figure 2-6As shown in the figure, an embodiment of the present invention provides a DC-DC converter with a frequency-locked control loop. The converter can be a boost, buck, or buck-boost topology. This embodiment will be described in detail using the widely used boost converter as an example.

[0057] This DC-DC converter consists of two main parts: a main power circuit and a control chip. The main power circuit includes: an input capacitor C. IN The components include an inductor L, a power switch M0 (typically an N-channel MOSFET), a freewheeling diode D (or a synchronous rectifier), and an output capacitor C. OUT The source of the power switch M0 is connected to ground (GND) through a sampling resistor Rsense. The inductor L is connected to the input voltage V. IN The anode of the freewheeling diode D is connected to the drain of the power switch M0, and the cathode of the freewheeling diode D is connected to the output voltage V. OUT The control chip integrates an error amplifier (EA), a pulse width modulation (PWM) module, a turn-off time control module (Toff_ctrl), and a power transistor driver module (Driver).

[0058] In this circuit, the non-inverting input of the error amplifier EA (serving as the first input) receives the voltage from the output voltage V. OUT The voltage feedback signal V obtained by voltage division through resistors RFB1 and RFB2 FB The inverting input of the error amplifier EA (as the second input) receives a high-precision, low-temperature-drift bandgap reference voltage signal V. REF The error amplifier EA responds to the voltage feedback signal V. FB With reference voltage signal V REF The error between them is amplified, and the output error amplification signal V is generated. COMP .

[0059] The first input terminal of the pulse width modulation (PWM) module (e.g., the non-inverting input of a comparator) is connected to the output terminal of the error amplifier EA to receive the error amplification signal V. COMP The second input of the pulse width modulation (PWM) module (e.g., the inverting input of the comparator) receives a sampling signal Vsense characterizing the inductor current, which is the voltage across the sampling resistor Rsense (Vsense = IL × RSENSE, where IL is the current flowing through the power switch M0 and the inductor L). The third and fourth inputs of the PWM module receive the turn-off time reference signal Toff_ref and the turn-off time ramp signal Toff_ramp from the turn-off time control module, respectively.

[0060] The first input of the turn-off time control module Toff_ctrl is connected to the output feedback node of the power transistor driver module Driver, and receives the final power transistor drive signal V. DRV The second input of the shutdown time control module Toff_ctrl receives a high-stability reference clock signal CLK_ref provided by an external crystal oscillator or clock generator. The first output of the shutdown time control module Toff_ctrl outputs the shutdown time reference signal Toff_ref to the third input of the pulse width modulation module PWM, and its second output outputs the shutdown time ramp signal Toff_ramp to the fourth input of the pulse width modulation module PWM.

[0061] The input of the power transistor driver module (Driver) is connected to the output of the pulse width modulation (PWM) module, receiving a logic combination consisting of a first control signal (turn-on end signal) and a second control signal (turn-off end signal) generated by the PWM module. The Driver module performs level shifting and current amplification on this combination signal to generate a gate drive signal V with sufficient driving capability. DRV It directly controls the on and off states of the power switch M0.

[0062] Working principle:

[0063] The converter in this embodiment achieves voltage regulation and frequency locking through three cooperating loops: a voltage loop, a current loop, and a frequency loop.

[0064] The voltage loop and current loop work together to determine the conduction time (Ton): the core of the voltage loop is the error amplifier EA. Its output error amplification signal V... COMP It is a DC level that directly sets the system's allowed peak inductor current threshold. When the load increases, causing the output voltage V... OUT When it drops slightly, the voltage feedback signal V FB The error amplification signal V output by the error amplifier EA is reduced. COMP An increase means that a higher peak inductor current is allowed, thus delivering more energy to the output in each cycle, increasing the output voltage V. OUT Recovery.

[0065] The current loop is a fast, cycle-by-cycle control loop. At the start of each switching cycle (i.e., after the power switch M0 turns on), the inductor current IL rises linearly, and the sampling signal Vsense generated by the sampling resistor Rsense also rises accordingly. The first comparator inside the pulse width modulation (PWM) module (corresponding to the received Vsense)... COMP (and the input of Vsense) continuously compare the sampled signal Vsense with the error amplification signal V COMP When Vsense rises to equal VCOMP When the voltage level is reached, the output of the first comparator flips, generating a high-level pulse as the first control signal (i.e., the Ton_end signal). This signal is sent to the logic control unit, indicating that the conduction phase of the current cycle should end. Subsequently, the logic control unit instructs the power transistor driver module to apply the drive signal V. DRV Pulling the signal low turns off the power switch M0. Therefore, the on-time Ton is from the current sampling signal Vsense to the error amplification signal V. COMP The timing is dynamically determined, enabling peak current control and ensuring the system's fast transient response.

[0066] The frequency loop independently determines the off-time (Toff) to achieve frequency locking:

[0067] The goal of the frequency loop is to adjust the off time Toff so that the switching period Tsw (Tsw=Ton+Toff) is fixed, that is, the switching frequency Fsw is locked to the frequency Fref of the high-stability reference clock signal CLK_ref.

[0068] The shutdown time control module Toff_ctrl is key to achieving this goal. It performs the following functions:

[0069] (1) Frequency detection and error voltage generation: The turn-off time control module Toff_ctrl contains a frequency detection circuit, which continuously monitors the drive signal V. DRV The actual switching frequency Fsw_act is calculated and compared with the reference frequency Fref. A preferred implementation uses two identical frequency-to-voltage converters (FVCs) to convert V... DRV And CLK_ref is converted into a DC voltage V proportional to its frequency. DE and V RE Frequency error information is inherent in the voltage difference ΔV = V. DE -V RE middle.

[0070] (2) Error Integration and Reference Generation: The voltage difference ΔV is fed into an integrator (e.g., a capacitor driven by a transconductance amplifier, or a switched capacitor integrator 203). The integrator performs continuous-time or discrete-time integration on ΔV. If the actual frequency Fsw_act is too high (V DE <V RE If Fsw_act is low (V), the integrator output voltage increases; if Fsw_act is low (V), the integrator output voltage increases. DE >V RE If the integrator output voltage decreases, the output voltage of the integrator will drop. The output voltage of the integrator is the off-time reference signal Toff_ref. It is a slowly varying DC or low-frequency signal whose high or low level encodes the direction and magnitude of the off-time adjustment required to correct the frequency error.

[0071] (3) Ramp signal generation: Simultaneously, a ramp signal generator 204 drives the signal V. DRV It operates to trigger the signal. Whenever the drive signal V... DRV When the voltage level is low (power switch M0 is off), the ramp signal generator 204 starts, generating a voltage ramp that rises linearly from zero, i.e., the turn-off time ramp signal Toff_ramp. When the drive signal V... DRV When the signal goes high (power switch M0 is turned on), the turn-off time ramp signal Toff_ramp is quickly reset to zero. Therefore, the turn-off time ramp signal Toff_ramp is generated fresh in each turn-off period, and its slope is fixed.

[0072] The closed-loop adjustment and locking process for the shutdown time is as follows:

[0073] The turn-off time reference signal Toff_ref and the turn-off time ramp signal Toff_ramp are fed to the second comparator inside the pulse width modulation module (PWM) (corresponding to the input terminal that receives these two signals). During the turn-off period of the power switch M0, the turn-off time ramp signal Toff_ramp rises linearly. The second comparator continuously compares the turn-off time ramp signal Toff_ramp with the turn-off time reference signal Toff_ref.

[0074] When the voltage value of Toff_ramp rises to equal the Toff_ref level, the output of the second comparator flips, generating a high-level pulse as the second control signal (i.e., the Toff_end signal). This signal is sent to the logic control unit, indicating that the turn-off phase of the current cycle should end. Subsequently, the logic control unit instructs the power transistor driver module to apply the drive signal V... DRV Pull it up to restart the power switch M0, and a new switching cycle begins.

[0075] If due to input voltage V IN Disturbances such as increased load or lighter load cause the actual switching frequency Fsw_act to rise, then the V output of the frequency detection circuit will... DEAs the voltage drops, ΔV becomes negative, and the off-time reference signal Toff_ref output by the integrator rises accordingly. In the next off-time period, the off-time ramp signal Toff_ramp takes longer to rise to this higher Toff_ref threshold, thus the off-time Toff is automatically extended. Since the on-time Ton is mainly determined by the current loop based on load conditions and its variation is relatively small, the extension of the off-time Toff directly leads to a longer switching period Tsw, causing Fsw_act to fall back towards Fref. Conversely, if Fsw_act decreases, Toff_ref decreases, Toff shortens, and Fsw_act rises. Through this dynamic adjustment, the system ultimately locks the average switching frequency to the frequency of the external reference clock CLK_ref.

[0076] This invention achieves complete off-time adjustment autonomously through a frequency feedback loop. This loop only needs to acquire the power transistor drive signal (reflecting the actual switching frequency) and an external low-frequency reference clock signal. It directly generates the off-time reference through internal frequency discrimination and integration, completely eliminating the need to sample the input voltage from the chip pins. This effectively avoids the chip stress, noise interference, and potential safety isolation challenges that may arise from high-voltage input signals. This makes the invention particularly suitable for applications with stringent requirements for high-voltage safety, functional safety, and electrical isolation, such as automotive electronics and industrial control, thus broadening the chip's application range.

[0077] Furthermore, this invention introduces an independent frequency feedback loop to form a precise frequency phase-locked loop. During steady-state operation, the system can actively and dynamically adjust the turn-off time of each cycle, locking the average switching frequency with high precision to the frequency of an external stable reference clock. This concentrates the spectral energy of the switching noise to a very narrow, known frequency range, achieving a transformation from "broadband noise" to "narrowband noise." Consequently, the design of subsequent EMI filtering stages becomes simpler and more effective; the filter only needs to attenuate this fixed frequency and its finite harmonics, significantly reducing the filter's size, cost, and design complexity.

[0078] By combining the frequency control loop with a traditional voltage-current dual-loop peak current control architecture, the frequency loop adjusts much slower than the current loop during dynamic processes such as system startup, load transients, or sudden input voltage changes. In these situations, system behavior is entirely dominated by the fast peak current control loop. Its operating mode is identical to that of a traditional frequency converter. By rapidly adjusting the inductor peak current (i.e., the on-time Ton) cycle by cycle, it can provide a millisecond- or even microsecond-level rapid response to system disturbances, ensuring minimal overshoot / undershoot and fast recovery of the output voltage. Furthermore, because the switching frequency is locked to a known, stable value, the system no longer experiences unexpected frequency drift that could cause it to fall into the operating frequency band or resonant point of other sensitive circuits (such as RF receivers, sensors, and audio systems). This significantly improves the predictability and reliability of the entire electronic system.

[0079] Example 2, as a further preferred embodiment of Example 1, the off-time control module Toff_ctrl includes: a first frequency discriminator 201, a second frequency discriminator 202, a switched capacitor integrator 203, and a ramp signal generator 204;

[0080] The input terminal of the first frequency discriminator 201 is connected to the drive signal V of the power switch M0. DRV Feedback node. The high and low levels of this drive signal directly reflect the switching state of the power switch transistor, and its frequency is the actual switching frequency (F_act) of the DC-DC converter. The core function of the first frequency discriminator 201 is to perform frequency-to-voltage (FV) conversion. By inputting a periodic square wave signal (V... DRV This is converted into a proportional DC voltage signal (first voltage signal V). DE Internally, a constant current source is typically used to periodically charge and discharge the capacitor, and the average voltage is extracted through a low-pass filter. This average voltage value has a linear or monotonic relationship with the frequency of the input signal.

[0081] The input of the second frequency discriminator 202 receives an external reference clock signal (CLK_ref). This signal provides a highly stable and accurate target locking frequency (F_ref). The second frequency discriminator 202 converts F_ref into a second DC voltage signal (the second voltage signal V) with the exact same circuit structure and conversion ratio as the first frequency discriminator 201. RE ).

[0082] The two differential input terminals of the switched capacitor integrator 203 receive the first voltage signal V from the first frequency discriminator 201 and the second frequency discriminator 202, respectively. DE Second voltage signal V RE To obtain the first voltage signal V DE Second voltage signal V REThe difference calculated: ΔV = V DE -V RE This difference ΔV directly quantifies the error between the actual switching frequency and the target locking frequency. If F_act > F_ref, then V DE >V RE ΔV is positive; otherwise it is negative.

[0083] Afterwards, the switched capacitor integrator 203 performs continuous-time integration on the error voltage ΔV. The purpose of the integration operation is: (1) to accumulate historical errors: even if the instantaneous error at a certain moment is very small, the small deviations over a long period of time will be accumulated to ensure the final locking accuracy. (2) to provide loop stability: the integral element belongs to integral regulation in the control system, which helps to eliminate steady-state errors and enable the system to eventually track the reference frequency without error. The output voltage of the switched capacitor integrator 203 is the off-time reference signal Toff_ref. Therefore, the off-time reference signal Toff_ref is a slowly changing DC signal, and its voltage level carries the off-time adjustment information required to correct the accumulated frequency error (for example, an increase in Toff_ref means that the off-time needs to be extended to reduce the frequency).

[0084] The ramp signal generator 204 is synchronized with the switching action of the power switching transistor MO. When the drive signal V... DRV When the voltage is low (power switch MO is off), the ramp signal generator 204 starts, and the internal constant current source charges a capacitor, generating a ramp voltage (Toff_ramp) that rises linearly from zero. The slope of this ramp is fixed.

[0085] In the pulse width modulation (PWM) module, the off-time reference signal Toff_ref serves as the comparison threshold, and the off-time ramp signal Toff_ramp serves as the comparison object. During the off-time phase of each switching cycle, Toff_ramp rises linearly. When Toff_ramp rises to equal Toff_ref, the comparator within the PWM module flips, generating a turn-off end signal, thereby terminating the current off-time phase and initiating a new cycle. Therefore, the length of the off-time (Toff) is determined by the time it takes for Toff_ramp to rise from 0 to the Toff_ref level. The higher the Toff_ref voltage, the longer the required rise time, and the longer the Toff; conversely, the lower the Toff voltage, the longer the required rise time, and the longer the Toff.

[0086] This embodiment constructs a complete analog frequency-locking loop. The "frequency error detection and integration" path, composed of a frequency discriminator and a switched-capacitor integrator 203, has a very low bandwidth, primarily responding to slow frequency changes and DC deviations, focusing on providing extremely high steady-state frequency accuracy. The "off-time execution" path, composed of a ramp generator and a comparator, is a fast, cycle-by-cycle control path. Furthermore, the peak current loop, which determines the on-time (Ton), is completely independent and high-speed. This effectively decouples the system's fast dynamic response (handled by the current loop) from its high-precision frequency locking (handled by the frequency loop). During dynamic processes such as load changes, the frequency loop has almost no impact; in steady state, the frequency loop operates precisely, firmly locking the switching frequency. Therefore, it effectively solves the technical challenge of the contradiction between dynamic performance and frequency stability in traditional solutions. Compared to all-digital solutions requiring high-speed ADCs, digital filters, and processors, this solution requires no programming, eliminates quantization noise and switching noise interference from digital clocks, consumes less power, and is less sensitive to power supply noise.

[0087] By setting up two identical frequency discriminators, the actual switching frequency signal (drive signal) and the target frequency signal (reference clock) are processed separately. Due to the high degree of consistency in circuit structure, device parameters, and operating environment, the conversion gain, temperature drift, and process deviation of the two channels can achieve excellent matching. Therefore, the difference (ΔV) between the first and second voltage signals output by the two discriminators can reflect the true error between the actual frequency and the target frequency with extremely pure and accurate values, providing a high-quality input signal for subsequent precise error correction and fundamentally ensuring the accuracy and stability of the final frequency-locked loop.

[0088] A switched-capacitor integrator 203 is employed as the core for frequency error processing. Switched-capacitor technology utilizes the transfer and redistribution of capacitor charge to achieve analog computation, with its integration time constant determined by the capacitance ratio and clock frequency. Therefore, this switched-capacitor integrator 203 can perform highly linear integration of the error voltage difference output by the frequency discriminator with extremely low drift. This effectively avoids the temperature drift and nonlinearity problems caused by resistors in conventional active RC integrators, thus ensuring the long-term accuracy and stability of the converter's locked frequency over a wide temperature range and its entire lifespan.

[0089] The operation of the ramp signal generator 204 is directly controlled by the power transistor drive signal. When the drive signal indicates off, it immediately begins generating a linear ramp; when the drive signal indicates on, it immediately resets. This hard synchronization mechanism ensures that the start and end points of the generated off-time ramp signal are strictly aligned with the off phase of each switching cycle. This allows the frequency loop's regulation to be applied accurately and without delay to each switching cycle. This design avoids the phase error or regulation lag that may be introduced by using asynchronous timers, improving the response speed and transient regulation accuracy of the frequency locking loop.

[0090] In Example 3, as a further preferred embodiment of Example 1, the first frequency discriminator 201 and the second frequency discriminator 202 have the same structure; both the first frequency discriminator 201 and the second frequency discriminator 202 include: a frequency division unit, a frequency to voltage conversion unit, and a filtering unit;

[0091] The frequency divider unit includes a D flip-flop. The clock input of the D flip-flop receives the input clock signal, and the D input is shorted to its own inverted output QN, forming a classic T' flip-flop. The non-inverting output Q of the D flip-flop outputs the frequency divider control signal; the rising edge of each input clock signal triggers the D flip-flop to toggle its state once. Therefore, the square wave signal frequency at the output Q is exactly half the input clock frequency, and the duty cycle is always 50%. This reduces the switching frequency or reference clock frequency, which could be as high as hundreds of kHz or even MHz, to a more manageable intermediate frequency. This not only reduces the switching speed requirements of the subsequent analog switches (MOS3, MOS4), reduces switching losses and charge injection effects, but also generates a control signal with a strictly 50% duty cycle.

[0092] The frequency-to-voltage conversion unit includes a first capacitor CA, a constant current source IBIAS1, a third switch MOS3, a fourth switch MOS4, and a second capacitor CS. The first terminal of the constant current source IBIAS1 is connected to the power supply, and the second terminal is connected to the first node N1. The first capacitor CA is connected between the first node N1 and ground. The source of the third switch MOS3 is connected to the first node N1, the drain is connected to the second node N2, and the gate receives the frequency division control signal. The second capacitor CS is connected between the second node N2 and ground. The fourth switch MOS4 is connected in parallel across the second capacitor CS. The gate of the fourth switch MOS4 receives the frequency division control signal, and the conduction state of the fourth switch MOS4 is opposite to that of the third switch MOS3.

[0093] Therefore, during the charging phase (when the output Q is high): the third switch MOS3 is turned on, and the fourth switch MOS4 is turned off. A constant bias current IBIAS1 flows into the circuit node. Since the third switch MOS3 is turned on, this current is divided into two paths: one part (I... CAThe first capacitor CA is charged until its voltage V is applied. N1 Slowly rising; another part (I CS The second capacitor CS is charged. CS stores energy during this stage. During the discharge / holding stage (when the output Q is low): the third switch MOS3 is turned off, and the fourth switch MOS4 is turned on. The current path of the constant bias current IBIAS1 is cut off by MOS3. At the same time, the conduction of MOS4 short-circuits the two ends of capacitor CS, causing the charge stored in the previous stage to be quickly discharged, and the voltage returns to zero. As for capacitor CA, due to the effect of the op-amp virtual ground or other high-impedance nodes (although the op-amp is not explicitly shown in the figure, such circuits usually rely on the op-amp virtual ground to maintain the potential of the other end of CA, which is existing technology), it has no fast discharge path, so it will basically maintain the voltage it reached at the end of the charging stage.

[0094] Within each complete input clock cycle (corresponding to one high level and one low level of the divided square wave), CA is charged by the constant bias current IBIAS1 only during the half-cycle of the high level of the square wave. Therefore, the average voltage increment (ΔV) on CA within one cycle is... CA The voltage V at node N1 is directly proportional to the charging time, while the charging time (high-level width) is inversely proportional to the frequency of the input signal (F_in). Therefore, the average voltage V at node N1 is... N1_avg =Q / CA =(IBIAS1×0.5) / (CA×F_in). V N1_avg It is inversely proportional to the input frequency F_in. With proper design of subsequent processing, it can be easily converted to a direct proportional relationship or this inverse proportionality characteristic can be directly utilized.

[0095] The filtering unit typically consists of one or more RC low-pass filters. Its input is connected to the first node N1, used to perform low-pass filtering on the pulsating voltage signal at the first node N1, and outputs a first voltage signal V. DE Or the second voltage signal V RE The purpose is to completely filter out the high-frequency noise generated by the switching charging and discharging, and obtain an extremely smooth DC voltage signal V. DE or V RE Furthermore, by setting its bandwidth to be much lower than the switching frequency but higher than the expected adjustment bandwidth of the frequency loop, it is possible to ensure that unnecessary noise is suppressed while effectively transmitting frequency control information.

[0096] This embodiment uses a constant current source IBIAS1 to charge capacitor CA, ensuring a linear increase in charging voltage. A square wave with a strict 50% duty cycle generated by a D flip-flop is used as the control signal, precisely defining the charging time as half a cycle within each input cycle. This eliminates conversion errors caused by duty cycle jitter or asymmetry, accurately mapping frequency information to charging time. By completely discharging and resetting CS during the low-level phase of each cycle using the fourth switch MOS4, each charging cycle starts from a defined initial state (zero charge), avoiding charge accumulation errors and guaranteeing the consistency and long-term accuracy of the conversion cycle.

[0097] Example 4, as a further preferred embodiment of Example 1, the ramp signal generator 204 includes: a second capacitor Cr, a charging constant current source IBIAS2, a fifth switch MOS5, and a sixth switch MOS6;

[0098] The first terminal of the charging constant current source IBIAS2 is connected to the power supply, and the second terminal is connected to the source of the fifth switching transistor MOS5; the drain of the fifth switching transistor MOS5 is connected to the third node N3, and the gate receives the drive signal V from the power switching transistor. DRV The inverted signal; the second capacitor Cr is connected between the third node N3 and ground; the sixth switch MOS6 is connected in parallel across the two ends of the second capacitor Cr, and the gate of the sixth switch MOS6 receives the drive signal V from the power switch. DRV The third node N3 outputs the turn-off time ramp signal Toff_ramp.

[0099] When the drive signal V DRV When the voltage level is low, it indicates that the power switch MOSFET is in the off state. At this time, the gate of the fifth switch MOSFET 5 receives V. DRV The inverted signal (i.e., high level) causes the fifth switch MOS5 to conduct; simultaneously, the gate of the sixth switch MOS6 directly receives V. DRV (Low level), therefore the sixth switch MOS6 is turned off. At this time, the conducting MOS5 connects the charging constant current source IBIAS2 to the upper plate of the second capacitor Cr (the third node N3). The charging constant current source IBIAS2 begins to charge the second capacitor Cr. Driven by the constant current IBIAS2, the voltage across the second capacitor Cr, i.e., the voltage of node N3 to ground, will rise linearly at a constant rate. The voltage at the third node N3 is the output turn-off time ramp signal Toff_ramp. Throughout the turn-off phase, the turn-off time ramp signal Toff_ramp increases strictly linearly from approximately zero potential (assuming the previous cycle has been fully discharged). And its slope K... slope =IBIAS2 / Cr is precisely set by the constant current source current and the capacitance value.

[0100] When the power transistor drive signal V DRV When the voltage jumps to a high level, it indicates the start of a new switching cycle, and the power switch MOSFET enters the on state, ending the off-time. At this time, the gate of the fifth switch MOSFET 5 becomes low (inverted signal), thus turning off MOSFET 5 and cutting off the charging path of the constant current source IBIAS2; simultaneously, the gate of the sixth switch MOSFET 6 becomes high, thus turning on MOSFET 6. The turned-on MOSFET 6 directly short-circuits the two ends of the second capacitor Cr, forming a low-resistance discharge loop. The charge stored in the second capacitor Cr is quickly discharged to ground through MOSFET 6. In a very short time (determined by the on-resistance of MOSFET 6 and the capacitance of Cr, much shorter than the switching cycle), the voltage Toff_ramp across the second capacitor Cr is pulled back to near zero potential (ground level), preparing for linear charging in the next off-time cycle. The off-time ramp signal Toff_ramp remains at this low level throughout the on-phase.

[0101] The entire operating cycle of the ramp signal generator 204 is entirely dependent on the state of the power switch (i.e., V). DRV Driven by a signal, each switching cycle repeats the process of "linear charging to generate a ramp during the off-time and rapid discharging to reset during the on-time." Therefore, the off-time ramp signal Toff_ramp is a periodic sawtooth wave signal with the same start and end time and period as the Toff phase. This achieves precise clock-level synchronization with the main power switch operation. This effectively avoids phase deviations, accumulated errors, or start-up delays that may occur when using independent oscillators or delay lines, ensuring that each off-time measurement starts from absolute zero. This allows the frequency loop's adjustment to be applied instantly and without deviation in each switching cycle, greatly improving the dynamic accuracy and response speed of the frequency locking loop.

[0102] By directly short-circuiting and discharging the second capacitor Cr through the sixth switch MOS6, the turn-off time ramp signal Toff_ramp can be reset to ground potential in a very short time. This effectively ensures that at the beginning of each turn-off cycle, the turn-off time ramp signal Toff_ramp rises from a defined and consistent initial voltage (zero volts). In integrated circuits, the charging constant current source IBIAS2 can be generated by a bandgap reference circuit, exhibiting extremely low temperature coefficient and power supply voltage dependence. The second capacitor Cr is typically a MOS capacitor or a MIM capacitor, whose capacitance value is very stable. Therefore, the ramp slope K... slope It is a highly stable constant that does not change significantly with temperature, input voltage or process angle, thus providing a stable time reference for the entire frequency locking loop and ensuring the long-term stability of the frequency locking point.

[0103] Example 5, as a further preferred embodiment of Example 1, the switched capacitor integrator 203 includes: an integrating operational amplifier, an integrating capacitor Ci, a sampling capacitor Cq, a first switching transistor MOS1, a second switching transistor MOS2, a first voltage buffer, and a second voltage buffer;

[0104] The input terminal of the first voltage buffer receives the first voltage signal V. DE The output of the first voltage buffer is connected to the source of the first switching transistor MOS1; the input of the second voltage buffer receives the second voltage signal V. RE The output of the second voltage buffer is connected to the lower plate of the sampling capacitor Cq and the non-inverting input of the integrating operational amplifier; the inverting input of the integrating operational amplifier is connected to the source of the second switching transistor MOS2 and the first terminal of the integrating capacitor Ci; the output of the integrating operational amplifier outputs the turn-off time reference signal Toff_ref and is connected to the second terminal of the integrating capacitor Ci; the upper plate of the sampling capacitor Cq is connected to the drain of the first switching transistor MOS1 and the drain of the second switching transistor MOS2; the gates of the first switching transistor MOS1 and the second switching transistor MOS2 receive a set of first clock signals Φ1 and second clock signals Φ2 that are out of phase and do not overlap.

[0105] During the sampling phase (when the first clock signal Φ1 is valid and the second clock signal Φ2 is invalid), the first switch MOS1 is turned on and the second switch MOS2 is turned off. At this time, the voltage V from the first frequency discriminator 201 is... DE After being driven by the first voltage buffer, the voltage V is applied to the upper plate of the sampling capacitor Cq. The voltage V from the second frequency discriminator 202... RE After being driven by the second voltage buffer, the voltage is applied to the lower plate of the sampling capacitor Cq and the non-inverting input of the integrating operational amplifier. Since the second switch MOS2 is turned off, the integrator feedback loop is open at this moment, and the voltage across the integrating capacitor Ci (i.e., Toff_ref) remains unchanged from the value at the end of the previous stage. The sampling capacitor Cq is charged to V... DE With V RE The instantaneous voltage difference between them, i.e., V Cq =V DE -V RE This stage accurately samples and maintains the voltage difference between the two input signals at the current moment.

[0106] During the integration / charge transfer phase (when the second clock signal Φ2 is active and the first clock signal Φ1 is inactive), the first switch MOS1 is turned off and the second switch MOS2 is turned on. At this time, because the first switch MOS1 is turned off, the input signal V is... DEThe upper plate of sampling capacitor Cq is isolated from the upper plate of Cq. Meanwhile, the second switch MOS2 is turned on, connecting the upper plate of sampling capacitor Cq to the inverting input (virtual ground) of the integrating operational amplifier. At this time, the lower plate of sampling capacitor Cq remains connected to the non-inverting input of the operational amplifier, with a potential of V. RE Due to the "virtual short" characteristic of the operational amplifier, the potential at its inverting input is forced to be equal to the potential V at its non-inverting input. RE Therefore, at the instant of switching from the first clock signal Φ1 to the second clock signal Φ2, the potential of the upper plate of the sampling capacitor Cq changes from V... DE Forced to be pulled to V RE According to the law of conservation of charge, the charge ΔQ corresponding to the change in potential of the upper plate of the sampling capacitor Cq is = Cq × (V RE -V DE The charge ΔQ cannot remain on the sampling capacitor Cq and must flow into or out of the node connected to it. Since the inverting input is a high-impedance virtual point, almost all of this charge ΔQ is transferred to the integrating capacitor Ci.

[0107] If V DE >V RE If the actual frequency is too low, then ΔQ is negative (the sampling capacitor Cq stores more charge in stage Φ1 than is needed in stage Φ2), meaning that a net charge is drawn from the integrating capacitor Ci, causing the voltage across Ci to drop. According to the op-amp characteristics, the output voltage Toff_ref therefore increases.

[0108] If V DE <V RE (i.e., the actual frequency is too high), then ΔQ is positive, which means that a net charge is injected into the integrating capacitor Ci, the voltage across the integrating capacitor Ci rises, and the output voltage Toff_ref decreases as a result.

[0109] The charge transfer amount ΔQ is related to the input voltage difference (V). DE -V RE The charge is proportional to the input differential voltage. Within each clock cycle T_clk, the transferred charge is accumulated on the integrating capacitor Ci, thereby changing Toff_ref. This achieves discrete-time integration of the input differential voltage.

[0110] The two stages described above are performed at high speed and alternately, driven by non-overlapping clocks Φ1 and Φ2. The clock frequencies (i.e., switching frequencies) of Φ1 and Φ2 are typically much higher than the bandwidth of the frequency-locked loop. Thus, the switched-capacitor integrator 203 corrects the input frequency error signal (V... DE -V RE The process involves near-continuous integration, resulting in a smooth rise or fall in the output Toff_ref, whose voltage value accurately reflects the accumulated frequency error.

[0111] Throughout the process, the core gain (Cq / Ci) and equivalent time constant of the switched-capacitor integrator 203 are determined solely by the ratio of the two capacitors. In integrated circuit manufacturing, by employing precision layout design techniques such as common centroid and interdigitated capacitors, the ratio of the two capacitors can achieve a matching accuracy of up to 0.1% or even higher, and is almost unaffected by absolute process deviations. This makes the transfer function of the switched-capacitor integrator 203 extremely accurate and predictable, fundamentally guaranteeing the high precision and repeatability of the Toff_ref signal generation. This ensures that the locking point of the frequency-locked loop hardly drifts with environmental changes. Furthermore, the circuit uses a fully differential input method; V DE and V RE These are connected to the two ends of the sampling capacitor Cq and processed as a differential signal. During the charge transfer phase, due to the "virtual short" effect of the op-amp, the potential of the lower plate of Cq is replicated to the upper plate. Any voltage simultaneously present at V... DE and V RE Common-mode noise or disturbances (such as power supply ripple and substrate noise) are largely canceled out during differential subtraction. This provides a "quiet" environment for error signal extraction by the differential structure of the switched-capacitor integrator 203, greatly improving the anti-interference and robustness of the frequency-locked loop.

[0112] Example 6, as a further preferred embodiment of Example 1, obtains the sampling signal characterizing the inductor current by connecting a sampling resistor in series between the source of the power switch and the power supply ground. The sampling signal is obtained by detecting the voltage across the sampling resistor. According to Ohm's law, the current flowing through the sampling resistor Rsense (i.e., the power switch current, which is equal to the inductor current IL during the conduction phase) is strictly proportional to the voltage drop Vsense across it. This linear relationship does not depend on the nonlinear characteristics of any device, ensuring that the current detection itself does not introduce nonlinear distortion. The sampling resistor Rsense can be a high-precision, low-temperature-drift metal thin-film resistor or a laser-trimmed integrated diffused resistor. Its resistance value can be precisely controlled and calibrated during manufacturing. Therefore, the gain of the current-to-voltage conversion (i.e., the resistance value Rsense) is highly accurate and stable, ensuring the absolute accuracy and repeatability of the current sampling signal. By using an independent sampling resistor Rsense, its temperature coefficient can be made very small (even negative temperature coefficient for compensation), and its linearity is independent of operating conditions. This completely decouples the current sensing function from the nonlinearity and temperature drift characteristics of the power switch. Regardless of changes in chip temperature or fluctuations in power switch performance, the current sampling gain remains stable, thereby greatly enhancing the system's robustness, reliability, and performance consistency across the entire temperature range and lifespan.

[0113] Example 7, as a further preferred embodiment of Example 1, uses a boost converter as the DC-DC converter. The power switch of the boost converter is located on the low side (grounded), and its drain is connected to the switching node (SW). When the switch is turned off, the voltage at the SW node rises above the input voltage (V) due to the inductor freewheeling current. IN The level (V) SW ≈V OUT The voltage at this high-voltage node experiences a dramatic voltage jump (from 0 to V) during the switching instant. OUT With its extremely high dv / dt, the high-voltage switching frequency (F_sw) is a major source of common-mode EMI noise. If the switching frequency itself is unstable or fluctuates, the noise energy generated by this high-voltage switching will be spread across a wider frequency band, making filtering extremely difficult. When applied to boost converters, this means that the noise spectrum generated by the high-voltage switching at the SW node is strictly limited to the discrete spectrum of the reference frequency F_ref and its harmonics. This greatly simplifies the EMI filtering design required at the output and SW node (e.g., using simple LC filters or ferrite beads) and significantly reduces the levels of conducted and radiated noise, making it easier to meet automotive electronics EMC standards such as CISPR 25.

[0114] Example 8, as Figure 7 As shown, this embodiment discloses a frequency locking control method for a DC-DC converter. Through software configuration or hardware state machine logic control, the following steps are executed sequentially or in parallel during each switching cycle of the converter to achieve stable regulation of the output voltage and precise locking of the switching frequency:

[0115] S1: Voltage error detection and amplification;

[0116] Detect the output voltage of the DC-DC converter (such as Rfb1 and Rfb2), and sample the output voltage V in real time. OUT This yields a proportionally scaled-down voltage feedback signal V. FB This voltage feedback signal V FB With a high-precision, low-temperature drift bandgap reference voltage signal V REF Simultaneously, the input is passed to an analog error amplifier EA. The output voltage feedback signal V is then processed by the error amplifier EA. FB With reference voltage signal V REF The comparison and amplification process outputs an error amplification signal V. COMP Error amplification signal V COMP The DC level directly reflects V OUT The degree of deviation from the target value sets the threshold for the allowed peak inductor current in the next cycle.

[0117] S2: Inductor current sampling;

[0118] A precision sampling resistor, Rsense, is connected in series between the source of the power switch MO and the power supply ground. When the power switch is turned on, the inductor current IL flowing through its channel also flows through the sampling resistor Rsense. By detecting the voltage Vsense across the sampling resistor Rsense, a current sampling signal that is strictly proportional to the instantaneous value of the inductor current IL is obtained. This signal is sent to the PWM control logic in real time.

[0119] S3: On-time control;

[0120] At the start of each switching cycle (after the power switch is turned on), the hardware comparator continuously compares the current sampling signal Vsense with the error amplification signal V. COMP When the instantaneous value of Vsense rises to equal V... COMP When the voltage level is low, a transition occurs at the comparator output, and this transition edge is identified as a conduction end signal (such as the Ton_end pulse). This signal triggers the control logic, immediately terminating the conduction phase of the current cycle and turning off the power switch. Therefore, the conduction time Ton catches up with Vsense. COMP The timing is dynamically determined, thus achieving peak current control.

[0121] S4: Obtaining the actual switching frequency;

[0122] The drive signal V that ultimately drives the power switch is directly obtained from the output of the power transistor driver module. DRV The high and low levels of this signal directly correspond to the on and off states of the power transistor. A frequency detection module (such as a counter or frequency discriminator) is used to detect V. DRV The signal is processed. The actual switching period Tsw_act can be calculated by measuring the time interval between two consecutive rising (or falling) edges; its reciprocal is the actual switching frequency Fsw_act. Alternatively, V can be processed directly. DRV The edge information is used to generate frequency information related to Fsw_act.

[0123] S5: Frequency error detection;

[0124] A highly stable reference clock signal CLK_ref is introduced from outside the chip, and its frequency Fref is the target frequency to be locked. The Fsw_act obtained in step S4 is compared with Fref. A preferred simulation implementation is to separately convert V... DRV CLK_ref is fed into two identical frequency-to-voltage converters (FVCs). The first FVC outputs a DC voltage V proportional to Fsw_act. Fsw The second FVC outputs a DC voltage V that is proportional to Fref. Fref Frequency error information is inherent in the voltage difference ΔV = V.Fsw -V Fref Among them.

[0125] S6: Generation of turn-off time reference signal;

[0126] The frequency error voltage ΔV obtained in step S5 is input into an integrator (preferably the switched capacitor integrator 203 described in Embodiment 1). The integrator performs continuous-time integration on the error voltage ΔV. If Fsw_act is too high (V... Fsw <V Fref If ΔV is negative, the integrator output voltage rises; if Fsw_act is low (V Fsw >V Fref (ΔV is positive) the integrator output voltage decreases. The slowly changing DC voltage output by the integrator is the off-time reference signal Toff_ref. Its voltage level encodes the amount of off-time adjustment required to correct the accumulated frequency error.

[0127] S7: Turn-off time ramp signal generation;

[0128] This step is strictly synchronized with the state of the power switch. A driven signal V is used. DRV A controlled ramp generator. When V DRV When V is low (power switch off), the ramp generator is enabled, and its internal constant current source charges a capacitor, generating a voltage ramp that rises linearly from zero (or some initial level), i.e., the turn-off time ramp signal Toff_ramp. When V DRV When the voltage goes high (power transistor is on), the ramp generator is immediately disabled, its capacitor is rapidly discharged, and Toff_ramp is reset to its initial level. Therefore, Toff_ramp is regenerated during each turn-off period.

[0129] S8: Shutdown time control;

[0130] During the turn-off phase of each switching cycle, another hardware comparator continuously compares the turn-off time ramp signal Toff_ramp with the turn-off time reference signal Toff_ref. When the linearly rising turn-off time ramp signal Toff_ramp reaches the Toff_ref level, the comparator outputs a transition edge, which is identified as a turn-off end signal (such as a Toff_end pulse). This signal triggers the control logic, immediately terminating the turn-off phase of the current cycle and turning on the power transistor. Therefore, the turn-off time Toff is determined by the moment when Toff_ramp catches up with Toff_ref.

[0131] S9: Drive signal generation;

[0132] This is implemented using a set-reset (SR) flip-flop or an equivalent logic control unit. The turn-off end signal (Toff_end) acts as a set signal, causing the flip-flop to output a high level, driving the power switch to turn on and starting a new cycle. The turn-on end signal (Ton_end) acts as a reset signal, causing the flip-flop to output a low level, driving the power switch to turn off. This cycle repeats, generating the drive signal V for the power switch. DRV Control its alternating on and off states.

[0133] S10: Frequency-locked closed-loop regulation; This step describes the dynamic working process of the closed-loop negative feedback system constituted by the above steps S4 to S9.

[0134] After the system powers on or is disturbed, the actual frequency Fsw_act deviates from the target Fref. This deviation is detected in S5, integrated in S6, and then Toff_ref is adjusted. In the new cycle, the change in Toff_ref alters the off-time Toff through S7 and S8, thereby changing the switching period Tsw (Tsw = Ton + Toff), which ultimately has a feedback effect on Fsw_act. This closed-loop mechanism ensures that if Fsw_act is too high, Toff_ref increases, leading to a longer Toff, which in turn reduces Fsw_act; and vice versa. Through iterative adjustments over multiple cycles, Fsw_act dynamically converges and stably locks onto the target frequency Fref, achieving high-precision frequency locking in steady state.

[0135] This embodiment achieves a clear separation of control responsibilities logically through an original step division (S1-S3 as the fast loop and S4-S8 as the slow loop). The voltage / current inner loop (fast loop) is dedicated to rapid energy regulation at the millisecond / microsecond level, ensuring dynamic response; the frequency outer loop (slow loop) is dedicated to frequency error accumulation and correction across multiple cycles, ensuring steady-state accuracy. This decoupling design on the time scale ensures, from a methodological perspective, that the two loops do not interfere with each other and their advantages are superimposed. This fundamentally overcomes the inherent deficiency of existing single-loop control methods that cannot simultaneously achieve speed and accuracy. Furthermore, the core frequency locking path (S4-S8) is completely independent of the specific parameters of the main power topology. It does not rely on "detecting V..." IN Instead of using the traditional physical model for calculating Toff, this method is based on the universal feedback control principle of "measurement-comparison-integration-adjustment". Therefore, it can be seamlessly applied to various topologies such as boost, buck, and buck-boost, requiring only the adaptation of the corresponding S1-S3 steps. Furthermore, this invention completely eliminates the need to sample signals from high-potential, high-noise power nodes, thus eliminating the safety risks of high voltage introduction into the control terminal at the method level, making it possible to develop power chips with high isolation and high functional safety levels.

[0136] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A DC-DC converter with a frequency-locked control loop, characterized in that: It includes an error amplifier, a pulse width modulation module, a turn-off time control module, and a power transistor driver module; The first input terminal of the error amplifier receives the output voltage feedback signal of the DC-DC converter, and the second input terminal of the error amplifier receives the reference voltage signal. The error amplifier is used to amplify the error between the output voltage feedback signal and the reference voltage signal and output the error amplification signal. The first input terminal of the pulse width modulation module is connected to the output terminal of the error amplifier to receive the error amplification signal. The second input terminal of the pulse width modulation module receives a sampling signal characterizing the inductor current, which is used to generate a first control signal to end the conduction phase of the power switch when the sampling signal reaches the error amplification signal. The third and fourth input terminals of the pulse width modulation module receive a turn-off time reference signal and a turn-off time ramp signal, respectively, which are used to generate a second control signal to end the turn-off phase of the power switch when the turn-off time ramp signal reaches the turn-off time reference signal. The first input terminal of the turn-off time control module is connected to the feedback node of the drive signal of the power switch, and the second input terminal of the turn-off time control module receives an externally provided reference clock signal. The first output terminal of the turn-off time control module outputs a turn-off time reference signal to the third input terminal of the pulse width modulation module, and the second output terminal of the turn-off time control module outputs a turn-off time ramp signal to the fourth input terminal of the pulse width modulation module. The turn-off time control module is used to detect the error between the actual switching frequency of the drive signal and the target frequency of the reference clock signal, and generate a turn-off time reference signal based on the error to adjust the turn-off time of the power switch in a closed loop, so that the actual switching frequency is locked to the target frequency. The input terminal of the power transistor drive module is connected to the output terminal of the pulse width modulation module, and is used to generate and output a drive signal according to the first control signal and the second control signal to control the power switch transistor to turn on and off.

2. A DC-DC converter with a frequency-locked control loop according to claim 1, characterized in that: The shutdown time control module includes: The first frequency discriminator (201) has its input terminal connected to the feedback node of the driving signal, and is used to convert the frequency of the driving signal into a first voltage signal; The second frequency discriminator (202) receives the reference clock signal at its input terminal and is used to convert the frequency of the reference clock signal into a second voltage signal. The switched capacitor integrator (203) receives a first voltage signal at its first differential input terminal and a second voltage signal at its second differential input terminal. It is used to perform integration calculation on the difference between the first voltage signal and the second voltage signal and output the integration result as a turn-off time reference signal. A ramp signal generator (204) has its input connected to the feedback node of the drive signal and is used to generate a linearly rising turn-off time ramp signal during the period when the drive signal indicates that the power switch is turned off.

3. A DC-DC converter with a frequency-locked control loop according to claim 2, characterized in that: The first frequency discriminator (201) and the second frequency discriminator (202) have the same structure; both the first frequency discriminator (201) and the second frequency discriminator (202) include: a frequency division unit, a frequency to voltage conversion unit and a filtering unit; The frequency division unit includes a D flip-flop, the clock terminal of the D flip-flop receives the input clock signal, the D terminal of the D flip-flop is connected to its own inverted output terminal (QN), and the non-inverted output terminal (Q) of the D flip-flop outputs the frequency division control signal. The frequency-to-voltage conversion unit includes a first capacitor (C). A ), constant current source (I) BIAS1 ), third switch (MOS3), fourth switch (MOS4) and second capacitor (C) S The constant current source (I) BIAS1 The first end of the capacitor (C) is connected to the power supply, and the second end is connected to the first node (N1); the first capacitor (C) A The third switch (MOS3) is connected between the first node (N1) and ground; the source of the third switch (MOS3) is connected to the first node (N1), the drain is connected to the second node (N2), and the gate receives the frequency division control signal; the second capacitor (C) is connected between the first node (N1) and ground. S The fourth switch (MOS4) is connected between the second node (N2) and ground; the fourth switch (MOS4) is connected in parallel with the second capacitor (C). S At both ends of the circuit, the gate of the fourth switch (MOS4) receives the frequency division control signal, and the conduction state of the fourth switch (MOS4) is opposite to that of the third switch (MOS3). The input terminal of the filtering unit is connected to the first node (N1) and is used to filter the voltage signal on the first node (N1) and output a first voltage signal (V). DE ) or second voltage signal (V RE ).

4. A DC-DC converter with frequency locking control loop according to claim 1, characterized in that: The ramp signal generator (204) includes: a second capacitor (Cr), a charging constant current source (I... BIAS2 ), the fifth switch (MOS5), and the sixth switch (MOS6); The charging constant current source (I) BIAS2 The first terminal of the transistor is connected to the power supply, and the second terminal is connected to the source of the fifth switching transistor (MOS5); the drain of the fifth switching transistor (MOS5) is connected to the third node (N3), and the gate receives the drive signal (V) from the power switching transistor. DRV The second capacitor (Cr) is connected between the third node (N3) and ground; the sixth switch (MOS6) is connected in parallel across the second capacitor (Cr), and the gate of the sixth switch (MOS6) receives the drive signal (V) from the power switch. DRV ); The third node (N3) outputs the turn-off time ramp signal (Toff_ramp); when the drive signal (V DRV When the signal is low, the power switch is turned off. At this time, the fifth switch (MOS5) is turned on and the sixth switch (MOS6) is turned off, and the charging constant current source (I) BIAS2 The second capacitor (Cr) is charged with a constant current, causing the turn-off time ramp signal (Toff_ramp) to rise linearly; when the drive signal (V) DRV When the signal is high, it indicates that the power switch is turned on. At this time, the fifth switch (MOS5) is turned off and the sixth switch (MOS6) is turned on. The second capacitor (Cr) discharges rapidly through the sixth switch (MOS6), causing the turn-off time ramp signal (Toff_ramp) to reset to a low level.

5. A DC-DC converter with a frequency-locked control loop according to claim 1, characterized in that: The switched capacitor integrator (203) includes: an integrating operational amplifier, an integrating capacitor (Ci), a sampling capacitor (Cq), a first switching transistor (MOS1), a second switching transistor (MOS2), a first voltage buffer, and a second voltage buffer; The input terminal of the first voltage buffer receives the first voltage signal (V). DE The output of the first voltage buffer is connected to the source of the first switching transistor (MOS1); the input of the second voltage buffer receives the second voltage signal (V). RE The output of the second voltage buffer is connected to the lower plate of the sampling capacitor (Cq) and the non-inverting input of the integrating operational amplifier; the inverting input of the integrating operational amplifier is connected to the source of the second switching transistor (MOS2) and the first terminal of the integrating capacitor (Ci); the output of the integrating operational amplifier outputs a turn-off time reference signal (Toff_ref) and is connected to the second terminal of the integrating capacitor (Ci); the upper plate of the sampling capacitor (Cq) is connected to the drain of the first switching transistor (MOS1) and the drain of the second switching transistor (MOS2); the gates of the first switching transistor (MOS1) and the second switching transistor (MOS2) receive a set of first clock signals (Φ1) and second clock signals (Φ2) that are out of phase and do not overlap. When the first clock signal (Φ1) is valid, the first switch (MOS1) is turned on and the second switch (MOS2) is turned off, and the sampling capacitor (Cq) is charged to the first voltage signal (V). DE ) and the second voltage signal (V RE The difference voltage between the two; when the second clock signal (Φ2) is valid, the first switch (MOS1) is turned off and the second switch (MOS2) is turned on, the sampling capacitor (Cq) is connected between the inverting input terminal and the non-inverting input terminal of the integrating operational amplifier, and the charge corresponding to the difference voltage is transferred to the integrating capacitor (Ci), thereby adjusting the off-time reference signal (Toff_ref) output by the integrating operational amplifier.

6. A DC-DC converter with a frequency-locked control loop according to claim 1, characterized in that: The sampling signal characterizing the inductor current is obtained by connecting a sampling resistor in series between the source of the power switch and the power supply ground, and obtaining the sampling signal by detecting the voltage across the sampling resistor.

7. A DC-DC converter with frequency locking control loop according to claim 1, characterized in that: The DC-DC converter is a boost converter.

8. A frequency-locking control method for a DC-DC converter, characterized in that, Includes the following steps: S1: Voltage error detection and amplification; The output voltage of the DC-DC converter is detected, and an output voltage feedback signal is obtained by voltage division; the output voltage feedback signal is compared and amplified with a reference voltage signal to generate an error amplification signal. S2: Inductor current sampling; The inductor current flowing through the power switch is detected and converted into a current sampling signal by a sampling circuit; S3: On-time control; In each switching cycle, the current sampling signal is compared with the error amplification signal; When the current sampling signal reaches the error amplification signal, an on-end signal is generated to control the power switch to turn off, thereby determining and ending the on-time of that cycle; S4: Acquisition of actual switching frequency; Acquire the drive signal of the power switch transistor, and determine the actual switching frequency of the DC-DC converter based on the edge or period of the drive signal. S5: Frequency error detection; provides an external reference clock signal with the target locking frequency; compares the actual switching frequency with the target locking frequency to obtain frequency error information; S6: Generation of turn-off time reference signal; The frequency error information is converted into an analog voltage error signal, and the voltage error signal is integrated to generate a turn-off time reference signal; wherein, the level of the turn-off time reference signal is related to the frequency error and is used to indicate the required turn-off time length. S7: Turn-off time ramp signal generation; During the power switch turn-off period, a turn-off time ramp signal that rises linearly from an initial level is generated; During the power switch turn-on period, the turn-off time ramp signal is reset to the initial level; S8: Turn-off time control; During the turn-off phase of each switching cycle, the turn-off time ramp signal is compared with the turn-off time reference signal; When the turn-off time ramp signal reaches the turn-off time reference signal, a turn-off end signal is generated, and the power switch is controlled to turn on, thereby determining and ending the turn-off time of the cycle. S9: Drive signal generation; Based on the turn-on end signal and turn-off end signal, generate and output the drive signal of the power switch to control its alternating turn-on and turn-off; S10: Frequency locking closed-loop adjustment; by repeatedly executing steps S4 to S9, the frequency error between the actual switching frequency and the target locking frequency is fed back to the turn-off time control loop via the turn-off time reference signal; the turn-off time of each cycle is adjusted through closed-loop negative feedback so that the actual switching frequency dynamically converges and locks to the target locking frequency.

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