Asymmetric two-path synthesized CMOS (complementary metal oxide semiconductor) power amplifier

Abstract

The invention relates to an asymmetric two-path synthesized CMOS power amplifier, and the amplifier comprises an input transformer Balun TF1 which is used for converting an input single-end radio frequency signal into a differential signal; the driving amplifier DA0 is used for amplifying the differential signal; the quadrature coupler QC is used for dividing the amplified differential signal into two paths of signals and inputting the two paths of signals into the power amplification circuit; the power amplification circuit is used for performing power amplification on the two paths of signals output by the quadrature coupler QC through an asymmetric two-path circuit to obtain two paths of power-amplified signals; and the power synthesis circuit is used for synthesizing and outputting the two paths of power-amplified signals. On the premise of ensuring the output power, the bandwidth is expanded, and meanwhile, the rollback efficiency and the linearity are enhanced.

Description

Technical Field

[0001] This invention relates to the field of radio frequency integrated circuit design technology, and in particular to an asymmetric two-way synthesized CMOS power amplifier. Background Technology

[0002] In modern wireless communication systems, such as 5G millimeter-wave communication, future 6G terahertz communication, and automotive millimeter-wave radar, stringent requirements are placed on the performance of power amplifiers, including high output power, high efficiency, wide bandwidth, and linearity. CMOS technology, with its advantages of high integration, low cost, and compatibility with digital circuits, has become one of the mainstream choices for power amplifier (PA) design. However, CMOS technology suffers from problems at high frequencies, such as low breakdown voltage, high substrate loss, and deterioration of device characteristics, which limit further improvements in PA performance.

[0003] In power amplifier (PA) design, power combining techniques are often used to achieve high output power by combining the output signals of multiple sub-PAs. Dual-path combining is a common power combining method, and the impedance transformation network, as a key component of the power combining system, is responsible for converting the output impedance of the sub-PAs to an impedance matched to the load. Its performance directly affects the efficiency and bandwidth of the PA. Traditional symmetrical impedance transformation networks struggle to simultaneously meet the design goals of high efficiency and wide bandwidth when dealing with complex high-frequency signal characteristics and diverse application scenarios.

[0004] An asymmetric Doherty power amplifier is disclosed in the prior art, which achieves higher power back-off efficiency and bandwidth in the 2-10 GHz operating frequency range. However, the negative capacitor technology and stepped impedance matching technology used in the design are not applicable to the Ka band, and the bandwidth will be significantly narrowed at high frequencies.

[0005] The prior art discloses a two-channel symmetrical Ka-band power combining amplifier with an operating frequency range of 18-22 GHz. It adopts two identical symmetrical circuit structures, with each amplifier and matching circuit designed exactly the same, to achieve current-mode power combining (transformer + T-type network). The saturated output power at 20 GHz is 22.28 dBm, and the peak AE is 20.3%. However, the back-off efficiency and linearity need to be optimized.

[0006] Therefore, developing novel impedance transformation networks is of great significance for improving the performance of CMOS power amplifiers in dual-channel synthesis. This invention proposes an asymmetric dual-channel synthesized CMOS power amplifier, in which the two amplifier circuits are designed independently according to their different focuses, with different amplifier and matching circuit parameters, for use in millimeter-wave wireless communication front-ends. Summary of the Invention

[0007] The purpose of this invention is to provide an asymmetric two-channel synthesized CMOS power amplifier that expands bandwidth while ensuring output power, and enhances back-off efficiency and linearity, making it suitable for millimeter-wave wireless communication front-ends.

[0008] To achieve the above objectives, the present invention provides the following solution:

[0009] An asymmetric two-channel synthesized CMOS power amplifier, comprising:

[0010] The input transformer balun TF1 is used to convert the input single-ended radio frequency signal into a differential signal;

[0011] The driver amplifier DA_0 is used to amplify the differential signal;

[0012] The quadrature coupler (QC) is used to split the amplified differential signal into two signals, which are then input to the power amplifier circuit.

[0013] A power amplifier circuit is used to amplify the two signals output by the quadrature coupler QC through an asymmetrical two-way circuit to obtain two amplified signals.

[0014] The power combining circuit is used to combine and output two power amplified signals.

[0015] Optionally, the two signals output by the quadrature coupler QC include two signals with a phase difference of 90°.

[0016] Optionally, the output terminal of the input transformer balun TF1 is connected to the input terminal of the driver amplifier DA_0, and the bias terminal of the input transformer balun TF1 is connected to the bias voltage V. b The output terminal of the drive amplifier DA_0 is connected to the input terminal of the quadrature coupler QC.

[0017] Optionally, the power amplifier circuit includes a first amplification unit and a second amplification unit;

[0018] The first amplification unit includes a first driver stage amplifier DA_1, a first power stage amplifier PA_1, matching transformers TF2 and TF4. The first output terminal of the quadrature coupler QC is connected to the input terminal of the matching transformer TF2. The output terminal of the matching transformer TF2 is connected to the input terminal of the first driver stage amplifier DA_1. The bias terminal of the first driver stage amplifier DA_1 is connected to V... b1 The output of the first driver amplifier DA_1 is connected to the input of the matching transformer TF4, and the output of the matching transformer TF4 is connected to the input of the first power amplifier PA_1. The power supply terminals of both the first driver amplifier DA_1 and the first power amplifier PA_1 are connected to the supply voltage V.DD ;

[0019] The second amplification unit includes a second driver amplifier DA_2, a second power amplifier PA_2, and matching transformers TF3 and TF5. The second output of the quadrature coupler QC is connected to the input of the matching transformer TF3; the output of the matching transformer TF3 is connected to the input of the second driver amplifier DA_2; and the bias terminal of the second driver amplifier DA_2 is connected to V. b2 The output of the second driver amplifier DA_2 is connected to the input of the matching transformer TF5. The output of the matching transformer TF5 is connected to the input of the second power amplifier PA_2. The power supply terminals of both the second driver amplifier DA_2 and the second power amplifier PA_2 are connected to V. DD .

[0020] Optionally, the first driver stage amplifier DA_1 and the second driver stage amplifier DA_2 have different gate widths, and the first power stage amplifier PA_1 and the second power stage amplifier PA_2 have different gate widths.

[0021] Optionally, the first driver stage amplifier DA_1 is used to amplify one of the signals output by the quadrature coupler QC.

[0022] The first power stage amplifier PA_1 is used to amplify the power of the signal amplified by the first driver stage amplifier DA_1.

[0023] The second driver stage amplifier DA_2 is used to amplify the other signal output from the quadrature coupler QC.

[0024] The second power stage amplifier PA_2 is used to amplify the power of the signal amplified by the second driver stage amplifier DA_2.

[0025] Optionally, the power combining circuit includes a power combining transformer TF6 and RF. out Terminal, wherein the power combining transformer TF6 combines the two power-amplified signals and from RF out Terminal output.

[0026] The beneficial effects of the present invention are: (1) The orthogonal coupler is divided into two circuits with a 90-degree phase difference. Each circuit has a different transformer. By differentiating the electrical length, the phase is synchronized during output synthesis, thus achieving better broadband performance.

[0027] (2) The amplifier designs of the two circuits are different. Different sizes of transistors are selected to construct the common-source amplifier. The smaller size has high linearity and efficiency, while the larger size has high output power. One circuit mainly improves the output power with a larger size, while the other mainly maintains linearity and power consumption with a smaller size. The bias voltages of the two amplifiers are also different and can be dynamically configured according to the requirements. They can provide greater output power, linearity and power efficiency.

[0028] (3) The two signals are orthogonal, which improves anti-interference capability and linearity. When the two signals are symmetrical, interference is easily generated between in-phase signals, requiring the addition of an isolation layer; however, when orthogonal asymmetrical phase separation is used, there is natural isolation between the two signals, eliminating the need for additional isolation design. This improves the overall performance of the amplifier. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 This is a structural diagram of an asymmetric two-way synthesized CMOS power amplifier according to an embodiment of the present invention;

[0031] Figure 2 The phase and phase difference of the two output signals of the power amplifier in this embodiment of the invention;

[0032] Figure 3 This is a simulation diagram of the S-parameters of the power amplifier according to an embodiment of the present invention;

[0033] Figure 4 This is a power simulation diagram of the power amplifier according to an embodiment of the present invention. Detailed Implementation

[0034] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0035] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0036] The short wavelength of 5G millimeter-wave bands amplifies the effects of frequency-dependent circuit parasitic parameters (such as transmission line parasitic inductance and substrate coupling capacitance). Traditional two-way symmetrical structures are prone to reduced power amplifier synthesis efficiency over wide bandwidths due to phase shift. Furthermore, the fixed structure of symmetrical networks makes them less adaptable to different frequency signals, hindering flexible adjustment of impedance matching conditions and making wideband operation difficult. Simultaneously, interference between the two in-phase signals easily occurs, leading to decreased linearity and efficiency.

[0037] Based on the above problems, this embodiment proposes an asymmetric two-way synthesized CMOS power amplifier, such as... Figure 1 As shown, it includes:

[0038] The input transformer balun TF1 is used to convert the input single-ended radio frequency signal into a differential signal;

[0039] The driver amplifier DA_0 is used to amplify the differential signal;

[0040] The quadrature coupler (QC) is used to split the amplified differential signal into two signals, which are then input to the power amplifier circuit.

[0041] The power amplifier circuit is used to amplify the two signals output from the quadrature coupler QC through an asymmetrical two-way circuit, and obtain two amplified signals.

[0042] The power combining circuit is used to combine and output two power amplified signals.

[0043] Specifically, the input transformer balun TF1 consists of two coils, which are used to convert the input single-ended RF signal into a differential signal and perform impedance matching of the signal, so as to provide a suitable input form for the subsequent input driver amplifier DA_0.

[0044] Furthermore, the two signals output by the quadrature coupler QC include two signals with a 90° phase difference. The driver amplifier DA_0, acting as a preamplifier, initially amplifies the signal after conversion by TF1, providing sufficient signal strength for the subsequent quadrature coupler QC and the two amplification branches.

[0045] Quadrature Coupler (QC): Internally containing inductors, capacitors, and other components, it splits a single input signal into two signals with a 90° phase difference. The QC divides the signal into two circuits with a 90° phase difference, each with a different transformer. By varying the transformer length, phase synchronization is achieved during output synthesis, resulting in better broadband performance.

[0046] Furthermore, the output terminal of the input transformer balun TF1 is connected to the input terminal of the driver amplifier DA_0, and the bias terminal of the input transformer balun TF1 is connected to the bias voltage V. bThe output of the driver amplifier DA_0 is connected to the input of the quadrature coupler QC.

[0047] Furthermore, the power amplifier circuit includes a first amplification unit and a second amplification unit;

[0048] The first amplification unit includes a first-stage driver amplifier DA_1, a first-stage power amplifier PA_1, and matching transformers TF2 and TF4. The first output terminal of the quadrature coupler QC is connected to the input terminal of matching transformer TF2. The output terminal of matching transformer TF2 is connected to the input terminal of the first-stage driver amplifier DA_1. The bias terminal of the first-stage driver amplifier DA_1 is connected to V... b1 The output of the first driver amplifier DA_1 is connected to the input of the matching transformer TF4, and the output of the matching transformer TF4 is connected to the input of the first power amplifier PA_1. The power supply terminals of both the first driver amplifier DA_1 and the first power amplifier PA_1 are connected to the supply voltage V. DD ;

[0049] The second amplification unit includes a second driver amplifier DA_2, a second power amplifier PA_2, and matching transformers TF3 and TF5. The second output of the quadrature coupler QC is connected to the input of the matching transformer TF3; the output of the matching transformer TF3 is connected to the input of the second driver amplifier DA_2; and the bias terminal of the second driver amplifier DA_2 is connected to V... b2 The output of the second driver amplifier DA_2 is connected to the input of the matching transformer TF5. The output of the matching transformer TF5 is connected to the input of the second power amplifier PA_2. The power supply terminals of both the second driver amplifier DA_2 and the second power amplifier PA_2 are connected to V. DD .

[0050] Specifically, the output of the input driver amplifier DA_0 is connected to the input of the quadrature coupler QC, forming a transmission path from the preamplified signal to the splitter unit.

[0051] Furthermore, the first driver stage amplifier DA_1 and the second driver stage amplifier DA_2 have different gate widths, and the first power stage amplifier PA_1 and the second power stage amplifier PA_2 also have different gate widths.

[0052] In one embodiment, the driver stage amplifiers DA_0 and DA_1 are common-source amplifiers constructed using MOS transistors with a gate width of 60µm, and DA_2 is a common-source amplifier constructed using MOS transistors with a gate width of 120µm; PA_1 is a common-source amplifier with a gate width of 160µm, and PA_2 is a common-source amplifier with a gate width of 240µm.

[0053] The coil inductance values ​​of the matching transformers are as follows: TF1: main coil 200pH, secondary coil 300pH; TF2: main coil 330pH, secondary coil 310pH; TF3: main coil 210pH, secondary coil 230pH; TF4: main coil 180pH, secondary coil 80pH; TF5: main coil 120pH, secondary coil 50pH; TF6: both main coil 1 and secondary coil 1 are 200pH, and both main coil 2 and secondary coil 2 are 120pH.

[0054] The two circuits have different amplifier designs, using transistors of different sizes to build common-source amplifiers. One circuit uses a large transistor to increase output power, while the other uses a small transistor to maintain linearity and power consumption.

[0055] Furthermore, the first driver stage amplifier DA_1 is used to amplify one of the signals output from the quadrature coupler QC.

[0056] The first power stage amplifier PA_1 is used to amplify the signal amplified by the first driver stage amplifier DA_1.

[0057] The second driver stage amplifier DA_2 is used to amplify the other signal output from the quadrature coupler QC.

[0058] The second power stage amplifier PA_2 is used to amplify the signal amplified by the second driver stage amplifier DA_2.

[0059] Specifically, the first driver stage amplifier DA_1 amplifies one of the signals output from the quadrature coupler QC, improving the signal's driving capability. The first power stage amplifier PA_1 amplifies the signal amplified by DA_1, further enhancing the signal power. The second driver stage amplifier DA_2 amplifies the other signal output from the quadrature coupler QC. The second power stage amplifier PA_2 amplifies the signal amplified by DA_2. Matching transformers TF2~TF5 are used in each signal transmission process to achieve impedance matching between different amplification stages, ensuring efficient signal transmission.

[0060] Furthermore, the power combining circuit includes a power combining transformer TF6 and RF. out At the terminal, the power combining transformer TF6, composed of two coils, combines the two amplified power signals and receives them from the RF circuit. out Terminal output.

[0061] The operation of an asymmetric two-way synthesized CMOS power amplifier includes:

[0062] Input and preamplification stage: RF signal from RF in The single-ended input signal first enters the input transformer balun TF1, which converts the single-ended input signal into a differential signal. The converted differential signal is then input to the input driver amplifier DA_0, which performs initial amplification to provide sufficient signal strength for subsequent processing. b The bias voltage for DA_0 is provided through the coil tap of TF1, and the operating power supply is V. DD , through the coil taps of TF2 and TF3.

[0063] Quadrature splitting stage: The signal amplified by DA_0 is input to the quadrature coupler QC. Based on the phase characteristics of the coupling circuit, the quadrature coupler QC utilizes the interaction of its internal inductors, capacitors, and other components to split the input signal into two signals with a 90° phase difference. In principle, the quadrature coupler, through specific impedance matching and signal coupling methods, causes different phase delays in the input signal along the two different coupling paths, thereby achieving a 90° phase difference output between the two signals.

[0064] First amplification stage:

[0065] Components: Composed of driver stage amplifier DA_1, power stage amplifier PA_1, and matching transformers TF2 and TF4.

[0066] Working process: One signal output from the quadrature coupler QC first undergoes impedance matching via matching transformer TF2 before being input to the driver stage amplifier DA_1; the signal amplified by DA_1 then undergoes matching again via matching transformer TF4 before being input to the power stage amplifier PA_1 for power amplification. b1 The coil taps of TF2 and TF4 provide bias voltages for DA_1 and PA_1 respectively, and VDD provides the operating power for DA_1 and PA_1.

[0067] Second amplification stage:

[0068] Components: Composed of driver stage amplifier DA_2, power stage amplifier PA_2, and matching transformers TF3 and TF5.

[0069] Working process: The other signal output from the quadrature coupler QC, after impedance matching by the matching transformer TF3, is input to the driver stage amplifier DA_2; the signal amplified by DA_2 is matched by the matching transformer TF5 and then input to the power stage amplifier PA_2 for power amplification. b2 Bias voltages are provided to DA_2 and PA_2 respectively through the coil taps of TF3 and TF5, V DD Provide operating power for DA_2 and PA_2.

[0070] Power combining and output stage: The two signals, each amplified separately, are input to the output power combining transformer TF6. TF6 combines these two signals, and the final amplified RF signal is output from RF... out Terminal output.

[0071] This embodiment simulates the two-channel output phase, S-parameters, output power, and power efficiency of the designed power amplifier.

[0072] like Figure 2 As shown, the phase difference between the two output signals of the amplifier is controlled within 5° in the 24-33GHz range, which can effectively improve the efficiency of power combining of the two channels and increase the output power and gain of the amplifier.

[0073] like Figure 3 As shown, the simulated maximum gain of the power amplifier reaches 24 dB, and the bandwidth of the gain covers 25-31 GHz; the return loss is good.

[0074] like Figure 4 As shown, the maximum output power in the simulation is 21.5 dBm. This is greater than 20 dBm in the 24-33 GHz range.

[0075] The linearity (output 1dB compression point) is greater than 18dBm in the 26-32GHz range, with a maximum of 19dBm;

[0076] The power efficiency is greater than 25% in the 24-32GHz range, with a maximum of 27.2%; the power amplifier demonstrates excellent performance in terms of power, linearity, and efficiency.

[0077] The embodiments described above are merely preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Various modifications and improvements made to the technical solutions of the present invention by those skilled in the art without departing from the spirit of the present invention should fall within the protection scope defined by the claims of the present invention.

Claims

1. An asymmetric two-path combined CMOS power amplifier characterized by, The application relates to a power amplifier circuit. The application comprises: an input transformer balun TF1 for converting an input single-end radio frequency signal into a differential signal; a driver amplifier DA_0 for amplifying the differential signal; a quadrature coupler QC for splitting the amplified differential signal into two signals and inputting the two signals into a power amplifier circuit; the power amplifier circuit for power-amplifying the two signals output by the quadrature coupler QC through an asymmetric two-path circuit to obtain two power-amplified signals; 2. The asymmetric two-path synthesized CMOS power amplifier of claim 1, wherein, a power combining circuit for combining the two power-amplified signals and outputting the combined signal.

3. The asymmetric two-path synthesized CMOS power amplifier of claim 1, wherein, The output end of the input transformer balun TF1 is connected with the input end of the drive amplifier DA_0, and the bias end of the input transformer balun TF1 is connected with a bias voltage V b The output end of the drive amplifier DA_0 is connected with the input end of the quadrature coupler QC.

4. The asymmetric two-path synthesized CMOS power amplifier of claim 1, wherein, The two signals output by the quadrature coupler QC comprise two signals with a phase difference of 90 degrees. The first path amplification unit comprises a first path driver stage amplifier DA_1, a first path power stage amplifier PA_1, matching transformers TF2 and TF4, wherein the first path output end of the quadrature coupler QC is connected to the input end of the matching transformer TF2, the output end of the matching transformer TF2 is connected to the input end of the first path driver stage amplifier DA_1, the bias end of the first path driver stage amplifier DA_1 is connected to V b1 , the output end of the first path driver stage amplifier DA_1 is connected to the input end of the matching transformer TF4, and the output end of the matching transformer TF4 is connected to the input end of the first path power stage amplifier PA_1; the power supply ends of the first path driver stage amplifier DA_1 and the first path power stage amplifier PA_1 are connected to the power supply voltage V DD . The second path amplification unit comprises a second path driver stage amplifier DA_2, a second path power stage amplifier PA_2, matching transformers TF3 and TF5, wherein the second path output end of the quadrature coupler QC is connected to the input end of the matching transformer TF3; the output end of the matching transformer TF3 is connected to the input end of the second path driver stage amplifier DA_2, the bias end of the second path driver stage amplifier DA_2 is connected to V b2 , the output end of the second path driver stage amplifier DA_2 is connected to the input end of the matching transformer TF5, the output end of the matching transformer TF5 is connected to the input end of the second path power stage amplifier PA_2, and the power supply ends of the second path driver stage amplifier DA_2 and the second path power stage amplifier PA_2 are both connected to V DD .

5. The asymmetric two-path synthesized CMOS power amplifier of claim 4, wherein, The power amplifier circuit comprises a first-path amplification unit and a second-path amplification unit.

6. The asymmetric two-path synthesized CMOS power amplifier of claim 4, wherein, The gate widths of the first-path driver-stage amplifier DA_1 and the second-path driver-stage amplifier DA_2 are different, and the gate widths of the first-path power-stage amplifier PA_1 and the second-path power-stage amplifier PA_2 are different. The first-path driver-stage amplifier DA_1 is used for driver-stage amplifying one of the two signals output by the quadrature coupler QC; The first-path power-stage amplifier PA_1 is used for power-amplifying the signal amplified by the first-path driver-stage amplifier DA_1; The second-path driver-stage amplifier DA_2 is used for driver-stage amplifying the other of the two signals output by the quadrature coupler QC; The second-path power-stage amplifier PA_2 is used for power-amplifying the signal amplified by the second-path driver-stage amplifier DA_2.

7. The asymmetric two-path synthesized CMOS power amplifier of claim 1, wherein, The power combining circuit includes a power combining transformer TF6 and RF out ends, wherein the power combining transformer TF6 combines the signals amplified by the two paths and outputs from the RF out ends, wherein the power combining transformer TF6 combines the signals amplified by the two paths and outputs from the RF

Images