Control method of VDMOS (Vertical Double-diffused Metal Oxide Semiconductor) device

Abstract

The invention provides a control method of a VDMOS device. According to the method, an upper tube grid voltage signal of an upper tube VDMOS device and a lower tube grid voltage signal of a lower tube VDMOS device in a circuit are acquired, and initial dead time is determined according to the upper tube grid voltage signal and the lower tube grid voltage signal, so that target dead time is determined according to a load state in the circuit and the initial dead time. According to the method, the target dead time is dynamically adjusted to turn off an upper tube VDMOS device and a lower tube VDMOS device in the audio power amplifier circuit at the same time, so that the circuit can keep a stable working state under different load conditions by dynamically adjusting the target dead time.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data processing, in particular to a control method of VDMOS device. BACKGROUND

[0002] In the field of audio power amplifier, VDMOS device is widely used due to its high input impedance, fast switching speed and good thermal stability.

[0003] In the prior art, the VDMOS device in the audio power amplifier circuit is usually designed with a fixed dead time. This design method sets a relatively safe dead time according to the parameters provided in the device manual at the initial stage of circuit design, to ensure that the upper and lower tubes will not be turned on at the same time under normal working conditions, thereby avoiding the risk of short circuit.

[0004] However, in actual application, the load state of the audio power amplifier will change constantly with the change of the audio signal. The fixed dead time design cannot dynamically adjust the dead time according to the real-time change of the load, resulting in that the circuit performance cannot reach the optimal state under light load or heavy load conditions. For example, under light load conditions, too long dead time will introduce unnecessary switching crossover distortion, reducing the sound quality; while under heavy load conditions, too short dead time may increase the risk of short circuit. SUMMARY

[0005] The present application provides a control method of VDMOS device, which dynamically adjusts the target dead time, so that the audio power amplifier circuit can maintain stable working state under different load conditions, thereby reducing the influence of dead time on sound quality and efficiency, and improving the overall performance of the audio power amplifier circuit.

[0006] In a first aspect, the present application provides a control method of VDMOS device, characterized in that comprising:

[0007] obtaining an upper tube gate voltage signal of an upper tube VDMOS device and a lower tube gate voltage signal of a lower tube VDMOS device in a circuit;

[0008] determining an upper tube turn-on delay and an upper tube turn-off delay according to the upper tube gate voltage signal, and determining a lower tube turn-on delay and a lower tube turn-off delay according to the lower tube gate voltage signal;

[0009] determining a first characteristic time length according to the upper tube turn-on delay and the lower tube turn-off delay, and determining a second characteristic time length according to the upper tube turn-off delay and the lower tube turn-on delay, to determine the larger time length between the first characteristic time length and the second characteristic time length as an initial dead time;

[0010] The target dead time is determined according to a load state in the circuit and the initial dead time.

[0011] Optionally, the upper tube conduction delay or the lower tube conduction delay is a time length from when the gate voltage of the corresponding VDMOS device reaches a voltage threshold to when the collector current starts to rise.

[0012] The upper tube conduction delay or the lower tube conduction delay is a time length from when the gate voltage of the corresponding VDMOS device drops below the voltage threshold to when the collector current drops to zero.

[0013] Optionally, the target dead time is determined according to a load state in the audio power amplifier circuit and the initial dead time, including:

[0014] The load current of the circuit is obtained, and if the load current is lower than a preset current threshold, the load state is determined as a light load state.

[0015] If the load state is the light load state, a time length is shortened on the basis of the initial dead time to determine the target dead time.

[0016] Optionally, the time length is shortened on the basis of the initial dead time to determine the target dead time, including:

[0017] The target dead time is determined by using Formula 1 and according to the initial dead time and the load current wherein the Formula 1 is:

[0018]

[0019] wherein, is the preset current threshold.

[0020] Optionally, after the target dead time is determined according to the initial dead time and the load current the target dead time further includes:

[0021] If the target dead time is less than a preset lower limit of dead time, the target dead time is updated as the preset lower limit of dead time.

[0022] Optionally, the time length is shortened on the basis of the initial dead time to determine the target dead time, including:

[0023] The target dead time is determined as a calibration dead time, wherein the calibration dead time is greater than a preset lower limit of dead time and less than the initial dead time.​

[0024] Optionally, after the target dead time is determined, the method further comprises:

[0025] If the re-determined load current is higher than or equal to the preset current threshold, it is determined that the load state is a non-light load state, and the target dead time is switched to the initial dead time, so as to simultaneously turn off the upper VDMOS device and the lower VDMOS device in the audio power amplifier circuit by using the initial dead time.

[0026] In a second aspect, the present application provides an audio power amplifier circuit, comprising:

[0027] The upper VDMOS device and the lower VDMOS device are determined to have a dead time by the control method of any one of the possible VDMOS devices in the first aspect, so as to be simultaneously turned off.

[0028] In a third aspect, the present application provides an electronic device, comprising:

[0029] a processor; and

[0030] a memory for storing executable instructions of the processor;

[0031] The processor is configured to execute any one of the possible methods in the first aspect by executing the executable instructions.

[0032] In a fourth aspect, the present application provides a computer readable storage medium, wherein the computer readable storage medium stores computer execution instructions, and the computer execution instructions are executed by a processor to implement any one of the possible methods in the first aspect.

[0033] The VDMOS device control method provided in this application acquires the gate voltage signals of the upper and lower VDMOS transistors in an audio power amplifier circuit. It then determines the turn-on and turn-off delays of the upper transistor based on the gate voltage signal, and the turn-on and turn-off delays of the lower transistor based on the gate voltage signal. A first characteristic duration is then determined based on the turn-on and turn-off delays, and a second characteristic duration is determined based on the turn-off and turn-on delays. The larger of the first and second characteristic durations is chosen as the initial dead time. A target dead time is then determined based on the load state and the initial dead time in the audio power amplifier circuit. This target dead time is used to simultaneously turn off the upper and lower VDMOS transistors in the audio power amplifier circuit. By dynamically adjusting the target dead time, the audio power amplifier circuit can maintain a stable operating state under different load conditions, thereby reducing the impact of dead time on sound quality and efficiency, and improving the overall performance of the audio power amplifier circuit. Attached Figure Description

[0034] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0035] Figure 1 This is a schematic flowchart illustrating a control method for a VDMOS device according to an example embodiment of this application;

[0036] Figure 2 This is a flowchart illustrating a control method for a VDMOS device according to another exemplary embodiment of this application;

[0037] Figure 3 This is a schematic diagram of the structure of an electronic device according to an example embodiment of this application.

[0038] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0039] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0040] Figure 1 is a flowchart of a control method of a VDMOS device according to an example embodiment of the present application. As shown in the figure, the control method of the VDMOS device provided by the present embodiment comprises the following steps. Figure 1

[0041] S101, obtaining an upper tube gate voltage signal of an upper tube VDMOS device and a lower tube gate voltage signal of a lower tube VDMOS device in an audio power amplifier circuit.

[0042] First, in the audio power amplifier circuit, the gate (G) of the upper tube VDMOS device (Q1) and the lower tube VDMOS device (Q2) can be connected to the signal collection port through resistance voltage division or directly, so as to measure the gate voltage. Then, a high-impedance differential probe or an optocoupler isolator can be further connected to two channels of an oscilloscope, so as to respectively collect the upper tube gate voltage signal (VGS1) and the lower tube gate voltage signal (VGS2).

[0043] It is worth noting that the above measurement process can be performed after the completion of the circuit construction, thereby providing an analysis basis for subsequent initial dead time, or can be performed in the subsequent optimization iteration process of the current, thereby updating and iterating the initial dead time, or a measurement module can be set in the audio power amplifier circuit to realize real-time measurement. The specific setting mode can be set according to the demand of the audio power amplifier circuit, which is not specifically limited in the present embodiment.

[0044] S102, determining the upper tube conduction delay and the upper tube turn-off delay according to the upper tube gate voltage signal, and determining the lower tube conduction delay and the lower tube turn-off delay according to the lower tube gate voltage signal.

[0045] Specifically, the cursor measurement function or the automatic measurement function of the oscilloscope can be used to measure the conduction delay and the turn-off delay of the upper tube and the lower tube, respectively.

[0046] The upper tube conduction delay or the lower tube conduction delay is the time length from when the gate voltage of the corresponding VDMOS device reaches the threshold voltage to when the collector current begins to rise. In actual measurement, it can be the time interval from when the gate voltage reaches the threshold voltage (such as 10V) to when the collector current begins to rise significantly (such as reaching 10% of the rated current).

[0047] The upper tube turn-off delay or the lower tube turn-off delay is the time length from when the gate voltage of the corresponding VDMOS device drops below the threshold voltage to when the collector current drops to zero. In actual measurement, it can be the time interval from when the gate voltage drops below the threshold voltage to when the collector current drops to near zero (such as less than 1% of the rated current).​

[0048] S103, determining a first characteristic duration according to the upper tube turn-on delay and the lower tube turn-off delay, and determining a second characteristic duration according to the upper tube turn-off delay and the lower tube turn-on delay, so as to determine the greater one of the first characteristic duration and the second characteristic duration as the initial dead time.

[0049] In this step, the upper tube turn-on delay and the lower tube turn-off delay can be accumulated to determine the first characteristic duration. Then, the upper tube turn-off delay and the lower tube turn-on delay are accumulated to determine the second characteristic duration. Then, the first characteristic duration and the second characteristic duration are compared to determine the greater one of the first characteristic duration and the second characteristic duration as the initial dead time.

[0050] By determining the first characteristic duration according to the upper tube turn-on delay and the lower tube turn-off delay, and determining the second characteristic duration according to the upper tube turn-off delay and the lower tube turn-on delay, so as to determine the greater one of the first characteristic duration and the second characteristic duration as the initial dead time, the simultaneous turn-on (shoot-through) of the upper and lower tube VDMOS devices in the audio power amplifier circuit can be effectively avoided, and the large current impact and circuit damage caused by the shoot-through can be prevented. In addition, it can provide a reasonable time basis for subsequent dynamic dead time adjustment, which can ensure the safety of the circuit and improve the efficiency of dynamic dead time adjustment.

[0051] It is worth noting that the existing VDMOS devices are designed with fixed dead time, which cannot adapt to the dynamic load changes of the audio power amplifier. For example, the prior art usually sets a single dead time value according to the device manual parameters, but does not consider the delay parameter changes caused by temperature drift and device aging. The above steps can solve the reliability problem in the parameter drift scenario by real-time acquisition of the upper / lower tube gate voltage signal, calculation of the turn-on / off delay time, and dynamic adjustment of the dead time.

[0052] In addition, the above steps combine the upper tube turn-on delay and the lower tube turn-off delay as the first characteristic duration, combine the upper tube turn-off delay and the lower tube turn-on delay as the second characteristic duration, and take the greater value as the initial dead time, which effectively solves the technical problem that the single-side delay calculation in the prior art is easily disturbed by noise.

[0053] S104, determining a target dead time according to the load state in the audio power amplifier circuit and the initial dead time.

[0054] In this step, the target dead time for simultaneously turning off the upper VDMOS device and the lower VDMOS device in the audio power amplifier circuit can be determined according to the load state in the audio power amplifier circuit and the initial dead time. In addition, the load state can be various load states preset for the audio power amplifier circuit, and different load states can be set according to voltage signal characteristics and / or current signal characteristics in the circuit as classification criteria.

[0055] In this embodiment, the upper gate voltage signal of the upper VDMOS device and the lower gate voltage signal of the lower VDMOS device in the audio power amplifier circuit are obtained, and then the upper conduction delay and the upper turn-off delay are determined according to the upper gate voltage signal, and the lower conduction delay and the lower turn-off delay are determined according to the lower gate voltage signal. Then, the first characteristic time length is determined according to the upper conduction delay and the lower turn-off delay, and the second characteristic time length is determined according to the upper turn-off delay and the lower conduction delay. The greater of the first characteristic time length and the second characteristic time length is determined as the initial dead time. The target dead time is determined according to the load state in the audio power amplifier circuit and the initial dead time, so that the upper VDMOS device and the lower VDMOS device in the audio power amplifier circuit are simultaneously turned off by using the target dead time. Thus, by dynamically adjusting the target dead time, the audio power amplifier circuit can maintain a stable working state under different load conditions, thereby reducing the influence of the dead time on the sound quality and efficiency, and improving the overall performance of the audio power amplifier circuit.

[0056] Further, since the target dead time can be dynamically adjusted according to the load state, the dead time can be optimized in real time according to the change of the load. In the audio power amplifier circuit, the load state changes constantly with the change of the audio signal, and different loads have different requirements for the dead time. For example, when the load is light, a smaller dead time can ensure high efficiency of the circuit; when the load is heavy, the dead time needs to be appropriately increased to prevent the upper and lower tubes from being directly connected. In the prior art, a fixed dead time is usually used, which cannot be dynamically adjusted according to the change of the load, resulting in that the performance of the circuit under different load conditions cannot be optimized. The above embodiment can dynamically adjust the target dead time, thereby solving the problem of performance degradation of the circuit caused by the fixed setting of the traditional dead time which cannot adapt to the change of different load states.

[0057] Figure 2 is a flowchart of a control method of a VDMOS device according to another example embodiment of the present application. As shown in Figure 2 the control method of the VDMOS device provided by the embodiment includes:

[0058] S201, obtaining an upper tube gate voltage signal of an upper tube VDMOS device and a lower tube gate voltage signal of a lower tube VDMOS device in an audio power amplifier circuit.

[0059] Firstly, in the audio power amplifier circuit, the gate (G) of the upper tube VDMOS device (Q1) and the lower tube VDMOS device (Q2) can be connected to the signal collection port through resistance voltage division or direct connection, so as to measure the gate voltage. Then, the high-impedance differential probe or the optocoupler isolator can be further connected to two channels of the oscilloscope, so as to collect the upper tube gate voltage signal (VGS1) and the lower tube gate voltage signal (VGS2) respectively.

[0060] S202, determining the upper tube turn-on delay and the upper tube turn-off delay according to the upper tube gate voltage signal, and determining the lower tube turn-on delay and the lower tube turn-off delay according to the lower tube gate voltage signal.

[0061] Specifically, the turn-on delay and the turn-off delay of the upper tube and the lower tube can be measured respectively by using the cursor measurement function or the automatic measurement function of the oscilloscope.

[0062] The upper tube turn-on delay or the lower tube turn-on delay is the time length from when the gate voltage of the corresponding VDMOS device reaches the voltage threshold to when the collector current begins to rise. In actual measurement, it can be the time interval from when the gate voltage reaches the threshold voltage (such as 10V) to when the collector current begins to rise significantly (such as reaching 10% of the rated current).

[0063] The upper tube turn-off delay or the lower tube turn-off delay is the time length from when the gate voltage of the corresponding VDMOS device drops below the voltage threshold to when the collector current drops to zero. In actual measurement, it can be the time interval from when the gate voltage drops below the threshold voltage to when the collector current drops to near zero (such as less than 1% of the rated current).

[0064] S203, determining the first characteristic time length according to the upper tube turn-on delay and the lower tube turn-off delay, and determining the second characteristic time length according to the upper tube turn-off delay and the lower tube turn-on delay, so as to determine the larger one of the first characteristic time length and the second characteristic time length as the initial dead time.

[0065] In this step, the upper tube turn-on delay and the lower tube turn-off delay can be added to determine the first characteristic time length. Then, the upper tube turn-off delay and the lower tube turn-on delay are added to determine the second characteristic time length. Then, the first characteristic time length and the second characteristic time length are compared to determine the larger one of the first characteristic time length and the second characteristic time length as the initial dead time.

[0066] S204, obtaining the load current of the audio power amplifier circuit, and determining that the load state is a light load state if the load current is lower than a preset current threshold.

[0067] In this step, a small resistance sampling resistor (such as 0.1Ω) can be connected in series at the output of the audio power amplifier, or a non-contact current monitoring device such as a Hall sensor can be used to collect the load current signal in real time. Then, the voltage drop across the sampling resistor or the output signal of the Hall sensor is amplified and filtered by an operational amplifier to eliminate high-frequency noise interference. Next, the conditioned signal is input to a comparator for comparison with a preset current threshold (such as 5A corresponding to a 0.5V sampling voltage).

[0068] If the comparator outputs a low-level signal (i.e., the load current is lower than the threshold), the microcontroller or field programmable gate array determines that the load state is a light load state; otherwise, if it outputs a high-level signal, it determines that it is not a light load state (such as heavy load or full load). The microcontroller or field programmable gate array can be configured with a timer interrupt to periodically (such as every 100μs) read the comparator state to ensure the real-time nature of the load state determination.

[0069] In a specific embodiment, assuming the preset current threshold is 5A and the sampling resistor is 0.1Ω. When the load current is 3A, the sampling voltage is 0.3V, which is lower than the threshold of 0.5V, the comparator outputs a low level, and the MCU determines that it is a light load state; when the load current rises to 6A, the sampling voltage is 0.6V, the comparator outputs a high level, and it is determined to be a non-light load state.

[0070] S205, if the load state is a light load state, then shorten the time on the basis of the initial dead time to determine the target dead time.

[0071] It is worth noting that the loss of a VDMOS device is divided into switching loss and conduction loss. Switching loss occurs during the transition of the device turning on / off and is directly related to the dead time; conduction loss depends on the device on-resistance and load current. In a light load state (such as load current below a preset threshold), the conduction loss is significantly reduced, and the switching loss becomes the main part of the total loss. At this time, shortening the dead time can reduce the energy loss of the device during the transition, thereby improving the overall efficiency.

[0072] Especially in the audio power amplifier circuit, the switching speed of the VDMOS device is affected by the gate charge and the driving current. In a light load state, the load current is small, the rate of change of the gate voltage is accelerated, and the device turn-on / off delay is shortened. If the dead time is fixed, it may cause the actual dead time to be too long relative to the device switching speed, resulting in unnecessary delay. Therefore, shortening the dead time can make the device switching action closely follow the input signal, reduce the phase delay, and improve the high-frequency response capability. In the audio power amplifier circuit, high-frequency signals have very high requirements for timing accuracy, and dead time optimization can significantly improve the restoration of high-frequency details.

[0073] If the dead time is too long, the load current may generate a reverse current due to the release of inductive energy during the conduction of the freewheeling diode, causing the gate voltage of the upper and lower tubes to fluctuate, triggering subharmonic oscillation. This oscillation will superimpose on the output signal, forming low-frequency noise. By shortening the dead time, the oscillation frequency can be increased to the audio frequency band, which can be easily filtered out by the filter circuit, thus eliminating noise interference.

[0074] Specifically, in a light load state, the amplitude of the audio signal is usually small, and the probability of the output voltage approaching the zero-crossing point is higher. A long dead time will cause the upper and lower VDMOS devices to be in the off state near the zero-crossing point for a longer time, and the load current will flow through the freewheeling diode (or body diode) during this period. Since the freewheeling diode has a conduction voltage drop, this will cause the output voltage waveform to have a "dead zone distortion" near the zero-crossing point, i.e., crossover distortion. The crossover distortion is manifested as a discontinuity or sudden change in the output signal near the zero-crossing point, introducing nonlinear distortion components and reducing the purity of the sound quality.

[0075] Secondly, a long dead time will also cause the VDMOS device to be in an incomplete conduction or incomplete off state during the switching process, which will increase the nonlinearity of the device. Nonlinearity will cause additional harmonic components in the audio signal, i.e., harmonic distortion. The harmonic distortion is manifested as the presence of additional frequency components in the output signal that are integer multiples of the original signal frequency. These components will interfere with the original audio signal and reduce the clarity of the sound quality.

[0076] Furthermore, in a light load state, a long dead time will also cause the switching action of the VDMOS device to be delayed, causing the output signal to have a phase shift relative to the input signal, resulting in phase distortion. The phase distortion is manifested as a change in the phase relationship of different frequency components in the output signal, causing the stereo sense and positioning sense of the sound quality to decrease.

[0077] In addition, in a light load state, the audio signal may also contain transient components that change rapidly. A long dead time will prolong the response time of the VDMOS device to the transient signal, causing the output signal to fail to accurately track the changes in the input signal. The poor transient response is manifested as a delay or overshoot in the output signal during transient changes, reducing the dynamic performance and clarity of the sound quality.

[0078] Finally, a long dead time may also cause the load current to generate a reverse current due to the release of inductive energy during the conduction of the freewheeling diode, which may cause the gate voltage of the upper and lower tubes to fluctuate, producing noise. In addition, a long dead time may also increase the influence of other noise sources (such as thermal noise, shot noise, etc.) in the circuit. The increase in noise level is manifested as the presence of additional noise components in the output signal, reducing the signal-to-noise ratio and clarity of the sound quality.

[0079] In one possible implementation, the target dead time can be determined as the calibration dead time, wherein the calibration dead time is greater than a preset lower dead time limit and less than the initial dead time. Optionally, the preset lower dead time limit can be determined first by the shortest upper-side turn-off time and the shortest lower-side turn-on time of the VDMOS device, and then the aforementioned calibration dead time can be determined by setting a safety threshold.

[0080] In another specific implementation, Formula 1 can be used, and the initial dead time can be determined. and load current Determine the target dead zone time Formula 1 is:

[0081]

[0082] in, This is the preset current threshold.

[0083] As the threshold between light load and full load, It is usually set to 20%-30% of the device's maximum rated current. For example, when the rated current is 10A, It covers common light-load scenarios for audio amplifiers (such as silent or low-volume playback).

[0084] And if because of If the time is too low, the target dead time determined by Formula 1 above will be insufficient, which will easily lead to shoot-through short circuits or reverse recovery failures.

[0085] Specifically, for example, because The target dead time determined by Formula 1 is 40ns, while the shortest turn-off time of the upper transistor in an audio power amplifier circuit is 50ns, and the shortest turn-on time of the lower transistor is 30ns. Therefore, the required minimum dead time is 80ns. Thus, if because... If the dead time is too low, and the target dead time is 40ns as determined by Formula 1 above, a shoot-through short circuit will occur. In this case, it is necessary to forcibly extend the dead time to avoid overlap of the drive signals of the upper and lower transistors.

[0086] For reverse recovery, after the upper transistor is turned off, the load current freewheels through the parasitic diode of the lower transistor. When the lower transistor is turned on, the diode needs to release its stored charge to complete the reverse recovery. If the dead time is insufficient, the lower transistor will turn on before the diode has fully recovered, which will lead to excessive voltage generated by the reverse recovery current and the line inductance. The resulting voltage spike may exceed the device's withstand voltage, leading to breakdown of the gate oxide layer of the VDMOS device.

[0087] Therefore, to further address the aforementioned issues, we can consider adjusting the initial dead time. and load current determining target dead time Afterwards, if the target dead time is less than a preset dead time lower limit time, the target dead time is updated to the preset dead time lower limit time. Optionally, the preset dead time lower limit time can be determined by the shortest upper tube off time, the shortest lower tube on time and the safety threshold of the VDMOS device.

[0088] S206, if the redetermined load current is higher than or equal to the preset current threshold, it is determined that the load state is a non-light load state, and the target dead time is switched to the initial dead time.

[0089] In this step, if the redetermined load current is higher than or equal to the preset current threshold, it is determined that the load state is a non-light load state, and the target dead time is switched to the initial dead time, so as to simultaneously turn off the upper tube VDMOS device and the lower tube VDMOS device in the audio power amplifier circuit by using the initial dead time.

[0090] When it is detected that the load current jumps from the light load area to the non-light load area (such as the audio signal suddenly increases from low volume to high volume), a switching signal is immediately generated. The current target dead time is replaced by the initial dead time. Specifically, the driving signal timing of the upper tube and the lower tube can be updated synchronously by a digital signal processor or a special driving chip, so as to ensure that the dead time switching has no delay.

[0091] In the above embodiment, the dead time is shortened to maximize the efficiency when the load is light, so as to meet the demand of the audio equipment for low power consumption. When the load is not light, the initial dead time is restored to ensure safety and avoid maintenance costs caused by device damage.

[0092] Compared with the prior art, the above embodiment only needs to add a current sampling circuit and a comparator, and then realizes by simple threshold comparison and parameter switching logic, without complex algorithms (such as model predictive control), which is much lower than the scheme of using more voltage-resistant devices.

[0093] It is worth mentioning that when the dead time of the audio power amplifier is dynamically adjusted in S205 and S206, if the difference between the dead times of the two time periods is large, the switching frequency of the VDMOS device will change, which will cause power supply ripple (such as switching noise coupled to the output stage through the power supply path). At this time, the power supply ripple appears as a low-frequency hum or a high-frequency squeal in the audio frequency band. Therefore, in order to avoid the power supply ripple caused by the large difference between the dead times of the two time periods, the dead time in S205 and S206 can be adjusted by piecewise linear adjustment when the difference between the dead times of the two time periods is large, that is, the dead time is gradually shortened by a fixed step (such as 10 ns / step) instead of being directly switched to the target value. Specifically, if it is determined that the difference between the current dead time and the dead time to be switched is greater than a preset time threshold, the dead time is gradually shortened by a fixed step when the dead time is switched, until the target value is switched.

[0094] Figure 3 is a structural schematic diagram of an electronic device according to an example embodiment. As shown in Figure 3 the embodiment provides an electronic device 300, which includes a processor 301 and a memory 302; wherein:

[0095] The memory 302 is used to store computer programs, and the memory can also be a flash memory.

[0096] The processor 301 is used to execute the execution instructions stored in the memory, so as to realize each step in the above method. For details, please refer to the related description in the foregoing method embodiment.

[0097] Optionally, the memory 302 can be independent or integrated with the processor 301.

[0098] When the memory 302 is a device independent of the processor 301, the electronic device 300 can further include:

[0099] The bus 303 is used to connect the memory 302 and the processor 301.

[0100] The embodiment also provides a readable storage medium, and the readable storage medium stores a computer program. When at least one processor of an electronic device executes the computer program, the electronic device executes the method provided by the various embodiments.

[0101] The embodiment also provides a program product, and the program product includes a computer program stored in a readable storage medium. At least one processor of an electronic device can read the computer program from the readable storage medium, and the at least one processor executes the computer program to make the electronic device implement the method provided by the various embodiments.

[0102] Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. It is intended that the specification and examples be considered as exemplary only, with the true scope and spirit of the application being indicated by the following claims.

[0103] It is to be understood that the application is not limited to the precise construction hereinafter described and as shown in the attached drawings, and that various changes in form and detail can be made therein without departing from the scope thereof. The scope of the application is limited only by the claims which follow.

Claims

1. A control method for a VDMOS device, characterized in that, include: Acquire the gate voltage signal of the upper VDMOS device and the gate voltage signal of the lower VDMOS device in the circuit; The turn-on delay and turn-off delay of the upper transistor are determined based on the upper transistor gate voltage signal, and the turn-on delay and turn-off delay of the lower transistor are determined based on the lower transistor gate voltage signal. A first characteristic duration is determined based on the upper tube turn-on delay and the lower tube turn-off delay, and a second characteristic duration is determined based on the upper tube turn-off delay and the lower tube turn-on delay, so that the larger of the first characteristic duration and the second characteristic duration is determined as the initial dead time. The target dead time is determined based on the load state in the circuit and the initial dead time.

2. The control method for the VDMOS device according to claim 1, characterized in that, The upper transistor turn-on delay or the lower transistor turn-on delay is the time from when the gate voltage of the corresponding VDMOS device reaches the voltage threshold to when the collector current begins to rise. The upper transistor turn-off delay or the lower transistor turn-off delay is the time it takes for the gate voltage of the corresponding VDMOS device to drop below the voltage threshold until the collector current drops to zero.

3. The control method for the VDMOS device according to claim 1, characterized in that, Determining the target dead time based on the load state in the circuit and the initial dead time includes: Obtain the load current of the circuit; if the load current is lower than a preset current threshold, determine that the load state is a light load state. If the load state is the light load state, the duration is shortened based on the initial dead time to determine the target dead time.

4. The control method for the VDMOS device according to claim 3, characterized in that, The step of shortening the duration based on the initial dead time to determine the target dead time includes: Using Formula 1, and based on the initial dead time... and the load current Determine the target dead time Formula 1 is: in, The preset current threshold is defined as follows.

5. The control method for the VDMOS device according to claim 4, characterized in that, According to the initial dead time and the load current Determine the target dead time Following that, it also includes: If the target dead time is less than the preset lower limit dead time, then the target dead time is updated to the preset lower limit dead time.

6. The control method for the VDMOS device according to claim 3, characterized in that, The step of shortening the duration based on the initial dead time to determine the target dead time includes: The target dead time is determined as the calibration dead time, wherein the calibration dead time is greater than the preset lower dead time and less than the initial dead time.

7. The control method for the VDMOS device according to any one of claims 3-6, characterized in that, After determining the target dead time, the method further includes: If the load current is re-determined to be higher than or equal to the preset current threshold, then the load state is determined to be a non-light load state, and the target dead time is switched to the initial dead time.

8. A circuit, characterized in that, include: Upper-side VDMOS device and lower-side VDMOS device; The upper VDMOS device and the lower VDMOS device determine the dead time using the VDMOS device control method as described in any one of claims 1-7, so as to perform simultaneous turn-off.

9. An electronic device, characterized in that, include: processor; as well as, Memory for storing the executable instructions of the processor; The processor is configured to execute the method of any one of claims 1 to 7 by executing the executable instructions.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the method as described in any one of claims 1 to 7.

Images